// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// SPDX-FileCopyrightText: 1986 Xilinx, Inc. All Rights Reserved.
// SPDX-License-Identifier: Apache-2.0
// ==============================================================

/***************************** Include Files *********************************/
#include <villas/fpga/ips/rtds2gpu/xrtds2gpu.h>

/************************** Function Implementation *************************/
#ifndef __linux__
int XRtds2gpu_CfgInitialize(XRtds2gpu *InstancePtr,
                            XRtds2gpu_Config *ConfigPtr) {
  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(ConfigPtr != NULL);

  InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress;
  InstancePtr->IsReady = XIL_COMPONENT_IS_READY;

  return XST_SUCCESS;
}
#endif

void XRtds2gpu_Start(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_AP_CTRL) &
         0x80;
  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL,
                     Data | 0x01);
}

u32 XRtds2gpu_IsDone(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_AP_CTRL);
  return (Data >> 1) & 0x1;
}

u32 XRtds2gpu_IsIdle(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_AP_CTRL);
  return (Data >> 2) & 0x1;
}

u32 XRtds2gpu_IsReady(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_AP_CTRL);
  // Check ap_start to see if the pcore is ready for next input
  return !(Data & 0x1);
}

void XRtds2gpu_EnableAutoRestart(XRtds2gpu *InstancePtr) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL,
                     0x80);
}

void XRtds2gpu_DisableAutoRestart(XRtds2gpu *InstancePtr) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL,
                     0);
}

void XRtds2gpu_Set_baseaddr(XRtds2gpu *InstancePtr, u32 Data) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress,
                     XRTDS2GPU_CTRL_ADDR_BASEADDR_DATA, Data);
}

u32 XRtds2gpu_Get_baseaddr(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_BASEADDR_DATA);
  return Data;
}

void XRtds2gpu_Set_data_offset(XRtds2gpu *InstancePtr, u32 Data) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress,
                     XRTDS2GPU_CTRL_ADDR_DATA_OFFSET_DATA, Data);
}

u32 XRtds2gpu_Get_data_offset(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_DATA_OFFSET_DATA);
  return Data;
}

void XRtds2gpu_Set_doorbell_offset(XRtds2gpu *InstancePtr, u32 Data) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress,
                     XRTDS2GPU_CTRL_ADDR_DOORBELL_OFFSET_DATA, Data);
}

u32 XRtds2gpu_Get_doorbell_offset(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_DOORBELL_OFFSET_DATA);
  return Data;
}

void XRtds2gpu_Set_frame_size(XRtds2gpu *InstancePtr, u32 Data) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress,
                     XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA, Data);
}

u32 XRtds2gpu_Get_frame_size(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA);
  return Data;
}

u32 XRtds2gpu_Get_status(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_STATUS_DATA);
  return Data;
}

u32 XRtds2gpu_Get_status_vld(XRtds2gpu *InstancePtr) {
  u32 Data;

  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_STATUS_CTRL);
  return Data & 0x1;
}

void XRtds2gpu_InterruptGlobalEnable(XRtds2gpu *InstancePtr) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_GIE, 1);
}

void XRtds2gpu_InterruptGlobalDisable(XRtds2gpu *InstancePtr) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_GIE, 0);
}

void XRtds2gpu_InterruptEnable(XRtds2gpu *InstancePtr, u32 Mask) {
  u32 Register;

  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Register =
      XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER);
  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER,
                     Register | Mask);
}

void XRtds2gpu_InterruptDisable(XRtds2gpu *InstancePtr, u32 Mask) {
  u32 Register;

  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  Register =
      XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER);
  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER,
                     Register & (~Mask));
}

void XRtds2gpu_InterruptClear(XRtds2gpu *InstancePtr, u32 Mask) {
  Xil_AssertVoid(InstancePtr != NULL);
  Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_ISR,
                     Mask);
}

u32 XRtds2gpu_InterruptGetEnabled(XRtds2gpu *InstancePtr) {
  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  return XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_IER);
}

u32 XRtds2gpu_InterruptGetStatus(XRtds2gpu *InstancePtr) {
  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

  return XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress,
                           XRTDS2GPU_CTRL_ADDR_ISR);
}
