{
  "aurora_aurora_8b10b_ch0": {
    "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
    "parameters": {
      "component_name": "design_1_aurora_8b10b_0_0",
      "channel_enable": "X0Y0",
      "c_refclk_loc_p": "BL8",
      "c_refclk_loc_n": "BL7",
      "c_column_used": "right",
      "c_ucolumn_used": "right",
      "c_family": "virtex7",
      "c_device": "xc7vx485t",
      "c_row_used": "None",
      "c_xpackage": "ffg1761",
      "c_xspeedgrade": -2,
      "c_aurora_lanes": 1,
      "c_lane_width": 4,
      "c_active_transceiverquads": 1,
      "c_start_quad": "X0Y0",
      "c_start_lane": "X0Y0",
      "c_refclk_source": "none",
      "interface_mode": "Framing",
      "c_stream": "false",
      "dataflow_config": "Duplex",
      "backchannel_mode": "Sidebands",
      "c_simplex": "false",
      "c_simplex_mode": "TX",
      "flow_mode": "None",
      "c_nfc": "false",
      "c_nfc_mode": "IMM",
      "c_ufc": "false",
      "c_example_simulation": "false",
      "c_gtwiz_out": "false",
      "c_line_rate": 2,
      "cc_line_rate": 2,
      "c_refclk_frequency": "250.000",
      "cc_refclk_frequency": "250.000",
      "c_init_clk": "100.0",
      "drp_freq": "100.0",
      "c_gt_loc_1": 1,
      "c_gt_loc_2": "X",
      "c_gt_loc_3": "X",
      "c_gt_loc_4": "X",
      "c_gt_loc_5": "X",
      "c_gt_loc_6": "X",
      "c_gt_loc_7": "X",
      "c_gt_loc_8": "X",
      "c_gt_loc_9": "X",
      "c_gt_loc_10": "X",
      "c_gt_loc_11": "X",
      "c_gt_loc_12": "X",
      "c_gt_loc_13": "X",
      "c_gt_loc_14": "X",
      "c_gt_loc_15": "X",
      "c_gt_loc_16": "X",
      "c_gt_loc_17": "X",
      "c_gt_loc_18": "X",
      "c_gt_loc_19": "X",
      "c_gt_loc_20": "X",
      "c_gt_loc_21": "X",
      "c_gt_loc_22": "X",
      "c_gt_loc_23": "X",
      "c_gt_loc_24": "X",
      "c_gt_loc_25": "X",
      "c_gt_loc_26": "X",
      "c_gt_loc_27": "X",
      "c_gt_loc_28": "X",
      "c_gt_loc_29": "X",
      "c_gt_loc_30": "X",
      "c_gt_loc_31": "X",
      "c_gt_loc_32": "X",
      "c_gt_loc_33": "X",
      "c_gt_loc_34": "X",
      "c_gt_loc_35": "X",
      "c_gt_loc_36": "X",
      "c_gt_loc_37": "X",
      "c_gt_loc_38": "X",
      "c_gt_loc_39": "X",
      "c_gt_loc_40": "X",
      "c_gt_loc_41": "X",
      "c_gt_loc_42": "X",
      "c_gt_loc_43": "X",
      "c_gt_loc_44": "X",
      "c_gt_loc_45": "X",
      "c_gt_loc_46": "X",
      "c_gt_loc_47": "X",
      "c_gt_loc_48": "X",
      "c_gt_clock_1": "GTXQ0",
      "c_gt_clock_2": "None",
      "c_use_scrambler": "false",
      "c_use_chipscope": "false",
      "c_drp_if": "false",
      "transceivercontrol": "false",
      "c_use_crc": "true",
      "supportlevel": 1,
      "c_use_byteswap": "false",
      "c_cpll_fbdiv": 2,
      "c_cpll_fbdiv_45": 4,
      "c_cpll_refclk_div": 1,
      "c_rxoutdiv": 2,
      "c_txoutdiv": 2,
      "user_interface": "AXI_4_Streaming",
      "c_ufcbuswidthselect": 32,
      "c_ufcrembuswidthselect": 2,
      "c_ufcstrbbuswidthselect": 4,
      "c_rembuswidthselect": 2,
      "isv7gth": "false",
      "gtquadcnt": 1,
      "port7dmonitorout": 7,
      "is_7series": "true",
      "singleend_initclk": "true",
      "singleend_gtrefclk": "true",
      "c_double_gtrxreset": "false",
      "c_doccport_enable": "false",
      "is_board": "vc707",
      "usdrpaddr_width": 8,
      "usdmon_width": 16,
      "txdiffctrl_width": 3,
      "ins_loss_nyq": 14,
      "rx_eq_mode": "AUTO",
      "rx_coupling": "AC",
      "rx_termination": "PROGRAMMABLE",
      "rx_termination_prog_value": 800,
      "rx_ppm_offset": 200,
      "edk_iptype": "PERIPHERAL"
    },
    "ports": [
      {
        "role": "master",
        "target": "crossbar_axis_interconnect_0_xbar:S00_AXIS",
        "name": "USER_DATA_M_AXI_RX"
      },
      {
        "role": "slave",
        "target": "crossbar_axis_interconnect_0_xbar:M00_AXIS",
        "name": "USER_DATA_S_AXI_TX"
      }
    ]
  },
  "aurora_aurora_8b10b_ch1": {
    "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
    "parameters": {
      "component_name": "design_1_aurora_8b10b_1_0",
      "channel_enable": "X0Y0",
      "c_refclk_loc_p": "BL8",
      "c_refclk_loc_n": "BL7",
      "c_column_used": "right",
      "c_ucolumn_used": "right",
      "c_family": "virtex7",
      "c_device": "xc7vx485t",
      "c_row_used": "None",
      "c_xpackage": "ffg1761",
      "c_xspeedgrade": -2,
      "c_aurora_lanes": 1,
      "c_lane_width": 4,
      "c_active_transceiverquads": 1,
      "c_start_quad": "X0Y0",
      "c_start_lane": "X0Y0",
      "c_refclk_source": "none",
      "interface_mode": "Framing",
      "c_stream": "false",
      "dataflow_config": "Duplex",
      "backchannel_mode": "Sidebands",
      "c_simplex": "false",
      "c_simplex_mode": "TX",
      "flow_mode": "None",
      "c_nfc": "false",
      "c_nfc_mode": "IMM",
      "c_ufc": "false",
      "c_example_simulation": "false",
      "c_gtwiz_out": "false",
      "c_line_rate": 2,
      "cc_line_rate": 2,
      "c_refclk_frequency": "250.000",
      "cc_refclk_frequency": "250.000",
      "c_init_clk": "100.0",
      "drp_freq": "100.0",
      "c_gt_loc_1": 1,
      "c_gt_loc_2": "X",
      "c_gt_loc_3": "X",
      "c_gt_loc_4": "X",
      "c_gt_loc_5": "X",
      "c_gt_loc_6": "X",
      "c_gt_loc_7": "X",
      "c_gt_loc_8": "X",
      "c_gt_loc_9": "X",
      "c_gt_loc_10": "X",
      "c_gt_loc_11": "X",
      "c_gt_loc_12": "X",
      "c_gt_loc_13": "X",
      "c_gt_loc_14": "X",
      "c_gt_loc_15": "X",
      "c_gt_loc_16": "X",
      "c_gt_loc_17": "X",
      "c_gt_loc_18": "X",
      "c_gt_loc_19": "X",
      "c_gt_loc_20": "X",
      "c_gt_loc_21": "X",
      "c_gt_loc_22": "X",
      "c_gt_loc_23": "X",
      "c_gt_loc_24": "X",
      "c_gt_loc_25": "X",
      "c_gt_loc_26": "X",
      "c_gt_loc_27": "X",
      "c_gt_loc_28": "X",
      "c_gt_loc_29": "X",
      "c_gt_loc_30": "X",
      "c_gt_loc_31": "X",
      "c_gt_loc_32": "X",
      "c_gt_loc_33": "X",
      "c_gt_loc_34": "X",
      "c_gt_loc_35": "X",
      "c_gt_loc_36": "X",
      "c_gt_loc_37": "X",
      "c_gt_loc_38": "X",
      "c_gt_loc_39": "X",
      "c_gt_loc_40": "X",
      "c_gt_loc_41": "X",
      "c_gt_loc_42": "X",
      "c_gt_loc_43": "X",
      "c_gt_loc_44": "X",
      "c_gt_loc_45": "X",
      "c_gt_loc_46": "X",
      "c_gt_loc_47": "X",
      "c_gt_loc_48": "X",
      "c_gt_clock_1": "GTXQ0",
      "c_gt_clock_2": "None",
      "c_use_scrambler": "false",
      "c_use_chipscope": "false",
      "c_drp_if": "false",
      "transceivercontrol": "false",
      "c_use_crc": "true",
      "supportlevel": 0,
      "c_use_byteswap": "false",
      "c_cpll_fbdiv": 2,
      "c_cpll_fbdiv_45": 4,
      "c_cpll_refclk_div": 1,
      "c_rxoutdiv": 2,
      "c_txoutdiv": 2,
      "user_interface": "AXI_4_Streaming",
      "c_ufcbuswidthselect": 32,
      "c_ufcrembuswidthselect": 2,
      "c_ufcstrbbuswidthselect": 4,
      "c_rembuswidthselect": 2,
      "isv7gth": "false",
      "gtquadcnt": 1,
      "port7dmonitorout": 7,
      "is_7series": "true",
      "singleend_initclk": "false",
      "singleend_gtrefclk": "false",
      "c_double_gtrxreset": "false",
      "c_doccport_enable": "false",
      "is_board": "vc707",
      "usdrpaddr_width": 8,
      "usdmon_width": 16,
      "txdiffctrl_width": 3,
      "ins_loss_nyq": 14,
      "rx_eq_mode": "AUTO",
      "rx_coupling": "AC",
      "rx_termination": "PROGRAMMABLE",
      "rx_termination_prog_value": 800,
      "rx_ppm_offset": 200,
      "edk_iptype": "PERIPHERAL"
    },
    "ports": [
      {
        "role": "master",
        "target": "crossbar_axis_interconnect_0_xbar:S01_AXIS",
        "name": "USER_DATA_M_AXI_RX"
      },
      {
        "role": "slave",
        "target": "crossbar_axis_interconnect_0_xbar:M01_AXIS",
        "name": "USER_DATA_S_AXI_TX"
      }
    ]
  },
  "aurora_aurora_8b10b_ch2": {
    "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
    "parameters": {
      "component_name": "design_1_aurora_8b10b_3_0",
      "channel_enable": "X0Y0",
      "c_refclk_loc_p": "BL8",
      "c_refclk_loc_n": "BL7",
      "c_column_used": "right",
      "c_ucolumn_used": "right",
      "c_family": "virtex7",
      "c_device": "xc7vx485t",
      "c_row_used": "None",
      "c_xpackage": "ffg1761",
      "c_xspeedgrade": -2,
      "c_aurora_lanes": 1,
      "c_lane_width": 4,
      "c_active_transceiverquads": 1,
      "c_start_quad": "X0Y0",
      "c_start_lane": "X0Y0",
      "c_refclk_source": "none",
      "interface_mode": "Framing",
      "c_stream": "false",
      "dataflow_config": "Duplex",
      "backchannel_mode": "Sidebands",
      "c_simplex": "false",
      "c_simplex_mode": "TX",
      "flow_mode": "None",
      "c_nfc": "false",
      "c_nfc_mode": "IMM",
      "c_ufc": "false",
      "c_example_simulation": "false",
      "c_gtwiz_out": "false",
      "c_line_rate": 2,
      "cc_line_rate": 2,
      "c_refclk_frequency": "250.000",
      "cc_refclk_frequency": "250.000",
      "c_init_clk": "100.0",
      "drp_freq": "100.0",
      "c_gt_loc_1": "X",
      "c_gt_loc_2": "X",
      "c_gt_loc_3": "X",
      "c_gt_loc_4": "X",
      "c_gt_loc_5": "X",
      "c_gt_loc_6": "X",
      "c_gt_loc_7": "X",
      "c_gt_loc_8": "X",
      "c_gt_loc_9": "X",
      "c_gt_loc_10": "X",
      "c_gt_loc_11": "X",
      "c_gt_loc_12": "X",
      "c_gt_loc_13": "X",
      "c_gt_loc_14": "X",
      "c_gt_loc_15": "X",
      "c_gt_loc_16": "X",
      "c_gt_loc_17": "X",
      "c_gt_loc_18": "X",
      "c_gt_loc_19": "X",
      "c_gt_loc_20": "X",
      "c_gt_loc_21": "X",
      "c_gt_loc_22": "X",
      "c_gt_loc_23": "X",
      "c_gt_loc_24": "X",
      "c_gt_loc_25": "X",
      "c_gt_loc_26": 1,
      "c_gt_loc_27": "X",
      "c_gt_loc_28": "X",
      "c_gt_loc_29": "X",
      "c_gt_loc_30": "X",
      "c_gt_loc_31": "X",
      "c_gt_loc_32": "X",
      "c_gt_loc_33": "X",
      "c_gt_loc_34": "X",
      "c_gt_loc_35": "X",
      "c_gt_loc_36": "X",
      "c_gt_loc_37": "X",
      "c_gt_loc_38": "X",
      "c_gt_loc_39": "X",
      "c_gt_loc_40": "X",
      "c_gt_loc_41": "X",
      "c_gt_loc_42": "X",
      "c_gt_loc_43": "X",
      "c_gt_loc_44": "X",
      "c_gt_loc_45": "X",
      "c_gt_loc_46": "X",
      "c_gt_loc_47": "X",
      "c_gt_loc_48": "X",
      "c_gt_clock_1": "GTXQ6",
      "c_gt_clock_2": "None",
      "c_use_scrambler": "false",
      "c_use_chipscope": "false",
      "c_drp_if": "false",
      "transceivercontrol": "false",
      "c_use_crc": "true",
      "supportlevel": 0,
      "c_use_byteswap": "false",
      "c_cpll_fbdiv": 2,
      "c_cpll_fbdiv_45": 4,
      "c_cpll_refclk_div": 1,
      "c_rxoutdiv": 2,
      "c_txoutdiv": 2,
      "user_interface": "AXI_4_Streaming",
      "c_ufcbuswidthselect": 32,
      "c_ufcrembuswidthselect": 2,
      "c_ufcstrbbuswidthselect": 4,
      "c_rembuswidthselect": 2,
      "isv7gth": "false",
      "gtquadcnt": 1,
      "port7dmonitorout": 7,
      "is_7series": "true",
      "singleend_initclk": "false",
      "singleend_gtrefclk": "false",
      "c_double_gtrxreset": "false",
      "c_doccport_enable": "false",
      "is_board": "vc707",
      "usdrpaddr_width": 8,
      "usdmon_width": 16,
      "txdiffctrl_width": 3,
      "ins_loss_nyq": 14,
      "rx_eq_mode": "AUTO",
      "rx_coupling": "AC",
      "rx_termination": "PROGRAMMABLE",
      "rx_termination_prog_value": 800,
      "rx_ppm_offset": 200,
      "edk_iptype": "PERIPHERAL"
    },
    "ports": [
      {
        "role": "master",
        "target": "crossbar_axis_interconnect_0_xbar:S02_AXIS",
        "name": "USER_DATA_M_AXI_RX"
      },
      {
        "role": "slave",
        "target": "crossbar_axis_interconnect_0_xbar:M02_AXIS",
        "name": "USER_DATA_S_AXI_TX"
      }
    ]
  },
  "aurora_aurora_8b10b_ch3": {
    "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
    "parameters": {
      "component_name": "design_1_aurora_8b10b_2_0",
      "channel_enable": "X0Y0",
      "c_refclk_loc_p": "BL8",
      "c_refclk_loc_n": "BL7",
      "c_column_used": "right",
      "c_ucolumn_used": "right",
      "c_family": "virtex7",
      "c_device": "xc7vx485t",
      "c_row_used": "None",
      "c_xpackage": "ffg1761",
      "c_xspeedgrade": -2,
      "c_aurora_lanes": 1,
      "c_lane_width": 4,
      "c_active_transceiverquads": 1,
      "c_start_quad": "X0Y0",
      "c_start_lane": "X0Y0",
      "c_refclk_source": "none",
      "interface_mode": "Framing",
      "c_stream": "false",
      "dataflow_config": "Duplex",
      "backchannel_mode": "Sidebands",
      "c_simplex": "false",
      "c_simplex_mode": "TX",
      "flow_mode": "None",
      "c_nfc": "false",
      "c_nfc_mode": "IMM",
      "c_ufc": "false",
      "c_example_simulation": "false",
      "c_gtwiz_out": "false",
      "c_line_rate": 2,
      "cc_line_rate": 2,
      "c_refclk_frequency": "250.000",
      "cc_refclk_frequency": "250.000",
      "c_init_clk": "100.0",
      "drp_freq": "100.0",
      "c_gt_loc_1": "X",
      "c_gt_loc_2": "X",
      "c_gt_loc_3": "X",
      "c_gt_loc_4": "X",
      "c_gt_loc_5": "X",
      "c_gt_loc_6": "X",
      "c_gt_loc_7": "X",
      "c_gt_loc_8": "X",
      "c_gt_loc_9": "X",
      "c_gt_loc_10": "X",
      "c_gt_loc_11": "X",
      "c_gt_loc_12": "X",
      "c_gt_loc_13": "X",
      "c_gt_loc_14": "X",
      "c_gt_loc_15": "X",
      "c_gt_loc_16": "X",
      "c_gt_loc_17": "X",
      "c_gt_loc_18": "X",
      "c_gt_loc_19": "X",
      "c_gt_loc_20": "X",
      "c_gt_loc_21": "X",
      "c_gt_loc_22": "X",
      "c_gt_loc_23": "X",
      "c_gt_loc_24": "X",
      "c_gt_loc_25": 1,
      "c_gt_loc_26": "X",
      "c_gt_loc_27": "X",
      "c_gt_loc_28": "X",
      "c_gt_loc_29": "X",
      "c_gt_loc_30": "X",
      "c_gt_loc_31": "X",
      "c_gt_loc_32": "X",
      "c_gt_loc_33": "X",
      "c_gt_loc_34": "X",
      "c_gt_loc_35": "X",
      "c_gt_loc_36": "X",
      "c_gt_loc_37": "X",
      "c_gt_loc_38": "X",
      "c_gt_loc_39": "X",
      "c_gt_loc_40": "X",
      "c_gt_loc_41": "X",
      "c_gt_loc_42": "X",
      "c_gt_loc_43": "X",
      "c_gt_loc_44": "X",
      "c_gt_loc_45": "X",
      "c_gt_loc_46": "X",
      "c_gt_loc_47": "X",
      "c_gt_loc_48": "X",
      "c_gt_clock_1": "GTXQ6",
      "c_gt_clock_2": "None",
      "c_use_scrambler": "false",
      "c_use_chipscope": "false",
      "c_drp_if": "false",
      "transceivercontrol": "false",
      "c_use_crc": "true",
      "supportlevel": 0,
      "c_use_byteswap": "false",
      "c_cpll_fbdiv": 2,
      "c_cpll_fbdiv_45": 4,
      "c_cpll_refclk_div": 1,
      "c_rxoutdiv": 2,
      "c_txoutdiv": 2,
      "user_interface": "AXI_4_Streaming",
      "c_ufcbuswidthselect": 32,
      "c_ufcrembuswidthselect": 2,
      "c_ufcstrbbuswidthselect": 4,
      "c_rembuswidthselect": 2,
      "isv7gth": "false",
      "gtquadcnt": 1,
      "port7dmonitorout": 7,
      "is_7series": "true",
      "singleend_initclk": "false",
      "singleend_gtrefclk": "false",
      "c_double_gtrxreset": "false",
      "c_doccport_enable": "false",
      "is_board": "vc707",
      "usdrpaddr_width": 8,
      "usdmon_width": 16,
      "txdiffctrl_width": 3,
      "ins_loss_nyq": 14,
      "rx_eq_mode": "AUTO",
      "rx_coupling": "AC",
      "rx_termination": "PROGRAMMABLE",
      "rx_termination_prog_value": 800,
      "rx_ppm_offset": 200,
      "edk_iptype": "PERIPHERAL"
    },
    "ports": [
      {
        "role": "master",
        "target": "crossbar_axis_interconnect_0_xbar:S03_AXIS",
        "name": "USER_DATA_M_AXI_RX"
      },
      {
        "role": "slave",
        "target": "crossbar_axis_interconnect_0_xbar:M03_AXIS",
        "name": "USER_DATA_S_AXI_TX"
      }
    ]
  },
  "axi_gpio_0": {
    "vlnv": "xilinx.com:ip:axi_gpio:2.0",
    "parameters": {
      "c_family": "virtex7",
      "c_s_axi_addr_width": 9,
      "c_s_axi_data_width": 32,
      "c_gpio_width": 8,
      "c_gpio2_width": 32,
      "c_all_inputs": 0,
      "c_all_inputs_2": 0,
      "c_all_outputs": 1,
      "c_all_outputs_2": 0,
      "c_interrupt_present": 0,
      "c_dout_default": 0,
      "c_tri_default": 4294967295,
      "c_is_dual": 0,
      "c_dout_default_2": 0,
      "c_tri_default_2": 4294967295,
      "component_name": "design_1_axi_gpio_0_0",
      "use_board_flow": "false",
      "gpio_board_interface": "led_8bits",
      "gpio2_board_interface": "Custom",
      "edk_iptype": "PERIPHERAL",
      "c_baseaddr": 0,
      "c_highaddr": 127
    }
  },
  "crossbar_axis_interconnect_0_xbar": {
    "vlnv": "xilinx.com:ip:axis_switch:1.1",
    "parameters": {
      "c_family": "virtex7",
      "c_num_si_slots": 6,
      "c_log_si_slots": 3,
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        "role": "slave",
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      {
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      {
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      {
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      {
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      {
        "role": "master",
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      }
    ],
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  },
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      "edk_iptype": "PERIPHERAL",
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  },
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    },
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      "component_name": "design_1_axi_dma_0_0",
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            "size": 4294967296
          }
        }
      },
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        "dma_pcie_pcie_axi_pcie_0": {
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            "size": 4294967296
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      },
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          }
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        "role": "master",
        "target": "crossbar_axis_interconnect_0_xbar:S04_AXIS",
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      },
      {
        "role": "slave",
        "target": "crossbar_axis_interconnect_0_xbar:M04_AXIS",
        "name": "S2MM"
      }
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      "s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
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    "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
    "parameters": {
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      "word_num": 16,
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      "edk_iptype": "PERIPHERAL",
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      "c_highaddr": 25599
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    "memory-view": {
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        "dma_pcie_pcie_axi_pcie_0": {
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            "size": 4294967296
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        }
      }
    }
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    "vlnv": "xilinx.com:ip:axi_pcie:2.9",
    "parameters": {
      "c_family": "virtex7",
      "c_instance": "design_1_axi_pcie_0_1",
      "c_s_axi_id_width": 2,
      "c_s_axi_addr_width": 32,
      "c_s_axi_data_width": 64,
      "c_m_axi_addr_width": 32,
      "c_m_axi_data_width": 64,
      "c_no_of_lanes": 1,
      "c_max_link_speed": 1,
      "c_pcie_use_mode": "3.0",
      "c_device_id": 28705,
      "c_vendor_id": 4334,
      "c_class_code": 360448,
      "c_ref_clk_freq": 0,
      "c_rev_id": 0,
      "c_subsystem_id": 7,
      "c_subsystem_vendor_id": 4334,
      "c_pcie_cap_slot_implemented": 0,
      "c_slot_clock_config": "TRUE",
      "c_msi_decode_enable": "TRUE",
      "c_int_fifo_depth": 0,
      "c_num_msi_req": 4,
      "c_interrupt_pin": 0,
      "c_comp_timeout": 0,
      "c_include_rc": 0,
      "c_s_axi_supports_narrow_burst": 1,
      "c_include_baroffset_reg": 1,
      "c_axibar_num": 1,
      "c_axibar2pciebar_0": 0,
      "c_axibar2pciebar_1": 0,
      "c_axibar2pciebar_2": 0,
      "c_axibar2pciebar_3": 0,
      "c_axibar2pciebar_4": 0,
      "c_axibar2pciebar_5": 0,
      "c_axibar_as_0": 0,
      "c_axibar_as_1": 0,
      "c_axibar_as_2": 0,
      "c_axibar_as_3": 0,
      "c_axibar_as_4": 0,
      "c_axibar_as_5": 0,
      "c_axibar_0": 0,
      "c_axibar_highaddr_0": 4294967295,
      "c_axibar_1": 4294967295,
      "c_axibar_highaddr_1": 0,
      "c_axibar_2": 4294967295,
      "c_axibar_highaddr_2": 0,
      "c_axibar_3": 4294967295,
      "c_axibar_highaddr_3": 0,
      "c_axibar_4": 4294967295,
      "c_axibar_highaddr_4": 0,
      "c_axibar_5": 4294967295,
      "c_axibar_highaddr_5": 0,
      "c_pciebar_num": 1,
      "c_pciebar_as": 0,
      "c_pciebar_len_0": 20,
      "c_pciebar2axibar_0": 0,
      "c_pciebar2axibar_0_sec": 1,
      "c_pciebar_len_1": 16,
      "c_pciebar2axibar_1": 4294967295,
      "c_pciebar2axibar_1_sec": 1,
      "c_pciebar_len_2": 16,
      "c_pciebar2axibar_2": 4294967295,
      "c_pciebar2axibar_2_sec": 1,
      "c_pcie_blk_locn": 3,
      "c_xlnx_ref_board": "VC707",
      "pcie_ext_clk": "FALSE",
      "pcie_ext_gt_common": "FALSE",
      "ext_ch_gt_drp": "FALSE",
      "shared_logic_in_core": "false",
      "transceiver_ctrl_status_ports": "FALSE",
      "ext_pipe_interface": "FALSE",
      "c_device": "xc7vx485t",
      "c_speed": -2,
      "axi_aclk_loopback": "false",
      "no_slv_err": "false",
      "c_rp_bar_hide": "FALSE",
      "enable_jtag_dbg": "false",
      "c_axibar_chk_slv_err": "false",
      "reduce_oob_freq": "false",
      "component_name": "design_1_axi_pcie_0_1",
      "include_rc": "PCI_Express_Endpoint_device",
      "ref_clk_freq": "100_MHz",
      "slot_clock_config": "true",
      "pcie_use_mode": "GES_and_Production",
      "no_of_lanes": "X1",
      "max_link_speed": "5.0_GT/s",
      "vendor_id": 4334,
      "device_id": 28705,
      "rev_id": 0,
      "subsystem_vendor_id": 4334,
      "subsystem_id": 7,
      "enable_class_code": "true",
      "class_code": 360448,
      "base_class_menu": "Memory_controller",
      "sub_class_interface_menu": "Other_memory_controller",
      "bar0_enabled": "true",
      "bar1_enabled": "false",
      "bar2_enabled": "false",
      "bar0_type": "Memory",
      "bar1_type": "N/A",
      "bar2_type": "N/A",
      "bar0_scale": "Megabytes",
      "bar1_scale": "N/A",
      "bar2_scale": "N/A",
      "bar0_size": 1,
      "bar1_size": 8,
      "bar2_size": 8,
      "pciebar2axibar_0": 0,
      "pciebar2axibar_1": 4294967295,
      "pciebar2axibar_2": 4294967295,
      "pciebar2axibar_1_sec": 1,
      "pciebar2axibar_0_sec": 1,
      "pciebar2axibar_2_sec": 1,
      "interrupt_pin": "false",
      "msi_decode_enabled": "true",
      "num_msi_req": 4,
      "int_fifo_depth": 16,
      "comp_timeout": "50us",
      "include_baroffset_reg": "true",
      "axibar_as_0": "false",
      "axibar_as_1": "false",
      "axibar_as_2": "false",
      "axibar_as_3": "false",
      "axibar_as_4": "false",
      "axibar_as_5": "false",
      "axibar_1": 4294967295,
      "axibar_2": 4294967295,
      "axibar_3": 4294967295,
      "axibar_4": 4294967295,
      "axibar_5": 4294967295,
      "axibar_highaddr_1": 0,
      "axibar_highaddr_2": 0,
      "axibar_highaddr_3": 0,
      "axibar_highaddr_4": 0,
      "axibar_highaddr_5": 0,
      "axibar2pciebar_0": 0,
      "axibar2pciebar_1": 0,
      "axibar2pciebar_2": 0,
      "axibar2pciebar_3": 0,
      "axibar2pciebar_4": 0,
      "axibar2pciebar_5": 0,
      "baseaddr": 4096,
      "highaddr": 8191,
      "s_axi_id_width": 2,
      "s_axi_addr_width": 32,
      "s_axi_data_width": 64,
      "m_axi_addr_width": 32,
      "m_axi_data_width": 64,
      "s_axi_supports_narrow_burst": "true",
      "bar_64bit": "false",
      "xlnx_ref_board": "VC707",
      "pcie_blk_locn": "X1Y0",
      "axibar_num": 1,
      "en_ext_clk": "false",
      "en_ext_gt_common": "false",
      "en_ext_ch_gt_drp": "false",
      "en_transceiver_status_ports": "false",
      "en_ext_pipe_interface": "false",
      "rp_bar_hide": "false",
      "edk_iptype": "PERIPHERAL",
      "axibar_0": 0,
      "axibar_highaddr_0": 4294967295
    },
    "memory-view": {
      "M_AXI": {
        "axi_gpio_0": {
          "Reg": {
            "baseaddr": 0,
            "highaddr": 127,
            "size": 128
          }
        },
        "crossbar_axis_interconnect_0_xbar": {
          "Reg": {
            "baseaddr": 4096,
            "highaddr": 5119,
            "size": 1024
          }
        },
        "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
          "reg0": {
            "baseaddr": 8192,
            "highaddr": 9215,
            "size": 1024
          }
        },
        "dma_pcie_axi_dma_0": {
          "Reg": {
            "baseaddr": 12288,
            "highaddr": 13311,
            "size": 1024
          }
        },
        "dino_axi_iic_0": {
          "Reg": {
            "baseaddr": 16384,
            "highaddr": 17407,
            "size": 1024
          }
        },
        "dino_registerif_0": {
          "reg0": {
            "baseaddr": 20480,
            "highaddr": 21503,
            "size": 1024
          }
        },
        "dma_pcie_axi_read_cache_0": {
          "reg0": {
            "baseaddr": 24576,
            "highaddr": 25599,
            "size": 1024
          }
        }
      }
    },
    "axi_bars": {
      "BAR0": {
        "translation": 0,
        "baseaddr": 0,
        "highaddr": 4294967295,
        "size": 4294967296
      }
    },
    "pcie_bars": {
      "BAR0": {
        "translation": 0
      }
    }
  },
  "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
    "vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0",
    "parameters": {
      "component_name": "design_1_axi_pcie_intc_0_0",
      "edk_iptype": "PERIPHERAL",
      "c_baseaddr": 8192,
      "c_highaddr": 9215
    }
  }
}
