# SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0

logging = {
    level = "debug"
}

fpgas = {
    vc707 = {
        interface = "pcie"
        id = "10ee:7021"
        slot = "0000:88:00.0"
        do_reset = true
        ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino.json"
        polling =  false
    }
}

nodes = {
    fpga_0 = {
        type = "fpga"
        card = "vc707"
        connect = ["0->3", "3->dma", "0<-dma"]
        timestep = 10e-3
    }
}

paths = (
    {
        in = "fpga_0"
        out = "fpga_0"
        hooks = ({ type = "print"})
    }
)
