{
  "axi_dma_0": {
    "vlnv": "xilinx.com:ip:axi_dma:7.1",
    "parameters": {
      "c_s_axi_lite_addr_width": 10,
      "c_s_axi_lite_data_width": 32,
      "c_dlytmr_resolution": 125,
      "c_prmry_is_aclk_async": 0,
      "c_enable_multi_channel": 0,
      "c_num_mm2s_channels": 1,
      "c_num_s2mm_channels": 1,
      "c_include_sg": 1,
      "c_sg_include_stscntrl_strm": 0,
      "c_sg_use_stsapp_length": 0,
      "c_sg_length_width": 14,
      "c_m_axi_sg_addr_width": 32,
      "c_m_axi_sg_data_width": 32,
      "c_m_axis_mm2s_cntrl_tdata_width": 32,
      "c_s_axis_s2mm_sts_tdata_width": 32,
      "c_micro_dma": 0,
      "c_include_mm2s": 1,
      "c_include_mm2s_sf": 1,
      "c_mm2s_burst_size": 16,
      "c_m_axi_mm2s_addr_width": 32,
      "c_m_axi_mm2s_data_width": 32,
      "c_m_axis_mm2s_tdata_width": 32,
      "c_include_mm2s_dre": 0,
      "c_include_s2mm": 1,
      "c_include_s2mm_sf": 1,
      "c_s2mm_burst_size": 16,
      "c_m_axi_s2mm_addr_width": 32,
      "c_m_axi_s2mm_data_width": 32,
      "c_s_axis_s2mm_tdata_width": 32,
      "c_include_s2mm_dre": 0,
      "c_increase_throughput": 0,
      "c_family": "virtexuplusHBM",
      "component_name": "design_1_axi_dma_0_0",
      "c_addr_width": 32,
      "c_single_interface": 0,
      "edk_iptype": "PERIPHERAL",
      "c_baseaddr": 0,
      "c_highaddr": 1023
    },
    "memory-view": {
      "M_AXI_SG": {
        "xdma_0": {
          "BAR0": {
            "baseaddr": 0,
            "highaddr": 4294967295,
            "size": 4294967296
          }
        }
      },
      "M_AXI_MM2S": {
        "xdma_0": {
          "BAR0": {
            "baseaddr": 0,
            "highaddr": 4294967295,
            "size": 4294967296
          }
        }
      },
      "M_AXI_S2MM": {
        "xdma_0": {
          "BAR0": {
            "baseaddr": 0,
            "highaddr": 4294967295,
            "size": 4294967296
          }
        }
      }
    },
    "ports": [
      {
        "role": "initiator",
        "target": "axis_switch_0:S00_AXIS",
        "name": "MM2S"
      },
      {
        "role": "target",
        "target": "axis_switch_0:M00_AXIS",
        "name": "S2MM"
      }
    ]
  },
  "axis_switch_0": {
    "vlnv": "xilinx.com:ip:axis_switch:1.1",
    "parameters": {
      "c_family": "virtexuplusHBM",
      "c_num_si_slots": 2,
      "c_log_si_slots": 1,
      "c_num_mi_slots": 2,
      "c_axis_tdata_width": 32,
      "c_axis_tid_width": 1,
      "c_axis_tdest_width": 1,
      "c_axis_tuser_width": 1,
      "c_axis_signal_set": 91,
      "c_arb_on_max_xfers": 1,
      "c_arb_on_num_cycles": 0,
      "c_arb_on_tlast": 0,
      "c_include_arbiter": 1,
      "c_arb_algorithm": 0,
      "c_output_reg": 0,
      "c_decoder_reg": 1,
      "c_m_axis_connectivity_array": 15,
      "c_m_axis_basetdest_array": 2,
      "c_m_axis_hightdest_array": 2,
      "c_routing_mode": 1,
      "c_s_axi_ctrl_addr_width": 7,
      "c_s_axi_ctrl_data_width": 32,
      "c_common_clock": 0,
      "num_si": 2,
      "num_mi": 2,
      "routing_mode": 1,
      "has_tready": 1,
      "tdata_num_bytes": 4,
      "has_tstrb": 0,
      "has_tkeep": 1,
      "has_tlast": 1,
      "tid_width": 0,
      "tdest_width": 1,
      "tuser_width": 0,
      "has_aclken": 0,
      "arb_on_max_xfers": 1,
      "arb_on_num_cycles": 0,
      "arb_on_tlast": 0,
      "arb_algorithm": 0,
      "decoder_reg": 1,
      "output_reg": 0,
      "common_clock": 0,
      "m00_axis_basetdest": 0,
      "m01_axis_basetdest": 1,
      "m02_axis_basetdest": 2,
      "m03_axis_basetdest": 3,
      "m04_axis_basetdest": 4,
      "m05_axis_basetdest": 5,
      "m06_axis_basetdest": 6,
      "m07_axis_basetdest": 7,
      "m08_axis_basetdest": 8,
      "m09_axis_basetdest": 9,
      "m10_axis_basetdest": 10,
      "m11_axis_basetdest": 11,
      "m12_axis_basetdest": 12,
      "m13_axis_basetdest": 13,
      "m14_axis_basetdest": 14,
      "m15_axis_basetdest": 15,
      "m00_axis_hightdest": 0,
      "m01_axis_hightdest": 1,
      "m02_axis_hightdest": 2,
      "m03_axis_hightdest": 3,
      "m04_axis_hightdest": 4,
      "m05_axis_hightdest": 5,
      "m06_axis_hightdest": 6,
      "m07_axis_hightdest": 7,
      "m08_axis_hightdest": 8,
      "m09_axis_hightdest": 9,
      "m10_axis_hightdest": 10,
      "m11_axis_hightdest": 11,
      "m12_axis_hightdest": 12,
      "m13_axis_hightdest": 13,
      "m14_axis_hightdest": 14,
      "m15_axis_hightdest": 15,
      "m00_s00_connectivity": 1,
      "m00_s01_connectivity": 1,
      "m00_s02_connectivity": 1,
      "m00_s03_connectivity": 1,
      "m00_s04_connectivity": 1,
      "m00_s05_connectivity": 1,
      "m00_s06_connectivity": 1,
      "m00_s07_connectivity": 1,
      "m00_s08_connectivity": 1,
      "m00_s09_connectivity": 1,
      "m00_s10_connectivity": 1,
      "m00_s11_connectivity": 1,
      "m00_s12_connectivity": 1,
      "m00_s13_connectivity": 1,
      "m00_s14_connectivity": 1,
      "m00_s15_connectivity": 1,
      "m01_s00_connectivity": 1,
      "m01_s01_connectivity": 1,
      "m01_s02_connectivity": 1,
      "m01_s03_connectivity": 1,
      "m01_s04_connectivity": 1,
      "m01_s05_connectivity": 1,
      "m01_s06_connectivity": 1,
      "m01_s07_connectivity": 1,
      "m01_s08_connectivity": 1,
      "m01_s09_connectivity": 1,
      "m01_s10_connectivity": 1,
      "m01_s11_connectivity": 1,
      "m01_s12_connectivity": 1,
      "m01_s13_connectivity": 1,
      "m01_s14_connectivity": 1,
      "m01_s15_connectivity": 1,
      "m02_s00_connectivity": 1,
      "m02_s01_connectivity": 1,
      "m02_s02_connectivity": 1,
      "m02_s03_connectivity": 1,
      "m02_s04_connectivity": 1,
      "m02_s05_connectivity": 1,
      "m02_s06_connectivity": 1,
      "m02_s07_connectivity": 1,
      "m02_s08_connectivity": 1,
      "m02_s09_connectivity": 1,
      "m02_s10_connectivity": 1,
      "m02_s11_connectivity": 1,
      "m02_s12_connectivity": 1,
      "m02_s13_connectivity": 1,
      "m02_s14_connectivity": 1,
      "m02_s15_connectivity": 1,
      "m03_s00_connectivity": 1,
      "m03_s01_connectivity": 1,
      "m03_s02_connectivity": 1,
      "m03_s03_connectivity": 1,
      "m03_s04_connectivity": 1,
      "m03_s05_connectivity": 1,
      "m03_s06_connectivity": 1,
      "m03_s07_connectivity": 1,
      "m03_s08_connectivity": 1,
      "m03_s09_connectivity": 1,
      "m03_s10_connectivity": 1,
      "m03_s11_connectivity": 1,
      "m03_s12_connectivity": 1,
      "m03_s13_connectivity": 1,
      "m03_s14_connectivity": 1,
      "m03_s15_connectivity": 1,
      "m04_s00_connectivity": 1,
      "m04_s01_connectivity": 1,
      "m04_s02_connectivity": 1,
      "m04_s03_connectivity": 1,
      "m04_s04_connectivity": 1,
      "m04_s05_connectivity": 1,
      "m04_s06_connectivity": 1,
      "m04_s07_connectivity": 1,
      "m04_s08_connectivity": 1,
      "m04_s09_connectivity": 1,
      "m04_s10_connectivity": 1,
      "m04_s11_connectivity": 1,
      "m04_s12_connectivity": 1,
      "m04_s13_connectivity": 1,
      "m04_s14_connectivity": 1,
      "m04_s15_connectivity": 1,
      "m05_s00_connectivity": 1,
      "m05_s01_connectivity": 1,
      "m05_s02_connectivity": 1,
      "m05_s03_connectivity": 1,
      "m05_s04_connectivity": 1,
      "m05_s05_connectivity": 1,
      "m05_s06_connectivity": 1,
      "m05_s07_connectivity": 1,
      "m05_s08_connectivity": 1,
      "m05_s09_connectivity": 1,
      "m05_s10_connectivity": 1,
      "m05_s11_connectivity": 1,
      "m05_s12_connectivity": 1,
      "m05_s13_connectivity": 1,
      "m05_s14_connectivity": 1,
      "m05_s15_connectivity": 1,
      "m06_s00_connectivity": 1,
      "m06_s01_connectivity": 1,
      "m06_s02_connectivity": 1,
      "m06_s03_connectivity": 1,
      "m06_s04_connectivity": 1,
      "m06_s05_connectivity": 1,
      "m06_s06_connectivity": 1,
      "m06_s07_connectivity": 1,
      "m06_s08_connectivity": 1,
      "m06_s09_connectivity": 1,
      "m06_s10_connectivity": 1,
      "m06_s11_connectivity": 1,
      "m06_s12_connectivity": 1,
      "m06_s13_connectivity": 1,
      "m06_s14_connectivity": 1,
      "m06_s15_connectivity": 1,
      "m07_s00_connectivity": 1,
      "m07_s01_connectivity": 1,
      "m07_s02_connectivity": 1,
      "m07_s03_connectivity": 1,
      "m07_s04_connectivity": 1,
      "m07_s05_connectivity": 1,
      "m07_s06_connectivity": 1,
      "m07_s07_connectivity": 1,
      "m07_s08_connectivity": 1,
      "m07_s09_connectivity": 1,
      "m07_s10_connectivity": 1,
      "m07_s11_connectivity": 1,
      "m07_s12_connectivity": 1,
      "m07_s13_connectivity": 1,
      "m07_s14_connectivity": 1,
      "m07_s15_connectivity": 1,
      "m08_s00_connectivity": 1,
      "m08_s01_connectivity": 1,
      "m08_s02_connectivity": 1,
      "m08_s03_connectivity": 1,
      "m08_s04_connectivity": 1,
      "m08_s05_connectivity": 1,
      "m08_s06_connectivity": 1,
      "m08_s07_connectivity": 1,
      "m08_s08_connectivity": 1,
      "m08_s09_connectivity": 1,
      "m08_s10_connectivity": 1,
      "m08_s11_connectivity": 1,
      "m08_s12_connectivity": 1,
      "m08_s13_connectivity": 1,
      "m08_s14_connectivity": 1,
      "m08_s15_connectivity": 1,
      "m09_s00_connectivity": 1,
      "m09_s01_connectivity": 1,
      "m09_s02_connectivity": 1,
      "m09_s03_connectivity": 1,
      "m09_s04_connectivity": 1,
      "m09_s05_connectivity": 1,
      "m09_s06_connectivity": 1,
      "m09_s07_connectivity": 1,
      "m09_s08_connectivity": 1,
      "m09_s09_connectivity": 1,
      "m09_s10_connectivity": 1,
      "m09_s11_connectivity": 1,
      "m09_s12_connectivity": 1,
      "m09_s13_connectivity": 1,
      "m09_s14_connectivity": 1,
      "m09_s15_connectivity": 1,
      "m10_s00_connectivity": 1,
      "m10_s01_connectivity": 1,
      "m10_s02_connectivity": 1,
      "m10_s03_connectivity": 1,
      "m10_s04_connectivity": 1,
      "m10_s05_connectivity": 1,
      "m10_s06_connectivity": 1,
      "m10_s07_connectivity": 1,
      "m10_s08_connectivity": 1,
      "m10_s09_connectivity": 1,
      "m10_s10_connectivity": 1,
      "m10_s11_connectivity": 1,
      "m10_s12_connectivity": 1,
      "m10_s13_connectivity": 1,
      "m10_s14_connectivity": 1,
      "m10_s15_connectivity": 1,
      "m11_s00_connectivity": 1,
      "m11_s01_connectivity": 1,
      "m11_s02_connectivity": 1,
      "m11_s03_connectivity": 1,
      "m11_s04_connectivity": 1,
      "m11_s05_connectivity": 1,
      "m11_s06_connectivity": 1,
      "m11_s07_connectivity": 1,
      "m11_s08_connectivity": 1,
      "m11_s09_connectivity": 1,
      "m11_s10_connectivity": 1,
      "m11_s11_connectivity": 1,
      "m11_s12_connectivity": 1,
      "m11_s13_connectivity": 1,
      "m11_s14_connectivity": 1,
      "m11_s15_connectivity": 1,
      "m12_s00_connectivity": 1,
      "m12_s01_connectivity": 1,
      "m12_s02_connectivity": 1,
      "m12_s03_connectivity": 1,
      "m12_s04_connectivity": 1,
      "m12_s05_connectivity": 1,
      "m12_s06_connectivity": 1,
      "m12_s07_connectivity": 1,
      "m12_s08_connectivity": 1,
      "m12_s09_connectivity": 1,
      "m12_s10_connectivity": 1,
      "m12_s11_connectivity": 1,
      "m12_s12_connectivity": 1,
      "m12_s13_connectivity": 1,
      "m12_s14_connectivity": 1,
      "m12_s15_connectivity": 1,
      "m13_s00_connectivity": 1,
      "m13_s01_connectivity": 1,
      "m13_s02_connectivity": 1,
      "m13_s03_connectivity": 1,
      "m13_s04_connectivity": 1,
      "m13_s05_connectivity": 1,
      "m13_s06_connectivity": 1,
      "m13_s07_connectivity": 1,
      "m13_s08_connectivity": 1,
      "m13_s09_connectivity": 1,
      "m13_s10_connectivity": 1,
      "m13_s11_connectivity": 1,
      "m13_s12_connectivity": 1,
      "m13_s13_connectivity": 1,
      "m13_s14_connectivity": 1,
      "m13_s15_connectivity": 1,
      "m14_s00_connectivity": 1,
      "m14_s01_connectivity": 1,
      "m14_s02_connectivity": 1,
      "m14_s03_connectivity": 1,
      "m14_s04_connectivity": 1,
      "m14_s05_connectivity": 1,
      "m14_s06_connectivity": 1,
      "m14_s07_connectivity": 1,
      "m14_s08_connectivity": 1,
      "m14_s09_connectivity": 1,
      "m14_s10_connectivity": 1,
      "m14_s11_connectivity": 1,
      "m14_s12_connectivity": 1,
      "m14_s13_connectivity": 1,
      "m14_s14_connectivity": 1,
      "m14_s15_connectivity": 1,
      "m15_s00_connectivity": 1,
      "m15_s01_connectivity": 1,
      "m15_s02_connectivity": 1,
      "m15_s03_connectivity": 1,
      "m15_s04_connectivity": 1,
      "m15_s05_connectivity": 1,
      "m15_s06_connectivity": 1,
      "m15_s07_connectivity": 1,
      "m15_s08_connectivity": 1,
      "m15_s09_connectivity": 1,
      "m15_s10_connectivity": 1,
      "m15_s11_connectivity": 1,
      "m15_s12_connectivity": 1,
      "m15_s13_connectivity": 1,
      "m15_s14_connectivity": 1,
      "m15_s15_connectivity": 1,
      "component_name": "design_1_axis_switch_0_0",
      "edk_iptype": "PERIPHERAL",
      "c_baseaddr": 1024,
      "c_highaddr": 2047
    },
    "ports": [
      {
        "role": "target",
        "target": "axi_dma_0:MM2S",
        "name": "S00_AXIS"
      },
      {
        "role": "initiator",
        "target": "axi_dma_0:S2MM",
        "name": "M00_AXIS"
      },
      {
        "role": "initiator",
        "target": "axis_switch_0:S01_AXIS",
        "name": "S01_AXIS"
      },
      {
        "role": "target",
        "target": "axis_switch_0:S01_AXIS",
        "name": "S01_AXIS"
      },
      {
        "role": "target",
        "target": "axis_switch_0:M01_AXIS",
        "name": "S01_AXIS"
      },
      {
        "role": "initiator",
        "target": "axis_switch_0:S01_AXIS",
        "name": "M01_AXIS"
      }
    ],
    "num_ports": 2
  },
  "xdma_0": {
    "vlnv": "xilinx.com:ip:xdma:4.1",
    "parameters": {
      "component_name": "design_1_xdma_0_1",
      "pl_upstream_facing": "true",
      "tl_legacy_mode_enable": "false",
      "pcie_blk_locn": "PCIE4C_X1Y0",
      "pl_link_cap_max_link_width": "X1",
      "pl_link_cap_max_link_speed": "16.0_GT/s",
      "ref_clk_freq": "100_MHz",
      "drp_clk_sel": "Internal",
      "free_run_freq": "100_MHz",
      "axi_addr_width": 32,
      "axi_data_width": "64_bit",
      "core_clk_freq": 1,
      "pll_type": 1,
      "user_clk_freq": 2,
      "silicon_rev": "Pre-Production",
      "pipe_sim": "false",
      "vdm_en": "true",
      "ext_ch_gt_drp": "false",
      "pcie3_drp": "false",
      "dedicate_perst": "false",
      "sys_reset_polarity": "ACTIVE_LOW",
      "mcap_enablement": "None",
      "ext_startup_primitive": "false",
      "pf0_vendor_id": 4334,
      "pf0_device_id": 9041,
      "pf0_revision_id": 0,
      "pf0_subsystem_vendor_id": "10EE",
      "pf0_subsystem_id": "0007",
      "pf0_class_code": "058000",
      "pf1_vendor_id": "10EE",
      "pf1_device_id": 1041,
      "pf1_revision_id": 0,
      "pf1_subsystem_vendor_id": 4334,
      "pf1_subsystem_id": 7,
      "pf1_class_code": "070001",
      "pf2_device_id": 1040,
      "pf2_revision_id": 0,
      "pf2_subsystem_id": 7,
      "pf3_device_id": 1039,
      "pf3_revision_id": 0,
      "pf3_subsystem_id": 7,
      "axilite_master_aperture_size": 13,
      "axilite_master_control": 0,
      "xdma_aperture_size": 9,
      "xdma_control": 4,
      "axist_bypass_aperture_size": 13,
      "axist_bypass_control": 0,
      "pf0_interrupt_pin": "INTA",
      "pf0_msi_cap_multimsgcap": "1_vector",
      "c_comp_timeout": 1,
      "c_timeout0_sel": 14,
      "c_timeout1_sel": 15,
      "c_timeout_mult": 3,
      "c_old_bridge_timeout": 0,
      "shared_logic": 1,
      "shared_logic_clk": "false",
      "shared_logic_both": "false",
      "shared_logic_gtc": "false",
      "shared_logic_gtc_7xg2": "false",
      "shared_logic_clk_7xg2": "false",
      "shared_logic_both_7xg2": "false",
      "en_transceiver_status_ports": "false",
      "is_board_project": 1,
      "en_gt_selection": "false",
      "select_quad": "GTY_Quad_227",
      "ultrascale": "FALSE",
      "ultrascale_plus": "TRUE",
      "versal": "false",
      "v7_gen3": "FALSE",
      "msi_enabled": "TRUE",
      "dev_port_type": 0,
      "xdma_axi_intf_mm": "AXI_Memory_Mapped",
      "xdma_pcie_64bit_en": "false",
      "xdma_axilite_master": "FALSE",
      "xdma_axist_bypass": "FALSE",
      "xdma_rnum_chnl": 1,
      "xdma_wnum_chnl": 1,
      "xdma_axilite_slave": "true",
      "xdma_num_usr_irq": 5,
      "xdma_rnum_rids": 32,
      "xdma_wnum_rids": 16,
      "c_m_axi_id_width": 4,
      "c_axibar_num": 1,
      "c_family": "virtexuplusHBM",
      "xdma_num_pcie_tag": 256,
      "en_axi_master_if": "true",
      "en_wchnl_0": "TRUE",
      "en_wchnl_1": "FALSE",
      "en_wchnl_2": "FALSE",
      "en_wchnl_3": "FALSE",
      "en_wchnl_4": "FALSE",
      "en_wchnl_5": "FALSE",
      "en_wchnl_6": "FALSE",
      "en_wchnl_7": "FALSE",
      "en_rchnl_0": "TRUE",
      "en_rchnl_1": "FALSE",
      "en_rchnl_2": "FALSE",
      "en_rchnl_3": "FALSE",
      "en_rchnl_4": "FALSE",
      "en_rchnl_5": "FALSE",
      "en_rchnl_6": "FALSE",
      "en_rchnl_7": "FALSE",
      "xdma_dsc_bypass": "false",
      "c_metering_on": 1,
      "rx_detect": "Default",
      "c_ats_enable": "false",
      "c_ats_cap_nextptr": 0,
      "c_pr_cap_nextptr": 0,
      "c_pri_enable": "false",
      "dsc_bypass_rd": 0,
      "dsc_bypass_wr": 0,
      "xdma_sts_ports": "false",
      "msix_enabled": "FALSE",
      "wr_ch0_enabled": "FALSE",
      "wr_ch1_enabled": "FALSE",
      "wr_ch2_enabled": "FALSE",
      "wr_ch3_enabled": "FALSE",
      "rd_ch0_enabled": "FALSE",
      "rd_ch1_enabled": "FALSE",
      "rd_ch2_enabled": "FALSE",
      "rd_ch3_enabled": "FALSE",
      "cfg_mgmt_if": "true",
      "rq_seq_num_ignore": 0,
      "cfg_ext_if": "false",
      "legacy_cfg_ext_if": "false",
      "c_parity_check": 0,
      "c_parity_gen": 0,
      "c_parity_prop": 0,
      "c_ecc_enable": 0,
      "en_debug_ports": "false",
      "vu9p_board": "false",
      "enable_jtag_dbg": "false",
      "enable_ltssm_dbg": "false",
      "enable_ibert": "false",
      "mm_slave_en": 1,
      "dma_en": 0,
      "c_axibar_0": 0,
      "c_axibar_1": 0,
      "c_axibar_2": 0,
      "c_axibar_3": 0,
      "c_axibar_4": 0,
      "c_axibar_5": 0,
      "c_axibar_highaddr_0": 4294967295,
      "c_axibar_highaddr_1": 0,
      "c_axibar_highaddr_2": 0,
      "c_axibar_highaddr_3": 0,
      "c_axibar_highaddr_4": 0,
      "c_axibar_highaddr_5": 0,
      "c_axibar2pciebar_0": 0,
      "c_axibar2pciebar_1": 0,
      "c_axibar2pciebar_2": 0,
      "c_axibar2pciebar_3": 0,
      "c_axibar2pciebar_4": 0,
      "c_axibar2pciebar_5": 0,
      "en_axi_slave_if": "true",
      "c_include_baroffset_reg": 1,
      "c_s_axi_id_width": 2,
      "c_s_axi_num_read": 8,
      "c_m_axi_num_read": 8,
      "c_m_axi_num_readq": 2,
      "c_s_axi_num_write": 8,
      "c_m_axi_num_write": 8,
      "c_m_axi_num_write_scale": 1,
      "msix_impl_ext": "FALSE",
      "axi_aclk_loopback": "false",
      "pf0_bar0_aperture_size": 13,
      "pf0_bar0_control": 4,
      "pf0_bar1_aperture_size": 5,
      "pf0_bar1_control": 0,
      "pf0_bar2_aperture_size": 5,
      "pf0_bar2_control": 0,
      "pf0_bar3_aperture_size": 5,
      "pf0_bar3_control": 0,
      "pf0_bar4_aperture_size": 5,
      "pf0_bar4_control": 0,
      "pf0_bar5_aperture_size": 5,
      "pf0_bar5_control": 0,
      "pf0_expansion_rom_aperture_size": 0,
      "pf0_expansion_rom_enable": "FALSE",
      "pciebar_num": 1,
      "c_pciebar2axibar_0": 0,
      "c_pciebar2axibar_1": 0,
      "c_pciebar2axibar_2": 0,
      "c_pciebar2axibar_3": 0,
      "c_pciebar2axibar_4": 0,
      "c_pciebar2axibar_5": 0,
      "c_pciebar2axibar_6": 0,
      "barlite1": 0,
      "barlite2": 7,
      "vcu118_board": "false",
      "enable_error_injection": "false",
      "split_dma": "false",
      "use_standard_interfaces": "false",
      "dma_2rp": "false",
      "sriov_active_vfs": 252,
      "pipe_line_stage": 2,
      "axis_pipe_line_stage": 0,
      "mult_pf_des": "false",
      "pf_swap": "false",
      "pf0_msix_tar_id": 8,
      "pf1_msix_tar_id": 9,
      "runbit_fix": "false",
      "usrint_expn": "false",
      "xlnx_ref_board": "AU55C",
      "gtwiz_in_core": 1,
      "gtcom_in_core": 2,
      "ins_loss_profile": "Add-in_Card",
      "func_mode": 0,
      "pf1_enabled": 0,
      "dma_reset_source_sel": "User_Reset",
      "pf1_bar0_aperture_size": 18,
      "pf1_bar0_control": 4,
      "pf1_bar1_aperture_size": 10,
      "pf1_bar1_control": 4,
      "pf1_bar2_aperture_size": 10,
      "pf1_bar2_control": 6,
      "pf1_bar3_aperture_size": 10,
      "pf1_bar3_control": 0,
      "pf1_bar4_aperture_size": 10,
      "pf1_bar4_control": 6,
      "pf1_bar5_aperture_size": 10,
      "pf1_bar5_control": 0,
      "pf1_expansion_rom_aperture_size": 0,
      "pf1_expansion_rom_enable": "FALSE",
      "pf1_pciebar2axibar_0": 0,
      "pf1_pciebar2axibar_1": 0,
      "pf1_pciebar2axibar_2": 0,
      "pf1_pciebar2axibar_3": 0,
      "pf1_pciebar2axibar_4": 0,
      "pf1_pciebar2axibar_5": 0,
      "pf1_pciebar2axibar_6": 0,
      "c_msix_int_table_en": 0,
      "vu9p_tul_ex": "false",
      "pcie_blk_type": 1,
      "ccix_enable": "FALSE",
      "ccix_dvsec": "FALSE",
      "ext_sys_clk_bufg": "false",
      "c_num_of_sc": 1,
      "usr_irq_exdes": "false",
      "axi_vip_in_exdes": "false",
      "pipe_debug_en": "FALSE",
      "xdma_non_incremental_exdes": "false",
      "xdma_st_infinite_desc_exdes": "false",
      "ext_xvc_vsec_enable": "false",
      "acs_ext_cap_enable": "false",
      "en_pcie_debug_ports": "FALSE",
      "multq_en": 0,
      "dma_mm": 0,
      "dma_st": 0,
      "c_pcie_pfs_supported": 0,
      "c_sriov_en": 0,
      "barlite_ext_pf0": 0,
      "barlite_ext_pf1": 0,
      "barlite_ext_pf2": 0,
      "barlite_ext_pf3": 0,
      "barlite_int_pf0": 0,
      "barlite_int_pf1": 0,
      "barlite_int_pf2": 0,
      "barlite_int_pf3": 0,
      "num_vfs_pf0": 0,
      "num_vfs_pf1": 0,
      "num_vfs_pf2": 0,
      "num_vfs_pf3": 0,
      "firstvf_offset_pf0": 0,
      "firstvf_offset_pf1": 0,
      "firstvf_offset_pf2": 0,
      "firstvf_offset_pf3": 0,
      "vf_barlite_ext_pf0": 0,
      "vf_barlite_ext_pf1": 0,
      "vf_barlite_ext_pf2": 0,
      "vf_barlite_ext_pf3": 0,
      "vf_barlite_int_pf0": 1,
      "vf_barlite_int_pf1": 1,
      "vf_barlite_int_pf2": 1,
      "vf_barlite_int_pf3": 1,
      "c_c2h_num_chnl": 1,
      "c_h2c_num_chnl": 1,
      "h2c_xdma_chnl": 15,
      "c2h_xdma_chnl": 15,
      "axisten_if_enable_msg_route": "27FFF",
      "enable_more": "FALSE",
      "disable_bram_pipeline": "false",
      "disable_eq_synchronizer": "false",
      "c_enable_resource_reduction": "FALSE",
      "gen4_eieos_0s7": "true",
      "c_s_axi_supports_narrow_burst": "false",
      "enable_ats_switch": "FALSE",
      "c_ats_switch_unique_bdf": 1,
      "bridge_burst": "true",
      "cfg_space_enable": "false",
      "c_last_core_cap_addr": 256,
      "c_vsec_cap_addr": 296,
      "soft_reset_en": "false",
      "interrupt_out_width": 1,
      "c_msi_rx_pin_en": 0,
      "c_msix_rx_pin_en": 1,
      "c_intx_rx_pin_en": 1,
      "msix_rx_decode_en": "FALSE",
      "pcie_id_if": "FALSE",
      "tl_pf_enable_reg": 1,
      "axsize_byte_access_en": "false",
      "split_dma_single_pf": "false",
      "rbar_enable": "false",
      "c_smmu_en": 0,
      "c_m_axi_awuser_width": 8,
      "c_m_axi_aruser_width": 8,
      "c_slave_read_64os_en": 0,
      "flr_enable": "false",
      "shell_bridge": "false",
      "msix_pcie_internal": "false",
      "versal_part_type": "S80",
      "functional_mode": "AXI_Bridge",
      "mode_selection": "Basic",
      "device_port_type": "PCI_Express_Endpoint_device",
      "axisten_freq": 250,
      "en_ext_ch_gt_drp": "false",
      "en_pcie_drp": "false",
      "mcap_fpga_bitstream_version": 0,
      "enable_code": 0,
      "vendor_id": "10EE",
      "pf0_use_class_code_lookup_assistant": "false",
      "pf0_base_class_menu": "Memory_controller",
      "pf0_class_code_base": "05",
      "pf0_sub_class_interface_menu": "Other_memory_controller",
      "pf0_class_code_sub": 80,
      "pf0_class_code_interface": 0,
      "axilite_master_en": "false",
      "axilite_master_size": 1,
      "axilite_master_scale": "Megabytes",
      "xdma_en": "true",
      "xdma_size": 64,
      "xdma_scale": "Kilobytes",
      "axist_bypass_en": "false",
      "axist_bypass_size": 1,
      "axist_bypass_scale": "Megabytes",
      "pciebar2axibar_axil_master": 0,
      "pciebar2axibar_xdma": 0,
      "pciebar2axibar_axist_bypass": 0,
      "pf0_msi_enabled": "true",
      "comp_timeout": "50ms",
      "timeout0_sel": 14,
      "timeout1_sel": 15,
      "timeout_mult": 3,
      "old_bridge_timeout": "false",
      "sys_rst_n_board_interface": "pcie_perstn",
      "pcie_board_interface": "Custom",
      "rx_ppm_offset": 0,
      "rx_ssc_ppm": 0,
      "ins_loss_nyq": 15,
      "phy_lp_txpreset": 4,
      "coreclk_freq": 250,
      "plltype": "QPLL0",
      "performance": "false",
      "pcie_extended_tag": "true",
      "pf0_link_status_slot_clock_config": "true",
      "pf0_msix_enabled": "false",
      "pf0_msix_cap_table_size": 0,
      "pf0_msix_cap_table_offset": 0,
      "pf0_msix_cap_table_bir": "BAR_0",
      "pf0_msix_cap_pba_offset": 0,
      "pf0_msix_cap_pba_bir": "BAR_0",
      "pf1_msix_enabled": "false",
      "pf1_msix_cap_table_size": "01F",
      "pf1_msix_cap_table_offset": "00009000",
      "pf1_msix_cap_table_bir": "BAR_0",
      "pf1_msix_cap_pba_offset": "00009FE0",
      "pf1_msix_cap_pba_bir": "BAR_0",
      "axil_master_64bit_en": "false",
      "axi_bypass_64bit_en": "false",
      "axil_master_prefetchable": "false",
      "xdma_pcie_prefetchable": "false",
      "axi_bypass_prefetchable": "false",
      "parity_settings": "None",
      "ecc_en": "false",
      "axi_id_width": 4,
      "type1_membase_memlimit_enable": "Disabled",
      "type1_prefetchable_membase_memlimit": "Disabled",
      "axibar_num": 1,
      "axibar_1": 0,
      "axibar_2": 0,
      "axibar_3": 0,
      "axibar_4": 0,
      "axibar_5": 0,
      "axibar_highaddr_1": 0,
      "axibar_highaddr_2": 0,
      "axibar_highaddr_3": 0,
      "axibar_highaddr_4": 0,
      "axibar_highaddr_5": 0,
      "axibar2pciebar_0": 0,
      "axibar2pciebar_1": 0,
      "axibar2pciebar_2": 0,
      "axibar2pciebar_3": 0,
      "axibar2pciebar_4": 0,
      "axibar2pciebar_5": 0,
      "include_baroffset_reg": "true",
      "baseaddr": 268435455,
      "highaddr": 0,
      "s_axi_id_width": 2,
      "pf0_msix_impl_locn": "Internal",
      "pf0_bar0_enabled": "true",
      "pf0_bar0_type": "Memory",
      "pf0_bar0_size": 1,
      "pf0_bar0_scale": "Megabytes",
      "pf0_bar0_64bit": "false",
      "pf0_bar0_prefetchable": "false",
      "pf0_bar1_enabled": "false",
      "pf0_bar1_type": "Memory",
      "pf0_bar1_size": 4,
      "pf0_bar1_scale": "Kilobytes",
      "pf0_bar1_64bit": "false",
      "pf0_bar1_prefetchable": "false",
      "pf0_bar2_enabled": "false",
      "pf0_bar2_type": "Memory",
      "pf0_bar2_size": 4,
      "pf0_bar2_scale": "Kilobytes",
      "pf0_bar2_64bit": "false",
      "pf0_bar2_prefetchable": "false",
      "pf0_bar3_enabled": "false",
      "pf0_bar3_type": "Memory",
      "pf0_bar3_size": 4,
      "pf0_bar3_scale": "Kilobytes",
      "pf0_bar3_64bit": "false",
      "pf0_bar3_prefetchable": "false",
      "pf0_bar4_enabled": "false",
      "pf0_bar4_type": "Memory",
      "pf0_bar4_size": 4,
      "pf0_bar4_scale": "Kilobytes",
      "pf0_bar4_64bit": "false",
      "pf0_bar4_prefetchable": "false",
      "pf0_bar5_enabled": "false",
      "pf0_bar5_type": "Memory",
      "pf0_bar5_size": 4,
      "pf0_bar5_scale": "Kilobytes",
      "pf0_bar5_64bit": "false",
      "pf0_bar5_prefetchable": "false",
      "pciebar2axibar_0": 0,
      "pciebar2axibar_1": 0,
      "pciebar2axibar_2": 0,
      "pciebar2axibar_3": 0,
      "pciebar2axibar_4": 0,
      "pciebar2axibar_5": 0,
      "pciebar2axibar_6": 0,
      "bar_indicator": "BAR_0",
      "bar0_indicator": 1,
      "bar1_indicator": 0,
      "bar2_indicator": 0,
      "bar3_indicator": 0,
      "bar4_indicator": 0,
      "bar5_indicator": 0,
      "en_dbg_descramble": "false",
      "pf1_use_class_code_lookup_assistant": "false",
      "pf1_base_class_menu": "Simple_communication_controllers",
      "pf1_class_code_base": "07",
      "pf1_class_code_sub": 0,
      "pf1_sub_class_interface_menu": "16450_compatible_serial_controller",
      "pf1_class_code_interface": "01",
      "pf1_interrupt_pin": "NONE",
      "pf1_msi_enabled": "false",
      "pf1_msi_cap_multimsgcap": "1_vector",
      "pf1_bar0_enabled": "true",
      "pf1_bar0_type": "Memory",
      "pf1_bar0_size": 32,
      "pf1_bar0_scale": "Megabytes",
      "pf1_bar0_64bit": "false",
      "pf1_bar0_prefetchable": "false",
      "pf1_bar1_enabled": "true",
      "pf1_bar1_type": "Memory",
      "pf1_bar1_size": 128,
      "pf1_bar1_scale": "Kilobytes",
      "pf1_bar1_64bit": "false",
      "pf1_bar1_prefetchable": "false",
      "pf1_bar2_enabled": "true",
      "pf1_bar2_type": "Memory",
      "pf1_bar2_size": 128,
      "pf1_bar2_scale": "Kilobytes",
      "pf1_bar2_64bit": "true",
      "pf1_bar2_prefetchable": "false",
      "pf1_bar3_enabled": "false",
      "pf1_bar3_type": "Memory",
      "pf1_bar3_size": 128,
      "pf1_bar3_scale": "Kilobytes",
      "pf1_bar3_64bit": "false",
      "pf1_bar3_prefetchable": "false",
      "pf1_bar4_enabled": "true",
      "pf1_bar4_type": "Memory",
      "pf1_bar4_size": 128,
      "pf1_bar4_scale": "Kilobytes",
      "pf1_bar4_64bit": "true",
      "pf1_bar4_prefetchable": "false",
      "pf1_bar5_enabled": "false",
      "pf1_bar5_type": "Memory",
      "pf1_bar5_size": 128,
      "pf1_bar5_scale": "Kilobytes",
      "pf1_bar5_prefetchable": "false",
      "pf2_class_code": "058000",
      "pf2_subsystem_vendor_id": "10EE",
      "pf2_use_class_code_lookup_assistant": "false",
      "pf2_base_class_menu": "Memory_controller",
      "pf2_class_code_base": "05",
      "pf2_class_code_sub": 80,
      "pf2_sub_class_interface_menu": "Other_memory_controller",
      "pf2_class_code_interface": 0,
      "pf2_interrupt_pin": "NONE",
      "pf2_msi_enabled": "false",
      "pf2_msi_cap_multimsgcap": "1_vector",
      "pf2_bar0_enabled": "true",
      "pf2_bar0_type": "Memory",
      "pf2_bar0_size": 128,
      "pf2_bar0_scale": "Kilobytes",
      "pf2_bar0_64bit": "false",
      "pf2_bar0_prefetchable": "false",
      "pf2_bar1_enabled": "true",
      "pf2_bar1_type": "Memory",
      "pf2_bar1_size": 128,
      "pf2_bar1_scale": "Kilobytes",
      "pf2_bar1_64bit": "false",
      "pf2_bar1_prefetchable": "false",
      "pf2_bar2_enabled": "true",
      "pf2_bar2_type": "Memory",
      "pf2_bar2_size": 128,
      "pf2_bar2_scale": "Kilobytes",
      "pf2_bar2_64bit": "false",
      "pf2_bar2_prefetchable": "false",
      "pf2_bar3_enabled": "true",
      "pf2_bar3_type": "Memory",
      "pf2_bar3_size": 128,
      "pf2_bar3_scale": "Kilobytes",
      "pf2_bar3_64bit": "false",
      "pf2_bar3_prefetchable": "false",
      "pf2_bar4_enabled": "true",
      "pf2_bar4_type": "Memory",
      "pf2_bar4_size": 128,
      "pf2_bar4_scale": "Kilobytes",
      "pf2_bar4_64bit": "false",
      "pf2_bar4_prefetchable": "false",
      "pf2_bar5_enabled": "true",
      "pf2_bar5_type": "Memory",
      "pf2_bar5_size": 128,
      "pf2_bar5_scale": "Kilobytes",
      "pf2_bar5_prefetchable": "false",
      "pf3_class_code": "058000",
      "pf3_subsystem_vendor_id": "10EE",
      "pf3_use_class_code_lookup_assistant": "false",
      "pf3_base_class_menu": "Memory_controller",
      "pf3_class_code_base": "05",
      "pf3_class_code_sub": 80,
      "pf3_sub_class_interface_menu": "Other_memory_controller",
      "pf3_class_code_interface": 0,
      "pf3_interrupt_pin": "NONE",
      "pf3_msi_enabled": "false",
      "pf3_msi_cap_multimsgcap": "1_vector",
      "pf3_bar0_enabled": "true",
      "pf3_bar0_type": "Memory",
      "pf3_bar0_size": 128,
      "pf3_bar0_scale": "Kilobytes",
      "pf3_bar0_64bit": "false",
      "pf3_bar0_prefetchable": "false",
      "pf3_bar1_enabled": "true",
      "pf3_bar1_type": "Memory",
      "pf3_bar1_size": 128,
      "pf3_bar1_scale": "Kilobytes",
      "pf3_bar1_64bit": "false",
      "pf3_bar1_prefetchable": "false",
      "pf3_bar2_enabled": "true",
      "pf3_bar2_type": "Memory",
      "pf3_bar2_size": 128,
      "pf3_bar2_scale": "Kilobytes",
      "pf3_bar2_64bit": "false",
      "pf3_bar2_prefetchable": "false",
      "pf3_bar3_enabled": "true",
      "pf3_bar3_type": "Memory",
      "pf3_bar3_size": 128,
      "pf3_bar3_scale": "Kilobytes",
      "pf3_bar3_64bit": "false",
      "pf3_bar3_prefetchable": "false",
      "pf3_bar4_enabled": "true",
      "pf3_bar4_type": "Memory",
      "pf3_bar4_size": 128,
      "pf3_bar4_scale": "Kilobytes",
      "pf3_bar4_64bit": "false",
      "pf3_bar4_prefetchable": "false",
      "pf3_bar5_enabled": "true",
      "pf3_bar5_type": "Memory",
      "pf3_bar5_size": 128,
      "pf3_bar5_scale": "Kilobytes",
      "pf3_bar5_prefetchable": "false",
      "prog_usr_irq_vec_map": "false",
      "rcfg_nph_fix_en": "false",
      "post_synth_sim_en": "false",
      "user_pf_two_axilite_bar_en": "false",
      "two_bypass_bar": "false",
      "en_l23_entry": "false",
      "pf2_pciebar2axibar_0": 0,
      "pf2_pciebar2axibar_1": 0,
      "pf2_pciebar2axibar_2": 0,
      "pf2_pciebar2axibar_3": 0,
      "pf2_pciebar2axibar_4": 0,
      "pf2_pciebar2axibar_5": 0,
      "pf3_pciebar2axibar_0": 0,
      "pf3_pciebar2axibar_1": 0,
      "pf3_pciebar2axibar_2": 0,
      "pf3_pciebar2axibar_3": 0,
      "pf3_pciebar2axibar_4": 0,
      "pf3_pciebar2axibar_5": 0,
      "gtwiz_in_core_us": 1,
      "gtwiz_in_core_usp": 1,
      "en_dma_and_bridge": "false",
      "en_coreclk_es1": "false",
      "vcu1525_ddr_ex": "false",
      "en_bridge": "false",
      "enable_ccix": "FALSE",
      "enable_dvsec": "FALSE",
      "gtcom_in_core_usp": 2,
      "en_mqdma": "false",
      "sriov_cap_enable": "false",
      "pf0_bar0_enabled_mqdma": "true",
      "pf0_bar0_type_mqdma": "DMA",
      "pf0_bar0_64bit_mqdma": "false",
      "pf0_bar0_prefetchable_mqdma": "false",
      "pf0_bar0_scale_mqdma": "Kilobytes",
      "pf0_bar0_size_mqdma": 128,
      "pf0_bar1_enabled_mqdma": "false",
      "pf0_bar1_type_mqdma": "N/A",
      "pf0_bar1_64bit_mqdma": "false",
      "pf0_bar1_prefetchable_mqdma": "false",
      "pf0_bar1_scale_mqdma": "Kilobytes",
      "pf0_bar1_size_mqdma": 128,
      "pf0_bar2_enabled_mqdma": "false",
      "pf0_bar2_type_mqdma": "N/A",
      "pf0_bar2_64bit_mqdma": "false",
      "pf0_bar2_prefetchable_mqdma": "false",
      "pf0_bar2_scale_mqdma": "Kilobytes",
      "pf0_bar2_size_mqdma": 128,
      "pf0_bar3_enabled_mqdma": "false",
      "pf0_bar3_type_mqdma": "N/A",
      "pf0_bar3_64bit_mqdma": "false",
      "pf0_bar3_prefetchable_mqdma": "false",
      "pf0_bar3_scale_mqdma": "Kilobytes",
      "pf0_bar3_size_mqdma": 128,
      "pf0_bar4_enabled_mqdma": "false",
      "pf0_bar4_type_mqdma": "N/A",
      "pf0_bar4_64bit_mqdma": "false",
      "pf0_bar4_prefetchable_mqdma": "false",
      "pf0_bar4_scale_mqdma": "Kilobytes",
      "pf0_bar4_size_mqdma": 128,
      "pf0_bar5_enabled_mqdma": "false",
      "pf0_bar5_type_mqdma": "N/A",
      "pf0_bar5_prefetchable_mqdma": "false",
      "pf0_bar5_scale_mqdma": "Kilobytes",
      "pf0_bar5_size_mqdma": 128,
      "pf1_bar0_enabled_mqdma": "true",
      "pf1_bar0_type_mqdma": "DMA",
      "pf1_bar0_64bit_mqdma": "false",
      "pf1_bar0_prefetchable_mqdma": "false",
      "pf1_bar0_scale_mqdma": "Kilobytes",
      "pf1_bar0_size_mqdma": 128,
      "pf1_bar1_enabled_mqdma": "false",
      "pf1_bar1_type_mqdma": "N/A",
      "pf1_bar1_64bit_mqdma": "false",
      "pf1_bar1_prefetchable_mqdma": "false",
      "pf1_bar1_scale_mqdma": "Kilobytes",
      "pf1_bar1_size_mqdma": 128,
      "pf1_bar2_enabled_mqdma": "false",
      "pf1_bar2_type_mqdma": "N/A",
      "pf1_bar2_64bit_mqdma": "false",
      "pf1_bar2_prefetchable_mqdma": "false",
      "pf1_bar2_scale_mqdma": "Kilobytes",
      "pf1_bar2_size_mqdma": 128,
      "pf1_bar3_enabled_mqdma": "false",
      "pf1_bar3_type_mqdma": "N/A",
      "pf1_bar3_64bit_mqdma": "false",
      "pf1_bar3_prefetchable_mqdma": "false",
      "pf1_bar3_scale_mqdma": "Kilobytes",
      "pf1_bar3_size_mqdma": 128,
      "pf1_bar4_enabled_mqdma": "false",
      "pf1_bar4_type_mqdma": "N/A",
      "pf1_bar4_64bit_mqdma": "false",
      "pf1_bar4_prefetchable_mqdma": "false",
      "pf1_bar4_scale_mqdma": "Kilobytes",
      "pf1_bar4_size_mqdma": 128,
      "pf1_bar5_enabled_mqdma": "false",
      "pf1_bar5_type_mqdma": "N/A",
      "pf1_bar5_prefetchable_mqdma": "false",
      "pf1_bar5_scale_mqdma": "Kilobytes",
      "pf1_bar5_size_mqdma": 128,
      "pf2_bar0_enabled_mqdma": "true",
      "pf2_bar0_type_mqdma": "DMA",
      "pf2_bar0_64bit_mqdma": "false",
      "pf2_bar0_prefetchable_mqdma": "false",
      "pf2_bar0_scale_mqdma": "Kilobytes",
      "pf2_bar0_size_mqdma": 128,
      "pf2_bar1_enabled_mqdma": "false",
      "pf2_bar1_type_mqdma": "N/A",
      "pf2_bar1_64bit_mqdma": "false",
      "pf2_bar1_prefetchable_mqdma": "false",
      "pf2_bar1_scale_mqdma": "Kilobytes",
      "pf2_bar1_size_mqdma": 128,
      "pf2_bar2_enabled_mqdma": "false",
      "pf2_bar2_type_mqdma": "N/A",
      "pf2_bar2_64bit_mqdma": "false",
      "pf2_bar2_prefetchable_mqdma": "false",
      "pf2_bar2_scale_mqdma": "Kilobytes",
      "pf2_bar2_size_mqdma": 128,
      "pf2_bar3_enabled_mqdma": "false",
      "pf2_bar3_type_mqdma": "N/A",
      "pf2_bar3_64bit_mqdma": "false",
      "pf2_bar3_prefetchable_mqdma": "false",
      "pf2_bar3_scale_mqdma": "Kilobytes",
      "pf2_bar3_size_mqdma": 128,
      "pf2_bar4_enabled_mqdma": "false",
      "pf2_bar4_type_mqdma": "N/A",
      "pf2_bar4_64bit_mqdma": "false",
      "pf2_bar4_prefetchable_mqdma": "false",
      "pf2_bar4_scale_mqdma": "Kilobytes",
      "pf2_bar4_size_mqdma": 128,
      "pf2_bar5_enabled_mqdma": "false",
      "pf2_bar5_type_mqdma": "N/A",
      "pf2_bar5_prefetchable_mqdma": "false",
      "pf2_bar5_scale_mqdma": "Kilobytes",
      "pf2_bar5_size_mqdma": 128,
      "pf3_bar0_enabled_mqdma": "true",
      "pf3_bar0_type_mqdma": "DMA",
      "pf3_bar0_64bit_mqdma": "false",
      "pf3_bar0_prefetchable_mqdma": "false",
      "pf3_bar0_scale_mqdma": "Kilobytes",
      "pf3_bar0_size_mqdma": 128,
      "pf3_bar1_enabled_mqdma": "false",
      "pf3_bar1_type_mqdma": "N/A",
      "pf3_bar1_64bit_mqdma": "false",
      "pf3_bar1_prefetchable_mqdma": "false",
      "pf3_bar1_scale_mqdma": "Kilobytes",
      "pf3_bar1_size_mqdma": 128,
      "pf3_bar2_enabled_mqdma": "false",
      "pf3_bar2_type_mqdma": "N/A",
      "pf3_bar2_64bit_mqdma": "false",
      "pf3_bar2_prefetchable_mqdma": "false",
      "pf3_bar2_scale_mqdma": "Kilobytes",
      "pf3_bar2_size_mqdma": 128,
      "pf3_bar3_enabled_mqdma": "false",
      "pf3_bar3_type_mqdma": "N/A",
      "pf3_bar3_64bit_mqdma": "false",
      "pf3_bar3_prefetchable_mqdma": "false",
      "pf3_bar3_scale_mqdma": "Kilobytes",
      "pf3_bar3_size_mqdma": 128,
      "pf3_bar4_enabled_mqdma": "false",
      "pf3_bar4_type_mqdma": "N/A",
      "pf3_bar4_64bit_mqdma": "false",
      "pf3_bar4_prefetchable_mqdma": "false",
      "pf3_bar4_scale_mqdma": "Kilobytes",
      "pf3_bar4_size_mqdma": 128,
      "pf3_bar5_enabled_mqdma": "false",
      "pf3_bar5_type_mqdma": "N/A",
      "pf3_bar5_prefetchable_mqdma": "false",
      "pf3_bar5_scale_mqdma": "Kilobytes",
      "pf3_bar5_size_mqdma": 128,
      "copy_pf0": "false",
      "copy_sriov_pf0": "true",
      "pf0_expansion_rom_enabled": "false",
      "pf0_expansion_rom_type": "N/A",
      "pf0_expansion_rom_scale": "Kilobytes",
      "pf0_expansion_rom_size": 4,
      "pf1_expansion_rom_type": "N/A",
      "pf1_expansion_rom_enabled": "false",
      "pf1_expansion_rom_scale": "Kilobytes",
      "pf1_expansion_rom_size": 4,
      "pf2_expansion_rom_type": "N/A",
      "pf2_expansion_rom_enabled": "false",
      "pf2_expansion_rom_scale": "Kilobytes",
      "pf2_expansion_rom_size": 4,
      "pf3_expansion_rom_type": "N/A",
      "pf3_expansion_rom_enabled": "false",
      "pf3_expansion_rom_scale": "Kilobytes",
      "pf3_expansion_rom_size": 4,
      "pf0_sriov_bar0_enabled": "true",
      "pf0_sriov_bar0_type": "DMA",
      "pf0_sriov_bar0_64bit": "false",
      "pf0_sriov_bar0_prefetchable": "false",
      "pf0_sriov_bar0_size": 2,
      "pf0_sriov_bar0_scale": "Kilobytes",
      "pf0_sriov_bar1_enabled": "false",
      "pf0_sriov_bar1_type": "N/A",
      "pf0_sriov_bar1_64bit": "false",
      "pf0_sriov_bar1_prefetchable": "false",
      "pf0_sriov_bar1_size": 2,
      "pf0_sriov_bar1_scale": "Kilobytes",
      "pf0_sriov_bar2_enabled": "false",
      "pf0_sriov_bar2_type": "N/A",
      "pf0_sriov_bar2_64bit": "false",
      "pf0_sriov_bar2_prefetchable": "false",
      "pf0_sriov_bar2_size": 2,
      "pf0_sriov_bar2_scale": "Kilobytes",
      "pf0_sriov_bar3_enabled": "false",
      "pf0_sriov_bar3_type": "N/A",
      "pf0_sriov_bar3_64bit": "false",
      "pf0_sriov_bar3_prefetchable": "false",
      "pf0_sriov_bar3_size": 2,
      "pf0_sriov_bar3_scale": "Kilobytes",
      "pf0_sriov_bar4_enabled": "false",
      "pf0_sriov_bar4_type": "N/A",
      "pf0_sriov_bar4_64bit": "false",
      "pf0_sriov_bar4_prefetchable": "false",
      "pf0_sriov_bar4_size": 2,
      "pf0_sriov_bar4_scale": "Kilobytes",
      "pf0_sriov_bar5_enabled": "false",
      "pf0_sriov_bar5_type": "N/A",
      "pf0_sriov_bar5_64bit": "false",
      "pf0_sriov_bar5_prefetchable": "false",
      "pf0_sriov_bar5_size": 2,
      "pf0_sriov_bar5_scale": "Kilobytes",
      "pf1_sriov_bar0_enabled": "true",
      "pf1_sriov_bar0_type": "DMA",
      "pf1_sriov_bar0_64bit": "false",
      "pf1_sriov_bar0_prefetchable": "false",
      "pf1_sriov_bar0_size": 2,
      "pf1_sriov_bar0_scale": "Kilobytes",
      "pf1_sriov_bar1_enabled": "false",
      "pf1_sriov_bar1_type": "N/A",
      "pf1_sriov_bar1_64bit": "false",
      "pf1_sriov_bar1_prefetchable": "false",
      "pf1_sriov_bar1_size": 2,
      "pf1_sriov_bar1_scale": "Kilobytes",
      "pf1_sriov_bar2_enabled": "false",
      "pf1_sriov_bar2_type": "N/A",
      "pf1_sriov_bar2_64bit": "false",
      "pf1_sriov_bar2_prefetchable": "false",
      "pf1_sriov_bar2_size": 2,
      "pf1_sriov_bar2_scale": "Kilobytes",
      "pf1_sriov_bar3_enabled": "false",
      "pf1_sriov_bar3_type": "N/A",
      "pf1_sriov_bar3_64bit": "false",
      "pf1_sriov_bar3_prefetchable": "false",
      "pf1_sriov_bar3_size": 2,
      "pf1_sriov_bar3_scale": "Kilobytes",
      "pf1_sriov_bar4_enabled": "false",
      "pf1_sriov_bar4_type": "N/A",
      "pf1_sriov_bar4_64bit": "false",
      "pf1_sriov_bar4_prefetchable": "false",
      "pf1_sriov_bar4_size": 2,
      "pf1_sriov_bar4_scale": "Kilobytes",
      "pf1_sriov_bar5_enabled": "false",
      "pf1_sriov_bar5_type": "N/A",
      "pf1_sriov_bar5_64bit": "false",
      "pf1_sriov_bar5_prefetchable": "false",
      "pf1_sriov_bar5_size": 2,
      "pf1_sriov_bar5_scale": "Kilobytes",
      "pf2_sriov_bar0_enabled": "true",
      "pf2_sriov_bar0_type": "DMA",
      "pf2_sriov_bar0_64bit": "false",
      "pf2_sriov_bar0_prefetchable": "false",
      "pf2_sriov_bar0_size": 2,
      "pf2_sriov_bar0_scale": "Kilobytes",
      "pf2_sriov_bar1_enabled": "false",
      "pf2_sriov_bar1_type": "N/A",
      "pf2_sriov_bar1_64bit": "false",
      "pf2_sriov_bar1_prefetchable": "false",
      "pf2_sriov_bar1_size": 2,
      "pf2_sriov_bar1_scale": "Kilobytes",
      "pf2_sriov_bar2_enabled": "false",
      "pf2_sriov_bar2_type": "N/A",
      "pf2_sriov_bar2_64bit": "false",
      "pf2_sriov_bar2_prefetchable": "false",
      "pf2_sriov_bar2_size": 2,
      "pf2_sriov_bar2_scale": "Kilobytes",
      "pf2_sriov_bar3_enabled": "false",
      "pf2_sriov_bar3_type": "N/A",
      "pf2_sriov_bar3_64bit": "false",
      "pf2_sriov_bar3_prefetchable": "false",
      "pf2_sriov_bar3_size": 2,
      "pf2_sriov_bar3_scale": "Kilobytes",
      "pf2_sriov_bar4_enabled": "false",
      "pf2_sriov_bar4_type": "N/A",
      "pf2_sriov_bar4_64bit": "false",
      "pf2_sriov_bar4_prefetchable": "false",
      "pf2_sriov_bar4_size": 2,
      "pf2_sriov_bar4_scale": "Kilobytes",
      "pf2_sriov_bar5_enabled": "false",
      "pf2_sriov_bar5_type": "N/A",
      "pf2_sriov_bar5_64bit": "false",
      "pf2_sriov_bar5_prefetchable": "false",
      "pf2_sriov_bar5_size": 2,
      "pf2_sriov_bar5_scale": "Kilobytes",
      "pf3_sriov_bar0_enabled": "true",
      "pf3_sriov_bar0_type": "DMA",
      "pf3_sriov_bar0_64bit": "false",
      "pf3_sriov_bar0_prefetchable": "false",
      "pf3_sriov_bar0_size": 2,
      "pf3_sriov_bar0_scale": "Kilobytes",
      "pf3_sriov_bar1_enabled": "false",
      "pf3_sriov_bar1_type": "N/A",
      "pf3_sriov_bar1_64bit": "false",
      "pf3_sriov_bar1_prefetchable": "false",
      "pf3_sriov_bar1_size": 2,
      "pf3_sriov_bar1_scale": "Kilobytes",
      "pf3_sriov_bar2_enabled": "false",
      "pf3_sriov_bar2_type": "N/A",
      "pf3_sriov_bar2_64bit": "false",
      "pf3_sriov_bar2_prefetchable": "false",
      "pf3_sriov_bar2_size": 2,
      "pf3_sriov_bar2_scale": "Kilobytes",
      "pf3_sriov_bar3_enabled": "false",
      "pf3_sriov_bar3_type": "N/A",
      "pf3_sriov_bar3_64bit": "false",
      "pf3_sriov_bar3_prefetchable": "false",
      "pf3_sriov_bar3_size": 2,
      "pf3_sriov_bar3_scale": "Kilobytes",
      "pf3_sriov_bar4_enabled": "false",
      "pf3_sriov_bar4_type": "N/A",
      "pf3_sriov_bar4_64bit": "false",
      "pf3_sriov_bar4_prefetchable": "false",
      "pf3_sriov_bar4_size": 2,
      "pf3_sriov_bar4_scale": "Kilobytes",
      "pf3_sriov_bar5_enabled": "false",
      "pf3_sriov_bar5_type": "N/A",
      "pf3_sriov_bar5_64bit": "false",
      "pf3_sriov_bar5_prefetchable": "false",
      "pf3_sriov_bar5_size": 2,
      "pf3_sriov_bar5_scale": "Kilobytes",
      "pf0_vendor_id_mqdma": "10EE",
      "pf1_vendor_id_mqdma": "10EE",
      "pf2_vendor_id_mqdma": "10EE",
      "pf3_vendor_id_mqdma": "10EE",
      "pf0_device_id_mqdma": 9041,
      "pf1_device_id_mqdma": "0007",
      "pf2_device_id_mqdma": 9241,
      "pf3_device_id_mqdma": 9341,
      "pf0_revision_id_mqdma": 0,
      "pf1_revision_id_mqdma": 0,
      "pf2_revision_id_mqdma": 0,
      "pf3_revision_id_mqdma": 0,
      "pf0_subsystem_vendor_id_mqdma": "10EE",
      "pf1_subsystem_vendor_id_mqdma": "10EE",
      "pf2_subsystem_vendor_id_mqdma": "10EE",
      "pf3_subsystem_vendor_id_mqdma": "10EE",
      "pf0_subsystem_id_mqdma": "0007",
      "pf1_subsystem_id_mqdma": "0007",
      "pf2_subsystem_id_mqdma": "0007",
      "pf3_subsystem_id_mqdma": "0007",
      "pf0_use_class_code_lookup_assistant_mqdma": "false",
      "pf1_use_class_code_lookup_assistant_mqdma": "false",
      "pf2_use_class_code_lookup_assistant_mqdma": "false",
      "pf3_use_class_code_lookup_assistant_mqdma": "false",
      "pf0_base_class_menu_mqdma": "Memory_controller",
      "pf0_class_code_base_mqdma": "05",
      "pf0_class_code_sub_mqdma": 80,
      "pf0_sub_class_interface_menu_mqdma": "Other_memory_controller",
      "pf0_class_code_interface_mqdma": 0,
      "pf0_class_code_mqdma": "058000",
      "pf1_base_class_menu_mqdma": "Memory_controller",
      "pf1_class_code_base_mqdma": "05",
      "pf1_class_code_sub_mqdma": 80,
      "pf1_sub_class_interface_menu_mqdma": "Other_memory_controller",
      "pf1_class_code_interface_mqdma": 0,
      "pf1_class_code_mqdma": "058000",
      "pf2_base_class_menu_mqdma": "Memory_controller",
      "pf2_class_code_base_mqdma": "05",
      "pf2_class_code_sub_mqdma": 80,
      "pf2_sub_class_interface_menu_mqdma": "Other_memory_controller",
      "pf2_class_code_interface_mqdma": 0,
      "pf2_class_code_mqdma": "058000",
      "pf3_base_class_menu_mqdma": "Memory_controller",
      "pf3_class_code_base_mqdma": "05",
      "pf3_class_code_sub_mqdma": 80,
      "pf3_sub_class_interface_menu_mqdma": "Other_memory_controller",
      "pf3_class_code_interface_mqdma": 0,
      "pf3_class_code_mqdma": "058000",
      "sriov_first_vf_offset": 1,
      "pf0_sriov_cap_ver": 1,
      "pf0_sriov_cap_initial_vf": 0,
      "pf0_sriov_func_dep_link": 0,
      "pf0_sriov_first_vf_offset": 0,
      "pf0_sriov_vf_device_id": "A041",
      "pf0_sriov_supported_page_size": "00000553",
      "pf1_sriov_cap_ver": 1,
      "pf1_sriov_cap_initial_vf": 0,
      "pf1_sriov_first_vf_offset": 0,
      "pf1_sriov_func_dep_link": "0001",
      "pf1_sriov_supported_page_size": "00000553",
      "pf1_sriov_vf_device_id": "A141",
      "pf2_sriov_cap_ver": 1,
      "pf2_sriov_cap_initial_vf": 0,
      "pf2_sriov_first_vf_offset": 0,
      "pf2_sriov_func_dep_link": "0002",
      "pf2_sriov_supported_page_size": "00000553",
      "pf2_sriov_vf_device_id": "A241",
      "pf3_sriov_cap_initial_vf": 0,
      "pf3_sriov_cap_ver": 1,
      "pf3_sriov_first_vf_offset": 0,
      "pf3_sriov_func_dep_link": "0003",
      "pf3_sriov_supported_page_size": "00000553",
      "pf3_sriov_vf_device_id": "A341",
      "pf0_ari_enabled": "false",
      "pf0_msix_enabled_mqdma": "false",
      "pf1_msix_enabled_mqdma": "false",
      "pf2_msix_enabled_mqdma": "false",
      "pf3_msix_enabled_mqdma": "false",
      "pf0_msix_cap_table_size_mqdma": 0,
      "pf1_msix_cap_table_size_mqdma": 0,
      "pf2_msix_cap_table_size_mqdma": 0,
      "pf3_msix_cap_table_size_mqdma": 0,
      "pf0_msix_cap_table_offset_mqdma": 0,
      "pf1_msix_cap_table_offset_mqdma": 0,
      "pf2_msix_cap_table_offset_mqdma": 0,
      "pf3_msix_cap_table_offset_mqdma": 0,
      "pf0_msix_cap_table_bir_mqdma": "BAR_0",
      "pf1_msix_cap_table_bir_mqdma": "BAR_0",
      "pf2_msix_cap_table_bir_mqdma": "BAR_0",
      "pf3_msix_cap_table_bir_mqdma": "BAR_0",
      "pf0_msix_cap_pba_offset_mqdma": 0,
      "pf1_msix_cap_pba_offset_mqdma": 0,
      "pf2_msix_cap_pba_offset_mqdma": 0,
      "pf3_msix_cap_pba_offset_mqdma": 0,
      "pf0_msix_cap_pba_bir_mqdma": "BAR_0",
      "pf1_msix_cap_pba_bir_mqdma": "BAR_0",
      "pf2_msix_cap_pba_bir_mqdma": "BAR_0",
      "pf3_msix_cap_pba_bir_mqdma": "BAR_0",
      "msi_x_options": "None",
      "dsc_bypass_rd_out": 0,
      "dsc_bypass_wr_out": 0,
      "num_queues": 1,
      "enable_auto_rxeq": "False",
      "enable_pcie_debug": "False",
      "en_axi_mm_mqdma": "true",
      "en_axi_st_mqdma": "false",
      "enable_more_clk": "false",
      "tl_credits_cd": 15,
      "tl_credits_ch": 15,
      "set_finite_credit": "false",
      "enable_resource_reduction": "false",
      "usplus_es1_seqnum_bypass": "false",
      "bridge_registers_offset_enable": "false",
      "enable_gen4": "true",
      "tandem_enable_rfsoc": "false",
      "local_test": "false",
      "ctrl_skip_mask": "true",
      "pf0_ats_enabled": "false",
      "pf0_pri_enabled": "false",
      "aspm_support": "No_ASPM",
      "pf0_aer_cap_ecrc_gen_and_check_capable": "false",
      "gen_pipe_debug": "false",
      "msi_rx_pin_en": "FALSE",
      "msix_rx_pin_en": "TRUE",
      "intx_rx_pin_en": "true",
      "msix_type": "HARD",
      "enable_lane_reversal": "false",
      "enable_mark_debug": "false",
      "master_cal_only": "false",
      "enable_multi_pcie": "false",
      "pf0_rbar_num": 1,
      "pf1_rbar_num": 1,
      "pf2_rbar_num": 1,
      "pf3_rbar_num": 1,
      "pf0_bar0_index": 0,
      "pf0_bar1_index": 7,
      "pf0_bar2_index": 7,
      "pf0_bar3_index": 7,
      "pf0_bar4_index": 7,
      "pf0_bar5_index": 7,
      "pf1_bar0_index": 0,
      "pf1_bar1_index": 7,
      "pf1_bar2_index": 7,
      "pf1_bar3_index": 7,
      "pf1_bar4_index": 7,
      "pf1_bar5_index": 7,
      "pf2_bar0_index": 0,
      "pf2_bar1_index": 7,
      "pf2_bar2_index": 7,
      "pf2_bar3_index": 7,
      "pf2_bar4_index": 7,
      "pf2_bar5_index": 7,
      "pf3_bar0_index": 0,
      "pf3_bar1_index": 7,
      "pf3_bar2_index": 7,
      "pf3_bar3_index": 7,
      "pf3_bar4_index": 7,
      "pf3_bar5_index": 7,
      "pf0_rbar_cap_bar0": 65520,
      "pf0_rbar_cap_bar1": 0,
      "pf0_rbar_cap_bar2": 0,
      "pf0_rbar_cap_bar3": 0,
      "pf0_rbar_cap_bar4": 0,
      "pf0_rbar_cap_bar5": 0,
      "pf1_rbar_cap_bar0": 65520,
      "pf1_rbar_cap_bar1": 0,
      "pf1_rbar_cap_bar2": 0,
      "pf1_rbar_cap_bar3": 0,
      "pf1_rbar_cap_bar4": 0,
      "pf1_rbar_cap_bar5": 0,
      "pf2_rbar_cap_bar0": 65520,
      "pf2_rbar_cap_bar1": 0,
      "pf2_rbar_cap_bar2": 0,
      "pf2_rbar_cap_bar3": 0,
      "pf2_rbar_cap_bar4": 0,
      "pf2_rbar_cap_bar5": 0,
      "pf3_rbar_cap_bar0": 65520,
      "pf3_rbar_cap_bar1": 0,
      "pf3_rbar_cap_bar2": 0,
      "pf3_rbar_cap_bar3": 0,
      "pf3_rbar_cap_bar4": 0,
      "pf3_rbar_cap_bar5": 0,
      "mpsoc_pl_rp_enable": "false",
      "enable_slave_read_64os": "false",
      "m_axib_num_write_scale": 1,
      "disable_gt_loc": "false",
      "disable_user_clock_root": "true",
      "enable_epyc_chipset_fix": "false",
      "broadcom_sbr_wa": "false",
      "tl_tx_mux_strict_priority": "false",
      "en_slot_cap_reg": "false",
      "slot_cap_reg": "00000040",
      "sim_model": "NO",
      "lane_order": "Bottom",
      "gt_loc_num": "X99Y99",
      "example_design_type": "RTL",
      "performance_exdes": "false",
      "descriptor_bypass_exdes": "false",
      "virtio_exdes": "false",
      "virtio_perf_exdes": "false",
      "insert_cips": "false",
      "en_bridge_slv": "true",
      "edk_iptype": "PERIPHERAL",
      "axibar_0": 0,
      "axibar_highaddr_0": 4294967295
    },
    "memory-view": {
      "M_AXI_B": {
        "axi_dma_0": {
          "Reg": {
            "baseaddr": 0,
            "highaddr": 1023,
            "size": 1024
          }
        },
        "axis_switch_0": {
          "Reg": {
            "baseaddr": 1024,
            "highaddr": 2047,
            "size": 1024
          }
        }
      }
    },
    "axi_bars": {
      "BAR0": {
        "translation": 0,
        "baseaddr": 0,
        "highaddr": 4294967295,
        "size": 4294967296
      }
    },
    "pcie_bars": {
      "BAR0": {
        "translation": 0
      }
    }
  }
}
