From 09598095734109c6504a192c70452f49be169128 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Fri, 11 Nov 2022 06:38:00 -0500 Subject: [PATCH] code style fixes Signed-off-by: Steffen Vogel --- fpga/include/villas/fpga/core.hpp | 84 +++++++++++-------------- fpga/include/villas/fpga/ips/bram.hpp | 12 ++-- fpga/include/villas/fpga/ips/dma.hpp | 22 +++---- fpga/include/villas/fpga/ips/pcie.hpp | 16 ++--- fpga/include/villas/fpga/ips/switch.hpp | 19 +++--- fpga/include/villas/fpga/node.hpp | 32 +++++----- fpga/lib/ips/switch.cpp | 6 +- fpga/lib/node.cpp | 18 ++---- 8 files changed, 95 insertions(+), 114 deletions(-) diff --git a/fpga/include/villas/fpga/core.hpp b/fpga/include/villas/fpga/core.hpp index 2659ebff8..3ebfb1194 100644 --- a/fpga/include/villas/fpga/core.hpp +++ b/fpga/include/villas/fpga/core.hpp @@ -121,127 +121,118 @@ public: // Generic management interface for IPs // Runtime setup of IP, should access and initialize hardware - virtual bool init() + virtual + bool init() { return true; } // Runtime check of IP, should verify basic functionality - virtual bool check() + virtual + bool check() { return true; } // Generic disabling of IP, meaning may depend on IP - virtual bool stop() + virtual + bool stop() { return true; } // Reset the IP, it should behave like freshly initialized afterwards - virtual bool reset() + virtual + bool reset() { return true; } // Print some debug information about the IP - virtual void dump(); + virtual + void dump(); protected: // Key-type for accessing maps addressTranslations and slaveAddressSpaces using MemoryBlockName = std::string; // Each IP can declare via this function which memory blocks it requires - virtual std::list - getMemoryBlocks() const + virtual + std::list getMemoryBlocks() const { return {}; } public: - const std::string& - getInstanceName() const + const std::string& getInstanceName() const { return id.getName(); } // Operators - bool - operator==(const Vlnv &otherVlnv) const + bool operator==(const Vlnv &otherVlnv) const { return id.getVlnv() == otherVlnv; } - bool - operator!=(const Vlnv &otherVlnv) const + bool operator!=(const Vlnv &otherVlnv) const { return id.getVlnv() != otherVlnv; } - bool - operator==(const IpIdentifier &otherId) const + bool operator==(const IpIdentifier &otherId) const { return this->id == otherId; } - bool - operator!=(const IpIdentifier &otherId) const + bool operator!=(const IpIdentifier &otherId) const { return this->id != otherId; } - bool - operator==(const std::string &otherName) const + bool operator==(const std::string &otherName) const { return getInstanceName() == otherName; } - bool - operator!=(const std::string &otherName) const + bool operator!=(const std::string &otherName) const { return getInstanceName() != otherName; } - bool - operator==(const Core &otherIp) const + bool operator==(const Core &otherIp) const { return this->id == otherIp.id; } - bool - operator!=(const Core &otherIp) const + bool operator!=(const Core &otherIp) const { return this->id != otherIp.id; } - friend std::ostream& - operator<< (std::ostream &stream, const Core &ip) + friend + std::ostream& operator<< (std::ostream &stream, const Core &ip) { return stream << ip.id; } protected: - uintptr_t - getBaseAddr(const MemoryBlockName &block) const + uintptr_t getBaseAddr(const MemoryBlockName &block) const { return getLocalAddr(block, 0); } - uintptr_t - getLocalAddr(const MemoryBlockName &block, uintptr_t address) const; + uintptr_t getLocalAddr(const MemoryBlockName &block, uintptr_t address) const; - MemoryManager::AddressSpaceId - getAddressSpaceId(const MemoryBlockName &block) const + MemoryManager::AddressSpaceId getAddressSpaceId(const MemoryBlockName &block) const { return slaveAddressSpaces.at(block); } - InterruptController* - getInterruptController(const std::string &interruptName) const; + InterruptController* getInterruptController(const std::string &interruptName) const; - MemoryManager::AddressSpaceId - getMasterAddrSpaceByInterface(const std::string &masterInterfaceName) const + MemoryManager::AddressSpaceId getMasterAddrSpaceByInterface(const std::string &masterInterfaceName) const { return busMasterInterfaces.at(masterInterfaceName); } @@ -292,8 +283,8 @@ public: using plugin::Plugin::Plugin; // Returns a running and checked FPGA IP - static Core::List - make(PCIeCard* card, json_t *json_ips); + static + Core::List make(PCIeCard* card, json_t *json_ips); virtual std::string getType() const @@ -306,8 +297,8 @@ protected: POLL, IRQ, }; - Logger - getLogger() const + + Logger getLogger() const { return villas::logging.get(getName()); } @@ -325,18 +316,19 @@ private: void configurePollingMode(Core &, PollingMode) { } - virtual Vlnv getCompatibleVlnv() const = 0; + virtual + Vlnv getCompatibleVlnv() const = 0; protected: - static Logger - getStaticLogger() + static + Logger getStaticLogger() { return villas::logging.get("core:factory"); } private: - static CoreFactory* - lookup(const Vlnv &vlnv); + static + CoreFactory* lookup(const Vlnv &vlnv); }; } /* namespace ip */ diff --git a/fpga/include/villas/fpga/ips/bram.hpp b/fpga/include/villas/fpga/ips/bram.hpp index 14a4f652b..2f1a688f6 100644 --- a/fpga/include/villas/fpga/ips/bram.hpp +++ b/fpga/include/villas/fpga/ips/bram.hpp @@ -64,20 +64,20 @@ public: return new Bram; } - virtual std::string - getName() const + virtual + std::string getName() const { return "Bram"; } - virtual std::string - getDescription() const + virtual + std::string getDescription() const { return "Block RAM"; } - virtual Vlnv - getCompatibleVlnv() const + virtual + Vlnv getCompatibleVlnv() const { return Vlnv("xilinx.com:ip:axi_bram_ctrl:"); } diff --git a/fpga/include/villas/fpga/ips/dma.hpp b/fpga/include/villas/fpga/ips/dma.hpp index 1be671aee..26885a604 100644 --- a/fpga/include/villas/fpga/ips/dma.hpp +++ b/fpga/include/villas/fpga/ips/dma.hpp @@ -64,20 +64,18 @@ public: void makeAccesibleFromVA(const MemoryBlock &mem); bool makeInaccesibleFromVA(const MemoryBlock &mem); - inline bool - hasScatterGather() const + inline + bool hasScatterGather() const { return xConfig.HasSg; } - const StreamVertex& - getDefaultSlavePort() const + const StreamVertex& getDefaultSlavePort() const { return getSlavePort(s2mmPort); } - const StreamVertex& - getDefaultMasterPort() const + const StreamVertex& getDefaultMasterPort() const { return getMasterPort(mm2sPort); } @@ -158,20 +156,20 @@ public: return new Dma; } - virtual std::string - getName() const + virtual + std::string getName() const { return "Dma"; } - virtual std::string - getDescription() const + virtual + std::string getDescription() const { return "Xilinx's AXI4 Direct Memory Access Controller"; } - virtual Vlnv - getCompatibleVlnv() const + virtual + Vlnv getCompatibleVlnv() const { return Vlnv("xilinx.com:ip:axi_dma:"); } diff --git a/fpga/include/villas/fpga/ips/pcie.hpp b/fpga/include/villas/fpga/ips/pcie.hpp index d7d825592..34e6e3cd3 100644 --- a/fpga/include/villas/fpga/ips/pcie.hpp +++ b/fpga/include/villas/fpga/ips/pcie.hpp @@ -61,8 +61,8 @@ private: class AxiPciExpressBridgeFactory : public CoreFactory { public: - static constexpr const char* - getCompatibleVlnvString() + static constexpr + const char* getCompatibleVlnvString() { return "xilinx.com:ip:axi_pcie:"; } @@ -74,20 +74,20 @@ public: return new AxiPciExpressBridge; } - virtual std::string - getName() const + virtual + std::string getName() const { return "AxiPciExpressBridge"; } - virtual std::string - getDescription() const + virtual + std::string getDescription() const { return "Xilinx's AXI-PCIe Bridge"; } - virtual Vlnv - getCompatibleVlnv() const + virtual + Vlnv getCompatibleVlnv() const { return Vlnv(getCompatibleVlnvString()); } diff --git a/fpga/include/villas/fpga/ips/switch.hpp b/fpga/include/villas/fpga/ips/switch.hpp index f6bfba11f..5f5ac4b87 100644 --- a/fpga/include/villas/fpga/ips/switch.hpp +++ b/fpga/include/villas/fpga/ips/switch.hpp @@ -64,16 +64,17 @@ private: Core* slaveIn; }; - int num_ports; XAxis_Switch xSwitch; + XAxis_Switch_Config xConfig; + std::map portMapping; }; class AxiStreamSwitchFactory : public NodeFactory { public: - static constexpr const char* - getCompatibleVlnvString() + static constexpr + const char* getCompatibleVlnvString() { return "xilinx.com:ip:axis_switch:"; } @@ -85,20 +86,20 @@ public: return new AxiStreamSwitch; } - virtual std::string - getName() const + virtual + std::string getName() const { return "AxiStreamSwitch"; } - virtual std::string - getDescription() const + virtual + std::string getDescription() const { return "Xilinx's AXI4-Stream switch"; } - virtual Vlnv - getCompatibleVlnv() const + virtual + Vlnv getCompatibleVlnv() const { return Vlnv(getCompatibleVlnvString()); } diff --git a/fpga/include/villas/fpga/node.hpp b/fpga/include/villas/fpga/node.hpp index d0be942b9..e63161672 100644 --- a/fpga/include/villas/fpga/node.hpp +++ b/fpga/include/villas/fpga/node.hpp @@ -51,8 +51,8 @@ public: return nodeName + "/" + portName + "(" + (isMaster ? "M" : "S") + ")"; } - friend std::ostream& - operator<< (std::ostream &stream, const StreamVertex &vertex) + friend + std::ostream& operator<< (std::ostream &stream, const StreamVertex &vertex) { return stream << vertex.getIdentifier() << ": " << vertex.getName(); } @@ -69,10 +69,9 @@ public: graph::DirectedGraph("stream:graph") { } - std::shared_ptr - getOrCreateStreamVertex(const std::string &node, - const std::string &port, - bool isMaster) + std::shared_ptr getOrCreateStreamVertex(const std::string &node, + const std::string &port, + bool isMaster) { for (auto &vertexEntry : vertices) { auto &vertex = vertexEntry.second; @@ -100,14 +99,12 @@ public: std::string nodeName; }; - const StreamVertex& - getMasterPort(const std::string &name) const + const StreamVertex& getMasterPort(const std::string &name) const { return *portsMaster.at(name); } - const StreamVertex& - getSlavePort(const std::string &name) const + const StreamVertex& getSlavePort(const std::string &name) const { return *portsSlave.at(name); } @@ -133,15 +130,15 @@ public: } // Used by easy-usage connect, will throw if not implemented by derived node - virtual const StreamVertex& - getDefaultSlavePort() const; + virtual + const StreamVertex& getDefaultSlavePort() const; // Used by easy-usage connect, will throw if not implemented by derived node - virtual const StreamVertex& - getDefaultMasterPort() const; + virtual + const StreamVertex& getDefaultMasterPort() const; - static const StreamGraph& - getGraph() + static + const StreamGraph& getGraph() { return streamGraph; } @@ -161,7 +158,8 @@ protected: std::map> portsMaster; std::map> portsSlave; - static StreamGraph streamGraph; + static + StreamGraph streamGraph; }; class NodeFactory : public CoreFactory { diff --git a/fpga/lib/ips/switch.cpp b/fpga/lib/ips/switch.cpp index 0f06650b7..45ea1b1b7 100644 --- a/fpga/lib/ips/switch.cpp +++ b/fpga/lib/ips/switch.cpp @@ -64,8 +64,7 @@ bool AxiStreamSwitch::init() return true; } -bool -AxiStreamSwitch::connectInternal(const std::string &portSlave, +bool AxiStreamSwitch::connectInternal(const std::string &portSlave, const std::string &portMaster) { // Check if slave port exists @@ -123,8 +122,7 @@ AxiStreamSwitch::connectInternal(const std::string &portSlave, return true; } -int -AxiStreamSwitch::portNameToNum(const std::string &portName) +int AxiStreamSwitch::portNameToNum(const std::string &portName) { const std::string number = portName.substr(1, 2); return std::stoi(number); diff --git a/fpga/lib/node.cpp b/fpga/lib/node.cpp index 8824e41a6..171bfa459 100644 --- a/fpga/lib/node.cpp +++ b/fpga/lib/node.cpp @@ -90,8 +90,7 @@ void NodeFactory::configure(Core &ip, json_t *cfg) } } -std::pair -Node::getLoopbackPorts() const +std::pair Node::getLoopbackPorts() const { for (auto& [masterName, masterVertex] : portsMaster) { for (auto& [slaveName, slaveVertex] : portsSlave) { @@ -157,29 +156,25 @@ bool Node::connect(const StreamVertex &from, const StreamVertex &to) return nextHopNodeIp->connect(*nextHopNode, to); } -const StreamVertex& -Node::getDefaultSlavePort() const +const StreamVertex& Node::getDefaultSlavePort() const { logger->error("No default slave port available"); throw std::exception(); } -const StreamVertex& -Node::getDefaultMasterPort() const +const StreamVertex& Node::getDefaultMasterPort() const { logger->error("No default master port available"); throw std::exception(); } -bool -Node::loopbackPossible() const +bool Node::loopbackPossible() const { auto ports = getLoopbackPorts(); return (not ports.first.empty()) and (not ports.second.empty()); } -bool -Node::connectInternal(const std::string &slavePort, +bool Node::connectInternal(const std::string &slavePort, const std::string &masterPort) { (void) slavePort; @@ -189,8 +184,7 @@ Node::connectInternal(const std::string &slavePort, return false; } -bool -Node::connectLoopback() +bool Node::connectLoopback() { auto ports = getLoopbackPorts(); const auto &portMaster = portsMaster[ports.first];