From 0aed1a1b12ee9a87dfb9c44eef54c48c695e8c49 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Wed, 31 Jan 2018 15:11:13 +0100 Subject: [PATCH] tests: moved initialization of FPGA stuff to fpga.cpp --- fpga/tests/CMakeLists.txt | 1 + fpga/tests/fpga.cpp | 98 +++++++++++++++++++++++++++++++++++++++ fpga/tests/main.cpp | 89 +---------------------------------- 3 files changed, 101 insertions(+), 87 deletions(-) create mode 100644 fpga/tests/fpga.cpp diff --git a/fpga/tests/CMakeLists.txt b/fpga/tests/CMakeLists.txt index edd6fdd3e..152413de1 100644 --- a/fpga/tests/CMakeLists.txt +++ b/fpga/tests/CMakeLists.txt @@ -1,5 +1,6 @@ set(SOURCES main.cpp + fpga.cpp # dma.c fifo.cpp # hls.c diff --git a/fpga/tests/fpga.cpp b/fpga/tests/fpga.cpp new file mode 100644 index 000000000..b5147f3b6 --- /dev/null +++ b/fpga/tests/fpga.cpp @@ -0,0 +1,98 @@ +/** FPGA related code for bootstrapping the unit-tests + * + * @file + * @author Steffen Vogel + * @copyright 2018, Steffen Vogel + * @license GNU General Public License (version 3) + * + * VILLASfpga + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + *********************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "global.hpp" + +#include + +#define FPGA_CARD "vc707" +#define TEST_CONFIG "../etc/fpga.json" +#define TEST_LEN 0x1000 + +#define CPU_HZ 3392389000 +#define FPGA_AXI_HZ 125000000 + +static struct pci pci; +static struct vfio_container vc; + +FpgaState state; + +static void init() +{ + int ret; + + FILE *f; + json_error_t err; + + villas::Plugin::dumpList(); + + ret = pci_init(&pci); + cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system"); + + ret = vfio_init(&vc); + cr_assert_eq(ret, 0, "Failed to initiliaze VFIO sub-system"); + + /* Parse FPGA configuration */ + f = fopen(TEST_CONFIG, "r"); + cr_assert_not_null(f, "Cannot open config file"); + + json_t *json = json_loadf(f, 0, &err); + cr_assert_not_null(json, "Cannot load JSON config"); + + fclose(f); + + json_t *fpgas = json_object_get(json, "fpgas"); + cr_assert_not_null(fpgas, "No section 'fpgas' found in config"); + cr_assert(json_object_size(json) > 0, "No FPGAs defined in config"); + + // get the FPGA card plugin + villas::Plugin* plugin = villas::Plugin::lookup(villas::Plugin::Type::FpgaCard, ""); + cr_assert_not_null(plugin, "No plugin for FPGA card found"); + villas::fpga::PCIeCardFactory* fpgaCardPlugin = dynamic_cast(plugin); + + // create all FPGA card instances using the corresponding plugin + state.cards = fpgaCardPlugin->make(fpgas, &pci, &vc); + + cr_assert(state.cards.size() != 0, "No FPGA cards found!"); + + json_decref(json); +} + +static void fini() +{ + // release all cards + state.cards.clear(); +} + +TestSuite(fpga, + .init = init, + .fini = fini, + .description = "VILLASfpga" +); diff --git a/fpga/tests/main.cpp b/fpga/tests/main.cpp index b5fa06f8b..321e44a64 100644 --- a/fpga/tests/main.cpp +++ b/fpga/tests/main.cpp @@ -23,96 +23,11 @@ #include #include - -#include -#include -#include -#include +#include +#include #include -#include -#include #include -#include "global.hpp" -#define FPGA_CARD "vc707" -#define TEST_CONFIG "../etc/fpga.json" -#define TEST_LEN 0x1000 - -#define CPU_HZ 3392389000 -#define FPGA_AXI_HZ 125000000 - -FpgaState state; - -static struct pci pci; -static struct vfio_container vc; - -static void init() -{ - int ret; - - FILE *f; - json_error_t err; - - villas::Plugin::dumpList(); - - auto logger = loggerGetOrCreate("unittest"); - spdlog::set_pattern("[%T] [%l] [%n] %v"); - spdlog::set_level(spdlog::level::debug); - - ret = pci_init(&pci); - cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system"); - - ret = vfio_init(&vc); - cr_assert_eq(ret, 0, "Failed to initiliaze VFIO sub-system"); - - /* Parse FPGA configuration */ - f = fopen(TEST_CONFIG, "r"); - cr_assert_not_null(f, "Cannot open config file"); - - json_t *json = json_loadf(f, 0, &err); - cr_assert_not_null(json, "Cannot load JSON config"); - - fclose(f); - - json_t *fpgas = json_object_get(json, "fpgas"); - cr_assert_not_null(fpgas, "No section 'fpgas' found in config"); - cr_assert(json_object_size(json) > 0, "No FPGAs defined in config"); - - // get the FPGA card plugin - villas::Plugin* plugin = villas::Plugin::lookup(villas::Plugin::Type::FpgaCard, ""); - cr_assert_not_null(plugin, "No plugin for FPGA card found"); - villas::fpga::PCIeCardFactory* fpgaCardPlugin = dynamic_cast(plugin); - - // create all FPGA card instances using the corresponding plugin - state.cards = fpgaCardPlugin->make(fpgas, &pci, &vc); - - cr_assert(state.cards.size() != 0, "No FPGA cards found!"); - - json_decref(json); -} - -static void fini() -{ - // release all cards - state.cards.clear(); -} - -TestSuite(fpga, - .init = init, - .fini = fini, - .description = "VILLASfpga" -); - -static void init_graph() -{ - spdlog::set_pattern("[%T] [%l] [%n] %v"); - spdlog::set_level(spdlog::level::debug); -} - -TestSuite(graph, - .init = init_graph, - .description = "Graph library" -);