From 0ce4e67bedf88894e67cc9843a57a7e850168697 Mon Sep 17 00:00:00 2001 From: Pascal Bauer Date: Mon, 26 Aug 2024 13:02:25 +0200 Subject: [PATCH] add bitstreams --- etc/fpga/zcu106-smmu/zcu106-smmu.json | 509 ++++ .../zcu106_aurora_dino_240808-2.json | 2472 +++++++++++++++++ 2 files changed, 2981 insertions(+) create mode 100644 etc/fpga/zcu106-smmu/zcu106-smmu.json create mode 100644 etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json diff --git a/etc/fpga/zcu106-smmu/zcu106-smmu.json b/etc/fpga/zcu106-smmu/zcu106-smmu.json new file mode 100644 index 000000000..7a124ea09 --- /dev/null +++ b/etc/fpga/zcu106-smmu/zcu106-smmu.json @@ -0,0 +1,509 @@ +{ + "axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "parameters": { + "c_s_axi_lite_addr_width": 10, + "c_s_axi_lite_data_width": 32, + "c_dlytmr_resolution": 125, + "c_prmry_is_aclk_async": 0, + "c_enable_multi_channel": 0, + "c_num_mm2s_channels": 1, + "c_num_s2mm_channels": 1, + "c_include_sg": 1, + "c_sg_include_stscntrl_strm": 0, + "c_sg_use_stsapp_length": 0, + "c_sg_length_width": 23, + "c_m_axi_sg_addr_width": 64, + "c_m_axi_sg_data_width": 32, + "c_m_axis_mm2s_cntrl_tdata_width": 32, + "c_s_axis_s2mm_sts_tdata_width": 32, + "c_micro_dma": 0, + "c_include_mm2s": 1, + "c_include_mm2s_sf": 1, + "c_mm2s_burst_size": 16, + "c_m_axi_mm2s_addr_width": 64, + "c_m_axi_mm2s_data_width": 128, + "c_m_axis_mm2s_tdata_width": 128, + "c_include_mm2s_dre": 0, + "c_include_s2mm": 1, + "c_include_s2mm_sf": 1, + "c_s2mm_burst_size": 16, + "c_m_axi_s2mm_addr_width": 64, + "c_m_axi_s2mm_data_width": 128, + "c_s_axis_s2mm_tdata_width": 128, + "c_include_s2mm_dre": 0, + "c_increase_throughput": 0, + "c_family": "zynquplus", + "component_name": "design_1_axi_dma_0_0", + "c_addr_width": 64, + "c_single_interface": 0, + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684354560, + "c_highaddr": 2684420095 + }, + "memory-view": { + "M_AXI_SG": { + "zynq_ultra_ps_e_0": { + "HPC1_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC1_QSPI": { + "baseaddr": 3221225472, + "highaddr": 3758096383, + "size": 536870912 + }, + "HPC1_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + }, + "M_AXI_MM2S": { + "zynq_ultra_ps_e_0": { + "HPC0_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC0_QSPI": { + "baseaddr": 3221225472, + "highaddr": 3758096383, + "size": 536870912 + }, + "HPC0_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + }, + "M_AXI_S2MM": { + "zynq_ultra_ps_e_0": { + "HPC0_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC0_QSPI": { + "baseaddr": 3221225472, + "highaddr": 3758096383, + "size": 536870912 + }, + "HPC0_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + } + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S00_AXIS", + "name": "MM2S" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M00_AXIS", + "name": "S2MM" + } + ] + }, + "axis_interconnect_0_xbar": { + "vlnv": "xilinx.com:ip:axis_switch:1.1", + "parameters": { + "c_family": "zynquplus", + "c_num_si_slots": 2, + "c_log_si_slots": 1, + "c_num_mi_slots": 2, + "c_axis_tdata_width": 128, + "c_axis_tid_width": 1, + "c_axis_tdest_width": 1, + "c_axis_tuser_width": 1, + "c_axis_signal_set": 91, + "c_arb_on_max_xfers": 1, + "c_arb_on_num_cycles": 0, + "c_arb_on_tlast": 0, + "c_include_arbiter": 1, + "c_arb_algorithm": 0, + "c_output_reg": 0, + "c_decoder_reg": 1, + "c_m_axis_connectivity_array": 15, + "c_m_axis_basetdest_array": 2, + "c_m_axis_hightdest_array": 2, + "c_routing_mode": 1, + "c_s_axi_ctrl_addr_width": 7, + "c_s_axi_ctrl_data_width": 32, + "c_common_clock": 0, + "num_si": 2, + "num_mi": 2, + "routing_mode": 1, + "has_tready": 1, + "tdata_num_bytes": 16, + "has_tstrb": 0, + "has_tkeep": 1, + "has_tlast": 1, + "tid_width": 0, + "tdest_width": 1, + "tuser_width": 0, + "has_aclken": 0, + "arb_on_max_xfers": 1, + "arb_on_num_cycles": 0, + "arb_on_tlast": 0, + "arb_algorithm": 0, + "decoder_reg": 1, + "output_reg": 0, + "common_clock": 0, + "m00_axis_basetdest": 0, + "m01_axis_basetdest": 1, + "m02_axis_basetdest": 2, + "m03_axis_basetdest": 3, + "m04_axis_basetdest": 4, + "m05_axis_basetdest": 5, + "m06_axis_basetdest": 6, + "m07_axis_basetdest": 7, + "m08_axis_basetdest": 8, + "m09_axis_basetdest": 9, + "m10_axis_basetdest": 10, + "m11_axis_basetdest": 11, + "m12_axis_basetdest": 12, + "m13_axis_basetdest": 13, + "m14_axis_basetdest": 14, + "m15_axis_basetdest": 15, + "m00_axis_hightdest": 0, + "m01_axis_hightdest": 1, + "m02_axis_hightdest": 2, + "m03_axis_hightdest": 3, + "m04_axis_hightdest": 4, + "m05_axis_hightdest": 5, + "m06_axis_hightdest": 6, + "m07_axis_hightdest": 7, + "m08_axis_hightdest": 8, + "m09_axis_hightdest": 9, + "m10_axis_hightdest": 10, + "m11_axis_hightdest": 11, + "m12_axis_hightdest": 12, + "m13_axis_hightdest": 13, + "m14_axis_hightdest": 14, + "m15_axis_hightdest": 15, + "m00_s00_connectivity": 1, + "m00_s01_connectivity": 1, + "m00_s02_connectivity": 1, + "m00_s03_connectivity": 1, + "m00_s04_connectivity": 1, + "m00_s05_connectivity": 1, + "m00_s06_connectivity": 1, + "m00_s07_connectivity": 1, + "m00_s08_connectivity": 1, + "m00_s09_connectivity": 1, + "m00_s10_connectivity": 1, + "m00_s11_connectivity": 1, + "m00_s12_connectivity": 1, + "m00_s13_connectivity": 1, + "m00_s14_connectivity": 1, + "m00_s15_connectivity": 1, + "m01_s00_connectivity": 1, + "m01_s01_connectivity": 1, + "m01_s02_connectivity": 1, + "m01_s03_connectivity": 1, + "m01_s04_connectivity": 1, + "m01_s05_connectivity": 1, + "m01_s06_connectivity": 1, + "m01_s07_connectivity": 1, + "m01_s08_connectivity": 1, + "m01_s09_connectivity": 1, + "m01_s10_connectivity": 1, + "m01_s11_connectivity": 1, + "m01_s12_connectivity": 1, + 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"m14_s09_connectivity": 1, + "m14_s10_connectivity": 1, + "m14_s11_connectivity": 1, + "m14_s12_connectivity": 1, + "m14_s13_connectivity": 1, + "m14_s14_connectivity": 1, + "m14_s15_connectivity": 1, + "m15_s00_connectivity": 1, + "m15_s01_connectivity": 1, + "m15_s02_connectivity": 1, + "m15_s03_connectivity": 1, + "m15_s04_connectivity": 1, + "m15_s05_connectivity": 1, + "m15_s06_connectivity": 1, + "m15_s07_connectivity": 1, + "m15_s08_connectivity": 1, + "m15_s09_connectivity": 1, + "m15_s10_connectivity": 1, + "m15_s11_connectivity": 1, + "m15_s12_connectivity": 1, + "m15_s13_connectivity": 1, + "m15_s14_connectivity": 1, + "m15_s15_connectivity": 1, + "component_name": "design_1_xbar_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684420096, + "c_highaddr": 2684485631 + }, + "ports": [ + { + "role": "slave", + "target": "axi_dma_0:MM2S", + "name": "S00_AXIS" + }, + { + "role": "master", + "target": "axi_dma_0:S2MM", + "name": "M00_AXIS" + }, + { + "role": "master", + "target": "axis_interconnect_0_xbar:S01_AXIS", + "name": "M01_AXIS" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M01_AXIS", + "name": "S01_AXIS" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M01_AXIS", + "name": "S01_AXIS" + }, + { + "role": "master", + "target": "axis_interconnect_0_xbar:S01_AXIS", + "name": "M01_AXIS" + } + ], + "num_ports": 2 + }, + "zynq_ultra_ps_e_0": { + "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3", + "memory-view": { + "M_AXI_HPM0_FPD": { + "axi_dma_0": { + "Reg": { + "baseaddr": 2684354560, + "highaddr": 2684420095, + "size": 65536 + } + }, + "axis_interconnect_0_xbar": { + "Reg": { + "baseaddr": 2684420096, + "highaddr": 2684485631, + "size": 65536 + } + } + } + } + } +} diff --git a/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json b/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json new file mode 100644 index 000000000..dfbd1fed9 --- /dev/null +++ b/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json @@ -0,0 +1,2472 @@ +{ + "aurora_aurora_8b10b_0": { + "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", + "parameters": { + "component_name": "design_1_aurora_8b10b_0_1", + "channel_enable": "X0Y10", + "c_refclk_loc_p": "W10", + "c_refclk_loc_n": "W9", + "c_column_used": "left", + "c_ucolumn_used": "right", + "c_family": "zynquplus", + "c_device": "xczu7ev", + "c_row_used": "None", + "c_xpackage": "ffvc1156", + "c_xspeedgrade": -2, + "c_aurora_lanes": 1, + "c_lane_width": 2, + "c_active_transceiverquads": 1, + "c_start_quad": "Quad_X0Y2", + "c_start_lane": "X0Y10", + "c_refclk_source": "X0Y10 clk1", + "interface_mode": "Framing", + "c_stream": "false", + "dataflow_config": "Duplex", + "backchannel_mode": "Sidebands", + "c_simplex": "false", + "c_simplex_mode": "TX", + "flow_mode": "None", + "c_nfc": "false", + "c_nfc_mode": "IMM", + "c_ufc": "false", + "c_example_simulation": "false", + "c_gtwiz_out": "false", + "c_line_rate": 2, + "cc_line_rate": 2, + "c_refclk_frequency": 250, + "cc_refclk_frequency": 250, + "c_init_clk": "99.990005", + "drp_freq": "50.0000", + "c_gt_loc_1": 1, + "c_gt_loc_2": "X", + "c_gt_loc_3": "X", + "c_gt_loc_4": "X", + "c_gt_loc_5": "X", + "c_gt_loc_6": "X", + "c_gt_loc_7": "X", + "c_gt_loc_8": "X", + "c_gt_loc_9": "X", + "c_gt_loc_10": "X", + "c_gt_loc_11": "X", + "c_gt_loc_12": "X", + "c_gt_loc_13": "X", + "c_gt_loc_14": "X", + "c_gt_loc_15": "X", + "c_gt_loc_16": "X", + "c_gt_loc_17": "X", + "c_gt_loc_18": "X", + "c_gt_loc_19": "X", + "c_gt_loc_20": "X", + "c_gt_loc_21": "X", + "c_gt_loc_22": "X", + "c_gt_loc_23": "X", + "c_gt_loc_24": "X", + "c_gt_loc_25": "X", + "c_gt_loc_26": "X", + "c_gt_loc_27": "X", + "c_gt_loc_28": "X", + "c_gt_loc_29": "X", + "c_gt_loc_30": "X", + "c_gt_loc_31": "X", + "c_gt_loc_32": "X", + "c_gt_loc_33": "X", + "c_gt_loc_34": "X", + "c_gt_loc_35": "X", + "c_gt_loc_36": "X", + "c_gt_loc_37": "X", + "c_gt_loc_38": "X", + "c_gt_loc_39": "X", + "c_gt_loc_40": "X", + "c_gt_loc_41": "X", + "c_gt_loc_42": "X", + "c_gt_loc_43": "X", + "c_gt_loc_44": "X", + "c_gt_loc_45": "X", + "c_gt_loc_46": "X", + "c_gt_loc_47": "X", + "c_gt_loc_48": "X", + "c_gt_clock_1": "GTHQ0", + "c_gt_clock_2": "None", + "c_use_scrambler": "false", + "c_use_chipscope": "false", + "c_drp_if": "false", + "transceivercontrol": "false", + "c_use_crc": "false", + "supportlevel": 1, + "c_use_byteswap": "false", + "c_cpll_fbdiv": 1, + "c_cpll_fbdiv_45": 5, + "c_cpll_refclk_div": 1, + "c_rxoutdiv": 1, + "c_txoutdiv": 1, + "user_interface": "AXI_4_Streaming", + "c_ufcbuswidthselect": 16, + "c_ufcrembuswidthselect": 1, + "c_ufcstrbbuswidthselect": 2, + "c_rembuswidthselect": 1, + "isv7gth": "false", + "gtquadcnt": 1, + "port7dmonitorout": 7, + "is_7series": "false", + "singleend_initclk": "true", + "singleend_gtrefclk": "false", + "c_double_gtrxreset": "false", + "c_doccport_enable": "false", + "is_board": "zcu106", + "usdrpaddr_width": 9, + "usdmon_width": 15, + "txdiffctrl_width": 4, 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