From 0ce4e67bedf88894e67cc9843a57a7e850168697 Mon Sep 17 00:00:00 2001
From: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Date: Mon, 26 Aug 2024 13:02:25 +0200
Subject: [PATCH] add bitstreams
---
etc/fpga/zcu106-smmu/zcu106-smmu.json | 509 ++++
.../zcu106_aurora_dino_240808-2.json | 2472 +++++++++++++++++
2 files changed, 2981 insertions(+)
create mode 100644 etc/fpga/zcu106-smmu/zcu106-smmu.json
create mode 100644 etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json
diff --git a/etc/fpga/zcu106-smmu/zcu106-smmu.json b/etc/fpga/zcu106-smmu/zcu106-smmu.json
new file mode 100644
index 000000000..7a124ea09
--- /dev/null
+++ b/etc/fpga/zcu106-smmu/zcu106-smmu.json
@@ -0,0 +1,509 @@
+{
+ "axi_dma_0": {
+ "vlnv": "xilinx.com:ip:axi_dma:7.1",
+ "parameters": {
+ "c_s_axi_lite_addr_width": 10,
+ "c_s_axi_lite_data_width": 32,
+ "c_dlytmr_resolution": 125,
+ "c_prmry_is_aclk_async": 0,
+ "c_enable_multi_channel": 0,
+ "c_num_mm2s_channels": 1,
+ "c_num_s2mm_channels": 1,
+ "c_include_sg": 1,
+ "c_sg_include_stscntrl_strm": 0,
+ "c_sg_use_stsapp_length": 0,
+ "c_sg_length_width": 23,
+ "c_m_axi_sg_addr_width": 64,
+ "c_m_axi_sg_data_width": 32,
+ "c_m_axis_mm2s_cntrl_tdata_width": 32,
+ "c_s_axis_s2mm_sts_tdata_width": 32,
+ "c_micro_dma": 0,
+ "c_include_mm2s": 1,
+ "c_include_mm2s_sf": 1,
+ "c_mm2s_burst_size": 16,
+ "c_m_axi_mm2s_addr_width": 64,
+ "c_m_axi_mm2s_data_width": 128,
+ "c_m_axis_mm2s_tdata_width": 128,
+ "c_include_mm2s_dre": 0,
+ "c_include_s2mm": 1,
+ "c_include_s2mm_sf": 1,
+ "c_s2mm_burst_size": 16,
+ "c_m_axi_s2mm_addr_width": 64,
+ "c_m_axi_s2mm_data_width": 128,
+ "c_s_axis_s2mm_tdata_width": 128,
+ "c_include_s2mm_dre": 0,
+ "c_increase_throughput": 0,
+ "c_family": "zynquplus",
+ "component_name": "design_1_axi_dma_0_0",
+ "c_addr_width": 64,
+ "c_single_interface": 0,
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684354560,
+ "c_highaddr": 2684420095
+ },
+ "memory-view": {
+ "M_AXI_SG": {
+ "zynq_ultra_ps_e_0": {
+ "HPC1_DDR_LOW": {
+ "baseaddr": 0,
+ "highaddr": 2147483647,
+ "size": 2147483648
+ },
+ "HPC1_QSPI": {
+ "baseaddr": 3221225472,
+ "highaddr": 3758096383,
+ "size": 536870912
+ },
+ "HPC1_DDR_HIGH": {
+ "baseaddr": 34359738368,
+ "highaddr": 68719476735,
+ "size": 34359738368
+ }
+ }
+ },
+ "M_AXI_MM2S": {
+ "zynq_ultra_ps_e_0": {
+ "HPC0_DDR_LOW": {
+ "baseaddr": 0,
+ "highaddr": 2147483647,
+ "size": 2147483648
+ },
+ "HPC0_QSPI": {
+ "baseaddr": 3221225472,
+ "highaddr": 3758096383,
+ "size": 536870912
+ },
+ "HPC0_DDR_HIGH": {
+ "baseaddr": 34359738368,
+ "highaddr": 68719476735,
+ "size": 34359738368
+ }
+ }
+ },
+ "M_AXI_S2MM": {
+ "zynq_ultra_ps_e_0": {
+ "HPC0_DDR_LOW": {
+ "baseaddr": 0,
+ "highaddr": 2147483647,
+ "size": 2147483648
+ },
+ "HPC0_QSPI": {
+ "baseaddr": 3221225472,
+ "highaddr": 3758096383,
+ "size": 536870912
+ },
+ "HPC0_DDR_HIGH": {
+ "baseaddr": 34359738368,
+ "highaddr": 68719476735,
+ "size": 34359738368
+ }
+ }
+ }
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S00_AXIS",
+ "name": "MM2S"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M00_AXIS",
+ "name": "S2MM"
+ }
+ ]
+ },
+ "axis_interconnect_0_xbar": {
+ "vlnv": "xilinx.com:ip:axis_switch:1.1",
+ "parameters": {
+ "c_family": "zynquplus",
+ "c_num_si_slots": 2,
+ "c_log_si_slots": 1,
+ "c_num_mi_slots": 2,
+ "c_axis_tdata_width": 128,
+ "c_axis_tid_width": 1,
+ "c_axis_tdest_width": 1,
+ "c_axis_tuser_width": 1,
+ "c_axis_signal_set": 91,
+ "c_arb_on_max_xfers": 1,
+ "c_arb_on_num_cycles": 0,
+ "c_arb_on_tlast": 0,
+ "c_include_arbiter": 1,
+ "c_arb_algorithm": 0,
+ "c_output_reg": 0,
+ "c_decoder_reg": 1,
+ "c_m_axis_connectivity_array": 15,
+ "c_m_axis_basetdest_array": 2,
+ "c_m_axis_hightdest_array": 2,
+ "c_routing_mode": 1,
+ "c_s_axi_ctrl_addr_width": 7,
+ "c_s_axi_ctrl_data_width": 32,
+ "c_common_clock": 0,
+ "num_si": 2,
+ "num_mi": 2,
+ "routing_mode": 1,
+ "has_tready": 1,
+ "tdata_num_bytes": 16,
+ "has_tstrb": 0,
+ "has_tkeep": 1,
+ "has_tlast": 1,
+ "tid_width": 0,
+ "tdest_width": 1,
+ "tuser_width": 0,
+ "has_aclken": 0,
+ "arb_on_max_xfers": 1,
+ "arb_on_num_cycles": 0,
+ "arb_on_tlast": 0,
+ "arb_algorithm": 0,
+ "decoder_reg": 1,
+ "output_reg": 0,
+ "common_clock": 0,
+ "m00_axis_basetdest": 0,
+ "m01_axis_basetdest": 1,
+ "m02_axis_basetdest": 2,
+ "m03_axis_basetdest": 3,
+ "m04_axis_basetdest": 4,
+ "m05_axis_basetdest": 5,
+ "m06_axis_basetdest": 6,
+ "m07_axis_basetdest": 7,
+ "m08_axis_basetdest": 8,
+ "m09_axis_basetdest": 9,
+ "m10_axis_basetdest": 10,
+ "m11_axis_basetdest": 11,
+ "m12_axis_basetdest": 12,
+ "m13_axis_basetdest": 13,
+ "m14_axis_basetdest": 14,
+ "m15_axis_basetdest": 15,
+ "m00_axis_hightdest": 0,
+ "m01_axis_hightdest": 1,
+ "m02_axis_hightdest": 2,
+ "m03_axis_hightdest": 3,
+ "m04_axis_hightdest": 4,
+ "m05_axis_hightdest": 5,
+ "m06_axis_hightdest": 6,
+ "m07_axis_hightdest": 7,
+ "m08_axis_hightdest": 8,
+ "m09_axis_hightdest": 9,
+ "m10_axis_hightdest": 10,
+ "m11_axis_hightdest": 11,
+ "m12_axis_hightdest": 12,
+ "m13_axis_hightdest": 13,
+ "m14_axis_hightdest": 14,
+ "m15_axis_hightdest": 15,
+ "m00_s00_connectivity": 1,
+ "m00_s01_connectivity": 1,
+ "m00_s02_connectivity": 1,
+ "m00_s03_connectivity": 1,
+ "m00_s04_connectivity": 1,
+ "m00_s05_connectivity": 1,
+ "m00_s06_connectivity": 1,
+ "m00_s07_connectivity": 1,
+ "m00_s08_connectivity": 1,
+ "m00_s09_connectivity": 1,
+ "m00_s10_connectivity": 1,
+ "m00_s11_connectivity": 1,
+ "m00_s12_connectivity": 1,
+ "m00_s13_connectivity": 1,
+ "m00_s14_connectivity": 1,
+ "m00_s15_connectivity": 1,
+ "m01_s00_connectivity": 1,
+ "m01_s01_connectivity": 1,
+ "m01_s02_connectivity": 1,
+ "m01_s03_connectivity": 1,
+ "m01_s04_connectivity": 1,
+ "m01_s05_connectivity": 1,
+ "m01_s06_connectivity": 1,
+ "m01_s07_connectivity": 1,
+ "m01_s08_connectivity": 1,
+ "m01_s09_connectivity": 1,
+ "m01_s10_connectivity": 1,
+ "m01_s11_connectivity": 1,
+ "m01_s12_connectivity": 1,
+ "m01_s13_connectivity": 1,
+ "m01_s14_connectivity": 1,
+ "m01_s15_connectivity": 1,
+ "m02_s00_connectivity": 1,
+ "m02_s01_connectivity": 1,
+ "m02_s02_connectivity": 1,
+ "m02_s03_connectivity": 1,
+ "m02_s04_connectivity": 1,
+ "m02_s05_connectivity": 1,
+ "m02_s06_connectivity": 1,
+ "m02_s07_connectivity": 1,
+ "m02_s08_connectivity": 1,
+ "m02_s09_connectivity": 1,
+ "m02_s10_connectivity": 1,
+ "m02_s11_connectivity": 1,
+ "m02_s12_connectivity": 1,
+ "m02_s13_connectivity": 1,
+ "m02_s14_connectivity": 1,
+ "m02_s15_connectivity": 1,
+ "m03_s00_connectivity": 1,
+ "m03_s01_connectivity": 1,
+ "m03_s02_connectivity": 1,
+ "m03_s03_connectivity": 1,
+ "m03_s04_connectivity": 1,
+ "m03_s05_connectivity": 1,
+ "m03_s06_connectivity": 1,
+ "m03_s07_connectivity": 1,
+ "m03_s08_connectivity": 1,
+ "m03_s09_connectivity": 1,
+ "m03_s10_connectivity": 1,
+ "m03_s11_connectivity": 1,
+ "m03_s12_connectivity": 1,
+ "m03_s13_connectivity": 1,
+ "m03_s14_connectivity": 1,
+ "m03_s15_connectivity": 1,
+ "m04_s00_connectivity": 1,
+ "m04_s01_connectivity": 1,
+ "m04_s02_connectivity": 1,
+ "m04_s03_connectivity": 1,
+ "m04_s04_connectivity": 1,
+ "m04_s05_connectivity": 1,
+ "m04_s06_connectivity": 1,
+ "m04_s07_connectivity": 1,
+ "m04_s08_connectivity": 1,
+ "m04_s09_connectivity": 1,
+ "m04_s10_connectivity": 1,
+ "m04_s11_connectivity": 1,
+ "m04_s12_connectivity": 1,
+ "m04_s13_connectivity": 1,
+ "m04_s14_connectivity": 1,
+ "m04_s15_connectivity": 1,
+ "m05_s00_connectivity": 1,
+ "m05_s01_connectivity": 1,
+ "m05_s02_connectivity": 1,
+ "m05_s03_connectivity": 1,
+ "m05_s04_connectivity": 1,
+ "m05_s05_connectivity": 1,
+ "m05_s06_connectivity": 1,
+ "m05_s07_connectivity": 1,
+ "m05_s08_connectivity": 1,
+ "m05_s09_connectivity": 1,
+ "m05_s10_connectivity": 1,
+ "m05_s11_connectivity": 1,
+ "m05_s12_connectivity": 1,
+ "m05_s13_connectivity": 1,
+ "m05_s14_connectivity": 1,
+ "m05_s15_connectivity": 1,
+ "m06_s00_connectivity": 1,
+ "m06_s01_connectivity": 1,
+ "m06_s02_connectivity": 1,
+ "m06_s03_connectivity": 1,
+ "m06_s04_connectivity": 1,
+ "m06_s05_connectivity": 1,
+ "m06_s06_connectivity": 1,
+ "m06_s07_connectivity": 1,
+ "m06_s08_connectivity": 1,
+ "m06_s09_connectivity": 1,
+ "m06_s10_connectivity": 1,
+ "m06_s11_connectivity": 1,
+ "m06_s12_connectivity": 1,
+ "m06_s13_connectivity": 1,
+ "m06_s14_connectivity": 1,
+ "m06_s15_connectivity": 1,
+ "m07_s00_connectivity": 1,
+ "m07_s01_connectivity": 1,
+ "m07_s02_connectivity": 1,
+ "m07_s03_connectivity": 1,
+ "m07_s04_connectivity": 1,
+ "m07_s05_connectivity": 1,
+ "m07_s06_connectivity": 1,
+ "m07_s07_connectivity": 1,
+ "m07_s08_connectivity": 1,
+ "m07_s09_connectivity": 1,
+ "m07_s10_connectivity": 1,
+ "m07_s11_connectivity": 1,
+ "m07_s12_connectivity": 1,
+ "m07_s13_connectivity": 1,
+ "m07_s14_connectivity": 1,
+ "m07_s15_connectivity": 1,
+ "m08_s00_connectivity": 1,
+ "m08_s01_connectivity": 1,
+ "m08_s02_connectivity": 1,
+ "m08_s03_connectivity": 1,
+ "m08_s04_connectivity": 1,
+ "m08_s05_connectivity": 1,
+ "m08_s06_connectivity": 1,
+ "m08_s07_connectivity": 1,
+ "m08_s08_connectivity": 1,
+ "m08_s09_connectivity": 1,
+ "m08_s10_connectivity": 1,
+ "m08_s11_connectivity": 1,
+ "m08_s12_connectivity": 1,
+ "m08_s13_connectivity": 1,
+ "m08_s14_connectivity": 1,
+ "m08_s15_connectivity": 1,
+ "m09_s00_connectivity": 1,
+ "m09_s01_connectivity": 1,
+ "m09_s02_connectivity": 1,
+ "m09_s03_connectivity": 1,
+ "m09_s04_connectivity": 1,
+ "m09_s05_connectivity": 1,
+ "m09_s06_connectivity": 1,
+ "m09_s07_connectivity": 1,
+ "m09_s08_connectivity": 1,
+ "m09_s09_connectivity": 1,
+ "m09_s10_connectivity": 1,
+ "m09_s11_connectivity": 1,
+ "m09_s12_connectivity": 1,
+ "m09_s13_connectivity": 1,
+ "m09_s14_connectivity": 1,
+ "m09_s15_connectivity": 1,
+ "m10_s00_connectivity": 1,
+ "m10_s01_connectivity": 1,
+ "m10_s02_connectivity": 1,
+ "m10_s03_connectivity": 1,
+ "m10_s04_connectivity": 1,
+ "m10_s05_connectivity": 1,
+ "m10_s06_connectivity": 1,
+ "m10_s07_connectivity": 1,
+ "m10_s08_connectivity": 1,
+ "m10_s09_connectivity": 1,
+ "m10_s10_connectivity": 1,
+ "m10_s11_connectivity": 1,
+ "m10_s12_connectivity": 1,
+ "m10_s13_connectivity": 1,
+ "m10_s14_connectivity": 1,
+ "m10_s15_connectivity": 1,
+ "m11_s00_connectivity": 1,
+ "m11_s01_connectivity": 1,
+ "m11_s02_connectivity": 1,
+ "m11_s03_connectivity": 1,
+ "m11_s04_connectivity": 1,
+ "m11_s05_connectivity": 1,
+ "m11_s06_connectivity": 1,
+ "m11_s07_connectivity": 1,
+ "m11_s08_connectivity": 1,
+ "m11_s09_connectivity": 1,
+ "m11_s10_connectivity": 1,
+ "m11_s11_connectivity": 1,
+ "m11_s12_connectivity": 1,
+ "m11_s13_connectivity": 1,
+ "m11_s14_connectivity": 1,
+ "m11_s15_connectivity": 1,
+ "m12_s00_connectivity": 1,
+ "m12_s01_connectivity": 1,
+ "m12_s02_connectivity": 1,
+ "m12_s03_connectivity": 1,
+ "m12_s04_connectivity": 1,
+ "m12_s05_connectivity": 1,
+ "m12_s06_connectivity": 1,
+ "m12_s07_connectivity": 1,
+ "m12_s08_connectivity": 1,
+ "m12_s09_connectivity": 1,
+ "m12_s10_connectivity": 1,
+ "m12_s11_connectivity": 1,
+ "m12_s12_connectivity": 1,
+ "m12_s13_connectivity": 1,
+ "m12_s14_connectivity": 1,
+ "m12_s15_connectivity": 1,
+ "m13_s00_connectivity": 1,
+ "m13_s01_connectivity": 1,
+ "m13_s02_connectivity": 1,
+ "m13_s03_connectivity": 1,
+ "m13_s04_connectivity": 1,
+ "m13_s05_connectivity": 1,
+ "m13_s06_connectivity": 1,
+ "m13_s07_connectivity": 1,
+ "m13_s08_connectivity": 1,
+ "m13_s09_connectivity": 1,
+ "m13_s10_connectivity": 1,
+ "m13_s11_connectivity": 1,
+ "m13_s12_connectivity": 1,
+ "m13_s13_connectivity": 1,
+ "m13_s14_connectivity": 1,
+ "m13_s15_connectivity": 1,
+ "m14_s00_connectivity": 1,
+ "m14_s01_connectivity": 1,
+ "m14_s02_connectivity": 1,
+ "m14_s03_connectivity": 1,
+ "m14_s04_connectivity": 1,
+ "m14_s05_connectivity": 1,
+ "m14_s06_connectivity": 1,
+ "m14_s07_connectivity": 1,
+ "m14_s08_connectivity": 1,
+ "m14_s09_connectivity": 1,
+ "m14_s10_connectivity": 1,
+ "m14_s11_connectivity": 1,
+ "m14_s12_connectivity": 1,
+ "m14_s13_connectivity": 1,
+ "m14_s14_connectivity": 1,
+ "m14_s15_connectivity": 1,
+ "m15_s00_connectivity": 1,
+ "m15_s01_connectivity": 1,
+ "m15_s02_connectivity": 1,
+ "m15_s03_connectivity": 1,
+ "m15_s04_connectivity": 1,
+ "m15_s05_connectivity": 1,
+ "m15_s06_connectivity": 1,
+ "m15_s07_connectivity": 1,
+ "m15_s08_connectivity": 1,
+ "m15_s09_connectivity": 1,
+ "m15_s10_connectivity": 1,
+ "m15_s11_connectivity": 1,
+ "m15_s12_connectivity": 1,
+ "m15_s13_connectivity": 1,
+ "m15_s14_connectivity": 1,
+ "m15_s15_connectivity": 1,
+ "component_name": "design_1_xbar_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684420096,
+ "c_highaddr": 2684485631
+ },
+ "ports": [
+ {
+ "role": "slave",
+ "target": "axi_dma_0:MM2S",
+ "name": "S00_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "axi_dma_0:S2MM",
+ "name": "M00_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S01_AXIS",
+ "name": "M01_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M01_AXIS",
+ "name": "S01_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M01_AXIS",
+ "name": "S01_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S01_AXIS",
+ "name": "M01_AXIS"
+ }
+ ],
+ "num_ports": 2
+ },
+ "zynq_ultra_ps_e_0": {
+ "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3",
+ "memory-view": {
+ "M_AXI_HPM0_FPD": {
+ "axi_dma_0": {
+ "Reg": {
+ "baseaddr": 2684354560,
+ "highaddr": 2684420095,
+ "size": 65536
+ }
+ },
+ "axis_interconnect_0_xbar": {
+ "Reg": {
+ "baseaddr": 2684420096,
+ "highaddr": 2684485631,
+ "size": 65536
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json b/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json
new file mode 100644
index 000000000..dfbd1fed9
--- /dev/null
+++ b/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json
@@ -0,0 +1,2472 @@
+{
+ "aurora_aurora_8b10b_0": {
+ "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
+ "parameters": {
+ "component_name": "design_1_aurora_8b10b_0_1",
+ "channel_enable": "X0Y10",
+ "c_refclk_loc_p": "W10",
+ "c_refclk_loc_n": "W9",
+ "c_column_used": "left",
+ "c_ucolumn_used": "right",
+ "c_family": "zynquplus",
+ "c_device": "xczu7ev",
+ "c_row_used": "None",
+ "c_xpackage": "ffvc1156",
+ "c_xspeedgrade": -2,
+ "c_aurora_lanes": 1,
+ "c_lane_width": 2,
+ "c_active_transceiverquads": 1,
+ "c_start_quad": "Quad_X0Y2",
+ "c_start_lane": "X0Y10",
+ "c_refclk_source": "X0Y10 clk1",
+ "interface_mode": "Framing",
+ "c_stream": "false",
+ "dataflow_config": "Duplex",
+ "backchannel_mode": "Sidebands",
+ "c_simplex": "false",
+ "c_simplex_mode": "TX",
+ "flow_mode": "None",
+ "c_nfc": "false",
+ "c_nfc_mode": "IMM",
+ "c_ufc": "false",
+ "c_example_simulation": "false",
+ "c_gtwiz_out": "false",
+ "c_line_rate": 2,
+ "cc_line_rate": 2,
+ "c_refclk_frequency": 250,
+ "cc_refclk_frequency": 250,
+ "c_init_clk": "99.990005",
+ "drp_freq": "50.0000",
+ "c_gt_loc_1": 1,
+ "c_gt_loc_2": "X",
+ "c_gt_loc_3": "X",
+ "c_gt_loc_4": "X",
+ "c_gt_loc_5": "X",
+ "c_gt_loc_6": "X",
+ "c_gt_loc_7": "X",
+ "c_gt_loc_8": "X",
+ "c_gt_loc_9": "X",
+ "c_gt_loc_10": "X",
+ "c_gt_loc_11": "X",
+ "c_gt_loc_12": "X",
+ "c_gt_loc_13": "X",
+ "c_gt_loc_14": "X",
+ "c_gt_loc_15": "X",
+ "c_gt_loc_16": "X",
+ "c_gt_loc_17": "X",
+ "c_gt_loc_18": "X",
+ "c_gt_loc_19": "X",
+ "c_gt_loc_20": "X",
+ "c_gt_loc_21": "X",
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+ "c_gt_loc_23": "X",
+ "c_gt_loc_24": "X",
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+ "c_gt_loc_33": "X",
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+ "c_gt_loc_42": "X",
+ "c_gt_loc_43": "X",
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+ "c_gt_loc_45": "X",
+ "c_gt_loc_46": "X",
+ "c_gt_loc_47": "X",
+ "c_gt_loc_48": "X",
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+ "c_gt_clock_2": "None",
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+ "c_use_chipscope": "false",
+ "c_drp_if": "false",
+ "transceivercontrol": "false",
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+ "supportlevel": 1,
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+ "c_cpll_fbdiv": 1,
+ "c_cpll_fbdiv_45": 5,
+ "c_cpll_refclk_div": 1,
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+ "user_interface": "AXI_4_Streaming",
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+ "c_ufcrembuswidthselect": 1,
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+ "isv7gth": "false",
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+ "port7dmonitorout": 7,
+ "is_7series": "false",
+ "singleend_initclk": "true",
+ "singleend_gtrefclk": "false",
+ "c_double_gtrxreset": "false",
+ "c_doccport_enable": "false",
+ "is_board": "zcu106",
+ "usdrpaddr_width": 9,
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+ "rx_eq_mode": "AUTO",
+ "rx_coupling": "AC",
+ "rx_termination": "PROGRAMMABLE",
+ "rx_termination_prog_value": 800,
+ "rx_ppm_offset": 200,
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S02_AXIS",
+ "name": "USER_DATA_M_AXI_RX"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M02_AXIS",
+ "name": "USER_DATA_S_AXI_TX"
+ }
+ ]
+ },
+ "axi_iic_0": {
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+ "parameters": {
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+ "c_s_axi_data_width": 32,
+ "c_iic_freq": 100000,
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+ "c_default_value": 0,
+ "component_name": "design_1_axi_iic_0_0",
+ "ten_bit_adr": "7_bit",
+ "axi_aclk_freq_mhz": "99.990005",
+ "iic_freq_khz": 100,
+ "use_board_flow": "false",
+ "iic_board_interface": "Custom",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684551168,
+ "c_highaddr": 2684616703
+ }
+ },
+ "axis_interconnect_0_xbar": {
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+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684420096,
+ "c_highaddr": 2684485631
+ },
+ "ports": [
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+ "target": "zynq_axi_dma_0:MM2S",
+ "name": "S00_AXIS"
+ },
+ {
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+ "target": "zynq_axi_dma_0:S2MM",
+ "name": "M00_AXIS"
+ },
+ {
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+ "target": "dino_dinoif_fast_nologic_0:M00_AXIS",
+ "name": "S01_AXIS"
+ },
+ {
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+ "target": "dino_dinoif_dac_0:S00_AXIS",
+ "name": "M01_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "aurora_aurora_8b10b_0:USER_DATA_M_AXI_RX",
+ "name": "S02_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "aurora_aurora_8b10b_0:USER_DATA_S_AXI_TX",
+ "name": "M02_AXIS"
+ },
+ {
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+ "target": "axis_interconnect_0_xbar:S03_AXIS",
+ "name": "S03_AXIS"
+ },
+ {
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+ "target": "axis_interconnect_0_xbar:S03_AXIS",
+ "name": "S03_AXIS"
+ },
+ {
+ "role": "target",
+ "target": "axis_interconnect_0_xbar:M03_AXIS",
+ "name": "S03_AXIS"
+ },
+ {
+ "role": "initiator",
+ "target": "axis_interconnect_0_xbar:S03_AXIS",
+ "name": "M03_AXIS"
+ }
+ ],
+ "num_ports": 4
+ },
+ "dino_dinoif_dac_0": {
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+ "i2c_channel": 1,
+ "parameters": {
+ "component_name": "design_1_dinoif_dac_0_0",
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M01_AXIS",
+ "name": "S00_AXIS"
+ }
+ ]
+ },
+ "dino_dinoif_fast_nologic_0": {
+ "vlnv": "xilinx.com:module_ref:dinoif_fast_nologic:1.0",
+ "i2c_channel": 0,
+ "parameters": {
+ "component_name": "design_1_dinoif_fast_nologic_0_0",
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S01_AXIS",
+ "name": "M00_AXIS"
+ }
+ ]
+ },
+ "dino_registerif_0": {
+ "vlnv": "xilinx.com:module_ref:registerif:1.0",
+ "parameters": {
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+ "c_axi_addr_width": 32,
+ "reg_addr_width": 10,
+ "component_name": "design_1_registerif_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684485632,
+ "c_highaddr": 2684551167
+ }
+ },
+ "zynq_axi_dma_0": {
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+ "parameters": {
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+ "c_s_axi_lite_data_width": 32,
+ "c_dlytmr_resolution": 125,
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+ "c_m_axi_sg_addr_width": 64,
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+ "c_m_axis_mm2s_cntrl_tdata_width": 32,
+ "c_s_axis_s2mm_sts_tdata_width": 32,
+ "c_micro_dma": 0,
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+ "c_s2mm_burst_size": 16,
+ "c_m_axi_s2mm_addr_width": 64,
+ "c_m_axi_s2mm_data_width": 128,
+ "c_s_axis_s2mm_tdata_width": 128,
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+ "c_increase_throughput": 0,
+ "c_family": "zynquplus",
+ "component_name": "design_1_axi_dma_0_0",
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+ "c_single_interface": 0,
+ "edk_iptype": "PERIPHERAL",
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+ "c_highaddr": 2684420095
+ },
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+ "highaddr": 1152921508364943359,
+ "size": 536870912
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+ "size": 34359738368
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+ "highaddr": 1152921508364943359,
+ "size": 536870912
+ }
+ }
+ },
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+ "size": 2147483648
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+ "size": 34359738368
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+ "highaddr": 1152921508364943359,
+ "size": 536870912
+ }
+ }
+ }
+ },
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+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S00_AXIS",
+ "name": "MM2S"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M00_AXIS",
+ "name": "S2MM"
+ }
+ ]
+ },
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+ "psu__protection__debug": 0,
+ "psu__protection__slaves": "LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1",
+ "psu__protection__presubsystems": "NONE",
+ "psu__protection__enable": 0,
+ "psu__ddr_sw_refresh_enabled": 1,
+ "psu__protection__lock_unused_segments": 0,
+ "psu__ep__ip": 0,
+ "psu__actual__ip": 1,
+ "subpreset1": "Custom",
+ "subpreset2": "Custom",
+ "psu_uiparam_generate_summary": "<Select>",
+ "psu_mio_tree_peripherals": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3",
+ "psu_mio_tree_signals": "sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out",
+ "psu_peripheral_board_preset": null,
+ "psu__nand__peripheral__io": "<Select>",
+ "psu__nand__peripheral__enable": 0,
+ "psu__nand__ready_busy__enable": 0,
+ "psu__nand__ready0_busy__enable": 0,
+ "psu__nand__ready1_busy__enable": 0,
+ "psu__nand__ready_busy__io": "<Select>",
+ "psu__nand__ready0_busy__io": "<Select>",
+ "psu__nand__ready1_busy__io": "<Select>",
+ "psu__nand__chip_enable__enable": 0,
+ "psu__nand__chip_enable__io": "<Select>",
+ "psu__nand__data_strobe__enable": 0,
+ "psu__nand__data_strobe__io": "<Select>",
+ "psu__pjtag__peripheral__enable": 0,
+ "psu__pjtag__peripheral__io": "<Select>",
+ "psu__pmu__aiback__enable": 0,
+ "psu__pmu__plerror__enable": 0,
+ "psu__pmu__peripheral__enable": 1,
+ "psu__pmu__peripheral__io": "<Select>",
+ "psu__pmu__emio_gpi__enable": 0,
+ "psu__pmu__emio_gpo__enable": 0,
+ "psu__pmu__gpi0__enable": 0,
+ "psu__pmu__gpi1__enable": 0,
+ "psu__pmu__gpi2__enable": 0,
+ "psu__pmu__gpi3__enable": 0,
+ "psu__pmu__gpi4__enable": 0,
+ "psu__pmu__gpi5__enable": 0,
+ "psu__pmu__gpo0__enable": 1,
+ "psu__pmu__gpo1__enable": 1,
+ "psu__pmu__gpo2__enable": 1,
+ "psu__pmu__gpo3__enable": 1,
+ "psu__pmu__gpo4__enable": 1,
+ "psu__pmu__gpo5__enable": 1,
+ "psu__pmu__gpi0__io": "<Select>",
+ "psu__pmu__gpi1__io": "<Select>",
+ "psu__pmu__gpi2__io": "<Select>",
+ "psu__pmu__gpi3__io": "<Select>",
+ "psu__pmu__gpi4__io": "<Select>",
+ "psu__pmu__gpi5__io": "<Select>",
+ "psu__pmu__gpo0__io": "MIO 32",
+ "psu__pmu__gpo1__io": "MIO 33",
+ "psu__pmu__gpo2__io": "MIO 34",
+ "psu__pmu__gpo3__io": "MIO 35",
+ "psu__pmu__gpo4__io": "MIO 36",
+ "psu__pmu__gpo5__io": "MIO 37",
+ "psu__pmu__gpo2__polarity": "low",
+ "psu__pmu__gpo3__polarity": "low",
+ "psu__pmu__gpo4__polarity": "low",
+ "psu__pmu__gpo5__polarity": "low",
+ "psu__csu__peripheral__enable": 0,
+ "psu__csu__peripheral__io": "<Select>",
+ "psu__qspi__peripheral__enable": 1,
+ "psu__qspi__peripheral__io": "MIO 0 .. 12",
+ "psu__qspi__peripheral__mode": "Dual Parallel",
+ "psu__qspi__peripheral__data_mode": "x4",
+ "psu__qspi__grp_fbclk__enable": 1,
+ "psu__qspi__grp_fbclk__io": "MIO 6",
+ "psu__sd0__peripheral__enable": 0,
+ "psu__sd0__peripheral__io": "<Select>",
+ "psu__sd0__grp_cd__enable": 0,
+ "psu__sd0__grp_cd__io": "<Select>",
+ "psu__sd0__grp_pow__enable": 0,
+ "psu__sd0__grp_pow__io": "<Select>",
+ "psu__sd0__grp_wp__enable": 0,
+ "psu__sd0__grp_wp__io": "<Select>",
+ "psu__sd0__slot_type": "<Select>",
+ "psu__sd0__reset__enable": 0,
+ "psu__sd0__data_transfer_mode": "<Select>",
+ "psu__sd1__peripheral__enable": 1,
+ "psu__sd1__peripheral__io": "MIO 39 .. 51",
+ "psu__sd1__grp_cd__enable": 1,
+ "psu__sd1__grp_cd__io": "MIO 45",
+ "psu__sd1__grp_pow__enable": 1,
+ "psu__sd1__grp_pow__io": "MIO 43",
+ "psu__sd1__grp_wp__enable": 1,
+ "psu__sd1__grp_wp__io": "MIO 44",
+ "psu__sd1__slot_type": "SD 3.0",
+ "psu__sd1__reset__enable": 0,
+ "psu__sd1__data_transfer_mode": "8Bit",
+ "psu__device_type": "EV",
+ "psu_smc_cycle_t0": "NA",
+ "psu_smc_cycle_t1": "NA",
+ "psu_smc_cycle_t2": "NA",
+ "psu_smc_cycle_t3": "NA",
+ "psu_smc_cycle_t4": "NA",
+ "psu_smc_cycle_t5": "NA",
+ "psu_smc_cycle_t6": "NA",
+ "psu__spi0__peripheral__enable": 0,
+ "psu__spi0__peripheral__io": "<Select>",
+ "psu__spi0__grp_ss0__enable": 0,
+ "psu__spi0__grp_ss0__io": "<Select>",
+ "psu__spi0__grp_ss1__enable": 0,
+ "psu__spi0__grp_ss1__io": "<Select>",
+ "psu__spi0__grp_ss2__enable": 0,
+ "psu__spi0__grp_ss2__io": "<Select>",
+ "psu__spi1__peripheral__enable": 0,
+ "psu__spi1__peripheral__io": "<Select>",
+ "psu__spi1__grp_ss0__enable": 0,
+ "psu__spi1__grp_ss0__io": "<Select>",
+ "psu__spi1__grp_ss1__enable": 0,
+ "psu__spi1__grp_ss1__io": "<Select>",
+ "psu__spi1__grp_ss2__enable": 0,
+ "psu__spi1__grp_ss2__io": "<Select>",
+ "psu__spi0_loop_spi1__enable": 0,
+ "psu__lpd_slcr__csupmu_wdt_clk_sel__select": "APB",
+ "psu__swdt0__peripheral__enable": 1,
+ "psu__swdt0__clock__enable": 0,
+ "psu__swdt0__reset__enable": 0,
+ "psu__swdt0__peripheral__io": "NA",
+ "psu__swdt0__clock__io": "<Select>",
+ "psu__swdt0__reset__io": "<Select>",
+ "psu__swdt1__peripheral__enable": 1,
+ "psu__swdt1__clock__enable": 0,
+ "psu__swdt1__reset__enable": 0,
+ "psu__swdt1__peripheral__io": "NA",
+ "psu__swdt1__clock__io": "<Select>",
+ "psu__swdt1__reset__io": "<Select>",
+ "psu__uart0__baud_rate": 115200,
+ "psu__trace__peripheral__enable": 0,
+ "psu__trace__peripheral__io": "<Select>",
+ "psu__trace__width": "<Select>",
+ "psu__trace__internal_width": 32,
+ "psu_sd0_internal_bus_width": 8,
+ "psu__ttc0__peripheral__enable": 1,
+ "psu__ttc0__clock__enable": 0,
+ "psu__ttc0__waveout__enable": 0,
+ "psu__ttc0__clock__io": "<Select>",
+ "psu__ttc0__waveout__io": "<Select>",
+ "psu__ttc0__peripheral__io": "NA",
+ "psu__ttc1__peripheral__enable": 1,
+ "psu__ttc1__peripheral__io": "NA",
+ "psu__uart1__baud_rate": 115200,
+ "psu__ttc1__clock__enable": 0,
+ "psu__ttc1__waveout__enable": 0,
+ "psu__ttc1__clock__io": "<Select>",
+ "psu__ttc1__waveout__io": "<Select>",
+ "psu__ttc2__peripheral__enable": 1,
+ "psu__ttc2__peripheral__io": "NA",
+ "psu__ttc2__clock__enable": 0,
+ "psu__ttc2__waveout__enable": 0,
+ "psu__ttc2__clock__io": "<Select>",
+ "psu__ttc2__waveout__io": "<Select>",
+ "psu__ttc3__peripheral__enable": 1,
+ "psu__ttc3__peripheral__io": "NA",
+ "psu__ttc3__clock__enable": 0,
+ "psu__ttc3__waveout__enable": 0,
+ "psu__ttc3__clock__io": "<Select>",
+ "psu__ttc3__waveout__io": "<Select>",
+ "psu__csupmu__peripheral__valid": 1,
+ "psu__ddrc__al": 0,
+ "psu__ddrc__bank_addr_count": 2,
+ "psu__ddrc__bus_width": "64 Bit",
+ "psu__ddrc__cl": 15,
+ "psu__ddrc__clock_stop_en": 0,
+ "psu_dynamic_ddr_config_en": 1,
+ "psu__ddrc__col_addr_count": 10,
+ "psu__ddrc__rank_addr_count": 0,
+ "psu__ddrc__cwl": 14,
+ "psu__ddrc__bg_addr_count": 2,
+ "psu__ddrc__device_capacity": "4096 MBits",
+ "psu__ddrc__dram_width": "8 Bits",
+ "psu__ddrc__ecc": "Disabled",
+ "psu__ddrc__ecc_scrub": 0,
+ "psu__ddrc__enable": 1,
+ "psu__ddrc__freq_mhz": 1,
+ "psu__ddrc__high_temp": "<Select>",
+ "psu__ddrc__memory_type": "DDR 4",
+ "psu__ddrc__partno": "<Select>",
+ "psu__ddrc__row_addr_count": 15,
+ "psu__ddrc__speed_bin": "DDR4_2133P",
+ "psu__ddrc__t_faw": "30.0",
+ "psu__ddrc__t_ras_min": 33,
+ "psu__ddrc__t_rc": "47.06",
+ "psu__ddrc__t_rcd": 15,
+ "psu__ddrc__t_rp": 15,
+ "psu__ddrc__train_data_eye": 1,
+ "psu__ddrc__train_read_gate": 1,
+ "psu__ddrc__train_write_level": 1,
+ "psu__ddrc__vref": 1,
+ "psu__ddrc__video_buffer_size": 0,
+ "psu__ddrc__brc_mapping": "ROW_BANK_COL",
+ "psu__ddrc__dimm_addr_mirror": 0,
+ "psu__ddrc__static_rd_mode": 0,
+ "psu__ddrc__ddr4_maxpwr_saving_en": 0,
+ "psu__ddrc__pwr_down_en": 0,
+ "psu__ddrc__deep_pwr_down_en": 0,
+ "psu__ddrc__pll_bypass": 0,
+ "psu__ddrc__ddr4_t_ref_mode": 0,
+ "psu__ddrc__ddr4_t_ref_range": "Normal (0-85)",
+ "psu__ddrc__ddr3_t_ref_range": "NA",
+ "psu__ddrc__ddr3l_t_ref_range": "NA",
+ "psu__ddrc__lpddr3_t_ref_range": "NA",
+ "psu__ddrc__lpddr4_t_ref_range": "NA",
+ "psu__ddrc__phy_dbi_mode": 0,
+ "psu__ddrc__dm_dbi": "DM_NO_DBI",
+ "psu__ddrc__components": "UDIMM",
+ "psu__ddrc__parity_enable": 0,
+ "psu__ddrc__ddr4_cal_mode_enable": 0,
+ "psu__ddrc__ddr4_crc_control": 0,
+ "psu__ddrc__fgrm": "1X",
+ "psu__ddrc__vendor_part": "OTHERS",
+ "psu__ddrc__sb_target": "15-15-15",
+ "psu__ddrc__lp_asr": "manual normal",
+ "psu__ddrc__ddr4_addr_mapping": 0,
+ "psu__ddrc__self_ref_abort": 0,
+ "psu__ddrc__derate_int_d": "<Select>",
+ "psu__ddrc__addr_mirror": 0,
+ "psu__ddrc__en_2nd_clk": 0,
+ "psu__ddrc__lpddr3_dualrank_sdp": 0,
+ "psu__ddrc__per_bank_refresh": 0,
+ "psu__ddrc__enable_dp_switch": 0,
+ "psu__ddrc__enable_lp4_slowboot": 0,
+ "psu__ddrc__enable_lp4_has_ecc_comp": 0,
+ "psu__ddrc__enable_2t_timing": 0,
+ "psu__ddrc__rd_dqs_center": 0,
+ "psu__ddrc__dqmap_0_3": 0,
+ "psu__ddrc__dqmap_4_7": 0,
+ "psu__ddrc__dqmap_8_11": 0,
+ "psu__ddrc__dqmap_12_15": 0,
+ "psu__ddrc__dqmap_16_19": 0,
+ "psu__ddrc__dqmap_20_23": 0,
+ "psu__ddrc__dqmap_24_27": 0,
+ "psu__ddrc__dqmap_28_31": 0,
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+ "psu_mio_35_polarity": "Default",
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+ "psu_mio_38_direction": "inout",
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+ "psu_mio_39_polarity": "Default",
+ "psu_mio_39_input_type": "cmos",
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+ "psu_mio_39_direction": "inout",
+ "psu_mio_40_pullupdown": "pullup",
+ "psu_mio_40_drive_strength": 12,
+ "psu_mio_40_polarity": "Default",
+ "psu_mio_40_input_type": "cmos",
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+ "psu_mio_40_direction": "inout",
+ "psu_mio_41_pullupdown": "pullup",
+ "psu_mio_41_drive_strength": 12,
+ "psu_mio_41_polarity": "Default",
+ "psu_mio_41_input_type": "cmos",
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+ "psu_mio_41_direction": "inout",
+ "psu_mio_42_pullupdown": "pullup",
+ "psu_mio_42_drive_strength": 12,
+ "psu_mio_42_polarity": "Default",
+ "psu_mio_42_input_type": "cmos",
+ "psu_mio_42_slew": "fast",
+ "psu_mio_42_direction": "inout",
+ "psu_mio_43_pullupdown": "pullup",
+ "psu_mio_43_drive_strength": 12,
+ "psu_mio_43_polarity": "Default",
+ "psu_mio_43_input_type": "cmos",
+ "psu_mio_43_slew": "fast",
+ "psu_mio_43_direction": "out",
+ "psu_mio_44_pullupdown": "pullup",
+ "psu_mio_44_drive_strength": 12,
+ "psu_mio_44_polarity": "Default",
+ "psu_mio_44_input_type": "cmos",
+ "psu_mio_44_slew": "fast",
+ "psu_mio_44_direction": "in",
+ "psu_mio_45_pullupdown": "pullup",
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