From 0ce4e67bedf88894e67cc9843a57a7e850168697 Mon Sep 17 00:00:00 2001
From: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Date: Mon, 26 Aug 2024 13:02:25 +0200
Subject: [PATCH] add bitstreams

---
 etc/fpga/zcu106-smmu/zcu106-smmu.json         |  509 ++++
 .../zcu106_aurora_dino_240808-2.json          | 2472 +++++++++++++++++
 2 files changed, 2981 insertions(+)
 create mode 100644 etc/fpga/zcu106-smmu/zcu106-smmu.json
 create mode 100644 etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json

diff --git a/etc/fpga/zcu106-smmu/zcu106-smmu.json b/etc/fpga/zcu106-smmu/zcu106-smmu.json
new file mode 100644
index 000000000..7a124ea09
--- /dev/null
+++ b/etc/fpga/zcu106-smmu/zcu106-smmu.json
@@ -0,0 +1,509 @@
+{
+  "axi_dma_0": {
+    "vlnv": "xilinx.com:ip:axi_dma:7.1",
+    "parameters": {
+      "c_s_axi_lite_addr_width": 10,
+      "c_s_axi_lite_data_width": 32,
+      "c_dlytmr_resolution": 125,
+      "c_prmry_is_aclk_async": 0,
+      "c_enable_multi_channel": 0,
+      "c_num_mm2s_channels": 1,
+      "c_num_s2mm_channels": 1,
+      "c_include_sg": 1,
+      "c_sg_include_stscntrl_strm": 0,
+      "c_sg_use_stsapp_length": 0,
+      "c_sg_length_width": 23,
+      "c_m_axi_sg_addr_width": 64,
+      "c_m_axi_sg_data_width": 32,
+      "c_m_axis_mm2s_cntrl_tdata_width": 32,
+      "c_s_axis_s2mm_sts_tdata_width": 32,
+      "c_micro_dma": 0,
+      "c_include_mm2s": 1,
+      "c_include_mm2s_sf": 1,
+      "c_mm2s_burst_size": 16,
+      "c_m_axi_mm2s_addr_width": 64,
+      "c_m_axi_mm2s_data_width": 128,
+      "c_m_axis_mm2s_tdata_width": 128,
+      "c_include_mm2s_dre": 0,
+      "c_include_s2mm": 1,
+      "c_include_s2mm_sf": 1,
+      "c_s2mm_burst_size": 16,
+      "c_m_axi_s2mm_addr_width": 64,
+      "c_m_axi_s2mm_data_width": 128,
+      "c_s_axis_s2mm_tdata_width": 128,
+      "c_include_s2mm_dre": 0,
+      "c_increase_throughput": 0,
+      "c_family": "zynquplus",
+      "component_name": "design_1_axi_dma_0_0",
+      "c_addr_width": 64,
+      "c_single_interface": 0,
+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 2684354560,
+      "c_highaddr": 2684420095
+    },
+    "memory-view": {
+      "M_AXI_SG": {
+        "zynq_ultra_ps_e_0": {
+          "HPC1_DDR_LOW": {
+            "baseaddr": 0,
+            "highaddr": 2147483647,
+            "size": 2147483648
+          },
+          "HPC1_QSPI": {
+            "baseaddr": 3221225472,
+            "highaddr": 3758096383,
+            "size": 536870912
+          },
+          "HPC1_DDR_HIGH": {
+            "baseaddr": 34359738368,
+            "highaddr": 68719476735,
+            "size": 34359738368
+          }
+        }
+      },
+      "M_AXI_MM2S": {
+        "zynq_ultra_ps_e_0": {
+          "HPC0_DDR_LOW": {
+            "baseaddr": 0,
+            "highaddr": 2147483647,
+            "size": 2147483648
+          },
+          "HPC0_QSPI": {
+            "baseaddr": 3221225472,
+            "highaddr": 3758096383,
+            "size": 536870912
+          },
+          "HPC0_DDR_HIGH": {
+            "baseaddr": 34359738368,
+            "highaddr": 68719476735,
+            "size": 34359738368
+          }
+        }
+      },
+      "M_AXI_S2MM": {
+        "zynq_ultra_ps_e_0": {
+          "HPC0_DDR_LOW": {
+            "baseaddr": 0,
+            "highaddr": 2147483647,
+            "size": 2147483648
+          },
+          "HPC0_QSPI": {
+            "baseaddr": 3221225472,
+            "highaddr": 3758096383,
+            "size": 536870912
+          },
+          "HPC0_DDR_HIGH": {
+            "baseaddr": 34359738368,
+            "highaddr": 68719476735,
+            "size": 34359738368
+          }
+        }
+      }
+    },
+    "ports": [
+      {
+        "role": "master",
+        "target": "axis_interconnect_0_xbar:S00_AXIS",
+        "name": "MM2S"
+      },
+      {
+        "role": "slave",
+        "target": "axis_interconnect_0_xbar:M00_AXIS",
+        "name": "S2MM"
+      }
+    ]
+  },
+  "axis_interconnect_0_xbar": {
+    "vlnv": "xilinx.com:ip:axis_switch:1.1",
+    "parameters": {
+      "c_family": "zynquplus",
+      "c_num_si_slots": 2,
+      "c_log_si_slots": 1,
+      "c_num_mi_slots": 2,
+      "c_axis_tdata_width": 128,
+      "c_axis_tid_width": 1,
+      "c_axis_tdest_width": 1,
+      "c_axis_tuser_width": 1,
+      "c_axis_signal_set": 91,
+      "c_arb_on_max_xfers": 1,
+      "c_arb_on_num_cycles": 0,
+      "c_arb_on_tlast": 0,
+      "c_include_arbiter": 1,
+      "c_arb_algorithm": 0,
+      "c_output_reg": 0,
+      "c_decoder_reg": 1,
+      "c_m_axis_connectivity_array": 15,
+      "c_m_axis_basetdest_array": 2,
+      "c_m_axis_hightdest_array": 2,
+      "c_routing_mode": 1,
+      "c_s_axi_ctrl_addr_width": 7,
+      "c_s_axi_ctrl_data_width": 32,
+      "c_common_clock": 0,
+      "num_si": 2,
+      "num_mi": 2,
+      "routing_mode": 1,
+      "has_tready": 1,
+      "tdata_num_bytes": 16,
+      "has_tstrb": 0,
+      "has_tkeep": 1,
+      "has_tlast": 1,
+      "tid_width": 0,
+      "tdest_width": 1,
+      "tuser_width": 0,
+      "has_aclken": 0,
+      "arb_on_max_xfers": 1,
+      "arb_on_num_cycles": 0,
+      "arb_on_tlast": 0,
+      "arb_algorithm": 0,
+      "decoder_reg": 1,
+      "output_reg": 0,
+      "common_clock": 0,
+      "m00_axis_basetdest": 0,
+      "m01_axis_basetdest": 1,
+      "m02_axis_basetdest": 2,
+      "m03_axis_basetdest": 3,
+      "m04_axis_basetdest": 4,
+      "m05_axis_basetdest": 5,
+      "m06_axis_basetdest": 6,
+      "m07_axis_basetdest": 7,
+      "m08_axis_basetdest": 8,
+      "m09_axis_basetdest": 9,
+      "m10_axis_basetdest": 10,
+      "m11_axis_basetdest": 11,
+      "m12_axis_basetdest": 12,
+      "m13_axis_basetdest": 13,
+      "m14_axis_basetdest": 14,
+      "m15_axis_basetdest": 15,
+      "m00_axis_hightdest": 0,
+      "m01_axis_hightdest": 1,
+      "m02_axis_hightdest": 2,
+      "m03_axis_hightdest": 3,
+      "m04_axis_hightdest": 4,
+      "m05_axis_hightdest": 5,
+      "m06_axis_hightdest": 6,
+      "m07_axis_hightdest": 7,
+      "m08_axis_hightdest": 8,
+      "m09_axis_hightdest": 9,
+      "m10_axis_hightdest": 10,
+      "m11_axis_hightdest": 11,
+      "m12_axis_hightdest": 12,
+      "m13_axis_hightdest": 13,
+      "m14_axis_hightdest": 14,
+      "m15_axis_hightdest": 15,
+      "m00_s00_connectivity": 1,
+      "m00_s01_connectivity": 1,
+      "m00_s02_connectivity": 1,
+      "m00_s03_connectivity": 1,
+      "m00_s04_connectivity": 1,
+      "m00_s05_connectivity": 1,
+      "m00_s06_connectivity": 1,
+      "m00_s07_connectivity": 1,
+      "m00_s08_connectivity": 1,
+      "m00_s09_connectivity": 1,
+      "m00_s10_connectivity": 1,
+      "m00_s11_connectivity": 1,
+      "m00_s12_connectivity": 1,
+      "m00_s13_connectivity": 1,
+      "m00_s14_connectivity": 1,
+      "m00_s15_connectivity": 1,
+      "m01_s00_connectivity": 1,
+      "m01_s01_connectivity": 1,
+      "m01_s02_connectivity": 1,
+      "m01_s03_connectivity": 1,
+      "m01_s04_connectivity": 1,
+      "m01_s05_connectivity": 1,
+      "m01_s06_connectivity": 1,
+      "m01_s07_connectivity": 1,
+      "m01_s08_connectivity": 1,
+      "m01_s09_connectivity": 1,
+      "m01_s10_connectivity": 1,
+      "m01_s11_connectivity": 1,
+      "m01_s12_connectivity": 1,
+      "m01_s13_connectivity": 1,
+      "m01_s14_connectivity": 1,
+      "m01_s15_connectivity": 1,
+      "m02_s00_connectivity": 1,
+      "m02_s01_connectivity": 1,
+      "m02_s02_connectivity": 1,
+      "m02_s03_connectivity": 1,
+      "m02_s04_connectivity": 1,
+      "m02_s05_connectivity": 1,
+      "m02_s06_connectivity": 1,
+      "m02_s07_connectivity": 1,
+      "m02_s08_connectivity": 1,
+      "m02_s09_connectivity": 1,
+      "m02_s10_connectivity": 1,
+      "m02_s11_connectivity": 1,
+      "m02_s12_connectivity": 1,
+      "m02_s13_connectivity": 1,
+      "m02_s14_connectivity": 1,
+      "m02_s15_connectivity": 1,
+      "m03_s00_connectivity": 1,
+      "m03_s01_connectivity": 1,
+      "m03_s02_connectivity": 1,
+      "m03_s03_connectivity": 1,
+      "m03_s04_connectivity": 1,
+      "m03_s05_connectivity": 1,
+      "m03_s06_connectivity": 1,
+      "m03_s07_connectivity": 1,
+      "m03_s08_connectivity": 1,
+      "m03_s09_connectivity": 1,
+      "m03_s10_connectivity": 1,
+      "m03_s11_connectivity": 1,
+      "m03_s12_connectivity": 1,
+      "m03_s13_connectivity": 1,
+      "m03_s14_connectivity": 1,
+      "m03_s15_connectivity": 1,
+      "m04_s00_connectivity": 1,
+      "m04_s01_connectivity": 1,
+      "m04_s02_connectivity": 1,
+      "m04_s03_connectivity": 1,
+      "m04_s04_connectivity": 1,
+      "m04_s05_connectivity": 1,
+      "m04_s06_connectivity": 1,
+      "m04_s07_connectivity": 1,
+      "m04_s08_connectivity": 1,
+      "m04_s09_connectivity": 1,
+      "m04_s10_connectivity": 1,
+      "m04_s11_connectivity": 1,
+      "m04_s12_connectivity": 1,
+      "m04_s13_connectivity": 1,
+      "m04_s14_connectivity": 1,
+      "m04_s15_connectivity": 1,
+      "m05_s00_connectivity": 1,
+      "m05_s01_connectivity": 1,
+      "m05_s02_connectivity": 1,
+      "m05_s03_connectivity": 1,
+      "m05_s04_connectivity": 1,
+      "m05_s05_connectivity": 1,
+      "m05_s06_connectivity": 1,
+      "m05_s07_connectivity": 1,
+      "m05_s08_connectivity": 1,
+      "m05_s09_connectivity": 1,
+      "m05_s10_connectivity": 1,
+      "m05_s11_connectivity": 1,
+      "m05_s12_connectivity": 1,
+      "m05_s13_connectivity": 1,
+      "m05_s14_connectivity": 1,
+      "m05_s15_connectivity": 1,
+      "m06_s00_connectivity": 1,
+      "m06_s01_connectivity": 1,
+      "m06_s02_connectivity": 1,
+      "m06_s03_connectivity": 1,
+      "m06_s04_connectivity": 1,
+      "m06_s05_connectivity": 1,
+      "m06_s06_connectivity": 1,
+      "m06_s07_connectivity": 1,
+      "m06_s08_connectivity": 1,
+      "m06_s09_connectivity": 1,
+      "m06_s10_connectivity": 1,
+      "m06_s11_connectivity": 1,
+      "m06_s12_connectivity": 1,
+      "m06_s13_connectivity": 1,
+      "m06_s14_connectivity": 1,
+      "m06_s15_connectivity": 1,
+      "m07_s00_connectivity": 1,
+      "m07_s01_connectivity": 1,
+      "m07_s02_connectivity": 1,
+      "m07_s03_connectivity": 1,
+      "m07_s04_connectivity": 1,
+      "m07_s05_connectivity": 1,
+      "m07_s06_connectivity": 1,
+      "m07_s07_connectivity": 1,
+      "m07_s08_connectivity": 1,
+      "m07_s09_connectivity": 1,
+      "m07_s10_connectivity": 1,
+      "m07_s11_connectivity": 1,
+      "m07_s12_connectivity": 1,
+      "m07_s13_connectivity": 1,
+      "m07_s14_connectivity": 1,
+      "m07_s15_connectivity": 1,
+      "m08_s00_connectivity": 1,
+      "m08_s01_connectivity": 1,
+      "m08_s02_connectivity": 1,
+      "m08_s03_connectivity": 1,
+      "m08_s04_connectivity": 1,
+      "m08_s05_connectivity": 1,
+      "m08_s06_connectivity": 1,
+      "m08_s07_connectivity": 1,
+      "m08_s08_connectivity": 1,
+      "m08_s09_connectivity": 1,
+      "m08_s10_connectivity": 1,
+      "m08_s11_connectivity": 1,
+      "m08_s12_connectivity": 1,
+      "m08_s13_connectivity": 1,
+      "m08_s14_connectivity": 1,
+      "m08_s15_connectivity": 1,
+      "m09_s00_connectivity": 1,
+      "m09_s01_connectivity": 1,
+      "m09_s02_connectivity": 1,
+      "m09_s03_connectivity": 1,
+      "m09_s04_connectivity": 1,
+      "m09_s05_connectivity": 1,
+      "m09_s06_connectivity": 1,
+      "m09_s07_connectivity": 1,
+      "m09_s08_connectivity": 1,
+      "m09_s09_connectivity": 1,
+      "m09_s10_connectivity": 1,
+      "m09_s11_connectivity": 1,
+      "m09_s12_connectivity": 1,
+      "m09_s13_connectivity": 1,
+      "m09_s14_connectivity": 1,
+      "m09_s15_connectivity": 1,
+      "m10_s00_connectivity": 1,
+      "m10_s01_connectivity": 1,
+      "m10_s02_connectivity": 1,
+      "m10_s03_connectivity": 1,
+      "m10_s04_connectivity": 1,
+      "m10_s05_connectivity": 1,
+      "m10_s06_connectivity": 1,
+      "m10_s07_connectivity": 1,
+      "m10_s08_connectivity": 1,
+      "m10_s09_connectivity": 1,
+      "m10_s10_connectivity": 1,
+      "m10_s11_connectivity": 1,
+      "m10_s12_connectivity": 1,
+      "m10_s13_connectivity": 1,
+      "m10_s14_connectivity": 1,
+      "m10_s15_connectivity": 1,
+      "m11_s00_connectivity": 1,
+      "m11_s01_connectivity": 1,
+      "m11_s02_connectivity": 1,
+      "m11_s03_connectivity": 1,
+      "m11_s04_connectivity": 1,
+      "m11_s05_connectivity": 1,
+      "m11_s06_connectivity": 1,
+      "m11_s07_connectivity": 1,
+      "m11_s08_connectivity": 1,
+      "m11_s09_connectivity": 1,
+      "m11_s10_connectivity": 1,
+      "m11_s11_connectivity": 1,
+      "m11_s12_connectivity": 1,
+      "m11_s13_connectivity": 1,
+      "m11_s14_connectivity": 1,
+      "m11_s15_connectivity": 1,
+      "m12_s00_connectivity": 1,
+      "m12_s01_connectivity": 1,
+      "m12_s02_connectivity": 1,
+      "m12_s03_connectivity": 1,
+      "m12_s04_connectivity": 1,
+      "m12_s05_connectivity": 1,
+      "m12_s06_connectivity": 1,
+      "m12_s07_connectivity": 1,
+      "m12_s08_connectivity": 1,
+      "m12_s09_connectivity": 1,
+      "m12_s10_connectivity": 1,
+      "m12_s11_connectivity": 1,
+      "m12_s12_connectivity": 1,
+      "m12_s13_connectivity": 1,
+      "m12_s14_connectivity": 1,
+      "m12_s15_connectivity": 1,
+      "m13_s00_connectivity": 1,
+      "m13_s01_connectivity": 1,
+      "m13_s02_connectivity": 1,
+      "m13_s03_connectivity": 1,
+      "m13_s04_connectivity": 1,
+      "m13_s05_connectivity": 1,
+      "m13_s06_connectivity": 1,
+      "m13_s07_connectivity": 1,
+      "m13_s08_connectivity": 1,
+      "m13_s09_connectivity": 1,
+      "m13_s10_connectivity": 1,
+      "m13_s11_connectivity": 1,
+      "m13_s12_connectivity": 1,
+      "m13_s13_connectivity": 1,
+      "m13_s14_connectivity": 1,
+      "m13_s15_connectivity": 1,
+      "m14_s00_connectivity": 1,
+      "m14_s01_connectivity": 1,
+      "m14_s02_connectivity": 1,
+      "m14_s03_connectivity": 1,
+      "m14_s04_connectivity": 1,
+      "m14_s05_connectivity": 1,
+      "m14_s06_connectivity": 1,
+      "m14_s07_connectivity": 1,
+      "m14_s08_connectivity": 1,
+      "m14_s09_connectivity": 1,
+      "m14_s10_connectivity": 1,
+      "m14_s11_connectivity": 1,
+      "m14_s12_connectivity": 1,
+      "m14_s13_connectivity": 1,
+      "m14_s14_connectivity": 1,
+      "m14_s15_connectivity": 1,
+      "m15_s00_connectivity": 1,
+      "m15_s01_connectivity": 1,
+      "m15_s02_connectivity": 1,
+      "m15_s03_connectivity": 1,
+      "m15_s04_connectivity": 1,
+      "m15_s05_connectivity": 1,
+      "m15_s06_connectivity": 1,
+      "m15_s07_connectivity": 1,
+      "m15_s08_connectivity": 1,
+      "m15_s09_connectivity": 1,
+      "m15_s10_connectivity": 1,
+      "m15_s11_connectivity": 1,
+      "m15_s12_connectivity": 1,
+      "m15_s13_connectivity": 1,
+      "m15_s14_connectivity": 1,
+      "m15_s15_connectivity": 1,
+      "component_name": "design_1_xbar_0",
+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 2684420096,
+      "c_highaddr": 2684485631
+    },
+    "ports": [
+      {
+        "role": "slave",
+        "target": "axi_dma_0:MM2S",
+        "name": "S00_AXIS"
+      },
+      {
+        "role": "master",
+        "target": "axi_dma_0:S2MM",
+        "name": "M00_AXIS"
+      },
+      {
+        "role": "master",
+        "target": "axis_interconnect_0_xbar:S01_AXIS",
+        "name": "M01_AXIS"
+      },
+      {
+        "role": "slave",
+        "target": "axis_interconnect_0_xbar:M01_AXIS",
+        "name": "S01_AXIS"
+      },
+      {
+        "role": "slave",
+        "target": "axis_interconnect_0_xbar:M01_AXIS",
+        "name": "S01_AXIS"
+      },
+      {
+        "role": "master",
+        "target": "axis_interconnect_0_xbar:S01_AXIS",
+        "name": "M01_AXIS"
+      }
+    ],
+    "num_ports": 2
+  },
+  "zynq_ultra_ps_e_0": {
+    "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3",
+    "memory-view": {
+      "M_AXI_HPM0_FPD": {
+        "axi_dma_0": {
+          "Reg": {
+            "baseaddr": 2684354560,
+            "highaddr": 2684420095,
+            "size": 65536
+          }
+        },
+        "axis_interconnect_0_xbar": {
+          "Reg": {
+            "baseaddr": 2684420096,
+            "highaddr": 2684485631,
+            "size": 65536
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json b/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json
new file mode 100644
index 000000000..dfbd1fed9
--- /dev/null
+++ b/etc/fpga/zcu106_aurora_dino/zcu106_aurora_dino_240808-2.json
@@ -0,0 +1,2472 @@
+{
+  "aurora_aurora_8b10b_0": {
+    "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
+    "parameters": {
+      "component_name": "design_1_aurora_8b10b_0_1",
+      "channel_enable": "X0Y10",
+      "c_refclk_loc_p": "W10",
+      "c_refclk_loc_n": "W9",
+      "c_column_used": "left",
+      "c_ucolumn_used": "right",
+      "c_family": "zynquplus",
+      "c_device": "xczu7ev",
+      "c_row_used": "None",
+      "c_xpackage": "ffvc1156",
+      "c_xspeedgrade": -2,
+      "c_aurora_lanes": 1,
+      "c_lane_width": 2,
+      "c_active_transceiverquads": 1,
+      "c_start_quad": "Quad_X0Y2",
+      "c_start_lane": "X0Y10",
+      "c_refclk_source": "X0Y10 clk1",
+      "interface_mode": "Framing",
+      "c_stream": "false",
+      "dataflow_config": "Duplex",
+      "backchannel_mode": "Sidebands",
+      "c_simplex": "false",
+      "c_simplex_mode": "TX",
+      "flow_mode": "None",
+      "c_nfc": "false",
+      "c_nfc_mode": "IMM",
+      "c_ufc": "false",
+      "c_example_simulation": "false",
+      "c_gtwiz_out": "false",
+      "c_line_rate": 2,
+      "cc_line_rate": 2,
+      "c_refclk_frequency": 250,
+      "cc_refclk_frequency": 250,
+      "c_init_clk": "99.990005",
+      "drp_freq": "50.0000",
+      "c_gt_loc_1": 1,
+      "c_gt_loc_2": "X",
+      "c_gt_loc_3": "X",
+      "c_gt_loc_4": "X",
+      "c_gt_loc_5": "X",
+      "c_gt_loc_6": "X",
+      "c_gt_loc_7": "X",
+      "c_gt_loc_8": "X",
+      "c_gt_loc_9": "X",
+      "c_gt_loc_10": "X",
+      "c_gt_loc_11": "X",
+      "c_gt_loc_12": "X",
+      "c_gt_loc_13": "X",
+      "c_gt_loc_14": "X",
+      "c_gt_loc_15": "X",
+      "c_gt_loc_16": "X",
+      "c_gt_loc_17": "X",
+      "c_gt_loc_18": "X",
+      "c_gt_loc_19": "X",
+      "c_gt_loc_20": "X",
+      "c_gt_loc_21": "X",
+      "c_gt_loc_22": "X",
+      "c_gt_loc_23": "X",
+      "c_gt_loc_24": "X",
+      "c_gt_loc_25": "X",
+      "c_gt_loc_26": "X",
+      "c_gt_loc_27": "X",
+      "c_gt_loc_28": "X",
+      "c_gt_loc_29": "X",
+      "c_gt_loc_30": "X",
+      "c_gt_loc_31": "X",
+      "c_gt_loc_32": "X",
+      "c_gt_loc_33": "X",
+      "c_gt_loc_34": "X",
+      "c_gt_loc_35": "X",
+      "c_gt_loc_36": "X",
+      "c_gt_loc_37": "X",
+      "c_gt_loc_38": "X",
+      "c_gt_loc_39": "X",
+      "c_gt_loc_40": "X",
+      "c_gt_loc_41": "X",
+      "c_gt_loc_42": "X",
+      "c_gt_loc_43": "X",
+      "c_gt_loc_44": "X",
+      "c_gt_loc_45": "X",
+      "c_gt_loc_46": "X",
+      "c_gt_loc_47": "X",
+      "c_gt_loc_48": "X",
+      "c_gt_clock_1": "GTHQ0",
+      "c_gt_clock_2": "None",
+      "c_use_scrambler": "false",
+      "c_use_chipscope": "false",
+      "c_drp_if": "false",
+      "transceivercontrol": "false",
+      "c_use_crc": "false",
+      "supportlevel": 1,
+      "c_use_byteswap": "false",
+      "c_cpll_fbdiv": 1,
+      "c_cpll_fbdiv_45": 5,
+      "c_cpll_refclk_div": 1,
+      "c_rxoutdiv": 1,
+      "c_txoutdiv": 1,
+      "user_interface": "AXI_4_Streaming",
+      "c_ufcbuswidthselect": 16,
+      "c_ufcrembuswidthselect": 1,
+      "c_ufcstrbbuswidthselect": 2,
+      "c_rembuswidthselect": 1,
+      "isv7gth": "false",
+      "gtquadcnt": 1,
+      "port7dmonitorout": 7,
+      "is_7series": "false",
+      "singleend_initclk": "true",
+      "singleend_gtrefclk": "false",
+      "c_double_gtrxreset": "false",
+      "c_doccport_enable": "false",
+      "is_board": "zcu106",
+      "usdrpaddr_width": 9,
+      "usdmon_width": 15,
+      "txdiffctrl_width": 4,
+      "ins_loss_nyq": 14,
+      "rx_eq_mode": "AUTO",
+      "rx_coupling": "AC",
+      "rx_termination": "PROGRAMMABLE",
+      "rx_termination_prog_value": 800,
+      "rx_ppm_offset": 200,
+      "edk_iptype": "PERIPHERAL"
+    },
+    "ports": [
+      {
+        "role": "master",
+        "target": "axis_interconnect_0_xbar:S02_AXIS",
+        "name": "USER_DATA_M_AXI_RX"
+      },
+      {
+        "role": "slave",
+        "target": "axis_interconnect_0_xbar:M02_AXIS",
+        "name": "USER_DATA_S_AXI_TX"
+      }
+    ]
+  },
+  "axi_iic_0": {
+    "vlnv": "xilinx.com:ip:axi_iic:2.1",
+    "parameters": {
+      "c_family": "zynquplus",
+      "c_s_axi_addr_width": 9,
+      "c_s_axi_data_width": 32,
+      "c_iic_freq": 100000,
+      "c_ten_bit_adr": 0,
+      "c_gpo_width": 1,
+      "c_s_axi_aclk_freq_hz": 99990005,
+      "c_scl_inertial_delay": 0,
+      "c_sda_inertial_delay": 0,
+      "c_sda_level": 1,
+      "c_smbus_pmbus_host": 0,
+      "c_disable_setup_violation_check": 0,
+      "c_static_timing_reg_width": 0,
+      "c_timing_reg_width": 32,
+      "c_default_value": 0,
+      "component_name": "design_1_axi_iic_0_0",
+      "ten_bit_adr": "7_bit",
+      "axi_aclk_freq_mhz": "99.990005",
+      "iic_freq_khz": 100,
+      "use_board_flow": "false",
+      "iic_board_interface": "Custom",
+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 2684551168,
+      "c_highaddr": 2684616703
+    }
+  },
+  "axis_interconnect_0_xbar": {
+    "vlnv": "xilinx.com:ip:axis_switch:1.1",
+    "parameters": {
+      "c_family": "zynquplus",
+      "c_num_si_slots": 4,
+      "c_log_si_slots": 2,
+      "c_num_mi_slots": 4,
+      "c_axis_tdata_width": 128,
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+      "c_axis_tuser_width": 1,
+      "c_axis_signal_set": 91,
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+      "c_output_reg": 0,
+      "c_decoder_reg": 1,
+      "c_m_axis_connectivity_array": 65535,
+      "c_m_axis_basetdest_array": 228,
+      "c_m_axis_hightdest_array": 228,
+      "c_routing_mode": 1,
+      "c_s_axi_ctrl_addr_width": 7,
+      "c_s_axi_ctrl_data_width": 32,
+      "c_common_clock": 0,
+      "num_si": 4,
+      "num_mi": 4,
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+      "has_tready": 1,
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+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 2684420096,
+      "c_highaddr": 2684485631
+    },
+    "ports": [
+      {
+        "role": "slave",
+        "target": "zynq_axi_dma_0:MM2S",
+        "name": "S00_AXIS"
+      },
+      {
+        "role": "master",
+        "target": "zynq_axi_dma_0:S2MM",
+        "name": "M00_AXIS"
+      },
+      {
+        "role": "slave",
+        "target": "dino_dinoif_fast_nologic_0:M00_AXIS",
+        "name": "S01_AXIS"
+      },
+      {
+        "role": "master",
+        "target": "dino_dinoif_dac_0:S00_AXIS",
+        "name": "M01_AXIS"
+      },
+      {
+        "role": "slave",
+        "target": "aurora_aurora_8b10b_0:USER_DATA_M_AXI_RX",
+        "name": "S02_AXIS"
+      },
+      {
+        "role": "master",
+        "target": "aurora_aurora_8b10b_0:USER_DATA_S_AXI_TX",
+        "name": "M02_AXIS"
+      },
+      {
+        "role": "initiator",
+        "target": "axis_interconnect_0_xbar:S03_AXIS",
+        "name": "S03_AXIS"
+      },
+      {
+        "role": "target",
+        "target": "axis_interconnect_0_xbar:S03_AXIS",
+        "name": "S03_AXIS"
+      },
+      {
+        "role": "target",
+        "target": "axis_interconnect_0_xbar:M03_AXIS",
+        "name": "S03_AXIS"
+      },
+      {
+        "role": "initiator",
+        "target": "axis_interconnect_0_xbar:S03_AXIS",
+        "name": "M03_AXIS"
+      }
+    ],
+    "num_ports": 4
+  },
+  "dino_dinoif_dac_0": {
+    "vlnv": "xilinx.com:module_ref:dinoif_dac:1.0",
+    "i2c_channel": 1,
+    "parameters": {
+      "component_name": "design_1_dinoif_dac_0_0",
+      "edk_iptype": "PERIPHERAL"
+    },
+    "ports": [
+      {
+        "role": "slave",
+        "target": "axis_interconnect_0_xbar:M01_AXIS",
+        "name": "S00_AXIS"
+      }
+    ]
+  },
+  "dino_dinoif_fast_nologic_0": {
+    "vlnv": "xilinx.com:module_ref:dinoif_fast_nologic:1.0",
+    "i2c_channel": 0,
+    "parameters": {
+      "component_name": "design_1_dinoif_fast_nologic_0_0",
+      "edk_iptype": "PERIPHERAL"
+    },
+    "ports": [
+      {
+        "role": "master",
+        "target": "axis_interconnect_0_xbar:S01_AXIS",
+        "name": "M00_AXIS"
+      }
+    ]
+  },
+  "dino_registerif_0": {
+    "vlnv": "xilinx.com:module_ref:registerif:1.0",
+    "parameters": {
+      "c_axi_data_width": 32,
+      "c_axi_addr_width": 32,
+      "reg_addr_width": 10,
+      "component_name": "design_1_registerif_0_0",
+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 2684485632,
+      "c_highaddr": 2684551167
+    }
+  },
+  "zynq_axi_dma_0": {
+    "vlnv": "xilinx.com:ip:axi_dma:7.1",
+    "parameters": {
+      "c_s_axi_lite_addr_width": 10,
+      "c_s_axi_lite_data_width": 32,
+      "c_dlytmr_resolution": 125,
+      "c_prmry_is_aclk_async": 0,
+      "c_enable_multi_channel": 0,
+      "c_num_mm2s_channels": 1,
+      "c_num_s2mm_channels": 1,
+      "c_include_sg": 1,
+      "c_sg_include_stscntrl_strm": 0,
+      "c_sg_use_stsapp_length": 0,
+      "c_sg_length_width": 23,
+      "c_m_axi_sg_addr_width": 64,
+      "c_m_axi_sg_data_width": 32,
+      "c_m_axis_mm2s_cntrl_tdata_width": 32,
+      "c_s_axis_s2mm_sts_tdata_width": 32,
+      "c_micro_dma": 0,
+      "c_include_mm2s": 1,
+      "c_include_mm2s_sf": 1,
+      "c_mm2s_burst_size": 16,
+      "c_m_axi_mm2s_addr_width": 64,
+      "c_m_axi_mm2s_data_width": 128,
+      "c_m_axis_mm2s_tdata_width": 128,
+      "c_include_mm2s_dre": 0,
+      "c_include_s2mm": 1,
+      "c_include_s2mm_sf": 1,
+      "c_s2mm_burst_size": 16,
+      "c_m_axi_s2mm_addr_width": 64,
+      "c_m_axi_s2mm_data_width": 128,
+      "c_s_axis_s2mm_tdata_width": 128,
+      "c_include_s2mm_dre": 0,
+      "c_increase_throughput": 0,
+      "c_family": "zynquplus",
+      "component_name": "design_1_axi_dma_0_0",
+      "c_addr_width": 64,
+      "c_single_interface": 0,
+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 2684354560,
+      "c_highaddr": 2684420095
+    },
+    "memory-view": {
+      "M_AXI_SG": {
+        "zynq_zynq_ultra_ps_e_0": {
+          "HPC1_DDR_LOW": {
+            "baseaddr": 0,
+            "highaddr": 2147483647,
+            "size": 2147483648
+          },
+          "HPC1_DDR_HIGH": {
+            "baseaddr": 34359738368,
+            "highaddr": 68719476735,
+            "size": 34359738368
+          },
+          "HPC1_QSPI": {
+            "baseaddr": 1152921507828072448,
+            "highaddr": 1152921508364943359,
+            "size": 536870912
+          }
+        }
+      },
+      "M_AXI_MM2S": {
+        "zynq_zynq_ultra_ps_e_0": {
+          "HPC0_DDR_LOW": {
+            "baseaddr": 0,
+            "highaddr": 2147483647,
+            "size": 2147483648
+          },
+          "HPC0_DDR_HIGH": {
+            "baseaddr": 34359738368,
+            "highaddr": 68719476735,
+            "size": 34359738368
+          },
+          "HPC0_QSPI": {
+            "baseaddr": 1152921507828072448,
+            "highaddr": 1152921508364943359,
+            "size": 536870912
+          }
+        }
+      },
+      "M_AXI_S2MM": {
+        "zynq_zynq_ultra_ps_e_0": {
+          "HPC0_DDR_LOW": {
+            "baseaddr": 0,
+            "highaddr": 2147483647,
+            "size": 2147483648
+          },
+          "HPC0_DDR_HIGH": {
+            "baseaddr": 34359738368,
+            "highaddr": 68719476735,
+            "size": 34359738368
+          },
+          "HPC0_QSPI": {
+            "baseaddr": 1152921507828072448,
+            "highaddr": 1152921508364943359,
+            "size": 536870912
+          }
+        }
+      }
+    },
+    "ports": [
+      {
+        "role": "master",
+        "target": "axis_interconnect_0_xbar:S00_AXIS",
+        "name": "MM2S"
+      },
+      {
+        "role": "slave",
+        "target": "axis_interconnect_0_xbar:M00_AXIS",
+        "name": "S2MM"
+      }
+    ]
+  },
+  "zynq_zynq_ultra_ps_e_0": {
+    "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3",
+    "parameters": {
+      "c_dp_use_audio": 0,
+      "c_dp_use_video": 0,
+      "c_maxigp0_data_width": 128,
+      "c_maxigp1_data_width": 128,
+      "c_maxigp2_data_width": 32,
+      "c_saxigp0_data_width": 128,
+      "c_saxigp1_data_width": 128,
+      "c_saxigp2_data_width": 128,
+      "c_saxigp3_data_width": 128,
+      "c_saxigp4_data_width": 128,
+      "c_saxigp5_data_width": 128,
+      "c_saxigp6_data_width": 128,
+      "c_use_diff_rw_clk_gp0": 0,
+      "c_use_diff_rw_clk_gp1": 0,
+      "c_use_diff_rw_clk_gp2": 0,
+      "c_use_diff_rw_clk_gp3": 0,
+      "c_use_diff_rw_clk_gp4": 0,
+      "c_use_diff_rw_clk_gp5": 0,
+      "c_use_diff_rw_clk_gp6": 0,
+      "c_en_fifo_enet0": 0,
+      "c_en_fifo_enet1": 0,
+      "c_en_fifo_enet2": 0,
+      "c_en_fifo_enet3": 0,
+      "c_pl_clk0_buf": "TRUE",
+      "c_pl_clk1_buf": "FALSE",
+      "c_pl_clk2_buf": "FALSE",
+      "c_pl_clk3_buf": "FALSE",
+      "c_trace_pipeline_width": 8,
+      "c_en_emio_trace": 0,
+      "c_trace_data_width": 32,
+      "c_use_debug_test": 0,
+      "c_sd0_internal_bus_width": 8,
+      "c_sd1_internal_bus_width": 8,
+      "c_num_f2p_0_intr_inputs": 3,
+      "c_num_f2p_1_intr_inputs": 1,
+      "c_emio_gpio_width": 1,
+      "c_num_fabric_resets": 1,
+      "psu_value_silversion": 3,
+      "psu__use__ddr_intf_requested": 0,
+      "psu__en_axi_status_ports": 0,
+      "psu__pss_ref_clk__freqmhz": "33.330",
+      "psu__pss_alt_ref_clk__freqmhz": "33.333",
+      "psu__video_ref_clk__freqmhz": "33.333",
+      "psu__aux_ref_clk__freqmhz": "33.333",
+      "psu__gt_ref_clk__freqmhz": "33.333",
+      "psu__video_ref_clk__enable": 0,
+      "psu__video_ref_clk__io": "<Select>",
+      "psu__pss_alt_ref_clk__enable": 0,
+      "psu__pss_alt_ref_clk__io": "<Select>",
+      "psu__can0__peripheral__enable": 0,
+      "psu__can0__peripheral__io": "<Select>",
+      "psu__can0__grp_clk__enable": 0,
+      "psu__can0__grp_clk__io": "<Select>",
+      "psu__can1__peripheral__enable": 1,
+      "psu__can1__peripheral__io": "MIO 24 .. 25",
+      "psu__can1__grp_clk__enable": 0,
+      "psu__can1__grp_clk__io": "<Select>",
+      "psu__can0_loop_can1__enable": 0,
+      "psu__dpaux__peripheral__enable": 1,
+      "psu__dpaux__peripheral__io": "MIO 27 .. 30",
+      "psu__enet0__grp_mdio__enable": 0,
+      "psu__act_ddr_freq_mhz": "1066.560059",
+      "psu__enet0__grp_mdio__io": "<Select>",
+      "psu__gem__tsu__enable": 0,
+      "psu__gem__tsu__io": "<Select>",
+      "psu__enet0__peripheral__enable": 0,
+      "psu__enet0__fifo__enable": 0,
+      "psu__enet0__ptp__enable": 0,
+      "psu__enet0__peripheral__io": "<Select>",
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+      "psu__fpga_pl1_enable": 0,
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+      "psu__enet2__peripheral__io": "<Select>",
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+      "psu__enet2__grp_mdio__io": "<Select>",
+      "psu__enet3__peripheral__enable": 1,
+      "psu__enet3__fifo__enable": 0,
+      "psu__enet3__ptp__enable": 0,
+      "psu__enet3__peripheral__io": "MIO 64 .. 75",
+      "psu__enet3__grp_mdio__enable": 1,
+      "psu__enet3__grp_mdio__io": "MIO 76 .. 77",
+      "psu__gpio_emio__peripheral__enable": 0,
+      "psu__gpio_emio__peripheral__io": "<Select>",
+      "psu__gpio0_mio__peripheral__enable": 1,
+      "psu__gpio0_mio__io": "MIO 0 .. 25",
+      "psu__gpio1_mio__peripheral__enable": 1,
+      "psu__gpio1_mio__io": "MIO 26 .. 51",
+      "psu__gpio2_mio__peripheral__enable": 0,
+      "psu__gpio2_mio__io": "<Select>",
+      "psu__i2c0__peripheral__enable": 1,
+      "psu__i2c0__peripheral__io": "MIO 14 .. 15",
+      "psu__i2c0__grp_int__enable": 0,
+      "psu__i2c0__grp_int__io": "<Select>",
+      "psu__i2c1__peripheral__enable": 1,
+      "psu__i2c1__peripheral__io": "MIO 16 .. 17",
+      "psu__i2c1__grp_int__enable": 0,
+      "psu__i2c1__grp_int__io": "<Select>",
+      "psu__i2c0_loop_i2c1__enable": 0,
+      "psu__testscan__peripheral__enable": 0,
+      "psu__pcie__peripheral__enable": 0,
+      "psu__pcie__peripheral__endpoint_enable": 1,
+      "psu__pcie__peripheral__rootport_enable": 0,
+      "psu__pcie__peripheral__endpoint_io": "<Select>",
+      "psu__pcie__peripheral__rootport_io": "<Select>",
+      "psu__pcie__lane0__enable": 0,
+      "psu__pcie__lane0__io": "<Select>",
+      "psu__pcie__lane1__enable": 0,
+      "psu__pcie__lane1__io": "<Select>",
+      "psu__pcie__lane2__enable": 0,
+      "psu__pcie__lane2__io": "<Select>",
+      "psu__pcie__lane3__enable": 0,
+      "psu__pcie__lane3__io": "<Select>",
+      "psu__pcie__reset__polarity": "Active Low",
+      "psu__gt__link_speed": "HBR",
+      "psu__gt__vlt_swng_lvl_4": 0,
+      "psu__gt__pre_emph_lvl_4": 0,
+      "psu__usb0__ref_clk_sel": "Ref Clk2",
+      "psu__usb0__ref_clk_freq": 26,
+      "psu__usb1__ref_clk_sel": "<Select>",
+      "psu__usb1__ref_clk_freq": "<Select>",
+      "psu__gem0__ref_clk_sel": "<Select>",
+      "psu__gem0__ref_clk_freq": "<Select>",
+      "psu__gem1__ref_clk_sel": "<Select>",
+      "psu__gem1__ref_clk_freq": "<Select>",
+      "psu__gem2__ref_clk_sel": "<Select>",
+      "psu__gem2__ref_clk_freq": "<Select>",
+      "psu__gem3__ref_clk_sel": "<Select>",
+      "psu__gem3__ref_clk_freq": "<Select>",
+      "psu__dp__ref_clk_sel": "Ref Clk3",
+      "psu__dp__ref_clk_freq": 27,
+      "psu__sata__ref_clk_sel": "Ref Clk1",
+      "psu__sata__ref_clk_freq": 125,
+      "psu__pcie__ref_clk_sel": "<Select>",
+      "psu__pcie__ref_clk_freq": "<Select>",
+      "psu__dp__lane_sel": "Dual Lower",
+      "psu__pcie__device_port_type": "<Select>",
+      "psu__pcie__maximum_link_width": "<Select>",
+      "psu__pcie__link_speed": "<Select>",
+      "psu__pcie__interface_width": "<Select>",
+      "psu__pcie__bar0_enable": 0,
+      "psu__pcie__bar0_type": "<Select>",
+      "psu__pcie__bar0_scale": "<Select>",
+      "psu__pcie__bar0_64bit": 0,
+      "psu__pcie__bar0_size": "<Select>",
+      "psu__pcie__bar0_val": null,
+      "psu__pcie__bar0_prefetchable": 0,
+      "psu__pcie__bar1_enable": 0,
+      "psu__pcie__bar1_type": "<Select>",
+      "psu__pcie__bar1_scale": "<Select>",
+      "psu__pcie__bar1_64bit": 0,
+      "psu__pcie__bar1_size": "<Select>",
+      "psu__pcie__bar1_val": null,
+      "psu__pcie__bar1_prefetchable": 0,
+      "psu__pcie__bar2_enable": 0,
+      "psu__pcie__bar2_type": "<Select>",
+      "psu__pcie__bar2_scale": "<Select>",
+      "psu__pcie__bar2_64bit": 0,
+      "psu__pcie__bar2_size": "<Select>",
+      "psu__pcie__bar2_val": null,
+      "psu__pcie__bar2_prefetchable": 0,
+      "psu__pcie__bar3_enable": 0,
+      "psu__pcie__bar3_type": "<Select>",
+      "psu__pcie__bar3_scale": "<Select>",
+      "psu__pcie__bar3_64bit": 0,
+      "psu__pcie__bar3_size": "<Select>",
+      "psu__pcie__bar3_val": null,
+      "psu__pcie__bar3_prefetchable": 0,
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+      "psu__pcie__bar4_type": "<Select>",
+      "psu__pcie__bar4_scale": "<Select>",
+      "psu__pcie__bar4_64bit": 0,
+      "psu__pcie__bar4_size": "<Select>",
+      "psu__pcie__bar4_val": null,
+      "psu__pcie__bar4_prefetchable": 0,
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+      "psu__pcie__bar5_type": "<Select>",
+      "psu__pcie__bar5_scale": "<Select>",
+      "psu__pcie__bar5_64bit": 0,
+      "psu__pcie__bar5_size": "<Select>",
+      "psu__pcie__bar5_val": null,
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+      "psu__pcie__erom_enable": 0,
+      "psu__pcie__erom_scale": "<Select>",
+      "psu__pcie__erom_size": "<Select>",
+      "psu__pcie__erom_val": null,
+      "psu__pcie__cap_slot_implemented": "<Select>",
+      "psu__pcie__max_payload_size": "<Select>",
+      "psu__pcie__legacy_interrupt": "<Select>",
+      "psu__pcie__vendor_id": null,
+      "psu__pcie__device_id": null,
+      "psu__pcie__revision_id": null,
+      "psu__pcie__subsystem_vendor_id": null,
+      "psu__pcie__subsystem_id": null,
+      "psu__pcie__base_class_menu": "<Select>",
+      "psu__pcie__use_class_code_lookup_assistant": "<Select>",
+      "psu__pcie__sub_class_interface_menu": "<Select>",
+      "psu__pcie__class_code_base": null,
+      "psu__pcie__class_code_sub": null,
+      "psu__pcie__class_code_interface": null,
+      "psu__pcie__class_code_value": null,
+      "psu__pcie__aer_capability": 0,
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+      "psu__pcie__header_log_overflow": 0,
+      "psu__pcie__receiver_err": 0,
+      "psu__pcie__surprise_down": 0,
+      "psu__pcie__flow_control_err": 0,
+      "psu__pcie__compltion_timeout": 0,
+      "psu__pcie__completer_abort": 0,
+      "psu__pcie__receiver_overflow": 0,
+      "psu__pcie__ecrc_err": 0,
+      "psu__pcie__acs_violaion": 0,
+      "psu__pcie__uncorrectabl_int_err": 0,
+      "psu__pcie__mc_blocked_tlp": 0,
+      "psu__pcie__atomicop_egress_blocked": 0,
+      "psu__pcie__tlp_prefix_blocked": 0,
+      "psu__pcie__flow_control_protocol_err": 0,
+      "psu__pcie__acs_violation": 0,
+      "psu__pcie__multiheader": 0,
+      "psu__pcie__ecrc_check": 0,
+      "psu__pcie__ecrc_gen": 0,
+      "psu__pcie__perm_root_err_update": 0,
+      "psu__pcie__crs_sw_visibility": 0,
+      "psu__pcie__intx_generation": 0,
+      "psu__pcie__intx_pin": "<Select>",
+      "psu__pcie__msi_capability": 0,
+      "psu__pcie__msi_64bit_addr_capable": 0,
+      "psu__pcie__msi_multiple_msg_capable": "<Select>",
+      "psu__pcie__msix_capability": 0,
+      "psu__pcie__msix_table_size": 0,
+      "psu__pcie__msix_table_offset": 0,
+      "psu__pcie__msix_bar_indicator": null,
+      "psu__pcie__msix_pba_offset": 0,
+      "psu__pcie__msix_pba_bar_indicator": null,
+      "psu__pcie__bridge_bar_indicator": "<Select>",
+      "psu_import_board_preset": null,
+      "psu__protection__subsystems": "PMU Firmware:PMU|Secure Subsystem:",
+      "psu__protection__masters_tz": "GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure",
+      "psu__protection__masters": "USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1",
+      "psu__protection__ddr_segments": "NONE",
+      "psu__protection__ocm_segments": "NONE",
+      "psu__protection__lpd_segments": "SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem",
+      "psu__protection__fpd_segments": "SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem",
+      "psu__protection__debug": 0,
+      "psu__protection__slaves": "LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1",
+      "psu__protection__presubsystems": "NONE",
+      "psu__protection__enable": 0,
+      "psu__ddr_sw_refresh_enabled": 1,
+      "psu__protection__lock_unused_segments": 0,
+      "psu__ep__ip": 0,
+      "psu__actual__ip": 1,
+      "subpreset1": "Custom",
+      "subpreset2": "Custom",
+      "psu_uiparam_generate_summary": "<Select>",
+      "psu_mio_tree_peripherals": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3",
+      "psu_mio_tree_signals": "sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out",
+      "psu_peripheral_board_preset": null,
+      "psu__nand__peripheral__io": "<Select>",
+      "psu__nand__peripheral__enable": 0,
+      "psu__nand__ready_busy__enable": 0,
+      "psu__nand__ready0_busy__enable": 0,
+      "psu__nand__ready1_busy__enable": 0,
+      "psu__nand__ready_busy__io": "<Select>",
+      "psu__nand__ready0_busy__io": "<Select>",
+      "psu__nand__ready1_busy__io": "<Select>",
+      "psu__nand__chip_enable__enable": 0,
+      "psu__nand__chip_enable__io": "<Select>",
+      "psu__nand__data_strobe__enable": 0,
+      "psu__nand__data_strobe__io": "<Select>",
+      "psu__pjtag__peripheral__enable": 0,
+      "psu__pjtag__peripheral__io": "<Select>",
+      "psu__pmu__aiback__enable": 0,
+      "psu__pmu__plerror__enable": 0,
+      "psu__pmu__peripheral__enable": 1,
+      "psu__pmu__peripheral__io": "<Select>",
+      "psu__pmu__emio_gpi__enable": 0,
+      "psu__pmu__emio_gpo__enable": 0,
+      "psu__pmu__gpi0__enable": 0,
+      "psu__pmu__gpi1__enable": 0,
+      "psu__pmu__gpi2__enable": 0,
+      "psu__pmu__gpi3__enable": 0,
+      "psu__pmu__gpi4__enable": 0,
+      "psu__pmu__gpi5__enable": 0,
+      "psu__pmu__gpo0__enable": 1,
+      "psu__pmu__gpo1__enable": 1,
+      "psu__pmu__gpo2__enable": 1,
+      "psu__pmu__gpo3__enable": 1,
+      "psu__pmu__gpo4__enable": 1,
+      "psu__pmu__gpo5__enable": 1,
+      "psu__pmu__gpi0__io": "<Select>",
+      "psu__pmu__gpi1__io": "<Select>",
+      "psu__pmu__gpi2__io": "<Select>",
+      "psu__pmu__gpi3__io": "<Select>",
+      "psu__pmu__gpi4__io": "<Select>",
+      "psu__pmu__gpi5__io": "<Select>",
+      "psu__pmu__gpo0__io": "MIO 32",
+      "psu__pmu__gpo1__io": "MIO 33",
+      "psu__pmu__gpo2__io": "MIO 34",
+      "psu__pmu__gpo3__io": "MIO 35",
+      "psu__pmu__gpo4__io": "MIO 36",
+      "psu__pmu__gpo5__io": "MIO 37",
+      "psu__pmu__gpo2__polarity": "low",
+      "psu__pmu__gpo3__polarity": "low",
+      "psu__pmu__gpo4__polarity": "low",
+      "psu__pmu__gpo5__polarity": "low",
+      "psu__csu__peripheral__enable": 0,
+      "psu__csu__peripheral__io": "<Select>",
+      "psu__qspi__peripheral__enable": 1,
+      "psu__qspi__peripheral__io": "MIO 0 .. 12",
+      "psu__qspi__peripheral__mode": "Dual Parallel",
+      "psu__qspi__peripheral__data_mode": "x4",
+      "psu__qspi__grp_fbclk__enable": 1,
+      "psu__qspi__grp_fbclk__io": "MIO 6",
+      "psu__sd0__peripheral__enable": 0,
+      "psu__sd0__peripheral__io": "<Select>",
+      "psu__sd0__grp_cd__enable": 0,
+      "psu__sd0__grp_cd__io": "<Select>",
+      "psu__sd0__grp_pow__enable": 0,
+      "psu__sd0__grp_pow__io": "<Select>",
+      "psu__sd0__grp_wp__enable": 0,
+      "psu__sd0__grp_wp__io": "<Select>",
+      "psu__sd0__slot_type": "<Select>",
+      "psu__sd0__reset__enable": 0,
+      "psu__sd0__data_transfer_mode": "<Select>",
+      "psu__sd1__peripheral__enable": 1,
+      "psu__sd1__peripheral__io": "MIO 39 .. 51",
+      "psu__sd1__grp_cd__enable": 1,
+      "psu__sd1__grp_cd__io": "MIO 45",
+      "psu__sd1__grp_pow__enable": 1,
+      "psu__sd1__grp_pow__io": "MIO 43",
+      "psu__sd1__grp_wp__enable": 1,
+      "psu__sd1__grp_wp__io": "MIO 44",
+      "psu__sd1__slot_type": "SD 3.0",
+      "psu__sd1__reset__enable": 0,
+      "psu__sd1__data_transfer_mode": "8Bit",
+      "psu__device_type": "EV",
+      "psu_smc_cycle_t0": "NA",
+      "psu_smc_cycle_t1": "NA",
+      "psu_smc_cycle_t2": "NA",
+      "psu_smc_cycle_t3": "NA",
+      "psu_smc_cycle_t4": "NA",
+      "psu_smc_cycle_t5": "NA",
+      "psu_smc_cycle_t6": "NA",
+      "psu__spi0__peripheral__enable": 0,
+      "psu__spi0__peripheral__io": "<Select>",
+      "psu__spi0__grp_ss0__enable": 0,
+      "psu__spi0__grp_ss0__io": "<Select>",
+      "psu__spi0__grp_ss1__enable": 0,
+      "psu__spi0__grp_ss1__io": "<Select>",
+      "psu__spi0__grp_ss2__enable": 0,
+      "psu__spi0__grp_ss2__io": "<Select>",
+      "psu__spi1__peripheral__enable": 0,
+      "psu__spi1__peripheral__io": "<Select>",
+      "psu__spi1__grp_ss0__enable": 0,
+      "psu__spi1__grp_ss0__io": "<Select>",
+      "psu__spi1__grp_ss1__enable": 0,
+      "psu__spi1__grp_ss1__io": "<Select>",
+      "psu__spi1__grp_ss2__enable": 0,
+      "psu__spi1__grp_ss2__io": "<Select>",
+      "psu__spi0_loop_spi1__enable": 0,
+      "psu__lpd_slcr__csupmu_wdt_clk_sel__select": "APB",
+      "psu__swdt0__peripheral__enable": 1,
+      "psu__swdt0__clock__enable": 0,
+      "psu__swdt0__reset__enable": 0,
+      "psu__swdt0__peripheral__io": "NA",
+      "psu__swdt0__clock__io": "<Select>",
+      "psu__swdt0__reset__io": "<Select>",
+      "psu__swdt1__peripheral__enable": 1,
+      "psu__swdt1__clock__enable": 0,
+      "psu__swdt1__reset__enable": 0,
+      "psu__swdt1__peripheral__io": "NA",
+      "psu__swdt1__clock__io": "<Select>",
+      "psu__swdt1__reset__io": "<Select>",
+      "psu__uart0__baud_rate": 115200,
+      "psu__trace__peripheral__enable": 0,
+      "psu__trace__peripheral__io": "<Select>",
+      "psu__trace__width": "<Select>",
+      "psu__trace__internal_width": 32,
+      "psu_sd0_internal_bus_width": 8,
+      "psu__ttc0__peripheral__enable": 1,
+      "psu__ttc0__clock__enable": 0,
+      "psu__ttc0__waveout__enable": 0,
+      "psu__ttc0__clock__io": "<Select>",
+      "psu__ttc0__waveout__io": "<Select>",
+      "psu__ttc0__peripheral__io": "NA",
+      "psu__ttc1__peripheral__enable": 1,
+      "psu__ttc1__peripheral__io": "NA",
+      "psu__uart1__baud_rate": 115200,
+      "psu__ttc1__clock__enable": 0,
+      "psu__ttc1__waveout__enable": 0,
+      "psu__ttc1__clock__io": "<Select>",
+      "psu__ttc1__waveout__io": "<Select>",
+      "psu__ttc2__peripheral__enable": 1,
+      "psu__ttc2__peripheral__io": "NA",
+      "psu__ttc2__clock__enable": 0,
+      "psu__ttc2__waveout__enable": 0,
+      "psu__ttc2__clock__io": "<Select>",
+      "psu__ttc2__waveout__io": "<Select>",
+      "psu__ttc3__peripheral__enable": 1,
+      "psu__ttc3__peripheral__io": "NA",
+      "psu__ttc3__clock__enable": 0,
+      "psu__ttc3__waveout__enable": 0,
+      "psu__ttc3__clock__io": "<Select>",
+      "psu__ttc3__waveout__io": "<Select>",
+      "psu__csupmu__peripheral__valid": 1,
+      "psu__ddrc__al": 0,
+      "psu__ddrc__bank_addr_count": 2,
+      "psu__ddrc__bus_width": "64 Bit",
+      "psu__ddrc__cl": 15,
+      "psu__ddrc__clock_stop_en": 0,
+      "psu_dynamic_ddr_config_en": 1,
+      "psu__ddrc__col_addr_count": 10,
+      "psu__ddrc__rank_addr_count": 0,
+      "psu__ddrc__cwl": 14,
+      "psu__ddrc__bg_addr_count": 2,
+      "psu__ddrc__device_capacity": "4096 MBits",
+      "psu__ddrc__dram_width": "8 Bits",
+      "psu__ddrc__ecc": "Disabled",
+      "psu__ddrc__ecc_scrub": 0,
+      "psu__ddrc__enable": 1,
+      "psu__ddrc__freq_mhz": 1,
+      "psu__ddrc__high_temp": "<Select>",
+      "psu__ddrc__memory_type": "DDR 4",
+      "psu__ddrc__partno": "<Select>",
+      "psu__ddrc__row_addr_count": 15,
+      "psu__ddrc__speed_bin": "DDR4_2133P",
+      "psu__ddrc__t_faw": "30.0",
+      "psu__ddrc__t_ras_min": 33,
+      "psu__ddrc__t_rc": "47.06",
+      "psu__ddrc__t_rcd": 15,
+      "psu__ddrc__t_rp": 15,
+      "psu__ddrc__train_data_eye": 1,
+      "psu__ddrc__train_read_gate": 1,
+      "psu__ddrc__train_write_level": 1,
+      "psu__ddrc__vref": 1,
+      "psu__ddrc__video_buffer_size": 0,
+      "psu__ddrc__brc_mapping": "ROW_BANK_COL",
+      "psu__ddrc__dimm_addr_mirror": 0,
+      "psu__ddrc__static_rd_mode": 0,
+      "psu__ddrc__ddr4_maxpwr_saving_en": 0,
+      "psu__ddrc__pwr_down_en": 0,
+      "psu__ddrc__deep_pwr_down_en": 0,
+      "psu__ddrc__pll_bypass": 0,
+      "psu__ddrc__ddr4_t_ref_mode": 0,
+      "psu__ddrc__ddr4_t_ref_range": "Normal (0-85)",
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+      "psu_ddr_ram_lowaddr_offset": 2147483648,
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+      "psu__ddr_qos_port0_type": "<Select>",
+      "psu__ddr_qos_port1_vn1_type": "<Select>",
+      "psu__ddr_qos_port1_vn2_type": "<Select>",
+      "psu__ddr_qos_port2_vn1_type": "<Select>",
+      "psu__ddr_qos_port2_vn2_type": "<Select>",
+      "psu__ddr_qos_port3_type": "<Select>",
+      "psu__ddr_qos_port4_type": "<Select>",
+      "psu__ddr_qos_port5_type": "<Select>",
+      "psu__ddr_qos_rd_lpr_thrshld": null,
+      "psu__ddr_qos_rd_hpr_thrshld": null,
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+      "psu__ddr_qos_hp1_wrqos": null,
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+      "psu__ddr_qos_hp2_wrqos": null,
+      "psu__ddr_qos_hp3_rdqos": null,
+      "psu__ddr_qos_hp3_wrqos": null,
+      "psu__ddr_qos_fix_hp0_rdqos": null,
+      "psu__ddr_qos_fix_hp0_wrqos": null,
+      "psu__ddr_qos_fix_hp1_rdqos": null,
+      "psu__ddr_qos_fix_hp1_wrqos": null,
+      "psu__ddr_qos_fix_hp2_rdqos": null,
+      "psu__ddr_qos_fix_hp2_wrqos": null,
+      "psu__ddr_qos_fix_hp3_rdqos": null,
+      "psu__ddr_qos_fix_hp3_wrqos": null,
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+      "psu__ocm_bank0__power__on": 1,
+      "psu__ocm_bank1__power__on": 1,
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+      "psu__tcm0b__power__on": 1,
+      "psu__tcm1a__power__on": 1,
+      "psu__tcm1b__power__on": 1,
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+      "psu__gpu_pp0__power__on": 1,
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+      "psu__acpu3__power__on": 1,
+      "psu__uart0__peripheral__enable": 1,
+      "psu__uart0__peripheral__io": "MIO 18 .. 19",
+      "psu__uart0__modem__enable": 0,
+      "psu__uart1__peripheral__enable": 1,
+      "psu__uart1__peripheral__io": "MIO 20 .. 21",
+      "psu__uart1__modem__enable": 0,
+      "psu__uart0_loop_uart1__enable": 0,
+      "psu__usb0__peripheral__enable": 1,
+      "psu__usb0__peripheral__io": "MIO 52 .. 63",
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+      "psu__usb0__reset__io": "<Select>",
+      "psu__usb__reset__mode": "Boot Pin",
+      "psu__usb__reset__polarity": "Active Low",
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+      "psu__usb1__peripheral__io": "<Select>",
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+      "psu__usb1__reset__io": "<Select>",
+      "psu__usb3_0__peripheral__enable": 1,
+      "psu__usb3_0__peripheral__io": "GT Lane2",
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+      "psu__usb3_1__peripheral__io": "<Select>",
+      "psu__usb3_0__emio__enable": 0,
+      "psu__usb2_0__emio__enable": 0,
+      "psu__usb3_1__emio__enable": 0,
+      "psu__usb2_1__emio__enable": 0,
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+      "psu__maxigp0__data_width": 128,
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+      "psu__saxigp6__data_width": 128,
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+      "psu__use__video": 0,
+      "psu__use__proc_event_bus": 0,
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+      "psu__ddr_high_address_gui_enable": 1,
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+      "psu_mio_0_pullupdown": "pullup",
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+      "psu_mio_0_polarity": "Default",
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+      "psu_mio_0_direction": "out",
+      "psu_mio_1_pullupdown": "pullup",
+      "psu_mio_1_drive_strength": 12,
+      "psu_mio_1_polarity": "Default",
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+      "psu_mio_1_direction": "inout",
+      "psu_mio_2_pullupdown": "pullup",
+      "psu_mio_2_drive_strength": 12,
+      "psu_mio_2_polarity": "Default",
+      "psu_mio_2_input_type": "cmos",
+      "psu_mio_2_slew": "fast",
+      "psu_mio_2_direction": "inout",
+      "psu_mio_3_pullupdown": "pullup",
+      "psu_mio_3_drive_strength": 12,
+      "psu_mio_3_polarity": "Default",
+      "psu_mio_3_input_type": "cmos",
+      "psu_mio_3_slew": "fast",
+      "psu_mio_3_direction": "inout",
+      "psu_mio_4_pullupdown": "pullup",
+      "psu_mio_4_drive_strength": 12,
+      "psu_mio_4_polarity": "Default",
+      "psu_mio_4_input_type": "cmos",
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+      "psu_mio_4_direction": "inout",
+      "psu_mio_5_pullupdown": "pullup",
+      "psu_mio_5_drive_strength": 12,
+      "psu_mio_5_polarity": "Default",
+      "psu_mio_5_input_type": "cmos",
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+      "psu_mio_5_direction": "out",
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+      "psu_mio_6_polarity": "Default",
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+      "psu_mio_6_direction": "out",
+      "psu_mio_7_pullupdown": "pullup",
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+      "psu_mio_7_polarity": "Default",
+      "psu_mio_7_input_type": "cmos",
+      "psu_mio_7_slew": "fast",
+      "psu_mio_7_direction": "out",
+      "psu_mio_8_pullupdown": "pullup",
+      "psu_mio_8_drive_strength": 12,
+      "psu_mio_8_polarity": "Default",
+      "psu_mio_8_input_type": "cmos",
+      "psu_mio_8_slew": "fast",
+      "psu_mio_8_direction": "inout",
+      "psu_mio_9_pullupdown": "pullup",
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+      "psu_mio_9_polarity": "Default",
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+      "psu_mio_9_direction": "inout",
+      "psu_mio_10_pullupdown": "pullup",
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+      "psu_mio_10_polarity": "Default",
+      "psu_mio_10_input_type": "cmos",
+      "psu_mio_10_slew": "fast",
+      "psu_mio_10_direction": "inout",
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+      "psu_mio_11_polarity": "Default",
+      "psu_mio_11_input_type": "cmos",
+      "psu_mio_11_slew": "fast",
+      "psu_mio_11_direction": "inout",
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+      "psu_mio_12_drive_strength": 12,
+      "psu_mio_12_polarity": "Default",
+      "psu_mio_12_input_type": "cmos",
+      "psu_mio_12_slew": "fast",
+      "psu_mio_12_direction": "out",
+      "psu_mio_13_pullupdown": "pullup",
+      "psu_mio_13_drive_strength": 12,
+      "psu_mio_13_polarity": "Default",
+      "psu_mio_13_input_type": "cmos",
+      "psu_mio_13_slew": "fast",
+      "psu_mio_13_direction": "inout",
+      "psu_mio_14_pullupdown": "pullup",
+      "psu_mio_14_drive_strength": 12,
+      "psu_mio_14_polarity": "Default",
+      "psu_mio_14_input_type": "cmos",
+      "psu_mio_14_slew": "fast",
+      "psu_mio_14_direction": "inout",
+      "psu_mio_15_pullupdown": "pullup",
+      "psu_mio_15_drive_strength": 12,
+      "psu_mio_15_polarity": "Default",
+      "psu_mio_15_input_type": "cmos",
+      "psu_mio_15_slew": "fast",
+      "psu_mio_15_direction": "inout",
+      "psu_mio_16_pullupdown": "pullup",
+      "psu_mio_16_drive_strength": 12,
+      "psu_mio_16_polarity": "Default",
+      "psu_mio_16_input_type": "cmos",
+      "psu_mio_16_slew": "fast",
+      "psu_mio_16_direction": "inout",
+      "psu_mio_17_pullupdown": "pullup",
+      "psu_mio_17_drive_strength": 12,
+      "psu_mio_17_polarity": "Default",
+      "psu_mio_17_input_type": "cmos",
+      "psu_mio_17_slew": "fast",
+      "psu_mio_17_direction": "inout",
+      "psu_mio_18_pullupdown": "pullup",
+      "psu_mio_18_drive_strength": 12,
+      "psu_mio_18_polarity": "Default",
+      "psu_mio_18_input_type": "cmos",
+      "psu_mio_18_slew": "fast",
+      "psu_mio_18_direction": "in",
+      "psu_mio_19_pullupdown": "pullup",
+      "psu_mio_19_drive_strength": 12,
+      "psu_mio_19_polarity": "Default",
+      "psu_mio_19_input_type": "cmos",
+      "psu_mio_19_slew": "fast",
+      "psu_mio_19_direction": "out",
+      "psu_mio_20_pullupdown": "pullup",
+      "psu_mio_20_drive_strength": 12,
+      "psu_mio_20_polarity": "Default",
+      "psu_mio_20_input_type": "cmos",
+      "psu_mio_20_slew": "fast",
+      "psu_mio_20_direction": "out",
+      "psu_mio_21_pullupdown": "pullup",
+      "psu_mio_21_drive_strength": 12,
+      "psu_mio_21_polarity": "Default",
+      "psu_mio_21_input_type": "cmos",
+      "psu_mio_21_slew": "fast",
+      "psu_mio_21_direction": "in",
+      "psu_mio_22_pullupdown": "pullup",
+      "psu_mio_22_drive_strength": 12,
+      "psu_mio_22_polarity": "Default",
+      "psu_mio_22_input_type": "cmos",
+      "psu_mio_22_slew": "fast",
+      "psu_mio_22_direction": "inout",
+      "psu_mio_23_pullupdown": "pullup",
+      "psu_mio_23_drive_strength": 12,
+      "psu_mio_23_polarity": "Default",
+      "psu_mio_23_input_type": "cmos",
+      "psu_mio_23_slew": "fast",
+      "psu_mio_23_direction": "inout",
+      "psu_mio_24_pullupdown": "pullup",
+      "psu_mio_24_drive_strength": 12,
+      "psu_mio_24_polarity": "Default",
+      "psu_mio_24_input_type": "cmos",
+      "psu_mio_24_slew": "fast",
+      "psu_mio_24_direction": "out",
+      "psu_mio_25_pullupdown": "pullup",
+      "psu_mio_25_drive_strength": 12,
+      "psu_mio_25_polarity": "Default",
+      "psu_mio_25_input_type": "cmos",
+      "psu_mio_25_slew": "fast",
+      "psu_mio_25_direction": "in",
+      "psu_mio_26_pullupdown": "pullup",
+      "psu_mio_26_drive_strength": 12,
+      "psu_mio_26_polarity": "Default",
+      "psu_mio_26_input_type": "cmos",
+      "psu_mio_26_slew": "fast",
+      "psu_mio_26_direction": "inout",
+      "psu_mio_27_pullupdown": "pullup",
+      "psu_mio_27_drive_strength": 12,
+      "psu_mio_27_polarity": "Default",
+      "psu_mio_27_input_type": "cmos",
+      "psu_mio_27_slew": "fast",
+      "psu_mio_27_direction": "out",
+      "psu_mio_28_pullupdown": "pullup",
+      "psu_mio_28_drive_strength": 12,
+      "psu_mio_28_polarity": "Default",
+      "psu_mio_28_input_type": "cmos",
+      "psu_mio_28_slew": "fast",
+      "psu_mio_28_direction": "in",
+      "psu_mio_29_pullupdown": "pullup",
+      "psu_mio_29_drive_strength": 12,
+      "psu_mio_29_polarity": "Default",
+      "psu_mio_29_input_type": "cmos",
+      "psu_mio_29_slew": "fast",
+      "psu_mio_29_direction": "out",
+      "psu_mio_30_pullupdown": "pullup",
+      "psu_mio_30_drive_strength": 12,
+      "psu_mio_30_polarity": "Default",
+      "psu_mio_30_input_type": "cmos",
+      "psu_mio_30_slew": "fast",
+      "psu_mio_30_direction": "in",
+      "psu_mio_31_pullupdown": "pullup",
+      "psu_mio_31_drive_strength": 12,
+      "psu_mio_31_polarity": "Default",
+      "psu_mio_31_input_type": "cmos",
+      "psu_mio_31_slew": "fast",
+      "psu_mio_31_direction": "inout",
+      "psu_mio_32_pullupdown": "pullup",
+      "psu_mio_32_drive_strength": 12,
+      "psu_mio_32_polarity": "Default",
+      "psu_mio_32_input_type": "cmos",
+      "psu_mio_32_slew": "fast",
+      "psu_mio_32_direction": "out",
+      "psu_mio_33_pullupdown": "pullup",
+      "psu_mio_33_drive_strength": 12,
+      "psu_mio_33_polarity": "Default",
+      "psu_mio_33_input_type": "cmos",
+      "psu_mio_33_slew": "fast",
+      "psu_mio_33_direction": "out",
+      "psu_mio_34_pullupdown": "pullup",
+      "psu_mio_34_drive_strength": 12,
+      "psu_mio_34_polarity": "Default",
+      "psu_mio_34_input_type": "cmos",
+      "psu_mio_34_slew": "fast",
+      "psu_mio_34_direction": "out",
+      "psu_mio_35_pullupdown": "pullup",
+      "psu_mio_35_drive_strength": 12,
+      "psu_mio_35_polarity": "Default",
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+      "psu__gen_ipi_9__master": "NONE",
+      "psu__gen_ipi_10__master": "NONE",
+      "psu__gen_ipi__trustzone": "<Select>",
+      "psu__irq_p2f_rpu_permon__int": 0,
+      "psu__irq_p2f_ocm_err__int": 0,
+      "psu__irq_p2f_lpd_apb__int": 0,
+      "psu__irq_p2f_r5_core0_ecc_err__int": 0,
+      "psu__irq_p2f_r5_core1_ecc_err__int": 0,
+      "psu__irq_p2f_nand__int": 0,
+      "psu__irq_p2f_qspi__int": 0,
+      "psu__irq_p2f_gpio__int": 0,
+      "psu__irq_p2f_i2c0__int": 0,
+      "psu__irq_p2f_i2c1__int": 0,
+      "psu__irq_p2f_spi0__int": 0,
+      "psu__irq_p2f_spi1__int": 0,
+      "psu__irq_p2f_uart0__int": 0,
+      "psu__irq_p2f_uart1__int": 0,
+      "psu__irq_p2f_can0__int": 0,
+      "psu__irq_p2f_can1__int": 0,
+      "psu__irq_p2f_lpd_apm__int": 0,
+      "psu__irq_p2f_rtc_alarm__int": 0,
+      "psu__irq_p2f_rtc_seconds__int": 0,
+      "psu__irq_p2f_clkmon__int": 0,
+      "psu__irq_p2f_pl_ipi__int": 0,
+      "psu__irq_p2f_rpu_ipi__int": 0,
+      "psu__irq_p2f_apu_ipi__int": 0,
+      "psu__irq_p2f_ttc0__int0": 0,
+      "psu__irq_p2f_ttc0__int1": 0,
+      "psu__irq_p2f_ttc0__int2": 0,
+      "psu__irq_p2f_ttc1__int0": 0,
+      "psu__irq_p2f_ttc1__int1": 0,
+      "psu__irq_p2f_ttc1__int2": 0,
+      "psu__irq_p2f_ttc2__int0": 0,
+      "psu__irq_p2f_ttc2__int1": 0,
+      "psu__irq_p2f_ttc2__int2": 0,
+      "psu__irq_p2f_ttc3__int0": 0,
+      "psu__irq_p2f_ttc3__int1": 0,
+      "psu__irq_p2f_ttc3__int2": 0,
+      "psu__irq_p2f_sdio0__int": 0,
+      "psu__irq_p2f_sdio1__int": 0,
+      "psu__irq_p2f_sdio0_wake__int": 0,
+      "psu__irq_p2f_sdio1_wake__int": 0,
+      "psu__irq_p2f_lp_wdt__int": 0,
+      "psu__irq_p2f_csupmu_wdt__int": 0,
+      "psu__irq_p2f_atb_lpd__int": 0,
+      "psu__irq_p2f_aib_axi__int": 0,
+      "psu__irq_p2f_ams__int": 0,
+      "psu__irq_p2f_ent0__int": 0,
+      "psu__irq_p2f_ent0_wakeup__int": 0,
+      "psu__irq_p2f_ent1__int": 0,
+      "psu__irq_p2f_ent1_wakeup__int": 0,
+      "psu__irq_p2f_ent2__int": 0,
+      "psu__irq_p2f_ent2_wakeup__int": 0,
+      "psu__irq_p2f_ent3__int": 0,
+      "psu__irq_p2f_ent3_wakeup__int": 0,
+      "psu__irq_p2f_usb3_endpoint__int0": 0,
+      "psu__irq_p2f_usb3_otg__int0": 0,
+      "psu__irq_p2f_usb3_endpoint__int1": 0,
+      "psu__irq_p2f_usb3_otg__int1": 0,
+      "psu__irq_p2f_usb3_pmu_wakeup__int": 0,
+      "psu__irq_p2f_adma_chan__int": 0,
+      "psu__irq_p2f_csu__int": 0,
+      "psu__irq_p2f_csu_dma__int": 0,
+      "psu__irq_p2f_efuse__int": 0,
+      "psu__irq_p2f_xmpu_lpd__int": 0,
+      "psu__irq_p2f_ddr_ss__int": 0,
+      "psu__irq_p2f_fp_wdt__int": 0,
+      "psu__irq_p2f_pcie_msi__int": 0,
+      "psu__irq_p2f_pcie_legacy__int": 0,
+      "psu__irq_p2f_pcie_dma__int": 0,
+      "psu__irq_p2f_pcie_msc__int": 0,
+      "psu__irq_p2f_dport__int": 0,
+      "psu__irq_p2f_fpd_apb__int": 0,
+      "psu__irq_p2f_fpd_atb_err__int": 0,
+      "psu__irq_p2f_dpdma__int": 0,
+      "psu__irq_p2f_apm_fpd__int": 0,
+      "psu__irq_p2f_gdma_chan__int": 0,
+      "psu__irq_p2f_gpu__int": 0,
+      "psu__irq_p2f_sata__int": 0,
+      "psu__irq_p2f_xmpu_fpd__int": 0,
+      "psu__irq_p2f_apu_cpumnt__int": 0,
+      "psu__irq_p2f_apu_cti__int": 0,
+      "psu__irq_p2f_apu_pmu__int": 0,
+      "psu__irq_p2f_apu_comm__int": 0,
+      "psu__irq_p2f_apu_l2err__int": 0,
+      "psu__irq_p2f_apu_exterr__int": 0,
+      "psu__irq_p2f_apu_regs__int": 0,
+      "psu__irq_p2f__intf_ppd_cci__int": 0,
+      "psu__irq_p2f__intf_fpd_smmu__int": 0,
+      "psu__num_f2p0__intr__inputs": 3,
+      "psu__num_f2p1__intr__inputs": 1,
+      "psu__num_fabric_resets": 1,
+      "psu__gpio_emio_width": 1,
+      "psu__hpm0_fpd__num_write_threads": 4,
+      "psu__hpm0_fpd__num_read_threads": 4,
+      "psu__hpm1_fpd__num_write_threads": 4,
+      "psu__hpm1_fpd__num_read_threads": 4,
+      "psu__hpm0_lpd__num_write_threads": 4,
+      "psu__hpm0_lpd__num_read_threads": 4,
+      "psu__tristate__inverted": 1,
+      "psu__gpio_emio__width": "[94:0]",
+      "psu__report__dbglog": 0,
+      "iic0_board_interface": "custom",
+      "iic1_board_interface": "custom",
+      "qspi_board_interface": "custom",
+      "nand_board_interface": "custom",
+      "sd0_board_interface": "custom",
+      "sd1_board_interface": "custom",
+      "can0_board_interface": "custom",
+      "can1_board_interface": "custom",
+      "pjtag_board_interface": "custom",
+      "pmu_board_interface": "custom",
+      "csu_board_interface": "custom",
+      "spi0_board_interface": "custom",
+      "spi1_board_interface": "custom",
+      "uart0_board_interface": "custom",
+      "uart1_board_interface": "custom",
+      "gpio_board_interface": "custom",
+      "swdt0_board_interface": "custom",
+      "swdt1_board_interface": "custom",
+      "trace_board_interface": "custom",
+      "ttc0_board_interface": "custom",
+      "ttc1_board_interface": "custom",
+      "ttc2_board_interface": "custom",
+      "ttc3_board_interface": "custom",
+      "gem0_board_interface": "custom",
+      "gem1_board_interface": "custom",
+      "gem2_board_interface": "custom",
+      "gem3_board_interface": "custom",
+      "usb0_board_interface": "custom",
+      "usb1_board_interface": "custom",
+      "pcie_board_interface": "custom",
+      "dp_board_interface": "custom",
+      "sata_board_interface": "custom",
+      "preset": "None",
+      "psu__sd0_route_through_fpd": 0,
+      "psu__sd1_route_through_fpd": 0,
+      "psu__nand_route_through_fpd": 0,
+      "psu__qspi_route_through_fpd": 0,
+      "psu__gem0_route_through_fpd": 0,
+      "psu__gem1_route_through_fpd": 0,
+      "psu__gem2_route_through_fpd": 0,
+      "psu__gem3_route_through_fpd": 0,
+      "psu__rpu_coherency": 0,
+      "psu__pmu_coherency": 0,
+      "psu__csu_coherency": 0,
+      "psu__usb0_coherency": 0,
+      "psu__usb1_coherency": 0,
+      "psu__lpdma0_coherency": 0,
+      "psu__lpdma1_coherency": 0,
+      "psu__lpdma2_coherency": 0,
+      "psu__lpdma3_coherency": 0,
+      "psu__lpdma4_coherency": 0,
+      "psu__lpdma5_coherency": 0,
+      "psu__lpdma6_coherency": 0,
+      "psu__lpdma7_coherency": 0,
+      "psu__sd0_coherency": 0,
+      "psu__sd1_coherency": 0,
+      "psu__nand_coherency": 0,
+      "psu__qspi_coherency": 0,
+      "psu__enet0__tsu__enable": 0,
+      "psu__enet1__tsu__enable": 0,
+      "psu__enet2__tsu__enable": 0,
+      "psu__enet3__tsu__enable": 0,
+      "psu__tsu__bufg_port_pair": 0,
+      "psu__tsu__bufg_port_loopback": 0,
+      "psu__gem0_coherency": 0,
+      "psu__gem1_coherency": 0,
+      "psu__gem2_coherency": 0,
+      "psu__gem3_coherency": 0,
+      "psu__afi0_coherency": 0,
+      "psu__afi1_coherency": 0,
+      "psu__fpdmasters_coherency": 0,
+      "psu__enable__ddr__refresh__signals": 0,
+      "psu__m_axi_gp0__freqmhz": "99.990005",
+      "psu__m_axi_gp1__freqmhz": 10,
+      "psu__m_axi_gp2__freqmhz": 10,
+      "psu__s_axi_gp0__freqmhz": "99.990005",
+      "psu__s_axi_gp1__freqmhz": "99.990005",
+      "psu__s_axi_gp2__freqmhz": 10,
+      "psu__s_axi_gp3__freqmhz": 10,
+      "psu__s_axi_gp4__freqmhz": 10,
+      "psu__s_axi_gp5__freqmhz": 10,
+      "psu__s_axi_gp6__freqmhz": 10,
+      "psu_sd1_internal_bus_width": 8,
+      "component_name": "design_1_zynq_ultra_ps_e_0_1",
+      "edk_iptype": "PERIPHERAL",
+      "c_baseaddr": 1152921507828072448,
+      "c_highaddr": 1152921508364943359
+    },
+    "memory-view": {
+      "M_AXI_HPM0_FPD": {
+        "zynq_axi_dma_0": {
+          "Reg": {
+            "baseaddr": 2684354560,
+            "highaddr": 2684420095,
+            "size": 65536
+          }
+        },
+        "axis_interconnect_0_xbar": {
+          "Reg": {
+            "baseaddr": 2684420096,
+            "highaddr": 2684485631,
+            "size": 65536
+          }
+        },
+        "dino_registerif_0": {
+          "reg0": {
+            "baseaddr": 2684485632,
+            "highaddr": 2684551167,
+            "size": 65536
+          }
+        },
+        "axi_iic_0": {
+          "Reg": {
+            "baseaddr": 2684551168,
+            "highaddr": 2684616703,
+            "size": 65536
+          }
+        }
+      }
+    }
+  }
+}