diff --git a/etc/fpga/zcu106-dino/zcu106-dino.json b/etc/fpga/zcu106-dino/zcu106-dino.json
index 6e1df813a..3052ae878 100644
--- a/etc/fpga/zcu106-dino/zcu106-dino.json
+++ b/etc/fpga/zcu106-dino/zcu106-dino.json
@@ -164,6 +164,9 @@
       "edk_iptype": "PERIPHERAL",
       "c_baseaddr": 2684551168,
       "c_highaddr": 2684616703
+    },
+    "irqs": {
+      "iic2intc_irpt": "zynq_zynq_ultra_ps_e_0:2"
     }
   },
   "axis_interconnect_0_xbar": {
@@ -683,7 +686,11 @@
         "target": "axis_interconnect_0_xbar:M00_AXIS",
         "name": "S2MM"
       }
-    ]
+    ],
+    "irqs": {
+      "mm2s_introut": "zynq_zynq_ultra_ps_e_0:0",
+      "s2mm_introut": "zynq_zynq_ultra_ps_e_0:1"
+    }
   },
   "zynq_axi_read_cache_0": {
     "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
@@ -2475,4 +2482,4 @@
       }
     }
   }
-}
\ No newline at end of file
+}
diff --git a/fpga/lib/utils.cpp b/fpga/lib/utils.cpp
index 4971b11f4..1449c9b96 100644
--- a/fpga/lib/utils.cpp
+++ b/fpga/lib/utils.cpp
@@ -155,7 +155,7 @@ bool fpga::ConnectString::configCrossBar(
   }
 
   auto dinoAdc = std::dynamic_pointer_cast<fpga::ip::DinoAdc>(
-      card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:")));
+      card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_adc:")));
   if (dinoAdc == nullptr) {
     logger->warn("No Dino ADC found on FPGA ");
   }
@@ -209,6 +209,7 @@ bool fpga::ConnectString::configCrossBar(
     }
     dest->connect(dest->getDefaultMasterPort(), src->getDefaultSlavePort());
   }
+  return true;
 }
 
 void fpga::setupColorHandling() {
diff --git a/tools/hwdef-parse.py b/tools/hwdef-parse.py
index f8c9abb4e..d7741b557 100755
--- a/tools/hwdef-parse.py
+++ b/tools/hwdef-parse.py
@@ -6,10 +6,12 @@ Author:     Steffen Vogel <post@steffenvogel.de>
 Author:     Daniel Krebs <github@daniel-krebs.net>
 Author:     Hatim Kanchwala <hatim@hatimak.me>
 Author:		Pascal Bauer <pascal.bauer@rwth-aachen.de>
+Author:     Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de
 SPDX-FileCopyrightText: 2017-2022 Steffen Vogel <post@steffenvogel.de>
 SPDX-FileCopyrightText: 2017-2022 Daniel Krebs <github@daniel-krebs.net>
 SPDX-FileCopyrightText: 2017-2022 Hatim Kanchwala <hatim@hatimak.me>
 SPDX-FileCopyrightText: 2023 Pascal Bauer <pascal.bauer@rwth-aachen.de>
+SPDX-FileCopyrightText: 2024 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 SPDX-License-Identifier: GPL-3.0-or-later
 
 This program is free software: you can redistribute it and/or modify
@@ -256,14 +258,26 @@ for busif in busifs:
 ips[switch.get("INSTANCE")]["num_ports"] = int(switch_ports / 2)
 
 # find interrupt assignments
-intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')
-if intc is not None:
-    intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0]
-    concat = root.xpath(
-        './/MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(
-            intr.get("SIGNAME")
-        )
-    )[0]
+
+
+
+# find interrupt assignments
+intr_controllers = []
+intr_signals = []
+
+intc_pcie = root.findall('.//MODULE[@MODTYPE="axi_pcie_intc"]')
+intc_zynq = root.findall('.//MODULE[@MODTYPE="zynq_ultra_ps_e"]')
+
+intr_controllers += intc_pcie
+for intc in intc_pcie:
+    intr_signals.append(intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0].get("SIGNAME"))
+
+intr_controllers += intc_zynq
+for intc in intc_zynq:
+    intr_signals.append(intc.xpath('.//PORT[@NAME="pl_ps_irq0" and @DIR="I"]')[0].get("SIGNAME"))
+
+for intc, intr in zip(intr_controllers, intr_signals):
+    concat = root.xpath('.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(intr))[0]
     ports = concat.xpath('.//PORT[@DIR="I"]')
 
     for port in ports: