diff --git a/fpga/Dockerfile b/fpga/Dockerfile index e7e08ae42..1734a5def 100644 --- a/fpga/Dockerfile +++ b/fpga/Dockerfile @@ -8,7 +8,7 @@ # by running: # make docker # -# @author Steffen Vogel +# @author Steffen Vogel # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC # @license GNU General Public License (version 3) # @@ -36,7 +36,7 @@ LABEL \ org.label-schema.license="GPL-3.0" \ org.label-schema.vendor="Institute for Automation of Complex Power Systems, RWTH Aachen University" \ org.label-schema.author.name="Steffen Vogel" \ - org.label-schema.author.email="stvogel@eonerc.rwth-aachen.de" \ + org.label-schema.author.email="post@steffenvogel.de" \ org.label-schema.description="A image containing all build-time dependencies for VILLASfpga based on Fedora" \ org.label-schema.url="http://fein-aachen.org/projects/villas-framework/" \ org.label-schema.vcs-url="https://git.rwth-aachen.de/VILLASframework/VILLASfpga" \ diff --git a/fpga/README.md b/fpga/README.md index 0548c9c53..1abfa2a50 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -12,7 +12,7 @@ User documentation is available here: -- 2018-2022 Steffen Vogel +- 2018-2022 Steffen Vogel - 2018 Daniel Krebs ## License @@ -46,7 +46,7 @@ For other licensing options please consult [Prof. Antonello Monti](mailto:amonti [![EONERC ACS Logo](doc/pictures/eonerc_logo.png)](http://www.acs.eonerc.rwth-aachen.de) - Niklas Eiling -- Steffen Vogel +- Steffen Vogel - Daniel Krebs [Institute for Automation of Complex Power Systems (ACS)](http://www.acs.eonerc.rwth-aachen.de) diff --git a/fpga/include/villas/fpga/card.hpp b/fpga/include/villas/fpga/card.hpp index 5a1e5741f..5b071089c 100644 --- a/fpga/include/villas/fpga/card.hpp +++ b/fpga/include/villas/fpga/card.hpp @@ -3,7 +3,7 @@ * This class represents a FPGA device. * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/config.h b/fpga/include/villas/fpga/config.h index 67c90b008..0f1c3960e 100644 --- a/fpga/include/villas/fpga/config.h +++ b/fpga/include/villas/fpga/config.h @@ -4,7 +4,7 @@ * This settings are not part of the configuration file. * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) * diff --git a/fpga/include/villas/fpga/core.hpp b/fpga/include/villas/fpga/core.hpp index a7cea5ab2..43c0cbe1e 100644 --- a/fpga/include/villas/fpga/core.hpp +++ b/fpga/include/villas/fpga/core.hpp @@ -3,7 +3,7 @@ * This class represents a module within the FPGA. * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/dma.hpp b/fpga/include/villas/fpga/ips/dma.hpp index 0d32f1468..dcf36d752 100644 --- a/fpga/include/villas/fpga/ips/dma.hpp +++ b/fpga/include/villas/fpga/ips/dma.hpp @@ -1,7 +1,7 @@ /** DMA driver * * @author Daniel Krebs - * @author Steffen Vogel + * @author Steffen Vogel * @author Niklas Eiling * @copyright 2018-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/emc.hpp b/fpga/include/villas/fpga/ips/emc.hpp index f66852b6b..61a1c329c 100644 --- a/fpga/include/villas/fpga/ips/emc.hpp +++ b/fpga/include/villas/fpga/ips/emc.hpp @@ -1,7 +1,7 @@ /** AXI External Memory Controller (EMC) * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2020, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/include/villas/fpga/ips/fifo.hpp b/fpga/include/villas/fpga/ips/fifo.hpp index 5c33b97a8..daca91164 100644 --- a/fpga/include/villas/fpga/ips/fifo.hpp +++ b/fpga/include/villas/fpga/ips/fifo.hpp @@ -2,7 +2,7 @@ * * These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*) * - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/gpio.hpp b/fpga/include/villas/fpga/ips/gpio.hpp index 2c73fc4ff..d12effe8f 100644 --- a/fpga/include/villas/fpga/ips/gpio.hpp +++ b/fpga/include/villas/fpga/ips/gpio.hpp @@ -1,7 +1,7 @@ /** AXI General Purpose IO (GPIO) * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2020, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/intc.hpp b/fpga/include/villas/fpga/ips/intc.hpp index d707b5140..c4fe8fcac 100644 --- a/fpga/include/villas/fpga/ips/intc.hpp +++ b/fpga/include/villas/fpga/ips/intc.hpp @@ -1,7 +1,7 @@ /** AXI-PCIe Interrupt controller * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/pcie.hpp b/fpga/include/villas/fpga/ips/pcie.hpp index 2c2316538..9b8269b99 100644 --- a/fpga/include/villas/fpga/ips/pcie.hpp +++ b/fpga/include/villas/fpga/ips/pcie.hpp @@ -3,7 +3,7 @@ * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*) * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/rtds.hpp b/fpga/include/villas/fpga/ips/rtds.hpp index 5fc84898b..7c38bce28 100644 --- a/fpga/include/villas/fpga/ips/rtds.hpp +++ b/fpga/include/villas/fpga/ips/rtds.hpp @@ -1,7 +1,7 @@ /** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis ) * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/include/villas/fpga/ips/switch.hpp b/fpga/include/villas/fpga/ips/switch.hpp index 46562d067..eb8cd1cb2 100644 --- a/fpga/include/villas/fpga/ips/switch.hpp +++ b/fpga/include/villas/fpga/ips/switch.hpp @@ -3,7 +3,7 @@ * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*) * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/ips/timer.hpp b/fpga/include/villas/fpga/ips/timer.hpp index 8f57968f9..6491c3c37 100644 --- a/fpga/include/villas/fpga/ips/timer.hpp +++ b/fpga/include/villas/fpga/ips/timer.hpp @@ -2,7 +2,7 @@ * * These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*) * - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/include/villas/fpga/node.hpp b/fpga/include/villas/fpga/node.hpp index 0ae11a2d9..8a3defed1 100644 --- a/fpga/include/villas/fpga/node.hpp +++ b/fpga/include/villas/fpga/node.hpp @@ -3,7 +3,7 @@ * This class represents a module within the FPGA. * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) diff --git a/fpga/lib/card.cpp b/fpga/lib/card.cpp index b82d8bf0b..4c7053540 100644 --- a/fpga/lib/card.cpp +++ b/fpga/lib/card.cpp @@ -1,6 +1,6 @@ /** FPGA card. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) * diff --git a/fpga/lib/core.cpp b/fpga/lib/core.cpp index df1bdb094..314771f0e 100644 --- a/fpga/lib/core.cpp +++ b/fpga/lib/core.cpp @@ -1,6 +1,6 @@ /** FPGA IP component. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) * diff --git a/fpga/lib/ips/emc.cpp b/fpga/lib/ips/emc.cpp index f471a8bf4..62d4a3cfb 100644 --- a/fpga/lib/ips/emc.cpp +++ b/fpga/lib/ips/emc.cpp @@ -1,6 +1,6 @@ /** AXI External Memory Controller (EMC) * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2020, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/lib/ips/fifo.cpp b/fpga/lib/ips/fifo.cpp index b649018df..3e4a9f7f9 100644 --- a/fpga/lib/ips/fifo.cpp +++ b/fpga/lib/ips/fifo.cpp @@ -2,7 +2,7 @@ * * These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*) * - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/lib/ips/gpio.cpp b/fpga/lib/ips/gpio.cpp index 1199394f9..669ca2b1a 100644 --- a/fpga/lib/ips/gpio.cpp +++ b/fpga/lib/ips/gpio.cpp @@ -1,6 +1,6 @@ /** AXI General Purpose IO (GPIO) * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2020, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/lib/ips/intc.cpp b/fpga/lib/ips/intc.cpp index bba726609..20d10dcaf 100644 --- a/fpga/lib/ips/intc.cpp +++ b/fpga/lib/ips/intc.cpp @@ -1,6 +1,6 @@ /** AXI-PCIe Interrupt controller * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/lib/ips/rtds.cpp b/fpga/lib/ips/rtds.cpp index b2dd672df..a84a5deb5 100644 --- a/fpga/lib/ips/rtds.cpp +++ b/fpga/lib/ips/rtds.cpp @@ -1,6 +1,6 @@ /** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis ) * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/lib/ips/switch.cpp b/fpga/lib/ips/switch.cpp index 588489470..86db05ab3 100644 --- a/fpga/lib/ips/switch.cpp +++ b/fpga/lib/ips/switch.cpp @@ -2,7 +2,7 @@ * * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*) * - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/lib/ips/timer.cpp b/fpga/lib/ips/timer.cpp index 3b5398753..d1a675ece 100644 --- a/fpga/lib/ips/timer.cpp +++ b/fpga/lib/ips/timer.cpp @@ -2,7 +2,7 @@ * * These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*) * - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) diff --git a/fpga/lib/vlnv.cpp b/fpga/lib/vlnv.cpp index 6f915113e..42abdf733 100644 --- a/fpga/lib/vlnv.cpp +++ b/fpga/lib/vlnv.cpp @@ -1,6 +1,6 @@ /** Vendor, Library, Name, Version (VLNV) tag * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC * @license GNU General Public License (version 3) * diff --git a/fpga/past-commits.txt b/fpga/past-commits.txt index 638d36fce..323e34876 100644 --- a/fpga/past-commits.txt +++ b/fpga/past-commits.txt @@ -22,7 +22,7 @@ a4120eda2d327aa537fa874885c200c858202fcc ips/dma: acknowledge interrupts in DMA --- -I, Steffen Vogel hereby sign-off-by all of my past commits to this repo subject to the Developer Certificate of Origin (DCO), Version 1.1. In the past I have used emails: post@steffenvogel.de, stvogel@eonerc.rwth-aachen.de +I, Steffen Vogel hereby sign-off-by all of my past commits to this repo subject to the Developer Certificate of Origin (DCO), Version 1.1. In the past I have used emails: post@steffenvogel.de, post@steffenvogel.de e256a94957294714d6bf645fa9c9f17253fa154e Merge branch 'fix-dockerfile' into 'master' 44fcb85aebeedc531b061d41c847eabbc8cee478 minor code-style fixes diff --git a/fpga/scripts/non_root.sh b/fpga/scripts/non_root.sh index 74ecf9000..187d534e9 100755 --- a/fpga/scripts/non_root.sh +++ b/fpga/scripts/non_root.sh @@ -2,7 +2,7 @@ # # Setup VFIO for non-root users # -# @author Steffen Vogel +# @author Steffen Vogel # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC # @license GNU General Public License (version 3) # diff --git a/fpga/scripts/rebind_device.sh b/fpga/scripts/rebind_device.sh index af0784626..17a019930 100755 --- a/fpga/scripts/rebind_device.sh +++ b/fpga/scripts/rebind_device.sh @@ -2,7 +2,7 @@ # # Detach and rebind a PCI device to a PCI kernel driver # -# @author Steffen Vogel +# @author Steffen Vogel # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC # @license GNU General Public License (version 3) # diff --git a/fpga/scripts/reset_pci_device.sh b/fpga/scripts/reset_pci_device.sh index 25c9fe26f..8c6112d80 100755 --- a/fpga/scripts/reset_pci_device.sh +++ b/fpga/scripts/reset_pci_device.sh @@ -2,7 +2,7 @@ # # Reset PCI devices like FPGAs after a reflash # -# @author Steffen Vogel +# @author Steffen Vogel # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC # @license GNU General Public License (version 3) # diff --git a/fpga/tests/unit/dma.cpp b/fpga/tests/unit/dma.cpp index 47b9f3530..66f62e783 100644 --- a/fpga/tests/unit/dma.cpp +++ b/fpga/tests/unit/dma.cpp @@ -1,6 +1,6 @@ /** DMA unit test. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/fifo.cpp b/fpga/tests/unit/fifo.cpp index 9ce52e419..d84f2f1f4 100644 --- a/fpga/tests/unit/fifo.cpp +++ b/fpga/tests/unit/fifo.cpp @@ -1,6 +1,6 @@ /** FIFO unit test. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/fpga.cpp b/fpga/tests/unit/fpga.cpp index c0fcd54b4..5a50ad2c2 100644 --- a/fpga/tests/unit/fpga.cpp +++ b/fpga/tests/unit/fpga.cpp @@ -1,6 +1,6 @@ /** FPGA related code for bootstrapping the unit-tests * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2018-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/global.hpp b/fpga/tests/unit/global.hpp index 9a820140b..18e097aee 100644 --- a/fpga/tests/unit/global.hpp +++ b/fpga/tests/unit/global.hpp @@ -1,6 +1,6 @@ /** Global include for tests. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/gpu.cpp b/fpga/tests/unit/gpu.cpp index 4ee247879..4a7087274 100644 --- a/fpga/tests/unit/gpu.cpp +++ b/fpga/tests/unit/gpu.cpp @@ -1,6 +1,6 @@ /** GPU unit tests. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/logging.cpp b/fpga/tests/unit/logging.cpp index 6075d0c35..f91007063 100644 --- a/fpga/tests/unit/logging.cpp +++ b/fpga/tests/unit/logging.cpp @@ -1,6 +1,6 @@ /** Logging utilities for unit test. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/main.cpp b/fpga/tests/unit/main.cpp index 1ecd007d3..b31c062bc 100644 --- a/fpga/tests/unit/main.cpp +++ b/fpga/tests/unit/main.cpp @@ -1,6 +1,6 @@ /** Main Unit Test entry point. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/rtds.cpp b/fpga/tests/unit/rtds.cpp index cc74eea6f..02b2e3bb7 100644 --- a/fpga/tests/unit/rtds.cpp +++ b/fpga/tests/unit/rtds.cpp @@ -1,6 +1,6 @@ /** RTDS AXI-Stream RTT unit test. * - * @author Steffen Vogel + * @author Steffen Vogel * @author Daniel Krebs * @copyright 2018-2022, Steffen Vogel, Daniel Krebs * @license GNU General Public License (version 3) diff --git a/fpga/tests/unit/rtds2gpu.cpp b/fpga/tests/unit/rtds2gpu.cpp index e6a37a0b1..23c6f8659 100644 --- a/fpga/tests/unit/rtds2gpu.cpp +++ b/fpga/tests/unit/rtds2gpu.cpp @@ -1,7 +1,7 @@ /** FIFO unit test. * * @file - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/rtds_rtt.cpp b/fpga/tests/unit/rtds_rtt.cpp index b1ca02eec..3bc392efe 100644 --- a/fpga/tests/unit/rtds_rtt.cpp +++ b/fpga/tests/unit/rtds_rtt.cpp @@ -1,6 +1,6 @@ /** RTDS AXI-Stream RTT unit test. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) * diff --git a/fpga/tests/unit/timer.cpp b/fpga/tests/unit/timer.cpp index dabff6be6..83504ae26 100644 --- a/fpga/tests/unit/timer.cpp +++ b/fpga/tests/unit/timer.cpp @@ -1,6 +1,6 @@ /** Timer/Counter unit test. * - * @author Steffen Vogel + * @author Steffen Vogel * @copyright 2017-2022, Steffen Vogel * @license GNU General Public License (version 3) *