From 26e6d69bfe1bcf00daef2de91ab06f7de1299887 Mon Sep 17 00:00:00 2001
From: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
Date: Wed, 13 Nov 2024 10:25:06 +0100
Subject: [PATCH] fpga: add --timestep option to villas-fpga-ctrl

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
---
 fpga/src/villas-fpga-ctrl.cpp | 52 +++--------------------------------
 1 file changed, 4 insertions(+), 48 deletions(-)

diff --git a/fpga/src/villas-fpga-ctrl.cpp b/fpga/src/villas-fpga-ctrl.cpp
index 6232ac782..ccf034199 100644
--- a/fpga/src/villas-fpga-ctrl.cpp
+++ b/fpga/src/villas-fpga-ctrl.cpp
@@ -69,52 +69,6 @@ void writeToDmaFromStdIn(std::shared_ptr<villas::fpga::ip::Dma> dma) {
     auto writeComp = dma->writeComplete();
     logger->debug("Wrote {} bytes", writeComp.bytes);
   }
-  // auto &alloc = villas::HostRam::getAllocator();
-
-  // const std::shared_ptr<villas::MemoryBlock> block[] = {
-  //  alloc.allocateBlock(0x200 * sizeof(uint32_t)),
-  //  alloc.allocateBlock(0x200 * sizeof(uint32_t))
-  // };
-  // villas::MemoryAccessor<int32_t> mem[] = {*block[0], *block[1]};
-
-  // for (auto b : block) {
-  //  dma->makeAccesibleFromVA(b);
-  // }
-
-  // size_t cur = 0, next = 1;
-  // std::ios::sync_with_stdio(false);
-  // std::string line;
-  // bool firstXfer = true;
-
-  // while(true) {
-  //  // Read values from stdin
-
-  //  std::getline(std::cin, line);
-  //  auto values = villas::utils::tokenize(line, ";");
-
-  //  size_t i = 0;
-  //  for (auto &value: values) {
-  //    if (value.empty()) continue;
-
-  //    const float number = std::stof(value);
-  //    mem[cur][i++] = number;
-  //  }
-
-  //  // Initiate write transfer
-  //  bool state = dma->write(*block[cur], i * sizeof(float));
-  //  if (!state)
-  //    logger->error("Failed to write to device");
-
-  //  if (!firstXfer) {
-  //    auto bytesWritten = dma->writeComplete();
-  //    logger->debug("Wrote {} bytes", bytesWritten.bytes);
-  //  } else {
-  //    firstXfer = false;
-  //  }
-
-  //  cur = next;
-  //  next = (next + 1) % (sizeof(mem) / sizeof(mem[0]));
-  // }
 }
 
 void readFromDmaToStdOut(
@@ -196,9 +150,11 @@ int main(int argc, char *argv[]) {
     bool dumpGraph = false;
     app.add_flag("--dump-graph", dumpGraph,
                  "Dumps the graph of memory regions into \"graph.dot\"");
-    bool dumpAuroraChannels = true;
+    bool dumpAuroraChannels = false;
     app.add_flag("--dump-aurora", dumpAuroraChannels,
                  "Dumps the detected Aurora channels.");
+    double timestep = 10e-3;
+    app.add_option("--timestep", timestep, "Timestep generated in the FPGA");
     app.parse(argc, argv);
 
     // Logging setup
@@ -249,7 +205,7 @@ int main(int argc, char *argv[]) {
 
     if (reg != nullptr &&
         card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
-      fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
+      fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, timestep);
     }
 
     if (writeToStdout || readFromStdin) {