diff --git a/fpga/etc/fpga.conf b/fpga/etc/fpga.conf deleted file mode 100644 index dbaf67ba2..000000000 --- a/fpga/etc/fpga.conf +++ /dev/null @@ -1,168 +0,0 @@ -/** Example configuration file for VILLASfpga / VILLASfpga. - * - * The syntax of this file is similar to JSON. - * A detailed description of the format can be found here: - * http://www.hyperrealm.com/libconfig/libconfig_manual.html#Configuration-Files - * - * @author Steffen Vogel - * @copyright 2017-2018, Institute for Automation of Complex Power Systems, EONERC - * @license GNU General Public License (version 3) - * - * VILLASfpga - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - *********************************************************************************/ - -# Some global settings are used by multiple configuration files -# and therefore defined in separate files -@include "global.conf" -@include "plugins.conf" - -############ Dictionary of FPGAs ############ - -fpgas = { - vc707 = { - id = "10ee:7022"; # Card identification - slot = "01:00.0"; # Usually only id or slot is required - - do_reset = true; # Perform a full reset of the FPGA board - # Requires a IP core named 'axi_reset_0' - - ############ List of IP cores on FPGA ############ - # - # Every IP core can have the following settings: - # baseaddr Baseaddress as accessible from BAR0 memory region - # irq Interrupt index of MSI interrupt controller - # port Port index of AXI4-Stream interconnect - - ips = { - ### Utility IPs - axi_pcie_intc_0 = { - vlnv = "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0"; - baseaddr = 0xb000; - }, - switch_0 = { - vlnv = "xilinx.com:ip:axis_interconnect:2.1" - baseaddr = 0x5000; - num_ports = 10; - - paths = ( - // { in = "fifo_mm_s_0", out = "fifo_mm_s_0" }, # Loopback fifo_mm_s_0 - // { in = "dma_0", out = "dma_0" }, # Loopback dma_0 - // { in = "dma_1", out = "dma_1" } # Loopback dma_1 - // { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux <-> RTDS - // { in = "rtds_axis_0", out = "dma_0", reverse = true } # Linux (dma_0) <-> RTDS - { in = "rtds_axis_0", out = "dma_1", reverse = true } # Linux (dma_1) <-> RTDS - // { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux (fifo_mm_s_0) <-> RTDS - // { in = "dma_0", out = "hls_dft_0", reverse = true } # DFT <-> Linux - // { in = "rtds_axis_0", out = "hls_dft_0", reverse = true }, # DFT <-> RTDS - ) - }, - axi_reset_0 = { - vlnv = "xilinx.com:ip:axi_gpio:2.0"; - baseaddr = 0x7000; - }, - timer_0 = { - vlnv = "xilinx.com:ip:axi_timer:2.0"; - baseaddr = 0x4000; - irq = 0; - }, - - ### Data mover IPs - dma_0 = { - vlnv = "xilinx.com:ip:axi_dma:7.1"; - baseaddr = 0x3000; - port = 1; - irq = 3; /* 3 - 4 */ - }, - dma_1 = { - vlnv = "xilinx.com:ip:axi_dma:7.1"; - baseaddr = 0x2000; - port = 6; - irq = 3; /* 3 - 4 */ - }, - fifo_mm_s_0 = { - vlnv = "xilinx.com:ip:axi_fifo_mm_s:4.1"; - baseaddr = 0x6000; - baseaddr_axi4 = 0xC000; - port = 2; - irq = 2; - }, - - ### Interface IPs - rtds_axis_0 = { - vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0"; - baseaddr = 0x8000; - port = 0; - irq = 5; /* 5 -7 */ - }, - - ### Model IPs - hls_dft_0 = { - vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0"; - baseaddr = 0x9000; - port = 5; - irq = 1; - - period = 400; /* in samples: 20ms / 50uS = 400*/ - harmonics = [ 0, 1, 3, 5, 7 ] - decimation = 0; /* 0 = disabled */ - //harmonics = [ 0, 1, 2, 5, 22 ] - }, - axis_data_fifo_0 = { - vlnv = "xilinx.com:ip:axis_data_fifo:1.1"; - port = 3; - }, - axis_data_fifo_1 = { - vlnv = "xilinx.com:ip:axis_data_fifo:1.1"; - port = 6; - }, - } - } -} - -############ Dictionary of nodes ############ - -nodes = { - dma_0 = { - type = "fpga"; # Datamovers to VILLASfpga - datamover = "dma_0"; # Name of IP core in fpga.ips - use_irqs = false; # Use polling or MSI interrupts? - }, - dma_1 = { - type = "fpga"; - datamover = "dma_1"; - use_irqs = false; - }, - fifo_0 = { - type = "fpga"; - datamover = "fifo_mm_s_0"; - use_irqs = false; - }, - simple_circuit = { - type = "cbuilder"; - model = "simple_circuit", - timestep = 25e-6; # in seconds - parameters = [ - 1.0, # R2 = 1 Ohm - 0.001 # C2 = 1000 uF - ]; - } -} - -############ List of paths ############ - -paths = ( - { in = "dma_1", out = "simple_circuit", reverse = true } -) diff --git a/fpga/etc/fpga.json b/fpga/etc/fpga.json deleted file mode 100644 index 8fc472482..000000000 --- a/fpga/etc/fpga.json +++ /dev/null @@ -1,575 +0,0 @@ -{ - "affinity": 1, - "stats": 3, - "name": "villas-acs", - "logging": { - "level": 5, - "faciltities": [ - "path", - "socket" - ], - "file": "/var/log/villas-node.log", - "syslog": true - }, - "http": { - "enabled": true, - "port": 80 - }, - "plugins": [ - "simple_circuit.so", - "example_hook.so" - ], - "fpgas": { - "vc707": { - "id": "10ee:7022", - "slot": "03:00.0", - "do_reset": true, - "ips": { - "bram_0_axi_bram_ctrl_0": { - "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.0", - "size": 8192 - }, - "hier_0_axi_dma_axi_dma_0": { - "vlnv": "xilinx.com:ip:axi_dma:7.1", - "memory-view": { - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - }, - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - }, - "M_AXI_SG": { - "hier_0_axi_dma_axi_dma_0": { - "Reg": { - "baseaddr": 4096, - "highaddr": 8191, - "size": 4096 - } - }, - "hier_0_axi_dma_axi_dma_1": { - "Reg": { - "baseaddr": 8192, - "highaddr": 12287, - "size": 4096 - } - }, - "hier_0_axi_fifo_mm_s_0": { - "Mem0": { - "baseaddr": 12288, - "highaddr": 16383, - "size": 4096 - }, - "Mem1": { - "baseaddr": 16384, - "highaddr": 24575, - "size": 8192 - } - }, - "pcie_0_axi_pcie_intc_0": { - "Reg": { - "baseaddr": 24576, - "highaddr": 28671, - "size": 4096 - } - }, - "pcie_0_axi_reset_0": { - "Reg": { - "baseaddr": 28672, - "highaddr": 32767, - "size": 4096 - } - }, - "timer_0_axi_timer_0": { - "Reg": { - "baseaddr": 32768, - "highaddr": 36863, - "size": 4096 - } - }, - "hier_0_hls_dft_0": { - "Reg": { - "baseaddr": 36864, - "highaddr": 40959, - "size": 4096 - } - }, - "hier_0_rtds_axis_0": { - "reg0": { - "baseaddr": 40960, - "highaddr": 45055, - "size": 4096 - } - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "Reg": { - "baseaddr": 45056, - "highaddr": 49151, - "size": 4096 - } - }, - "bram_0_axi_bram_ctrl_0": { - "Mem0": { - "baseaddr": 49152, - "highaddr": 57343, - "size": 8192 - } - }, - "hier_0_rtds2gpu_0": { - "Reg": { - "baseaddr": 57344, - "highaddr": 61439, - "size": 4096 - } - }, - "hier_0_gpu2rtds_0": { - "Reg": { - "baseaddr": 61440, - "highaddr": 65535, - "size": 4096 - } - }, - "pcie_0_axi_pcie_0": { - "CTL0": { - "baseaddr": 268435456, - "highaddr": 536870911, - "size": 268435456 - } - } - } - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS", - "name": "MM2S" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS", - "name": "S2MM" - } - ], - "irqs": { - "mm2s_introut": "pcie_0_axi_pcie_intc_0:3", - "s2mm_introut": "pcie_0_axi_pcie_intc_0:4" - } - }, - "hier_0_axi_dma_axi_dma_1": { - "vlnv": "xilinx.com:ip:axi_dma:7.1", - "memory-view": { - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - }, - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S06_AXIS", - "name": "MM2S" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M06_AXIS", - "name": "S2MM" - } - ], - "irqs": { - "mm2s_introut": "pcie_0_axi_pcie_intc_0:3", - "s2mm_introut": "pcie_0_axi_pcie_intc_0:4" - } - }, - "hier_0_axi_fifo_mm_s_0": { - "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS", - "name": "STR_TXD" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS", - "name": "STR_RXD" - } - ], - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:2" - } - }, - "hier_0_axis_data_fifo_0": { - "vlnv": "xilinx.com:ip:axis_data_fifo:1.1", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS", - "name": "AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS", - "name": "AXIS" - } - ] - }, - "hier_0_axis_data_fifo_1": { - "vlnv": "xilinx.com:ip:axis_data_fifo:1.1", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS", - "name": "AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS", - "name": "AXIS" - } - ] - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "vlnv": "xilinx.com:ip:axis_switch:1.1", - "ports": [ - { - "role": "slave", - "target": "hier_0_rtds_axis_0:m_axis", - "name": "S00_AXIS" - }, - { - "role": "master", - "target": "hier_0_rtds_axis_0:s_axis", - "name": "M00_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_dma_axi_dma_0:MM2S", - "name": "S01_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_dma_axi_dma_0:S2MM", - "name": "M01_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_fifo_mm_s_0:STR_TXD", - "name": "S02_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_fifo_mm_s_0:STR_RXD", - "name": "M02_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "S03_AXIS" - }, - { - "role": "master", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "M03_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "S04_AXIS" - }, - { - "role": "master", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "M04_AXIS" - }, - { - "role": "slave", - "target": "hier_0_hls_dft_0:output_r", - "name": "S05_AXIS" - }, - { - "role": "master", - "target": "hier_0_hls_dft_0:input_r", - "name": "M05_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_dma_axi_dma_1:MM2S", - "name": "S06_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_dma_axi_dma_1:S2MM", - "name": "M06_AXIS" - }, - { - "role": "slave", - "target": "hier_0_gpu2rtds_0:rtds_output", - "name": "S07_AXIS" - }, - { - "role": "master", - "target": "hier_0_rtds2gpu_0:rtds_input", - "name": "M07_AXIS" - } - ], - "num_ports": 8 - }, - "hier_0_gpu2rtds_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:hls:gpu2rtds:1.0", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S07_AXIS", - "name": "rtds_output" - } - ] - }, - "hier_0_hls_dft_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.1", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S05_AXIS", - "name": "output_r" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M05_AXIS", - "name": "input_r" - } - ], - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:1" - } - }, - "hier_0_rtds2gpu_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:hls:rtds2gpu:1.1", - "memory-view": { - "m_axi_axi_mm": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M07_AXIS", - "name": "rtds_input" - } - ] - }, - "hier_0_rtds_axis_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS", - "name": "m_axis" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS", - "name": "s_axis" - } - ], - "irqs": { - "irq_ts": "pcie_0_axi_pcie_intc_0:5", - "irq_overflow": "pcie_0_axi_pcie_intc_0:6", - "irq_case": "pcie_0_axi_pcie_intc_0:7" - } - }, - "pcie_0_axi_pcie_0": { - "vlnv": "xilinx.com:ip:axi_pcie:2.8", - "memory-view": { - "M_AXI": { - "hier_0_axi_dma_axi_dma_0": { - "Reg": { - "baseaddr": 4096, - "highaddr": 8191, - "size": 4096 - } - }, - "hier_0_axi_dma_axi_dma_1": { - "Reg": { - "baseaddr": 8192, - "highaddr": 12287, - "size": 4096 - } - }, - "hier_0_axi_fifo_mm_s_0": { - "Mem0": { - "baseaddr": 12288, - "highaddr": 16383, - "size": 4096 - }, - "Mem1": { - "baseaddr": 16384, - "highaddr": 24575, - "size": 8192 - } - }, - "pcie_0_axi_pcie_intc_0": { - "Reg": { - "baseaddr": 24576, - "highaddr": 28671, - "size": 4096 - } - }, - "pcie_0_axi_reset_0": { - "Reg": { - "baseaddr": 28672, - "highaddr": 32767, - "size": 4096 - } - }, - "timer_0_axi_timer_0": { - "Reg": { - "baseaddr": 32768, - "highaddr": 36863, - "size": 4096 - } - }, - "hier_0_hls_dft_0": { - "Reg": { - "baseaddr": 36864, - "highaddr": 40959, - "size": 4096 - } - }, - "hier_0_rtds_axis_0": { - "reg0": { - "baseaddr": 40960, - "highaddr": 45055, - "size": 4096 - } - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "Reg": { - "baseaddr": 45056, - "highaddr": 49151, - "size": 4096 - } - }, - "bram_0_axi_bram_ctrl_0": { - "Mem0": { - "baseaddr": 49152, - "highaddr": 57343, - "size": 8192 - } - }, - "hier_0_rtds2gpu_0": { - "Reg": { - "baseaddr": 57344, - "highaddr": 61439, - "size": 4096 - } - }, - "hier_0_gpu2rtds_0": { - "Reg": { - "baseaddr": 61440, - "highaddr": 65535, - "size": 4096 - } - }, - "pcie_0_axi_pcie_0": { - "CTL0": { - "baseaddr": 268435456, - "highaddr": 536870911, - "size": 268435456 - } - } - } - }, - "axi_bars": { - "BAR0": { - "translation": 0, - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - }, - "pcie_bars": { - "BAR0": { - "translation": 0 - } - } - }, - "pcie_0_axi_pcie_intc_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0" - }, - "pcie_0_axi_reset_0": { - "vlnv": "xilinx.com:ip:axi_gpio:2.0" - }, - "timer_0_axi_timer_0": { - "vlnv": "xilinx.com:ip:axi_timer:2.0", - "irqs": { - "generateout0": "pcie_0_axi_pcie_intc_0:0" - } - } - } - } - }, - "nodes": { - "dma_0": { - "type": "fpga", - "datamover": "dma_0", - "use_irqs": false - }, - "dma_1": { - "type": "fpga", - "datamover": "dma_1", - "use_irqs": false - }, - "fifo_0": { - "type": "fpga", - "datamover": "fifo_mm_s_0", - "use_irqs": false - }, - "simple_circuit": { - "type": "cbuilder", - "model": "simple_circuit", - "timestep": 2.5000000000000001e-5, - "parameters": [ - 1.0, - 0.001 - ] - } - }, - "paths": [ - { - "in": "dma_1", - "out": "simple_circuit", - "reverse": true - } - ] -} diff --git a/fpga/etc/vc707_villas.json b/fpga/etc/vc707_villas.json deleted file mode 100644 index a71a8fecd..000000000 --- a/fpga/etc/vc707_villas.json +++ /dev/null @@ -1,316 +0,0 @@ -{ - "affinity": 1, - "stats": 3, - "name": "villas-acs", - "logging": { - "level": 5, - "faciltities": [ - "path", - "socket" - ], - "file": "/var/log/villas-node.log", - "syslog": true - }, - "http": { - "enabled": true, - "port": 80 - }, - "plugins": [ - "simple_circuit.so", - "example_hook.so" - ], - "fpgas": { - "vc707": { - "id": "10ee:7022", - "do_reset": true, -"ips": -{ - "hier_0_aurora_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:user:aurora:1.9", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS", - "name": "m_axis" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS", - "name": "s_axis" - } - ] - }, - "pcie_0_axi_reset_0": { - "vlnv": "xilinx.com:ip:axi_gpio:2.0" - }, - "hier_0_axis_data_fifo_1": { - "vlnv": "xilinx.com:ip:axis_data_fifo:2.0", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS", - "name": "AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS", - "name": "AXIS" - } - ] - }, - "hier_0_axi_dma_axi_dma_0": { - "vlnv": "xilinx.com:ip:axi_dma:7.1", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS", - "name": "MM2S" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS", - "name": "S2MM" - } - ], - "memory-view": { - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - } - }, - "irqs": { - "mm2s_introut": "pcie_0_axi_pcie_intc_0:2", - "s2mm_introut": "pcie_0_axi_pcie_intc_0:3" - } - }, - "timer_0_axi_timer_0": { - "vlnv": "xilinx.com:ip:axi_timer:2.0", - "irqs": { - "generateout0": "pcie_0_axi_pcie_intc_0:0" - } - }, - "pcie_0_axi_pcie_0": { - "pcie_bars": { - "BAR0": { - "translation": 0 - } - }, - "axi_bars": { - "BAR0": { - "highaddr": 4294967295, - "translation": 0, - "baseaddr": 0, - "size": 4294967296 - } - }, - "vlnv": "xilinx.com:ip:axi_pcie:2.9", - "memory-view": { - "M_AXI": { - "hier_0_aurora_0": { - "reg0": { - "highaddr": 28671, - "baseaddr": 24576, - "size": 4096 - } - }, - "pcie_0_axi_pcie_0": { - "CTL0": { - "highaddr": 536870911, - "baseaddr": 268435456, - "size": 268435456 - } - }, - "hier_0_axi_dma_axi_dma_0": { - "Reg": { - "highaddr": 16383, - "baseaddr": 12288, - "size": 4096 - } - }, - "pcie_0_axi_pcie_intc_0": { - "reg0": { - "highaddr": 8191, - "baseaddr": 4096, - "size": 4096 - } - }, - "timer_0_axi_timer_0": { - "Reg": { - "highaddr": 20479, - "baseaddr": 16384, - "size": 4096 - } - }, - "hier_0_axi_fifo_mm_s_0": { - "Mem1": { - "highaddr": 57343, - "baseaddr": 49152, - "size": 8192 - }, - "Mem0": { - "highaddr": 40959, - "baseaddr": 32768, - "size": 8192 - } - }, - "pcie_0_axi_reset_0": { - "Reg": { - "highaddr": 32767, - "baseaddr": 28672, - "size": 4096 - } - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "Reg": { - "highaddr": 24575, - "baseaddr": 20480, - "size": 4096 - } - } - } - } - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "num_ports": 5, - "vlnv": "xilinx.com:ip:axis_switch:1.1", - "ports": [ - { - "role": "slave", - "target": "hier_0_aurora_0:m_axis", - "name": "S00_AXIS" - }, - { - "role": "master", - "target": "hier_0_aurora_0:s_axis", - "name": "M00_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_dma_axi_dma_0:MM2S", - "name": "S01_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_dma_axi_dma_0:S2MM", - "name": "M01_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_fifo_mm_s_0:STR_TXD", - "name": "S02_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_fifo_mm_s_0:STR_RXD", - "name": "M02_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "S03_AXIS" - }, - { - "role": "master", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "M03_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "S04_AXIS" - }, - { - "role": "master", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "M04_AXIS" - } - ] - }, - "hier_0_axis_data_fifo_0": { - "vlnv": "xilinx.com:ip:axis_data_fifo:2.0", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS", - "name": "AXIS" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS", - "name": "AXIS" - } - ] - }, - "pcie_0_axi_pcie_intc_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.3" - }, - "hier_0_axi_fifo_mm_s_0": { - "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2", - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS", - "name": "STR_TXD" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS", - "name": "STR_RXD" - } - ], - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:1" - } - } -} - } - }, - "nodes": { - "dma_0": { - "type": "fpga", - "datamover": "dma_0", - "use_irqs": false - }, - "dma_1": { - "type": "fpga", - "datamover": "dma_1", - "use_irqs": false - }, - "fifo_0": { - "type": "fpga", - "datamover": "fifo_mm_s_0", - "use_irqs": false - }, - "simple_circuit": { - "type": "cbuilder", - "model": "simple_circuit", - "timestep": 2.5000000000000001e-5, - "parameters": [ - 1.0, - 0.001 - ] - } - }, - "paths": [ - { - "in": "dma_1", - "out": "simple_circuit", - "reverse": true - } - ] -} -