diff --git a/fpga/include/villas/fpga/ips/dma.hpp b/fpga/include/villas/fpga/ips/dma.hpp
index f4175b0df..ce0c899da 100644
--- a/fpga/include/villas/fpga/ips/dma.hpp
+++ b/fpga/include/villas/fpga/ips/dma.hpp
@@ -10,10 +10,12 @@
 #pragma once
 
 #include <fmt/ostream.h>
+
 #include <villas/config.hpp>
 #include <villas/exceptions.hpp>
 #include <villas/fpga/node.hpp>
 #include <villas/memory.hpp>
+
 #include <xilinx/xaxidma.h>
 
 namespace villas {
diff --git a/fpga/lib/ips/dma.cpp b/fpga/lib/ips/dma.cpp
index 1ba98d108..872c0ae22 100644
--- a/fpga/lib/ips/dma.cpp
+++ b/fpga/lib/ips/dma.cpp
@@ -1,24 +1,23 @@
 /* DMA driver
  *
- * Author: Daniel Krebs <github@daniel-krebs.net>
  * Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
- * SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
+ * Author: Daniel Krebs <github@daniel-krebs.net>
+ * SPDX-FileCopyrightText: 2018-2024 Institute for Automation of Complex Power Systems, RWTH Aachen University
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <sstream>
 #include <string>
-
-#include "xilinx/xaxidma_bd.h"
-#include "xilinx/xaxidma_hw.h"
 #include <sys/types.h>
-#include <xilinx/xaxidma.h>
-
-#include <villas/memory.hpp>
 
 #include <villas/fpga/card.hpp>
 #include <villas/fpga/ips/dma.hpp>
 #include <villas/fpga/ips/intc.hpp>
+#include <villas/memory.hpp>
+
+#include <xilinx/xaxidma.h>
+#include <xilinx/xaxidma_bd.h>
+#include <xilinx/xaxidma_hw.h>
 
 // Max. size of a DMA transfer in simple mode
 #define FPGA_DMA_BOUNDARY 0x1000
@@ -116,7 +115,7 @@ void Dma::setupScatterGatherRingRx(uintptr_t physAddr, uintptr_t virtAddr) {
     throw RuntimeError("Failed to clone BD template: {}", ret);
 
   if (cyclic) {
-    /* Enable Cyclic DMA mode */
+    // Enable Cyclic DMA mode
     XAxiDma_BdRingEnableCyclicDMA(rxRingPtr);
     XAxiDma_SelectCyclicMode(&xDma, XAXIDMA_DEVICE_TO_DMA, 1);
   }
@@ -212,7 +211,7 @@ Dma::~Dma() {
       free(rxRingPtr->CyclicBd);
       rxRingPtr->CyclicBd = nullptr;
     }
-    // unampe SG memory Blocks
+    // Unmap SG memory Blocks
     if (sgRing) {
       card->unmapMemoryBlock(*sgRing);
     }
diff --git a/include/villas/nodes/fpga.hpp b/include/villas/nodes/fpga.hpp
index c292f4e56..a124efca3 100644
--- a/include/villas/nodes/fpga.hpp
+++ b/include/villas/nodes/fpga.hpp
@@ -32,7 +32,7 @@ protected:
   std::string cardName;
   std::list<std::string> connectStrings;
 
-  // This setting improves latency by remove various checks.
+  // This setting improves latency by removing various checks.
   // Use with caution! Requires read cache in FPGA design!
   // The common use case in VILLASfpga is that we have exactly
   // one write for every read and the number of exchanged signals