From 409340433dd464e69675d10829e0bd022a4b9989 Mon Sep 17 00:00:00 2001 From: Daniel Krebs Date: Tue, 13 Feb 2018 16:03:38 +0100 Subject: [PATCH] enable -Wall, -Wextra and -Werror and fix new errors (fixes #20) --- fpga/CMakeLists.txt | 1 + fpga/include/villas/dependency_graph_impl.hpp | 1 + fpga/include/villas/directed_graph.hpp | 4 ++++ fpga/include/villas/fpga/card.hpp | 6 ++++-- fpga/include/villas/fpga/ip.hpp | 2 +- fpga/lib/CMakeLists.txt | 2 ++ fpga/lib/ips/fifo.cpp | 2 +- fpga/lib/ips/switch.cpp | 2 +- fpga/tests/logging.cpp | 6 ++++-- 9 files changed, 19 insertions(+), 7 deletions(-) diff --git a/fpga/CMakeLists.txt b/fpga/CMakeLists.txt index 540ccee44..4025ae5b9 100644 --- a/fpga/CMakeLists.txt +++ b/fpga/CMakeLists.txt @@ -5,6 +5,7 @@ project(VILLASfpga C CXX) set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake) set (CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra -Werror") include_directories(thirdparty/spdlog/include) diff --git a/fpga/include/villas/dependency_graph_impl.hpp b/fpga/include/villas/dependency_graph_impl.hpp index 0b4be0869..b8090c2d0 100644 --- a/fpga/include/villas/dependency_graph_impl.hpp +++ b/fpga/include/villas/dependency_graph_impl.hpp @@ -97,6 +97,7 @@ DependencyGraph::getEvaluationOrder() const if(added == 0 and graph.size() > 0) { logger->error("Circular dependency detected! IPs not available:"); for(auto& [key, value] : graph) { + (void) value; logger->error(" {}", key); } break; diff --git a/fpga/include/villas/directed_graph.hpp b/fpga/include/villas/directed_graph.hpp index 8d964dae1..d6d2ee56b 100644 --- a/fpga/include/villas/directed_graph.hpp +++ b/fpga/include/villas/directed_graph.hpp @@ -242,6 +242,8 @@ public: { logger->info("Vertices:"); for(auto& [vertexId, vertex] : vertices) { + (void) vertexId; + // format connected vertices into a list std::stringstream ssEdges; for(auto& edge : vertex->edges) { @@ -253,6 +255,8 @@ public: logger->info("Edges:"); for(auto& [edgeId, edge] : edges) { + (void) edgeId; + logger->info(" {}: {} -> {}", *edge, edge->from, edge->to); } } diff --git a/fpga/include/villas/fpga/card.hpp b/fpga/include/villas/fpga/card.hpp index 729745ab8..20c89876d 100644 --- a/fpga/include/villas/fpga/card.hpp +++ b/fpga/include/villas/fpga/card.hpp @@ -48,8 +48,10 @@ #define PCI_FILTER_DEFAULT_FPGA { \ .id = { \ .vendor = FPGA_PCI_VID_XILINX, \ - .device = FPGA_PCI_PID_VFPGA \ - } \ + .device = FPGA_PCI_PID_VFPGA, \ + .class_code = 0 \ + }, \ + .slot = { } \ } namespace villas { diff --git a/fpga/include/villas/fpga/ip.hpp b/fpga/include/villas/fpga/ip.hpp index 53ac244ad..b71f5d700 100644 --- a/fpga/include/villas/fpga/ip.hpp +++ b/fpga/include/villas/fpga/ip.hpp @@ -161,7 +161,7 @@ private: virtual IpCore* create() = 0; /// Configure IP instance from JSON config - virtual bool configureJson(IpCore& ip, json_t *json) + virtual bool configureJson(IpCore& /* ip */, json_t* /* json */) { return true; } diff --git a/fpga/lib/CMakeLists.txt b/fpga/lib/CMakeLists.txt index 2302a32eb..ae55a332f 100644 --- a/fpga/lib/CMakeLists.txt +++ b/fpga/lib/CMakeLists.txt @@ -45,6 +45,8 @@ find_package(Threads) add_library(villas-fpga SHARED ${SOURCES}) +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra") + target_compile_definitions(villas-fpga PRIVATE BUILDID=\"abc\" _GNU_SOURCE diff --git a/fpga/lib/ips/fifo.cpp b/fpga/lib/ips/fifo.cpp index 087d3ad8f..9c465302e 100644 --- a/fpga/lib/ips/fifo.cpp +++ b/fpga/lib/ips/fifo.cpp @@ -67,7 +67,7 @@ bool Fifo::init() fifo_cfg.Axi4BaseAddress = getAddrMapped(this->baseaddr_axi4); // use AXI4 for Data, AXI4-Lite for control - fifo_cfg.Datainterface = (this->baseaddr_axi4 != -1) ? 1 : 0; + fifo_cfg.Datainterface = (this->baseaddr_axi4 != static_cast(-1)) ? 1 : 0; if (XLlFifo_CfgInitialize(&xFifo, &fifo_cfg, getBaseaddr()) != XST_SUCCESS) return false; diff --git a/fpga/lib/ips/switch.cpp b/fpga/lib/ips/switch.cpp index 9f5a73470..98c6534e2 100644 --- a/fpga/lib/ips/switch.cpp +++ b/fpga/lib/ips/switch.cpp @@ -53,7 +53,7 @@ AxiStreamSwitch::init() XAxisScr_RegUpdateEnable(&xSwitch); // initialize internal mapping - for(int portMaster = 0; portMaster < portsMaster.size(); portMaster++) { + for(size_t portMaster = 0; portMaster < portsMaster.size(); portMaster++) { portMapping[portMaster] = PORT_DISABLED; } diff --git a/fpga/tests/logging.cpp b/fpga/tests/logging.cpp index 64be9274f..cbb3f80b7 100644 --- a/fpga/tests/logging.cpp +++ b/fpga/tests/logging.cpp @@ -19,14 +19,16 @@ struct criterion_prefix_data { const char *color; }; -static void format_msg(char *buf, size_t buflen, const char *msg, va_list args) +static int format_msg(char *buf, size_t buflen, const char *msg, va_list args) { int len = vsnprintf(buf, buflen, msg, args); - + /* Strip new line */ char *nl = strchr(buf, '\n'); if (nl) *nl = 0; + + return len; } void criterion_log_noformat(enum criterion_severity severity, const char *msg)