From 4db0a980829890c48d15afa5a1ecdfb3495a1d4f Mon Sep 17 00:00:00 2001 From: daniel-k Date: Wed, 17 Jan 2018 16:32:14 +0100 Subject: [PATCH] scripts/hwdef-parse: add memory view for each instance --- fpga/scripts/hwdef-parse.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/fpga/scripts/hwdef-parse.py b/fpga/scripts/hwdef-parse.py index a1ca66923..24708112c 100755 --- a/fpga/scripts/hwdef-parse.py +++ b/fpga/scripts/hwdef-parse.py @@ -86,6 +86,9 @@ def vlnv_match(vlnv, whitelist): return False +def remove_prefix(text, prefix): + return text[text.startswith(prefix) and len(prefix):] + if len(sys.argv) < 2: print('Usage: {} path/to/*.hwdef'.format(sys.argv[0])) print(' {} path/to/*.xml'.format(sys.argv[0])) @@ -122,6 +125,23 @@ for module in modules: 'vlnv' : vlnv } + # populate memory view + mmap = module.find('.//MEMORYMAP') + if not mmap: + continue + + mem = ips[instance].setdefault('memory-view', {}) + for mrange in mmap: + mem_interface = remove_prefix(mrange.get('MASTERBUSINTERFACE'), 'M_AXI_') + mem_instance = mrange.get('INSTANCE') + + entry = mem.setdefault(mem_interface, {}).setdefault(mem_instance, {}) + + entry['baseaddr'] = int(mrange.get('BASEVALUE'), 16); + entry['highaddr'] = int(mrange.get('HIGHVALUE'), 16); + + + # find PCI-e module to extract memory map pcie = root.find('.//MODULE[@MODTYPE="axi_pcie"]') mmap = pcie.find('.//MEMORYMAP')