diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 3c2bf76e1..3a310fc4e 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -292,10 +292,10 @@ deploy:docker-dev-vscode:
before_script:
- docker login -u ${CI_REGISTRY_USER} -p ${CI_REGISTRY_PASSWORD} ${CI_REGISTRY}
script:
+ - docker manifest rm ${DOCKER_IMAGE}:latest || true
- docker manifest create ${DOCKER_IMAGE}:latest
${DOCKER_IMAGE}:${DOCKER_TAG}-x86_64
${DOCKER_IMAGE}:${DOCKER_TAG}-arm64
- ${DOCKER_IMAGE}:${DOCKER_TAG}-armhf
- docker manifest push ${DOCKER_IMAGE}:latest
tags:
- docker
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index 3106b0570..18ca39b4c 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -1,26 +1,8 @@
# Contribution guidelines
-## Coding standards
-
-We are following the [LLVM C++ Coding Standards](https://llvm.org/docs/CodingStandards.html).
-
-## Always work on feature branches
-
-Please branch from `master` to create a new _feature_ branch.
-
-Please create a new _feature_ branch for every new feature or fix.
-
-## Do not commit directly to `master`.
-
-Use your _feature_ branch.
-
-Please rebase your work against the `develop` before submitting a merge reqeuest.
-
-## Make the CI happy :-)
-
-Only branches which pass the CI can be merged.
+Visit the [contribution guidelines](https://villas.fein-aachen.org/docs/node/development/contributing/) in our documentation to understand how you can contribute to VILLASnode.
diff --git a/README.md b/README.md
index d67a05792..4d5a959e2 100644
--- a/README.md
+++ b/README.md
@@ -36,6 +36,11 @@ User documentation is available here:
- [MIOB](https://github.com/RWTH-ACS/miob)
- [DINO](https://github.com/RWTH-ACS/dino)
+## Contributing
+
+All contributions are welcome!
+If you want to contribute to VILLASnode, please visit the [contribution guidelines](https://villas.fein-aachen.org/docs/node/development/contributing/) in our documentation.
+
## License
This project is released under the terms of the [Apache 2.0 license](LICENSE).
@@ -47,10 +52,10 @@ We kindly ask all academic publications employing components of VILLASframework
For other licensing options please consult [Prof. Antonello Monti](mailto:amonti@eonerc.rwth-aachen.de).
-- SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
-- SPDX-FileCopyrightText: 2023 OPAL-RT Germany GmbH
-- SPDX-FileCopyrightText: 2022-2023 Niklas Eiling
-- SPDX-FileCopyrightText: 2018-2023 Steffen Vogel
+- SPDX-FileCopyrightText: 2014-2024 Institute for Automation of Complex Power Systems, RWTH Aachen University
+- SPDX-FileCopyrightText: 2023-2024 OPAL-RT Germany GmbH
+- SPDX-FileCopyrightText: 2022-2024 Niklas Eiling
+- SPDX-FileCopyrightText: 2018-2024 Steffen Vogel
- SPDX-FileCopyrightText: 2018 Daniel Krebs
- SPDX-License-Identifier: Apache-2.0
diff --git a/etc/examples/nodes/fpga.conf b/etc/examples/nodes/fpga.conf
index c1eb49033..5d6b121e5 100644
--- a/etc/examples/nodes/fpga.conf
+++ b/etc/examples/nodes/fpga.conf
@@ -11,7 +11,7 @@ fpgas = {
id = "10ee:7021"
slot = "0000:88:00.0"
do_reset = true
- ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino-v2.json"
+ ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino.json"
polling = false
}
}
diff --git a/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json b/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json
index 89d1e7780..78867a12f 100644
--- a/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json
+++ b/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json
@@ -229,7 +229,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
- "c_use_crc": "false",
+ "c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
@@ -367,7 +367,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
- "c_use_crc": "false",
+ "c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
@@ -505,7 +505,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
- "c_use_crc": "false",
+ "c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
@@ -913,8 +913,8 @@
"m15_s15_connectivity": 1,
"component_name": "design_1_xbar_0",
"edk_iptype": "PERIPHERAL",
- "c_baseaddr": 0,
- "c_highaddr": 1023
+ "c_baseaddr": 4096,
+ "c_highaddr": 5119
},
"ports": [
{
@@ -969,7 +969,7 @@
},
{
"role": "slave",
- "target": "dino_dinoif_fast_0:M00_AXIS",
+ "target": "dino_dinoif_adc_0:M00_AXIS",
"name": "S05_AXIS"
},
{
@@ -1015,6 +1015,21 @@
"dino_dinoif_dac_0": {
"vlnv": "xilinx.com:module_ref:dinoif_dac:1.0",
"i2c_channel": 1,
+ "parameters": {
+ "component_name": "design_1_dinoif_adc_0_0",
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
+ "name": "M00_AXIS"
+ }
+ ]
+ },
+ "dino_dinoif_fast_nologic_0": {
+ "vlnv": "xilinx.com:module_ref:dinoif_fast:1.0",
+ "i2c_channel": 0,
"parameters": {
"component_name": "design_1_dinoif_dac_0_0",
"edk_iptype": "PERIPHERAL"
@@ -1027,20 +1042,17 @@
}
]
},
- "dino_dinoif_fast_0": {
- "vlnv": "xilinx.com:module_ref:dinoif_fast:1.0",
- "i2c_channel": 0,
+ "dino_registerif_0": {
+ "vlnv": "xilinx.com:module_ref:registerif:1.0",
"parameters": {
- "component_name": "design_1_dinoif_fast_0_0",
- "edk_iptype": "PERIPHERAL"
- },
- "ports": [
- {
- "role": "master",
- "target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
- "name": "M00_AXIS"
- }
- ]
+ "c_axi_data_width": 32,
+ "c_axi_addr_width": 32,
+ "reg_addr_width": 10,
+ "component_name": "design_1_registerif_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 20480,
+ "c_highaddr": 21503
+ }
},
"dma_pcie_axi_dma_0": {
"vlnv": "xilinx.com:ip:axi_dma:7.1",
@@ -1130,6 +1142,29 @@
"s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
}
},
+ "dma_pcie_axi_read_cache_0": {
+ "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
+ "parameters": {
+ "c_axi_data_width": 32,
+ "c_axi_addr_width": 32,
+ "word_num": 16,
+ "component_name": "design_1_axi_read_cache_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 24576,
+ "c_highaddr": 25599
+ },
+ "memory-view": {
+ "M_AXI": {
+ "dma_pcie_pcie_axi_pcie_0": {
+ "BAR0": {
+ "baseaddr": 0,
+ "highaddr": 4294967295,
+ "size": 4294967296
+ }
+ }
+ }
+ }
+ },
"dma_pcie_pcie_axi_pcie_0": {
"vlnv": "xilinx.com:ip:axi_pcie:2.9",
"parameters": {
@@ -1158,7 +1193,7 @@
"c_interrupt_pin": 0,
"c_comp_timeout": 0,
"c_include_rc": 0,
- "c_s_axi_supports_narrow_burst": 0,
+ "c_s_axi_supports_narrow_burst": 1,
"c_include_baroffset_reg": 1,
"c_axibar_num": 1,
"c_axibar2pciebar_0": 0,
@@ -1281,7 +1316,7 @@
"s_axi_data_width": 64,
"m_axi_addr_width": 32,
"m_axi_data_width": 64,
- "s_axi_supports_narrow_burst": "false",
+ "s_axi_supports_narrow_burst": "true",
"bar_64bit": "false",
"xlnx_ref_board": "VC707",
"pcie_blk_locn": "X1Y0",
@@ -1332,6 +1367,20 @@
"highaddr": 17407,
"size": 1024
}
+ },
+ "dino_registerif_0": {
+ "reg0": {
+ "baseaddr": 20480,
+ "highaddr": 21503,
+ "size": 1024
+ }
+ },
+ "dma_pcie_axi_read_cache_0": {
+ "reg0": {
+ "baseaddr": 24576,
+ "highaddr": 25599,
+ "size": 1024
+ }
}
}
},
diff --git a/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json b/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json
index 2fe40000b..540447f5c 100644
--- a/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json
+++ b/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json
@@ -1,5 +1,5 @@
{
- "aurora_8b10b_ch0": {
+ "aurora_aurora_8b10b_ch0": {
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
"parameters": {
"component_name": "design_1_aurora_8b10b_0_0",
@@ -127,17 +127,17 @@
"ports": [
{
"role": "master",
- "target": "axis_interconnect_0_xbar:S00_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:S00_AXIS",
"name": "USER_DATA_M_AXI_RX"
},
{
"role": "slave",
- "target": "axis_interconnect_0_xbar:M00_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:M00_AXIS",
"name": "USER_DATA_S_AXI_TX"
}
]
},
- "aurora_8b10b_ch1": {
+ "aurora_aurora_8b10b_ch1": {
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
"parameters": {
"component_name": "design_1_aurora_8b10b_1_0",
@@ -229,7 +229,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
- "c_use_crc": "false",
+ "c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
@@ -265,17 +265,17 @@
"ports": [
{
"role": "master",
- "target": "axis_interconnect_0_xbar:S01_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:S01_AXIS",
"name": "USER_DATA_M_AXI_RX"
},
{
"role": "slave",
- "target": "axis_interconnect_0_xbar:M01_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:M01_AXIS",
"name": "USER_DATA_S_AXI_TX"
}
]
},
- "aurora_8b10b_ch2": {
+ "aurora_aurora_8b10b_ch2": {
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
"parameters": {
"component_name": "design_1_aurora_8b10b_3_0",
@@ -367,7 +367,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
- "c_use_crc": "false",
+ "c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
@@ -403,17 +403,17 @@
"ports": [
{
"role": "master",
- "target": "axis_interconnect_0_xbar:S02_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:S02_AXIS",
"name": "USER_DATA_M_AXI_RX"
},
{
"role": "slave",
- "target": "axis_interconnect_0_xbar:M02_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:M02_AXIS",
"name": "USER_DATA_S_AXI_TX"
}
]
},
- "aurora_8b10b_ch3": {
+ "aurora_aurora_8b10b_ch3": {
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
"parameters": {
"component_name": "design_1_aurora_8b10b_2_0",
@@ -505,7 +505,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
- "c_use_crc": "false",
+ "c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
@@ -541,104 +541,16 @@
"ports": [
{
"role": "master",
- "target": "axis_interconnect_0_xbar:S03_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:S03_AXIS",
"name": "USER_DATA_M_AXI_RX"
},
{
"role": "slave",
- "target": "axis_interconnect_0_xbar:M03_AXIS",
+ "target": "crossbar_axis_interconnect_0_xbar:M03_AXIS",
"name": "USER_DATA_S_AXI_TX"
}
]
},
- "axi_dma_0": {
- "vlnv": "xilinx.com:ip:axi_dma:7.1",
- "parameters": {
- "c_s_axi_lite_addr_width": 10,
- "c_s_axi_lite_data_width": 32,
- "c_dlytmr_resolution": 125,
- "c_prmry_is_aclk_async": 0,
- "c_enable_multi_channel": 0,
- "c_num_mm2s_channels": 1,
- "c_num_s2mm_channels": 1,
- "c_include_sg": 1,
- "c_sg_include_stscntrl_strm": 0,
- "c_sg_use_stsapp_length": 0,
- "c_sg_length_width": 14,
- "c_m_axi_sg_addr_width": 32,
- "c_m_axi_sg_data_width": 32,
- "c_m_axis_mm2s_cntrl_tdata_width": 32,
- "c_s_axis_s2mm_sts_tdata_width": 32,
- "c_micro_dma": 0,
- "c_include_mm2s": 1,
- "c_include_mm2s_sf": 1,
- "c_mm2s_burst_size": 16,
- "c_m_axi_mm2s_addr_width": 32,
- "c_m_axi_mm2s_data_width": 32,
- "c_m_axis_mm2s_tdata_width": 32,
- "c_include_mm2s_dre": 0,
- "c_include_s2mm": 1,
- "c_include_s2mm_sf": 1,
- "c_s2mm_burst_size": 16,
- "c_m_axi_s2mm_addr_width": 32,
- "c_m_axi_s2mm_data_width": 32,
- "c_s_axis_s2mm_tdata_width": 32,
- "c_include_s2mm_dre": 0,
- "c_increase_throughput": 0,
- "c_family": "virtex7",
- "component_name": "design_1_axi_dma_0_0",
- "c_addr_width": 32,
- "c_single_interface": 0,
- "edk_iptype": "PERIPHERAL",
- "c_baseaddr": 12288,
- "c_highaddr": 13311
- },
- "memory-view": {
- "M_AXI_SG": {
- "axi_pcie_0": {
- "BAR0": {
- "baseaddr": 0,
- "highaddr": 4294967295,
- "size": 4294967296
- }
- }
- },
- "M_AXI_MM2S": {
- "axi_pcie_0": {
- "BAR0": {
- "baseaddr": 0,
- "highaddr": 4294967295,
- "size": 4294967296
- }
- }
- },
- "M_AXI_S2MM": {
- "axi_pcie_0": {
- "BAR0": {
- "baseaddr": 0,
- "highaddr": 4294967295,
- "size": 4294967296
- }
- }
- }
- },
- "ports": [
- {
- "role": "master",
- "target": "axis_interconnect_0_xbar:S04_AXIS",
- "name": "MM2S"
- },
- {
- "role": "slave",
- "target": "axis_interconnect_0_xbar:M04_AXIS",
- "name": "S2MM"
- }
- ],
- "irqs": {
- "mm2s_introut": "axi_pcie_intc_0:0",
- "s2mm_introut": "axi_pcie_intc_0:1"
- }
- },
"axi_gpio_0": {
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
"parameters": {
@@ -666,234 +578,13 @@
"c_highaddr": 127
}
},
- "axi_pcie_0": {
- "vlnv": "xilinx.com:ip:axi_pcie:2.9",
- "parameters": {
- "c_family": "virtex7",
- "c_instance": "design_1_axi_pcie_0_1",
- "c_s_axi_id_width": 2,
- "c_s_axi_addr_width": 32,
- "c_s_axi_data_width": 64,
- "c_m_axi_addr_width": 32,
- "c_m_axi_data_width": 64,
- "c_no_of_lanes": 1,
- "c_max_link_speed": 1,
- "c_pcie_use_mode": "3.0",
- "c_device_id": 28705,
- "c_vendor_id": 4334,
- "c_class_code": 360448,
- "c_ref_clk_freq": 0,
- "c_rev_id": 0,
- "c_subsystem_id": 7,
- "c_subsystem_vendor_id": 4334,
- "c_pcie_cap_slot_implemented": 0,
- "c_slot_clock_config": "TRUE",
- "c_msi_decode_enable": "TRUE",
- "c_int_fifo_depth": 0,
- "c_num_msi_req": 5,
- "c_interrupt_pin": 0,
- "c_comp_timeout": 0,
- "c_include_rc": 0,
- "c_s_axi_supports_narrow_burst": 0,
- "c_include_baroffset_reg": 1,
- "c_axibar_num": 1,
- "c_axibar2pciebar_0": 0,
- "c_axibar2pciebar_1": 0,
- "c_axibar2pciebar_2": 0,
- "c_axibar2pciebar_3": 0,
- "c_axibar2pciebar_4": 0,
- "c_axibar2pciebar_5": 0,
- "c_axibar_as_0": 0,
- "c_axibar_as_1": 0,
- "c_axibar_as_2": 0,
- "c_axibar_as_3": 0,
- "c_axibar_as_4": 0,
- "c_axibar_as_5": 0,
- "c_axibar_0": 0,
- "c_axibar_highaddr_0": 4294967295,
- "c_axibar_1": 4294967295,
- "c_axibar_highaddr_1": 0,
- "c_axibar_2": 4294967295,
- "c_axibar_highaddr_2": 0,
- "c_axibar_3": 4294967295,
- "c_axibar_highaddr_3": 0,
- "c_axibar_4": 4294967295,
- "c_axibar_highaddr_4": 0,
- "c_axibar_5": 4294967295,
- "c_axibar_highaddr_5": 0,
- "c_pciebar_num": 1,
- "c_pciebar_as": 0,
- "c_pciebar_len_0": 20,
- "c_pciebar2axibar_0": 0,
- "c_pciebar2axibar_0_sec": 1,
- "c_pciebar_len_1": 16,
- "c_pciebar2axibar_1": 4294967295,
- "c_pciebar2axibar_1_sec": 1,
- "c_pciebar_len_2": 16,
- "c_pciebar2axibar_2": 4294967295,
- "c_pciebar2axibar_2_sec": 1,
- "c_pcie_blk_locn": 3,
- "c_xlnx_ref_board": "VC707",
- "pcie_ext_clk": "FALSE",
- "pcie_ext_gt_common": "FALSE",
- "ext_ch_gt_drp": "FALSE",
- "shared_logic_in_core": "false",
- "transceiver_ctrl_status_ports": "FALSE",
- "ext_pipe_interface": "FALSE",
- "c_device": "xc7vx485t",
- "c_speed": -2,
- "axi_aclk_loopback": "false",
- "no_slv_err": "false",
- "c_rp_bar_hide": "FALSE",
- "enable_jtag_dbg": "false",
- "c_axibar_chk_slv_err": "false",
- "reduce_oob_freq": "false",
- "component_name": "design_1_axi_pcie_0_1",
- "include_rc": "PCI_Express_Endpoint_device",
- "ref_clk_freq": "100_MHz",
- "slot_clock_config": "true",
- "pcie_use_mode": "GES_and_Production",
- "no_of_lanes": "X1",
- "max_link_speed": "5.0_GT/s",
- "vendor_id": 4334,
- "device_id": 28705,
- "rev_id": 0,
- "subsystem_vendor_id": 4334,
- "subsystem_id": 7,
- "enable_class_code": "true",
- "class_code": 360448,
- "base_class_menu": "Memory_controller",
- "sub_class_interface_menu": "Other_memory_controller",
- "bar0_enabled": "true",
- "bar1_enabled": "false",
- "bar2_enabled": "false",
- "bar0_type": "Memory",
- "bar1_type": "N/A",
- "bar2_type": "N/A",
- "bar0_scale": "Megabytes",
- "bar1_scale": "N/A",
- "bar2_scale": "N/A",
- "bar0_size": 1,
- "bar1_size": 8,
- "bar2_size": 8,
- "pciebar2axibar_0": 0,
- "pciebar2axibar_1": 4294967295,
- "pciebar2axibar_2": 4294967295,
- "pciebar2axibar_1_sec": 1,
- "pciebar2axibar_0_sec": 1,
- "pciebar2axibar_2_sec": 1,
- "interrupt_pin": "false",
- "msi_decode_enabled": "true",
- "num_msi_req": 5,
- "int_fifo_depth": 16,
- "comp_timeout": "50us",
- "include_baroffset_reg": "true",
- "axibar_as_0": "false",
- "axibar_as_1": "false",
- "axibar_as_2": "false",
- "axibar_as_3": "false",
- "axibar_as_4": "false",
- "axibar_as_5": "false",
- "axibar_1": 4294967295,
- "axibar_2": 4294967295,
- "axibar_3": 4294967295,
- "axibar_4": 4294967295,
- "axibar_5": 4294967295,
- "axibar_highaddr_1": 0,
- "axibar_highaddr_2": 0,
- "axibar_highaddr_3": 0,
- "axibar_highaddr_4": 0,
- "axibar_highaddr_5": 0,
- "axibar2pciebar_0": 0,
- "axibar2pciebar_1": 0,
- "axibar2pciebar_2": 0,
- "axibar2pciebar_3": 0,
- "axibar2pciebar_4": 0,
- "axibar2pciebar_5": 0,
- "baseaddr": 4096,
- "highaddr": 8191,
- "s_axi_id_width": 2,
- "s_axi_addr_width": 32,
- "s_axi_data_width": 64,
- "m_axi_addr_width": 32,
- "m_axi_data_width": 64,
- "s_axi_supports_narrow_burst": "false",
- "bar_64bit": "false",
- "xlnx_ref_board": "VC707",
- "pcie_blk_locn": "X1Y0",
- "axibar_num": 1,
- "en_ext_clk": "false",
- "en_ext_gt_common": "false",
- "en_ext_ch_gt_drp": "false",
- "en_transceiver_status_ports": "false",
- "en_ext_pipe_interface": "false",
- "rp_bar_hide": "false",
- "edk_iptype": "PERIPHERAL",
- "axibar_0": 0,
- "axibar_highaddr_0": 4294967295
- },
- "memory-view": {
- "M_AXI": {
- "axi_gpio_0": {
- "Reg": {
- "baseaddr": 0,
- "highaddr": 127,
- "size": 128
- }
- },
- "axis_interconnect_0_xbar": {
- "Reg": {
- "baseaddr": 4096,
- "highaddr": 5119,
- "size": 1024
- }
- },
- "axi_pcie_intc_0": {
- "reg0": {
- "baseaddr": 8192,
- "highaddr": 9215,
- "size": 1024
- }
- },
- "axi_dma_0": {
- "Reg": {
- "baseaddr": 12288,
- "highaddr": 13311,
- "size": 1024
- }
- }
- }
- },
- "axi_bars": {
- "BAR0": {
- "translation": 0,
- "baseaddr": 0,
- "highaddr": 4294967295,
- "size": 4294967296
- }
- },
- "pcie_bars": {
- "BAR0": {
- "translation": 0
- }
- }
- },
- "axi_pcie_intc_0": {
- "vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0",
- "parameters": {
- "component_name": "design_1_axi_pcie_intc_0_0",
- "edk_iptype": "PERIPHERAL",
- "c_baseaddr": 8192,
- "c_highaddr": 9215
- }
- },
- "axis_interconnect_0_xbar": {
+ "crossbar_axis_interconnect_0_xbar": {
"vlnv": "xilinx.com:ip:axis_switch:1.1",
"parameters": {
"c_family": "virtex7",
- "c_num_si_slots": 5,
+ "c_num_si_slots": 6,
"c_log_si_slots": 3,
- "c_num_mi_slots": 5,
+ "c_num_mi_slots": 6,
"c_axis_tdata_width": 32,
"c_axis_tid_width": 1,
"c_axis_tdest_width": 1,
@@ -906,15 +597,15 @@
"c_arb_algorithm": 0,
"c_output_reg": 0,
"c_decoder_reg": 1,
- "c_m_axis_connectivity_array": 33554431,
- "c_m_axis_basetdest_array": 10,
- "c_m_axis_hightdest_array": 10,
+ "c_m_axis_connectivity_array": 68719476735,
+ "c_m_axis_basetdest_array": 42,
+ "c_m_axis_hightdest_array": 42,
"c_routing_mode": 1,
"c_s_axi_ctrl_addr_width": 7,
"c_s_axi_ctrl_data_width": 32,
"c_common_clock": 0,
- "num_si": 5,
- "num_mi": 5,
+ "num_si": 6,
+ "num_mi": 6,
"routing_mode": 1,
"has_tready": 1,
"tdata_num_bytes": 4,
@@ -1222,60 +913,468 @@
"m15_s15_connectivity": 1,
"component_name": "design_1_xbar_0",
"edk_iptype": "PERIPHERAL",
- "c_baseaddr": 0,
- "c_highaddr": 1023
+ "c_baseaddr": 4096,
+ "c_highaddr": 5119
},
"ports": [
{
"role": "slave",
- "target": "aurora_8b10b_ch0:USER_DATA_M_AXI_RX",
+ "target": "aurora_aurora_8b10b_ch0:USER_DATA_M_AXI_RX",
"name": "S00_AXIS"
},
{
"role": "master",
- "target": "aurora_8b10b_ch0:USER_DATA_S_AXI_TX",
+ "target": "aurora_aurora_8b10b_ch0:USER_DATA_S_AXI_TX",
"name": "M00_AXIS"
},
{
"role": "slave",
- "target": "aurora_8b10b_ch1:USER_DATA_M_AXI_RX",
+ "target": "aurora_aurora_8b10b_ch1:USER_DATA_M_AXI_RX",
"name": "S01_AXIS"
},
{
"role": "master",
- "target": "aurora_8b10b_ch1:USER_DATA_S_AXI_TX",
+ "target": "aurora_aurora_8b10b_ch1:USER_DATA_S_AXI_TX",
"name": "M01_AXIS"
},
{
"role": "slave",
- "target": "aurora_8b10b_ch2:USER_DATA_M_AXI_RX",
+ "target": "aurora_aurora_8b10b_ch2:USER_DATA_M_AXI_RX",
"name": "S02_AXIS"
},
{
"role": "master",
- "target": "aurora_8b10b_ch2:USER_DATA_S_AXI_TX",
+ "target": "aurora_aurora_8b10b_ch2:USER_DATA_S_AXI_TX",
"name": "M02_AXIS"
},
{
"role": "slave",
- "target": "aurora_8b10b_ch3:USER_DATA_M_AXI_RX",
+ "target": "aurora_aurora_8b10b_ch3:USER_DATA_M_AXI_RX",
"name": "S03_AXIS"
},
{
"role": "master",
- "target": "aurora_8b10b_ch3:USER_DATA_S_AXI_TX",
+ "target": "aurora_aurora_8b10b_ch3:USER_DATA_S_AXI_TX",
"name": "M03_AXIS"
},
{
"role": "slave",
- "target": "axi_dma_0:MM2S",
+ "target": "dma_pcie_axi_dma_0:MM2S",
"name": "S04_AXIS"
},
{
"role": "master",
- "target": "axi_dma_0:S2MM",
+ "target": "dma_pcie_axi_dma_0:S2MM",
"name": "M04_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "dino_dinoif_adc_0:M00_AXIS",
+ "name": "S05_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "dino_dinoif_dac_0:S00_AXIS",
+ "name": "M05_AXIS"
}
- ]
+ ],
+ "num_ports": 6
+ },
+ "dino_axi_iic_0": {
+ "vlnv": "xilinx.com:ip:axi_iic:2.1",
+ "parameters": {
+ "c_family": "virtex7",
+ "c_s_axi_addr_width": 9,
+ "c_s_axi_data_width": 32,
+ "c_iic_freq": 100000,
+ "c_ten_bit_adr": 0,
+ "c_gpo_width": 1,
+ "c_s_axi_aclk_freq_hz": 125000000,
+ "c_scl_inertial_delay": 0,
+ "c_sda_inertial_delay": 0,
+ "c_sda_level": 1,
+ "c_smbus_pmbus_host": 0,
+ "c_disable_setup_violation_check": 0,
+ "c_static_timing_reg_width": 0,
+ "c_timing_reg_width": 32,
+ "c_default_value": 0,
+ "component_name": "design_1_axi_iic_0_0",
+ "ten_bit_adr": "7_bit",
+ "axi_aclk_freq_mhz": "125.0",
+ "iic_freq_khz": 100,
+ "use_board_flow": "false",
+ "iic_board_interface": "Custom",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 16384,
+ "c_highaddr": 17407
+ },
+ "irqs": {
+ "iic2intc_irpt": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:2"
+ }
+ },
+ "dino_registerif_0": {
+ "vlnv": "xilinx.com:module_ref:registerif:1.0",
+ "parameters": {
+ "c_axi_data_width": 32,
+ "c_axi_addr_width": 32,
+ "reg_addr_width": 10,
+ "component_name": "design_1_registerif_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 20480,
+ "c_highaddr": 21503
+ }
+ },
+ "dma_pcie_axi_dma_0": {
+ "vlnv": "xilinx.com:ip:axi_dma:7.1",
+ "parameters": {
+ "c_s_axi_lite_addr_width": 10,
+ "c_s_axi_lite_data_width": 32,
+ "c_dlytmr_resolution": 125,
+ "c_prmry_is_aclk_async": 0,
+ "c_enable_multi_channel": 0,
+ "c_num_mm2s_channels": 1,
+ "c_num_s2mm_channels": 1,
+ "c_include_sg": 1,
+ "c_sg_include_stscntrl_strm": 0,
+ "c_sg_use_stsapp_length": 0,
+ "c_sg_length_width": 14,
+ "c_m_axi_sg_addr_width": 32,
+ "c_m_axi_sg_data_width": 32,
+ "c_m_axis_mm2s_cntrl_tdata_width": 32,
+ "c_s_axis_s2mm_sts_tdata_width": 32,
+ "c_micro_dma": 0,
+ "c_include_mm2s": 1,
+ "c_include_mm2s_sf": 1,
+ "c_mm2s_burst_size": 16,
+ "c_m_axi_mm2s_addr_width": 32,
+ "c_m_axi_mm2s_data_width": 32,
+ "c_m_axis_mm2s_tdata_width": 32,
+ "c_include_mm2s_dre": 0,
+ "c_include_s2mm": 1,
+ "c_include_s2mm_sf": 1,
+ "c_s2mm_burst_size": 16,
+ "c_m_axi_s2mm_addr_width": 32,
+ "c_m_axi_s2mm_data_width": 32,
+ "c_s_axis_s2mm_tdata_width": 32,
+ "c_include_s2mm_dre": 0,
+ "c_increase_throughput": 0,
+ "c_family": "virtex7",
+ "component_name": "design_1_axi_dma_0_0",
+ "c_addr_width": 32,
+ "c_single_interface": 0,
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 12288,
+ "c_highaddr": 13311
+ },
+ "memory-view": {
+ "M_AXI_SG": {
+ "dma_pcie_pcie_axi_pcie_0": {
+ "BAR0": {
+ "baseaddr": 0,
+ "highaddr": 4294967295,
+ "size": 4294967296
+ }
+ }
+ },
+ "M_AXI_MM2S": {
+ "dma_pcie_pcie_axi_pcie_0": {
+ "BAR0": {
+ "baseaddr": 0,
+ "highaddr": 4294967295,
+ "size": 4294967296
+ }
+ }
+ },
+ "M_AXI_S2MM": {
+ "dma_pcie_pcie_axi_pcie_0": {
+ "BAR0": {
+ "baseaddr": 0,
+ "highaddr": 4294967295,
+ "size": 4294967296
+ }
+ }
+ }
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "crossbar_axis_interconnect_0_xbar:S04_AXIS",
+ "name": "MM2S"
+ },
+ {
+ "role": "slave",
+ "target": "crossbar_axis_interconnect_0_xbar:M04_AXIS",
+ "name": "S2MM"
+ }
+ ],
+ "irqs": {
+ "mm2s_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:0",
+ "s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
+ }
+ },
+ "dma_pcie_axi_read_cache_0": {
+ "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
+ "parameters": {
+ "c_axi_data_width": 32,
+ "c_axi_addr_width": 32,
+ "word_num": 16,
+ "component_name": "design_1_axi_read_cache_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 24576,
+ "c_highaddr": 25599
+ },
+ "memory-view": {
+ "M_AXI": {
+ "dma_pcie_pcie_axi_pcie_0": {
+ "BAR0": {
+ "baseaddr": 0,
+ "highaddr": 4294967295,
+ "size": 4294967296
+ }
+ }
+ }
+ }
+ },
+ "dma_pcie_pcie_axi_pcie_0": {
+ "vlnv": "xilinx.com:ip:axi_pcie:2.9",
+ "parameters": {
+ "c_family": "virtex7",
+ "c_instance": "design_1_axi_pcie_0_1",
+ "c_s_axi_id_width": 2,
+ "c_s_axi_addr_width": 32,
+ "c_s_axi_data_width": 64,
+ "c_m_axi_addr_width": 32,
+ "c_m_axi_data_width": 64,
+ "c_no_of_lanes": 1,
+ "c_max_link_speed": 1,
+ "c_pcie_use_mode": "3.0",
+ "c_device_id": 28705,
+ "c_vendor_id": 4334,
+ "c_class_code": 360448,
+ "c_ref_clk_freq": 0,
+ "c_rev_id": 0,
+ "c_subsystem_id": 7,
+ "c_subsystem_vendor_id": 4334,
+ "c_pcie_cap_slot_implemented": 0,
+ "c_slot_clock_config": "TRUE",
+ "c_msi_decode_enable": "TRUE",
+ "c_int_fifo_depth": 0,
+ "c_num_msi_req": 4,
+ "c_interrupt_pin": 0,
+ "c_comp_timeout": 0,
+ "c_include_rc": 0,
+ "c_s_axi_supports_narrow_burst": 1,
+ "c_include_baroffset_reg": 1,
+ "c_axibar_num": 1,
+ "c_axibar2pciebar_0": 0,
+ "c_axibar2pciebar_1": 0,
+ "c_axibar2pciebar_2": 0,
+ "c_axibar2pciebar_3": 0,
+ "c_axibar2pciebar_4": 0,
+ "c_axibar2pciebar_5": 0,
+ "c_axibar_as_0": 0,
+ "c_axibar_as_1": 0,
+ "c_axibar_as_2": 0,
+ "c_axibar_as_3": 0,
+ "c_axibar_as_4": 0,
+ "c_axibar_as_5": 0,
+ "c_axibar_0": 0,
+ "c_axibar_highaddr_0": 4294967295,
+ "c_axibar_1": 4294967295,
+ "c_axibar_highaddr_1": 0,
+ "c_axibar_2": 4294967295,
+ "c_axibar_highaddr_2": 0,
+ "c_axibar_3": 4294967295,
+ "c_axibar_highaddr_3": 0,
+ "c_axibar_4": 4294967295,
+ "c_axibar_highaddr_4": 0,
+ "c_axibar_5": 4294967295,
+ "c_axibar_highaddr_5": 0,
+ "c_pciebar_num": 1,
+ "c_pciebar_as": 0,
+ "c_pciebar_len_0": 20,
+ "c_pciebar2axibar_0": 0,
+ "c_pciebar2axibar_0_sec": 1,
+ "c_pciebar_len_1": 16,
+ "c_pciebar2axibar_1": 4294967295,
+ "c_pciebar2axibar_1_sec": 1,
+ "c_pciebar_len_2": 16,
+ "c_pciebar2axibar_2": 4294967295,
+ "c_pciebar2axibar_2_sec": 1,
+ "c_pcie_blk_locn": 3,
+ "c_xlnx_ref_board": "VC707",
+ "pcie_ext_clk": "FALSE",
+ "pcie_ext_gt_common": "FALSE",
+ "ext_ch_gt_drp": "FALSE",
+ "shared_logic_in_core": "false",
+ "transceiver_ctrl_status_ports": "FALSE",
+ "ext_pipe_interface": "FALSE",
+ "c_device": "xc7vx485t",
+ "c_speed": -2,
+ "axi_aclk_loopback": "false",
+ "no_slv_err": "false",
+ "c_rp_bar_hide": "FALSE",
+ "enable_jtag_dbg": "false",
+ "c_axibar_chk_slv_err": "false",
+ "reduce_oob_freq": "false",
+ "component_name": "design_1_axi_pcie_0_1",
+ "include_rc": "PCI_Express_Endpoint_device",
+ "ref_clk_freq": "100_MHz",
+ "slot_clock_config": "true",
+ "pcie_use_mode": "GES_and_Production",
+ "no_of_lanes": "X1",
+ "max_link_speed": "5.0_GT/s",
+ "vendor_id": 4334,
+ "device_id": 28705,
+ "rev_id": 0,
+ "subsystem_vendor_id": 4334,
+ "subsystem_id": 7,
+ "enable_class_code": "true",
+ "class_code": 360448,
+ "base_class_menu": "Memory_controller",
+ "sub_class_interface_menu": "Other_memory_controller",
+ "bar0_enabled": "true",
+ "bar1_enabled": "false",
+ "bar2_enabled": "false",
+ "bar0_type": "Memory",
+ "bar1_type": "N/A",
+ "bar2_type": "N/A",
+ "bar0_scale": "Megabytes",
+ "bar1_scale": "N/A",
+ "bar2_scale": "N/A",
+ "bar0_size": 1,
+ "bar1_size": 8,
+ "bar2_size": 8,
+ "pciebar2axibar_0": 0,
+ "pciebar2axibar_1": 4294967295,
+ "pciebar2axibar_2": 4294967295,
+ "pciebar2axibar_1_sec": 1,
+ "pciebar2axibar_0_sec": 1,
+ "pciebar2axibar_2_sec": 1,
+ "interrupt_pin": "false",
+ "msi_decode_enabled": "true",
+ "num_msi_req": 4,
+ "int_fifo_depth": 16,
+ "comp_timeout": "50us",
+ "include_baroffset_reg": "true",
+ "axibar_as_0": "false",
+ "axibar_as_1": "false",
+ "axibar_as_2": "false",
+ "axibar_as_3": "false",
+ "axibar_as_4": "false",
+ "axibar_as_5": "false",
+ "axibar_1": 4294967295,
+ "axibar_2": 4294967295,
+ "axibar_3": 4294967295,
+ "axibar_4": 4294967295,
+ "axibar_5": 4294967295,
+ "axibar_highaddr_1": 0,
+ "axibar_highaddr_2": 0,
+ "axibar_highaddr_3": 0,
+ "axibar_highaddr_4": 0,
+ "axibar_highaddr_5": 0,
+ "axibar2pciebar_0": 0,
+ "axibar2pciebar_1": 0,
+ "axibar2pciebar_2": 0,
+ "axibar2pciebar_3": 0,
+ "axibar2pciebar_4": 0,
+ "axibar2pciebar_5": 0,
+ "baseaddr": 4096,
+ "highaddr": 8191,
+ "s_axi_id_width": 2,
+ "s_axi_addr_width": 32,
+ "s_axi_data_width": 64,
+ "m_axi_addr_width": 32,
+ "m_axi_data_width": 64,
+ "s_axi_supports_narrow_burst": "true",
+ "bar_64bit": "false",
+ "xlnx_ref_board": "VC707",
+ "pcie_blk_locn": "X1Y0",
+ "axibar_num": 1,
+ "en_ext_clk": "false",
+ "en_ext_gt_common": "false",
+ "en_ext_ch_gt_drp": "false",
+ "en_transceiver_status_ports": "false",
+ "en_ext_pipe_interface": "false",
+ "rp_bar_hide": "false",
+ "edk_iptype": "PERIPHERAL",
+ "axibar_0": 0,
+ "axibar_highaddr_0": 4294967295
+ },
+ "memory-view": {
+ "M_AXI": {
+ "axi_gpio_0": {
+ "Reg": {
+ "baseaddr": 0,
+ "highaddr": 127,
+ "size": 128
+ }
+ },
+ "crossbar_axis_interconnect_0_xbar": {
+ "Reg": {
+ "baseaddr": 4096,
+ "highaddr": 5119,
+ "size": 1024
+ }
+ },
+ "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
+ "reg0": {
+ "baseaddr": 8192,
+ "highaddr": 9215,
+ "size": 1024
+ }
+ },
+ "dma_pcie_axi_dma_0": {
+ "Reg": {
+ "baseaddr": 12288,
+ "highaddr": 13311,
+ "size": 1024
+ }
+ },
+ "dino_axi_iic_0": {
+ "Reg": {
+ "baseaddr": 16384,
+ "highaddr": 17407,
+ "size": 1024
+ }
+ },
+ "dino_registerif_0": {
+ "reg0": {
+ "baseaddr": 20480,
+ "highaddr": 21503,
+ "size": 1024
+ }
+ },
+ "dma_pcie_axi_read_cache_0": {
+ "reg0": {
+ "baseaddr": 24576,
+ "highaddr": 25599,
+ "size": 1024
+ }
+ }
+ }
+ },
+ "axi_bars": {
+ "BAR0": {
+ "translation": 0,
+ "baseaddr": 0,
+ "highaddr": 4294967295,
+ "size": 4294967296
+ }
+ },
+ "pcie_bars": {
+ "BAR0": {
+ "translation": 0
+ }
+ }
+ },
+ "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
+ "vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0",
+ "parameters": {
+ "component_name": "design_1_axi_pcie_intc_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 8192,
+ "c_highaddr": 9215
+ }
}
}
diff --git a/etc/fpga/vc707.json b/etc/fpga/vc707.json
index a4580d57c..4cfa3e334 100644
--- a/etc/fpga/vc707.json
+++ b/etc/fpga/vc707.json
@@ -2,9 +2,9 @@
"fpgas": {
"vc707": {
"id": "10ee:7021",
- "slot": "0000:88:00.0",
+ "slot": "0000:89:00.0",
"do_reset": true,
- "ips": "vc707-xbar-pcie-dino/vc707-xbar-pcie-dino-v2.json",
+ "ips": "vc707-xbar-pcie/vc707-xbar-pcie.json",
"polling": true,
"interface": "pcie"
}
diff --git a/etc/fpga/zcu106-dino/zcu106-dino.json b/etc/fpga/zcu106-dino/zcu106-dino.json
new file mode 100644
index 000000000..3052ae878
--- /dev/null
+++ b/etc/fpga/zcu106-dino/zcu106-dino.json
@@ -0,0 +1,2485 @@
+{
+ "aurora_aurora_8b10b_ch0": {
+ "vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
+ "parameters": {
+ "component_name": "design_1_aurora_8b10b_0_2",
+ "channel_enable": "X0Y10",
+ "c_refclk_loc_p": "W10",
+ "c_refclk_loc_n": "W9",
+ "c_column_used": "left",
+ "c_ucolumn_used": "right",
+ "c_family": "zynquplus",
+ "c_device": "xczu7ev",
+ "c_row_used": "None",
+ "c_xpackage": "ffvc1156",
+ "c_xspeedgrade": -2,
+ "c_aurora_lanes": 1,
+ "c_lane_width": 2,
+ "c_active_transceiverquads": 1,
+ "c_start_quad": "Quad_X0Y2",
+ "c_start_lane": "X0Y10",
+ "c_refclk_source": "X0Y10 clk1",
+ "interface_mode": "Framing",
+ "c_stream": "false",
+ "dataflow_config": "Duplex",
+ "backchannel_mode": "Sidebands",
+ "c_simplex": "false",
+ "c_simplex_mode": "TX",
+ "flow_mode": "None",
+ "c_nfc": "false",
+ "c_nfc_mode": "IMM",
+ "c_ufc": "false",
+ "c_example_simulation": "false",
+ "c_gtwiz_out": "false",
+ "c_line_rate": 2,
+ "cc_line_rate": 2,
+ "c_refclk_frequency": 250,
+ "cc_refclk_frequency": 250,
+ "c_init_clk": "99.990005",
+ "drp_freq": "50.0000",
+ "c_gt_loc_1": 1,
+ "c_gt_loc_2": "X",
+ "c_gt_loc_3": "X",
+ "c_gt_loc_4": "X",
+ "c_gt_loc_5": "X",
+ "c_gt_loc_6": "X",
+ "c_gt_loc_7": "X",
+ "c_gt_loc_8": "X",
+ "c_gt_loc_9": "X",
+ "c_gt_loc_10": "X",
+ "c_gt_loc_11": "X",
+ "c_gt_loc_12": "X",
+ "c_gt_loc_13": "X",
+ "c_gt_loc_14": "X",
+ "c_gt_loc_15": "X",
+ "c_gt_loc_16": "X",
+ "c_gt_loc_17": "X",
+ "c_gt_loc_18": "X",
+ "c_gt_loc_19": "X",
+ "c_gt_loc_20": "X",
+ "c_gt_loc_21": "X",
+ "c_gt_loc_22": "X",
+ "c_gt_loc_23": "X",
+ "c_gt_loc_24": "X",
+ "c_gt_loc_25": "X",
+ "c_gt_loc_26": "X",
+ "c_gt_loc_27": "X",
+ "c_gt_loc_28": "X",
+ "c_gt_loc_29": "X",
+ "c_gt_loc_30": "X",
+ "c_gt_loc_31": "X",
+ "c_gt_loc_32": "X",
+ "c_gt_loc_33": "X",
+ "c_gt_loc_34": "X",
+ "c_gt_loc_35": "X",
+ "c_gt_loc_36": "X",
+ "c_gt_loc_37": "X",
+ "c_gt_loc_38": "X",
+ "c_gt_loc_39": "X",
+ "c_gt_loc_40": "X",
+ "c_gt_loc_41": "X",
+ "c_gt_loc_42": "X",
+ "c_gt_loc_43": "X",
+ "c_gt_loc_44": "X",
+ "c_gt_loc_45": "X",
+ "c_gt_loc_46": "X",
+ "c_gt_loc_47": "X",
+ "c_gt_loc_48": "X",
+ "c_gt_clock_1": "GTHQ0",
+ "c_gt_clock_2": "None",
+ "c_use_scrambler": "false",
+ "c_use_chipscope": "false",
+ "c_drp_if": "false",
+ "transceivercontrol": "false",
+ "c_use_crc": "true",
+ "supportlevel": 1,
+ "c_use_byteswap": "false",
+ "c_cpll_fbdiv": 1,
+ "c_cpll_fbdiv_45": 5,
+ "c_cpll_refclk_div": 1,
+ "c_rxoutdiv": 1,
+ "c_txoutdiv": 1,
+ "user_interface": "AXI_4_Streaming",
+ "c_ufcbuswidthselect": 16,
+ "c_ufcrembuswidthselect": 1,
+ "c_ufcstrbbuswidthselect": 2,
+ "c_rembuswidthselect": 1,
+ "isv7gth": "false",
+ "gtquadcnt": 1,
+ "port7dmonitorout": 7,
+ "is_7series": "false",
+ "singleend_initclk": "true",
+ "singleend_gtrefclk": "false",
+ "c_double_gtrxreset": "false",
+ "c_doccport_enable": "false",
+ "is_board": "zcu106",
+ "usdrpaddr_width": 9,
+ "usdmon_width": 15,
+ "txdiffctrl_width": 4,
+ "ins_loss_nyq": 14,
+ "rx_eq_mode": "AUTO",
+ "rx_coupling": "AC",
+ "rx_termination": "PROGRAMMABLE",
+ "rx_termination_prog_value": 800,
+ "rx_ppm_offset": 200,
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S02_AXIS",
+ "name": "USER_DATA_M_AXI_RX"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M02_AXIS",
+ "name": "USER_DATA_S_AXI_TX"
+ }
+ ]
+ },
+ "axi_iic_0": {
+ "vlnv": "xilinx.com:ip:axi_iic:2.1",
+ "parameters": {
+ "c_family": "zynquplus",
+ "c_s_axi_addr_width": 9,
+ "c_s_axi_data_width": 32,
+ "c_iic_freq": 100000,
+ "c_ten_bit_adr": 0,
+ "c_gpo_width": 1,
+ "c_s_axi_aclk_freq_hz": 99990005,
+ "c_scl_inertial_delay": 0,
+ "c_sda_inertial_delay": 0,
+ "c_sda_level": 1,
+ "c_smbus_pmbus_host": 0,
+ "c_disable_setup_violation_check": 0,
+ "c_static_timing_reg_width": 0,
+ "c_timing_reg_width": 32,
+ "c_default_value": 0,
+ "component_name": "design_1_axi_iic_0_0",
+ "ten_bit_adr": "7_bit",
+ "axi_aclk_freq_mhz": "99.990005",
+ "iic_freq_khz": 100,
+ "use_board_flow": "false",
+ "iic_board_interface": "Custom",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684551168,
+ "c_highaddr": 2684616703
+ },
+ "irqs": {
+ "iic2intc_irpt": "zynq_zynq_ultra_ps_e_0:2"
+ }
+ },
+ "axis_interconnect_0_xbar": {
+ "vlnv": "xilinx.com:ip:axis_switch:1.1",
+ "parameters": {
+ "c_family": "zynquplus",
+ "c_num_si_slots": 4,
+ "c_log_si_slots": 2,
+ "c_num_mi_slots": 4,
+ "c_axis_tdata_width": 128,
+ "c_axis_tid_width": 1,
+ "c_axis_tdest_width": 2,
+ "c_axis_tuser_width": 1,
+ "c_axis_signal_set": 91,
+ "c_arb_on_max_xfers": 1,
+ "c_arb_on_num_cycles": 0,
+ "c_arb_on_tlast": 0,
+ "c_include_arbiter": 1,
+ "c_arb_algorithm": 0,
+ "c_output_reg": 0,
+ "c_decoder_reg": 1,
+ "c_m_axis_connectivity_array": 65535,
+ "c_m_axis_basetdest_array": 228,
+ "c_m_axis_hightdest_array": 228,
+ "c_routing_mode": 1,
+ "c_s_axi_ctrl_addr_width": 7,
+ "c_s_axi_ctrl_data_width": 32,
+ "c_common_clock": 0,
+ "num_si": 4,
+ "num_mi": 4,
+ "routing_mode": 1,
+ "has_tready": 1,
+ "tdata_num_bytes": 16,
+ "has_tstrb": 0,
+ "has_tkeep": 1,
+ "has_tlast": 1,
+ "tid_width": 0,
+ "tdest_width": 2,
+ "tuser_width": 0,
+ "has_aclken": 0,
+ "arb_on_max_xfers": 1,
+ "arb_on_num_cycles": 0,
+ "arb_on_tlast": 0,
+ "arb_algorithm": 0,
+ "decoder_reg": 1,
+ "output_reg": 0,
+ "common_clock": 0,
+ "m00_axis_basetdest": 0,
+ "m01_axis_basetdest": 1,
+ "m02_axis_basetdest": 2,
+ "m03_axis_basetdest": 3,
+ "m04_axis_basetdest": 4,
+ "m05_axis_basetdest": 5,
+ "m06_axis_basetdest": 6,
+ "m07_axis_basetdest": 7,
+ "m08_axis_basetdest": 8,
+ "m09_axis_basetdest": 9,
+ "m10_axis_basetdest": 10,
+ "m11_axis_basetdest": 11,
+ "m12_axis_basetdest": 12,
+ "m13_axis_basetdest": 13,
+ "m14_axis_basetdest": 14,
+ "m15_axis_basetdest": 15,
+ "m00_axis_hightdest": 0,
+ "m01_axis_hightdest": 1,
+ "m02_axis_hightdest": 2,
+ "m03_axis_hightdest": 3,
+ "m04_axis_hightdest": 4,
+ "m05_axis_hightdest": 5,
+ "m06_axis_hightdest": 6,
+ "m07_axis_hightdest": 7,
+ "m08_axis_hightdest": 8,
+ "m09_axis_hightdest": 9,
+ "m10_axis_hightdest": 10,
+ "m11_axis_hightdest": 11,
+ "m12_axis_hightdest": 12,
+ "m13_axis_hightdest": 13,
+ "m14_axis_hightdest": 14,
+ "m15_axis_hightdest": 15,
+ "m00_s00_connectivity": 1,
+ "m00_s01_connectivity": 1,
+ "m00_s02_connectivity": 1,
+ "m00_s03_connectivity": 1,
+ "m00_s04_connectivity": 1,
+ "m00_s05_connectivity": 1,
+ "m00_s06_connectivity": 1,
+ "m00_s07_connectivity": 1,
+ "m00_s08_connectivity": 1,
+ "m00_s09_connectivity": 1,
+ "m00_s10_connectivity": 1,
+ "m00_s11_connectivity": 1,
+ "m00_s12_connectivity": 1,
+ "m00_s13_connectivity": 1,
+ "m00_s14_connectivity": 1,
+ "m00_s15_connectivity": 1,
+ "m01_s00_connectivity": 1,
+ "m01_s01_connectivity": 1,
+ "m01_s02_connectivity": 1,
+ "m01_s03_connectivity": 1,
+ "m01_s04_connectivity": 1,
+ "m01_s05_connectivity": 1,
+ "m01_s06_connectivity": 1,
+ "m01_s07_connectivity": 1,
+ "m01_s08_connectivity": 1,
+ "m01_s09_connectivity": 1,
+ "m01_s10_connectivity": 1,
+ "m01_s11_connectivity": 1,
+ "m01_s12_connectivity": 1,
+ "m01_s13_connectivity": 1,
+ "m01_s14_connectivity": 1,
+ "m01_s15_connectivity": 1,
+ "m02_s00_connectivity": 1,
+ "m02_s01_connectivity": 1,
+ "m02_s02_connectivity": 1,
+ "m02_s03_connectivity": 1,
+ "m02_s04_connectivity": 1,
+ "m02_s05_connectivity": 1,
+ "m02_s06_connectivity": 1,
+ "m02_s07_connectivity": 1,
+ "m02_s08_connectivity": 1,
+ "m02_s09_connectivity": 1,
+ "m02_s10_connectivity": 1,
+ "m02_s11_connectivity": 1,
+ "m02_s12_connectivity": 1,
+ "m02_s13_connectivity": 1,
+ "m02_s14_connectivity": 1,
+ "m02_s15_connectivity": 1,
+ "m03_s00_connectivity": 1,
+ "m03_s01_connectivity": 1,
+ "m03_s02_connectivity": 1,
+ "m03_s03_connectivity": 1,
+ "m03_s04_connectivity": 1,
+ "m03_s05_connectivity": 1,
+ "m03_s06_connectivity": 1,
+ "m03_s07_connectivity": 1,
+ "m03_s08_connectivity": 1,
+ "m03_s09_connectivity": 1,
+ "m03_s10_connectivity": 1,
+ "m03_s11_connectivity": 1,
+ "m03_s12_connectivity": 1,
+ "m03_s13_connectivity": 1,
+ "m03_s14_connectivity": 1,
+ "m03_s15_connectivity": 1,
+ "m04_s00_connectivity": 1,
+ "m04_s01_connectivity": 1,
+ "m04_s02_connectivity": 1,
+ "m04_s03_connectivity": 1,
+ "m04_s04_connectivity": 1,
+ "m04_s05_connectivity": 1,
+ "m04_s06_connectivity": 1,
+ "m04_s07_connectivity": 1,
+ "m04_s08_connectivity": 1,
+ "m04_s09_connectivity": 1,
+ "m04_s10_connectivity": 1,
+ "m04_s11_connectivity": 1,
+ "m04_s12_connectivity": 1,
+ "m04_s13_connectivity": 1,
+ "m04_s14_connectivity": 1,
+ "m04_s15_connectivity": 1,
+ "m05_s00_connectivity": 1,
+ "m05_s01_connectivity": 1,
+ "m05_s02_connectivity": 1,
+ "m05_s03_connectivity": 1,
+ "m05_s04_connectivity": 1,
+ "m05_s05_connectivity": 1,
+ "m05_s06_connectivity": 1,
+ "m05_s07_connectivity": 1,
+ "m05_s08_connectivity": 1,
+ "m05_s09_connectivity": 1,
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+ "m05_s12_connectivity": 1,
+ "m05_s13_connectivity": 1,
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+ "m06_s00_connectivity": 1,
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+ "m09_s15_connectivity": 1,
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+ "m10_s03_connectivity": 1,
+ "m10_s04_connectivity": 1,
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+ "m11_s15_connectivity": 1,
+ "m12_s00_connectivity": 1,
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+ "m12_s02_connectivity": 1,
+ "m12_s03_connectivity": 1,
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+ "m12_s15_connectivity": 1,
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+ "m13_s02_connectivity": 1,
+ "m13_s03_connectivity": 1,
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+ "m13_s15_connectivity": 1,
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+ "m14_s02_connectivity": 1,
+ "m14_s03_connectivity": 1,
+ "m14_s04_connectivity": 1,
+ "m14_s05_connectivity": 1,
+ "m14_s06_connectivity": 1,
+ "m14_s07_connectivity": 1,
+ "m14_s08_connectivity": 1,
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+ "m14_s10_connectivity": 1,
+ "m14_s11_connectivity": 1,
+ "m14_s12_connectivity": 1,
+ "m14_s13_connectivity": 1,
+ "m14_s14_connectivity": 1,
+ "m14_s15_connectivity": 1,
+ "m15_s00_connectivity": 1,
+ "m15_s01_connectivity": 1,
+ "m15_s02_connectivity": 1,
+ "m15_s03_connectivity": 1,
+ "m15_s04_connectivity": 1,
+ "m15_s05_connectivity": 1,
+ "m15_s06_connectivity": 1,
+ "m15_s07_connectivity": 1,
+ "m15_s08_connectivity": 1,
+ "m15_s09_connectivity": 1,
+ "m15_s10_connectivity": 1,
+ "m15_s11_connectivity": 1,
+ "m15_s12_connectivity": 1,
+ "m15_s13_connectivity": 1,
+ "m15_s14_connectivity": 1,
+ "m15_s15_connectivity": 1,
+ "component_name": "design_1_xbar_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684420096,
+ "c_highaddr": 2684485631
+ },
+ "ports": [
+ {
+ "role": "slave",
+ "target": "zynq_axi_dma_0:MM2S",
+ "name": "S00_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "zynq_axi_dma_0:S2MM",
+ "name": "M00_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "dino_dinoif_adc_0:M00_AXIS",
+ "name": "S01_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "dino_dinoif_dac_0:S00_AXIS",
+ "name": "M01_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "aurora_aurora_8b10b_ch0:USER_DATA_M_AXI_RX",
+ "name": "S02_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "aurora_aurora_8b10b_ch0:USER_DATA_S_AXI_TX",
+ "name": "M02_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S03_AXIS",
+ "name": "M03_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M03_AXIS",
+ "name": "S03_AXIS"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M03_AXIS",
+ "name": "S03_AXIS"
+ },
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S03_AXIS",
+ "name": "M03_AXIS"
+ }
+ ],
+ "num_ports": 4
+ },
+ "dino_dinoif_adc_0": {
+ "vlnv": "xilinx.com:module_ref:dinoif_adc:1.0",
+ "i2c_channel": 0,
+ "parameters": {
+ "component_name": "design_1_dinoif_adc_0_0",
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S01_AXIS",
+ "name": "M00_AXIS"
+ }
+ ]
+ },
+ "dino_dinoif_dac_0": {
+ "vlnv": "xilinx.com:module_ref:dinoif_dac:1.0",
+ "i2c_channel": 1,
+ "parameters": {
+ "component_name": "design_1_dinoif_dac_0_0",
+ "edk_iptype": "PERIPHERAL"
+ },
+ "ports": [
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M01_AXIS",
+ "name": "S00_AXIS"
+ }
+ ]
+ },
+ "dino_registerif_0": {
+ "vlnv": "xilinx.com:module_ref:registerif:1.0",
+ "parameters": {
+ "c_axi_data_width": 32,
+ "c_axi_addr_width": 32,
+ "reg_addr_width": 10,
+ "component_name": "design_1_registerif_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684485632,
+ "c_highaddr": 2684551167
+ }
+ },
+ "zynq_axi_dma_0": {
+ "vlnv": "xilinx.com:ip:axi_dma:7.1",
+ "parameters": {
+ "c_s_axi_lite_addr_width": 10,
+ "c_s_axi_lite_data_width": 32,
+ "c_dlytmr_resolution": 125,
+ "c_prmry_is_aclk_async": 0,
+ "c_enable_multi_channel": 0,
+ "c_num_mm2s_channels": 1,
+ "c_num_s2mm_channels": 1,
+ "c_include_sg": 1,
+ "c_sg_include_stscntrl_strm": 0,
+ "c_sg_use_stsapp_length": 0,
+ "c_sg_length_width": 23,
+ "c_m_axi_sg_addr_width": 64,
+ "c_m_axi_sg_data_width": 32,
+ "c_m_axis_mm2s_cntrl_tdata_width": 32,
+ "c_s_axis_s2mm_sts_tdata_width": 32,
+ "c_micro_dma": 0,
+ "c_include_mm2s": 1,
+ "c_include_mm2s_sf": 1,
+ "c_mm2s_burst_size": 16,
+ "c_m_axi_mm2s_addr_width": 64,
+ "c_m_axi_mm2s_data_width": 128,
+ "c_m_axis_mm2s_tdata_width": 128,
+ "c_include_mm2s_dre": 0,
+ "c_include_s2mm": 1,
+ "c_include_s2mm_sf": 1,
+ "c_s2mm_burst_size": 16,
+ "c_m_axi_s2mm_addr_width": 64,
+ "c_m_axi_s2mm_data_width": 128,
+ "c_s_axis_s2mm_tdata_width": 128,
+ "c_include_s2mm_dre": 0,
+ "c_increase_throughput": 0,
+ "c_family": "zynquplus",
+ "component_name": "design_1_axi_dma_0_0",
+ "c_addr_width": 64,
+ "c_single_interface": 0,
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684354560,
+ "c_highaddr": 2684420095
+ },
+ "memory-view": {
+ "M_AXI_MM2S": {
+ "zynq_zynq_ultra_ps_e_0": {
+ "HPC0_DDR_LOW": {
+ "baseaddr": 0,
+ "highaddr": 2147483647,
+ "size": 2147483648
+ },
+ "HPC0_DDR_HIGH": {
+ "baseaddr": 34359738368,
+ "highaddr": 68719476735,
+ "size": 34359738368
+ }
+ }
+ },
+ "M_AXI_S2MM": {
+ "zynq_zynq_ultra_ps_e_0": {
+ "HPC0_DDR_LOW": {
+ "baseaddr": 0,
+ "highaddr": 2147483647,
+ "size": 2147483648
+ },
+ "HPC0_DDR_HIGH": {
+ "baseaddr": 34359738368,
+ "highaddr": 68719476735,
+ "size": 34359738368
+ }
+ }
+ }
+ },
+ "ports": [
+ {
+ "role": "master",
+ "target": "axis_interconnect_0_xbar:S00_AXIS",
+ "name": "MM2S"
+ },
+ {
+ "role": "slave",
+ "target": "axis_interconnect_0_xbar:M00_AXIS",
+ "name": "S2MM"
+ }
+ ],
+ "irqs": {
+ "mm2s_introut": "zynq_zynq_ultra_ps_e_0:0",
+ "s2mm_introut": "zynq_zynq_ultra_ps_e_0:1"
+ }
+ },
+ "zynq_axi_read_cache_0": {
+ "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
+ "parameters": {
+ "c_axi_data_width": 32,
+ "c_axi_addr_width": 64,
+ "word_num": 16,
+ "component_name": "design_1_axi_read_cache_0_0",
+ "edk_iptype": "PERIPHERAL",
+ "c_baseaddr": 2684616704,
+ "c_highaddr": 2684682239
+ },
+ "memory-view": {
+ "M_AXI": {
+ "zynq_zynq_ultra_ps_e_0": {
+ "HPC1_DDR_LOW": {
+ "baseaddr": 0,
+ "highaddr": 2147483647,
+ "size": 2147483648
+ },
+ "HPC1_DDR_HIGH": {
+ "baseaddr": 34359738368,
+ "highaddr": 68719476735,
+ "size": 34359738368
+ }
+ }
+ }
+ }
+ },
+ "zynq_zynq_ultra_ps_e_0": {
+ "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3",
+ "parameters": {
+ "c_dp_use_audio": 0,
+ "c_dp_use_video": 0,
+ "c_maxigp0_data_width": 128,
+ "c_maxigp1_data_width": 128,
+ "c_maxigp2_data_width": 32,
+ "c_saxigp0_data_width": 128,
+ "c_saxigp1_data_width": 128,
+ "c_saxigp2_data_width": 128,
+ "c_saxigp3_data_width": 128,
+ "c_saxigp4_data_width": 128,
+ "c_saxigp5_data_width": 128,
+ "c_saxigp6_data_width": 128,
+ "c_use_diff_rw_clk_gp0": 0,
+ "c_use_diff_rw_clk_gp1": 0,
+ "c_use_diff_rw_clk_gp2": 0,
+ "c_use_diff_rw_clk_gp3": 0,
+ "c_use_diff_rw_clk_gp4": 0,
+ "c_use_diff_rw_clk_gp5": 0,
+ "c_use_diff_rw_clk_gp6": 0,
+ "c_en_fifo_enet0": 0,
+ "c_en_fifo_enet1": 0,
+ "c_en_fifo_enet2": 0,
+ "c_en_fifo_enet3": 0,
+ "c_pl_clk0_buf": "TRUE",
+ "c_pl_clk1_buf": "FALSE",
+ "c_pl_clk2_buf": "FALSE",
+ "c_pl_clk3_buf": "FALSE",
+ "c_trace_pipeline_width": 8,
+ "c_en_emio_trace": 0,
+ "c_trace_data_width": 32,
+ "c_use_debug_test": 0,
+ "c_sd0_internal_bus_width": 8,
+ "c_sd1_internal_bus_width": 8,
+ "c_num_f2p_0_intr_inputs": 3,
+ "c_num_f2p_1_intr_inputs": 1,
+ "c_emio_gpio_width": 1,
+ "c_num_fabric_resets": 1,
+ "psu_value_silversion": 3,
+ "psu__use__ddr_intf_requested": 0,
+ "psu__en_axi_status_ports": 0,
+ "psu__pss_ref_clk__freqmhz": "33.330",
+ "psu__pss_alt_ref_clk__freqmhz": "33.333",
+ "psu__video_ref_clk__freqmhz": "33.333",
+ "psu__aux_ref_clk__freqmhz": "33.333",
+ "psu__gt_ref_clk__freqmhz": "33.333",
+ "psu__video_ref_clk__enable": 0,
+ "psu__video_ref_clk__io": "