diff --git a/etc/fpga.conf b/etc/fpga.conf index 433be49cd..6c7ee4c0b 100644 --- a/etc/fpga.conf +++ b/etc/fpga.conf @@ -1,45 +1,80 @@ -affinity = 0xC; +# Example configuration file for VILLASfpga / VILLASnode +# +# The syntax of this file is similar to JSON. +# A detailed description of the format can be found here: +# http://www.hyperrealm.com/libconfig/libconfig_manual.html#Configuration-Files +# +# Author: Steffen Vogel +# Copyright: 2016, Institute for Automation of Complex Power Systems, EONERC +## -debug = 0; +############ Global Options ############ -stats = 1; +affinity = 0x0C; # Mask of cores the server should run on + # This also maps the NIC interrupts to those cores! + +priority = 50; # Priority for the server tasks. + # Usually the server is using a real-time FIFO + # scheduling algorithm + +debug = 5; # The level of verbosity for debug messages + # Higher number => increased verbosity + +stats = 3; # The interval in seconds to print path statistics. + # A value of 0 disables the statistics. + +name = "villas-acs" # The name of this VILLASnode. Might by used by node-types + # to identify themselves (default is the hostname). + +############ FPGA configuration ############ fpga = { - /* Card identification */ - id = "10ee:7022"; - slot = "01:00.0"; + id = "10ee:7022"; # Card identification + slot = "01:00.0"; # Usually only id or slot is required - do_reset = true; + do_reset = true; # Perform a full reset of the FPGA board + # Requires a IP core named 'axi_reset_0' + ############ List of IP cores on FPGA ############ + # + # Every IP core can have the following settings: + # baseaddr Baseaddress as accessible from BAR0 memory region + # irq Interrupt index of MSI interrupt controller + # port Port index of AXI4-Stream interconnect + ips = { + ### Utility IPs axi_pcie_intc_0 = { vlnv = "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0"; baseaddr = 0xb000; }, + switch_0 = { + vlnv = "xilinx.com:ip:axis_interconnect:2.1" + baseaddr = 0x5000; + num_ports = 10; + }, axi_reset_0 = { vlnv = "xilinx.com:ip:axi_gpio:2.0"; baseaddr = 0x7000; }, - bram_0 = { - vlnv = "xilinx.com:ip:axi_bram_ctrl:4.0"; - baseaddr = 0x0000; - size = 0x2000; - }, - dma_0 = { - vlnv = "xilinx.com:ip:axi_dma:7.1"; - baseaddr = 0x3000; - port = 1; - irq = 3; /* 3 - 4 */ - }, timer_0 = { vlnv = "xilinx.com:ip:axi_timer:2.0"; baseaddr = 0x4000; irq = 0; }, - switch_0 = { - vlnv = "xilinx.com:ip:axis_interconnect:2.1" - baseaddr = 0x5000; - num_ports = 10; + + ### Data mover IPs + dma_0 = { + vlnv = "xilinx.com:ip:axi_dma:7.1"; + baseaddr = 0x3000; + port = 1; + irq = 3; /* 3 - 4 */ + }, + dma_1 = { + vlnv = "xilinx.com:ip:axi_dma:7.1"; + baseaddr = 0x2000; + port = 6; + irq = 3; /* 3 - 4 */ }, fifo_mm_s_0 = { vlnv = "xilinx.com:ip:axi_fifo_mm_s:4.1"; @@ -48,30 +83,16 @@ fpga = { port = 2; irq = 2; }, + + ### Interface IPs rtds_axis_0 = { vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0"; baseaddr = 0x8000; port = 0; irq = 5; /* 5 -7 */ - - inputs = { - in = "axis_interconnect:0" - }, - outputs = { - out = "axis_interconnect:0", - }; - irqs = { - ts = "axi_pcie_intc_0:5", - ovfl = "axi_pcie_intc_0:6", - case = "axi_pcie_intc_0:7", - } - }, - dma_1 = { - vlnv = "xilinx.com:ip:axi_dma:7.1"; - baseaddr = 0x2000; - port = 6; - irq = 3; /* 3 - 4 */ }, + + ### Model IPs hls_dft_0 = { vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0"; baseaddr = 0x9000; @@ -80,7 +101,7 @@ fpga = { period = 400; /* in samples: 20ms / 50uS = 400*/ harmonics = [ 0, 1, 3, 5, 7 ] - decimation = 1; /* 0 = disabled */ + decimation = 0; /* 0 = disabled */ //harmonics = [ 0, 1, 2, 5, 22 ] }, axis_data_fifo_0 = { @@ -93,44 +114,49 @@ fpga = { }, } - /* Configure switch */ + ############ Switch config ############ + # Requires a single IP core with VLNV: + # xilinx.com:ip:axis_interconnect paths = ( -// DM Tests -// { in = "fifo_mm_s_0", out = "fifo_mm_s_0" }, -// { in = "dma_1", out = "dma_1" }, -// { in = "dma_0", out = "dma_0" } - -// DFT <-> RTDS -// { in = "rtds_axis_0", out = "hls_dft_0" }, -// { in = "hls_dft_0", out = "rtds_axis_0" } - -// Linux <-> RTDS -// { in = "rtds_axis_0", out = "dma_1" }, -// { in = "dma_1", out = "rtds_axis_0" } - -// DFT <-> Linux - { in = "dma_0", out = "hls_dft_0" }, - { in = "hls_dft_0", out = "dma_0" } +// { in = "fifo_mm_s_0", out = "fifo_mm_s_0" }, # Loopback fifo_mm_s_0 +// { in = "dma_0", out = "dma_0" }, # Loopback dma_0 +// { in = "dma_1", out = "dma_1" } # Loopback dma_1 +// { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux <-> RTDS +// { in = "rtds_axis_0", out = "dma_0", reverse = true } # Linux (dma_0) <-> RTDS + { in = "rtds_axis_0", out = "dma_1", reverse = true } # Linux (dma_1) <-> RTDS +// { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux (fifo_mm_s_0) <-> RTDS +// { in = "dma_0", out = "hls_dft_0", reverse = true } # DFT <-> Linux +// { in = "rtds_axis_0", out = "hls_dft_0", reverse = true }, # DFT <-> RTDS ) } +############ List of plugins ############ +# +# Additional node-types, hooks or VILLASfpga IP cores +# can be loaded by compiling them into a shared library and +# adding them to this list + plugins = [ "./lib/cbmodels/simple_circuit.so" ] +############ Dictionary of nodes ############ + nodes = { dma_0 = { - type = "fpga"; - datamover = "dma_0"; + type = "fpga"; # Datamovers to VILLASfpga + datamover = "dma_0"; # Name of IP core in fpga.ips + use_irqs = false; # Use polling or MSI interrupts? }, dma_1 = { type = "fpga"; datamover = "dma_1"; + use_irqs = false; }, fifo_0 = { type = "fpga"; datamover = "fifo_mm_s_0"; - use_irqs = true + use_irqs = false; }, simple_circuit = { type = "cbuilder"; @@ -143,7 +169,8 @@ nodes = { } } +############ List of paths ############ + paths = ( -// { in = "dma_1", out = "dma_1" }, { in = "dma_1", out = "simple_circuit", reverse = true } )