From 62cab0c4dcac36869d3f2596d483ce7061a06eca Mon Sep 17 00:00:00 2001 From: Niklas Eiling Date: Wed, 18 Jan 2023 15:20:57 +0100 Subject: [PATCH] clean up README.md add project description and related projects (MIOB and DINO) Signed-off-by: Niklas Eiling --- fpga/README.md | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index 1fb558ba8..9b774f6d6 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -2,8 +2,8 @@ [![build status](https://git.rwth-aachen.de/acs/public/villas/fpga/fpga/badges/master/pipeline.svg)](https://git.rwth-aachen.de/acs/public/villas/fpga/fpga/-/pipelines/) - -**TODO:** Write project description +VILLASfpga provides a flexbible, real-time capable interconnect between FPGAs and Linux, e.g., to connect simulators and devices for hardware-in-the loop simulations. VILLASfpga can guarantee fixed latencies in the nanosecond range. +VILLASfpga supports Xilinx FPGAs connected to a Linux system via PCI-Express or via a platform bus as found on MPSoC devices. ## Documentation @@ -19,7 +19,9 @@ User documentation is available here: - Steffen Vogel - Daniel Krebs [Institute for Automation of Complex Power Systems (ACS)](http://www.acs.eonerc.rwth-aachen.de) -[EON Energy Research Center (EONERC)](http://www.eonerc.rwth-aachen.de) [RWTH University Aachen, Germany](http://www.rwth-aachen.de)