diff --git a/fpga/gpu/include/villas/gpu.hpp b/fpga/gpu/include/villas/gpu.hpp index a421a3503..738e09872 100644 --- a/fpga/gpu/include/villas/gpu.hpp +++ b/fpga/gpu/include/villas/gpu.hpp @@ -112,5 +112,5 @@ private: Logger logger; }; -} // namespace villas -} // namespace gpu +} /* namespace villas */ +} /* namespace gpu */ diff --git a/fpga/gpu/kernels.hpp b/fpga/gpu/kernels.hpp index a6015bb12..7e08ca3cd 100644 --- a/fpga/gpu/kernels.hpp +++ b/fpga/gpu/kernels.hpp @@ -35,5 +35,5 @@ kernel_mailbox(volatile uint32_t *mailbox, volatile uint32_t* counter); __global__ void kernel_memcpy(volatile uint8_t* dst, volatile uint8_t* src, size_t length); -} // namespace villas -} // namespace gpu +} /* namespace villas */ +} /* namespace gpu */ diff --git a/fpga/include/villas/fpga/card.hpp b/fpga/include/villas/fpga/card.hpp index 2f5074bd8..6190f041d 100644 --- a/fpga/include/villas/fpga/card.hpp +++ b/fpga/include/villas/fpga/card.hpp @@ -138,7 +138,7 @@ public: { return villas::logging.get("PCIeCardFactory"); } }; -} // namespace fpga -} // namespace villas +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ip.hpp b/fpga/include/villas/fpga/ip.hpp index 2baa18593..1840e7308 100644 --- a/fpga/include/villas/fpga/ip.hpp +++ b/fpga/include/villas/fpga/ip.hpp @@ -28,8 +28,7 @@ * @{ */ -#ifndef VILLAS_IP_HPP -#define VILLAS_IP_HPP +#pragma once #include #include @@ -272,8 +271,6 @@ private: /** @} */ -} // namespace ip -} // namespace fpga -} // namespace villas - -#endif // VILLAS_IP_HPP +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ diff --git a/fpga/include/villas/fpga/ip_node.hpp b/fpga/include/villas/fpga/ip_node.hpp index 7aec8aeb6..854864127 100644 --- a/fpga/include/villas/fpga/ip_node.hpp +++ b/fpga/include/villas/fpga/ip_node.hpp @@ -28,8 +28,7 @@ * @{ */ -#ifndef VILLAS_IP_NODE_HPP -#define VILLAS_IP_NODE_HPP +#pragma once #include #include @@ -147,8 +146,6 @@ public: /** @} */ -} // namespace ip -} // namespace fpga -} // namespace villas - -#endif // VILLAS_IP_NODE_HPP +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ diff --git a/fpga/include/villas/fpga/ips/aurora.hpp b/fpga/include/villas/fpga/ips/aurora.hpp index d5fbc128c..10e55a0f7 100644 --- a/fpga/include/villas/fpga/ips/aurora.hpp +++ b/fpga/include/villas/fpga/ips/aurora.hpp @@ -82,8 +82,8 @@ public: }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/bram.hpp b/fpga/include/villas/fpga/ips/bram.hpp index e5ac0c424..6323ab5bc 100644 --- a/fpga/include/villas/fpga/ips/bram.hpp +++ b/fpga/include/villas/fpga/ips/bram.hpp @@ -80,8 +80,8 @@ public: { return {"xilinx.com:ip:axi_bram_ctrl:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/dma.hpp b/fpga/include/villas/fpga/ips/dma.hpp index 73768cbb8..2b9040a56 100644 --- a/fpga/include/villas/fpga/ips/dma.hpp +++ b/fpga/include/villas/fpga/ips/dma.hpp @@ -130,8 +130,8 @@ public: { return {"xilinx.com:ip:axi_dma:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/fifo.hpp b/fpga/include/villas/fpga/ips/fifo.hpp index b033e8b96..754aa96c4 100644 --- a/fpga/include/villas/fpga/ips/fifo.hpp +++ b/fpga/include/villas/fpga/ips/fifo.hpp @@ -107,8 +107,8 @@ public: { return {"xilinx.com:ip:axis_data_fifo:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/gpu2rtds.hpp b/fpga/include/villas/fpga/ips/gpu2rtds.hpp index 1aab1a2aa..1904a7c21 100644 --- a/fpga/include/villas/fpga/ips/gpu2rtds.hpp +++ b/fpga/include/villas/fpga/ips/gpu2rtds.hpp @@ -82,6 +82,6 @@ public: { return {"acs.eonerc.rwth-aachen.de:hls:gpu2rtds:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ diff --git a/fpga/include/villas/fpga/ips/hls.hpp b/fpga/include/villas/fpga/ips/hls.hpp index 1184fdfd9..24e44a3e7 100644 --- a/fpga/include/villas/fpga/ips/hls.hpp +++ b/fpga/include/villas/fpga/ips/hls.hpp @@ -132,6 +132,6 @@ protected: bool running; }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ diff --git a/fpga/include/villas/fpga/ips/intc.hpp b/fpga/include/villas/fpga/ips/intc.hpp index 66f124bb6..05dff9191 100644 --- a/fpga/include/villas/fpga/ips/intc.hpp +++ b/fpga/include/villas/fpga/ips/intc.hpp @@ -107,8 +107,8 @@ public: { return Vlnv(getCompatibleVlnvString()); } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/pcie.hpp b/fpga/include/villas/fpga/ips/pcie.hpp index d90febd89..48c6765eb 100644 --- a/fpga/include/villas/fpga/ips/pcie.hpp +++ b/fpga/include/villas/fpga/ips/pcie.hpp @@ -87,8 +87,8 @@ public: { return Vlnv(getCompatibleVlnvString()); } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/rtds.hpp b/fpga/include/villas/fpga/ips/rtds.hpp index 4f6d789e0..567369e98 100644 --- a/fpga/include/villas/fpga/ips/rtds.hpp +++ b/fpga/include/villas/fpga/ips/rtds.hpp @@ -79,8 +79,8 @@ public: { return {"acs.eonerc.rwth-aachen.de:user:rtds_axis:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/rtds2gpu.hpp b/fpga/include/villas/fpga/ips/rtds2gpu.hpp index b956805c3..ce5938cd6 100644 --- a/fpga/include/villas/fpga/ips/rtds2gpu.hpp +++ b/fpga/include/villas/fpga/ips/rtds2gpu.hpp @@ -91,6 +91,6 @@ public: { return {"acs.eonerc.rwth-aachen.de:hls:rtds2gpu:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ diff --git a/fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp b/fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp index ce7328417..b93f5c1da 100644 --- a/fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp +++ b/fpga/include/villas/fpga/ips/rtds2gpu/register_types.hpp @@ -1,5 +1,4 @@ -#ifndef REGISTER_TYPES_H -#define REGISTER_TYPES_H +#pragma once #include #include @@ -53,5 +52,3 @@ struct Rtds2GpuMemoryBuffer { T data[N]; reg_doorbell_t doorbell; }; - -#endif // REGISTER_TYPES_H diff --git a/fpga/include/villas/fpga/ips/switch.hpp b/fpga/include/villas/fpga/ips/switch.hpp index 36f1417fd..66c4e4801 100644 --- a/fpga/include/villas/fpga/ips/switch.hpp +++ b/fpga/include/villas/fpga/ips/switch.hpp @@ -94,8 +94,8 @@ public: { return Vlnv(getCompatibleVlnvString()); } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/ips/timer.hpp b/fpga/include/villas/fpga/ips/timer.hpp index c517c0adc..bc8cba0d0 100644 --- a/fpga/include/villas/fpga/ips/timer.hpp +++ b/fpga/include/villas/fpga/ips/timer.hpp @@ -95,8 +95,8 @@ public: { return {"xilinx.com:ip:axi_timer:"}; } }; -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ /** @} */ diff --git a/fpga/include/villas/fpga/vlnv.hpp b/fpga/include/villas/fpga/vlnv.hpp index 35b6c8640..63aac0611 100644 --- a/fpga/include/villas/fpga/vlnv.hpp +++ b/fpga/include/villas/fpga/vlnv.hpp @@ -79,7 +79,7 @@ private: std::string version; }; -} // namespace fpga -} // namespace villas +} /* namespace fpga */ +} /* namespace villas */ /** _FPGA_VLNV_HPP_ @} */