From 73c6ae1f71d11b56bd7c62c8702bce13637a5567 Mon Sep 17 00:00:00 2001 From: Daniel Krebs Date: Tue, 13 Feb 2018 18:56:42 +0100 Subject: [PATCH] hwdef-parse: follow OR-gate merging DMA interrupts Also update JSON config with the new output. --- fpga/etc/fpga.json | 12 ++++++++++-- fpga/scripts/hwdef-parse.py | 33 +++++++++++++++++++++++++++------ 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/fpga/etc/fpga.json b/fpga/etc/fpga.json index 2abcdc136..fe29ef418 100644 --- a/fpga/etc/fpga.json +++ b/fpga/etc/fpga.json @@ -147,7 +147,11 @@ "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:1", "name": "S2MM" } - ] + ], + "irqs": { + "mm2s_introut": "pcie_0_axi_pcie_intc_0:3", + "s2mm_introut": "pcie_0_axi_pcie_intc_0:4" + } }, "hier_0_axi_dma_axi_dma_1": { "vlnv": "xilinx.com:ip:axi_dma:7.1", @@ -182,7 +186,11 @@ "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:6", "name": "S2MM" } - ] + ], + "irqs": { + "mm2s_introut": "pcie_0_axi_pcie_intc_0:3", + "s2mm_introut": "pcie_0_axi_pcie_intc_0:4" + } }, "hier_0_axi_fifo_mm_s_0": { "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1", diff --git a/fpga/scripts/hwdef-parse.py b/fpga/scripts/hwdef-parse.py index 7f0c57863..12d96e4f2 100755 --- a/fpga/scripts/hwdef-parse.py +++ b/fpga/scripts/hwdef-parse.py @@ -200,7 +200,7 @@ ports = concat.xpath('.//PORT[@DIR="I"]') for port in ports: name = port.get('NAME') signame = port.get('SIGNAME') - + # Skip unconnected IRQs if not signame: continue @@ -213,13 +213,34 @@ for port in ports: instance = ip.get('INSTANCE') vlnv = ip.get('VLNV') + modtype = ip.get('MODTYPE') - port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0] - irqname = port.get('NAME') + originators = [] - if instance in ips: - irqs = ips[instance].setdefault('irqs', {}) - irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq) + # follow one level of OR gates merging interrupts (may be generalized later) + if modtype == 'util_vector_logic': + logic_op = ip.xpath('.//PARAMETER[@NAME="C_OPERATION"]')[0] + if logic_op.get('VALUE') == 'or': + # hardware interrupts sharing the same IRQ at the controller + ports = ip.xpath('.//PORT[@DIR="I"]') + for port in ports: + signame = port.get('SIGNAME') + ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0] + instance = ip.get('INSTANCE') + originators.append((instance, signame)) + else: + # consider this instance as originator + originators.append((instance, signame)) + + + for instance, signame in originators: + ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0] + port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0] + irqname = port.get('NAME') + + if instance in ips: + irqs = ips[instance].setdefault('irqs', {}) + irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq) # Find BRAM storage depths (size) brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')