From 80abbb866befe1413a9cae6c8ea4dc7bd1e15d72 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Thu, 27 Oct 2022 06:01:42 -0400 Subject: [PATCH] add latest vc707 config --- fpga/etc/fpgas.json | 2 +- fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie.json | 1282 +++++++++++++++++ 2 files changed, 1283 insertions(+), 1 deletion(-) create mode 100644 fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie.json diff --git a/fpga/etc/fpgas.json b/fpga/etc/fpgas.json index f50f037b2..42865c011 100644 --- a/fpga/etc/fpgas.json +++ b/fpga/etc/fpgas.json @@ -1,7 +1,7 @@ { "fpgas": { "vc707": { - "id": "10ee:7021", + "id": "10ee:7021", "slot": "0000:88:00.0", "do_reset": true, "ips": "etc/vc707-xbar-pcie/vc707-xbar-pcie.json" diff --git a/fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie.json b/fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie.json new file mode 100644 index 000000000..5491b7673 --- /dev/null +++ b/fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie.json @@ -0,0 +1,1282 @@ +{ + "aurora_8b10b_ch0": { + "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", + "parameters": { + "component_name": "design_1_aurora_8b10b_0_0", + "channel_enable": "X0Y0", + "c_refclk_loc_p": "BL8", + "c_refclk_loc_n": "BL7", + "c_column_used": "right", + "c_ucolumn_used": "right", + "c_family": "virtex7", + "c_device": "xc7vx485t", + "c_row_used": "None", + "c_xpackage": "ffg1761", + "c_xspeedgrade": -2, + "c_aurora_lanes": 1, + "c_lane_width": 4, + "c_active_transceiverquads": 1, + "c_start_quad": "X0Y0", + "c_start_lane": "X0Y0", + "c_refclk_source": "none", + "interface_mode": "Framing", + "c_stream": "false", + "dataflow_config": "Duplex", + "backchannel_mode": "Sidebands", + "c_simplex": "false", + "c_simplex_mode": "TX", + "flow_mode": "None", + "c_nfc": "false", + "c_nfc_mode": "IMM", + "c_ufc": "false", + "c_example_simulation": "false", + "c_gtwiz_out": "false", + "c_line_rate": 2, + "cc_line_rate": 2, + "c_refclk_frequency": "250.000", + "cc_refclk_frequency": "250.000", + "c_init_clk": "100.0", + "drp_freq": "100.0", + "c_gt_loc_1": 1, + "c_gt_loc_2": "X", + "c_gt_loc_3": "X", + "c_gt_loc_4": "X", + "c_gt_loc_5": "X", + "c_gt_loc_6": "X", + "c_gt_loc_7": "X", + "c_gt_loc_8": "X", + "c_gt_loc_9": "X", + "c_gt_loc_10": "X", + "c_gt_loc_11": "X", + "c_gt_loc_12": "X", + "c_gt_loc_13": "X", + "c_gt_loc_14": "X", + "c_gt_loc_15": "X", + "c_gt_loc_16": "X", + "c_gt_loc_17": "X", + "c_gt_loc_18": "X", + "c_gt_loc_19": "X", + "c_gt_loc_20": "X", + "c_gt_loc_21": "X", + "c_gt_loc_22": "X", + "c_gt_loc_23": "X", + "c_gt_loc_24": "X", + "c_gt_loc_25": "X", + "c_gt_loc_26": "X", + "c_gt_loc_27": "X", + "c_gt_loc_28": "X", + "c_gt_loc_29": "X", + "c_gt_loc_30": "X", + "c_gt_loc_31": "X", + "c_gt_loc_32": "X", + "c_gt_loc_33": "X", + "c_gt_loc_34": "X", + "c_gt_loc_35": "X", + "c_gt_loc_36": "X", + "c_gt_loc_37": "X", + "c_gt_loc_38": "X", + "c_gt_loc_39": "X", + "c_gt_loc_40": "X", + "c_gt_loc_41": "X", + "c_gt_loc_42": "X", + "c_gt_loc_43": "X", + "c_gt_loc_44": "X", + "c_gt_loc_45": "X", + "c_gt_loc_46": "X", + "c_gt_loc_47": "X", + "c_gt_loc_48": "X", + "c_gt_clock_1": "GTXQ0", + "c_gt_clock_2": "None", + "c_use_scrambler": "false", + "c_use_chipscope": "false", + "c_drp_if": "false", + "transceivercontrol": "false", + "c_use_crc": "true", + "supportlevel": 1, + "c_use_byteswap": "false", + "c_cpll_fbdiv": 2, + "c_cpll_fbdiv_45": 4, + "c_cpll_refclk_div": 1, + "c_rxoutdiv": 2, + "c_txoutdiv": 2, + "user_interface": "AXI_4_Streaming", + "c_ufcbuswidthselect": 32, + "c_ufcrembuswidthselect": 2, + "c_ufcstrbbuswidthselect": 4, + "c_rembuswidthselect": 2, + "isv7gth": "false", + "gtquadcnt": 1, + "port7dmonitorout": 7, + "is_7series": "true", + "singleend_initclk": "true", + "singleend_gtrefclk": "true", + "c_double_gtrxreset": "false", + "c_doccport_enable": "false", + "is_board": "vc707", + "usdrpaddr_width": 8, + "usdmon_width": 16, + "txdiffctrl_width": 3, + "ins_loss_nyq": 14, + "rx_eq_mode": "AUTO", + "rx_coupling": "AC", + "rx_termination": "PROGRAMMABLE", + "rx_termination_prog_value": 800, + "rx_ppm_offset": 200, + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S00_AXIS", + "name": "USER_DATA_M_AXI_RX" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M00_AXIS", + "name": "USER_DATA_S_AXI_TX" + } + ] + }, + "aurora_8b10b_ch1": { + "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", + "parameters": { + "component_name": "design_1_aurora_8b10b_1_0", + "channel_enable": "X0Y0", + "c_refclk_loc_p": "BL8", + "c_refclk_loc_n": "BL7", + "c_column_used": "right", + "c_ucolumn_used": "right", + "c_family": "virtex7", + "c_device": "xc7vx485t", + "c_row_used": "None", + "c_xpackage": "ffg1761", + "c_xspeedgrade": -2, + "c_aurora_lanes": 1, + "c_lane_width": 4, + "c_active_transceiverquads": 1, + "c_start_quad": "X0Y0", + "c_start_lane": "X0Y0", + "c_refclk_source": "none", + "interface_mode": "Framing", + "c_stream": "false", + "dataflow_config": "Duplex", + "backchannel_mode": "Sidebands", + "c_simplex": "false", + "c_simplex_mode": "TX", + "flow_mode": "None", + "c_nfc": "false", + "c_nfc_mode": "IMM", + "c_ufc": "false", + "c_example_simulation": "false", + "c_gtwiz_out": "false", + "c_line_rate": 2, + "cc_line_rate": 2, + "c_refclk_frequency": "250.000", + "cc_refclk_frequency": "250.000", + "c_init_clk": "100.0", + "drp_freq": "100.0", + "c_gt_loc_1": 1, + "c_gt_loc_2": "X", + "c_gt_loc_3": "X", + "c_gt_loc_4": "X", + "c_gt_loc_5": "X", + "c_gt_loc_6": "X", + "c_gt_loc_7": "X", + "c_gt_loc_8": "X", + "c_gt_loc_9": "X", + "c_gt_loc_10": "X", + "c_gt_loc_11": "X", + "c_gt_loc_12": "X", + "c_gt_loc_13": "X", + "c_gt_loc_14": "X", + "c_gt_loc_15": "X", + "c_gt_loc_16": "X", + "c_gt_loc_17": "X", + "c_gt_loc_18": "X", + "c_gt_loc_19": "X", + "c_gt_loc_20": "X", + "c_gt_loc_21": "X", + "c_gt_loc_22": "X", + "c_gt_loc_23": "X", + "c_gt_loc_24": "X", + "c_gt_loc_25": "X", + "c_gt_loc_26": "X", + "c_gt_loc_27": "X", + "c_gt_loc_28": "X", + "c_gt_loc_29": "X", + "c_gt_loc_30": "X", + "c_gt_loc_31": "X", + "c_gt_loc_32": "X", + "c_gt_loc_33": "X", + "c_gt_loc_34": "X", + "c_gt_loc_35": "X", + "c_gt_loc_36": "X", + "c_gt_loc_37": "X", + "c_gt_loc_38": "X", + "c_gt_loc_39": "X", + "c_gt_loc_40": "X", + "c_gt_loc_41": "X", + "c_gt_loc_42": "X", + "c_gt_loc_43": "X", + "c_gt_loc_44": "X", + "c_gt_loc_45": "X", + "c_gt_loc_46": "X", + "c_gt_loc_47": "X", + "c_gt_loc_48": "X", + "c_gt_clock_1": "GTXQ0", + "c_gt_clock_2": "None", + "c_use_scrambler": "false", + "c_use_chipscope": "false", + "c_drp_if": "false", + "transceivercontrol": "false", + "c_use_crc": "false", + "supportlevel": 0, + "c_use_byteswap": "false", + "c_cpll_fbdiv": 2, + "c_cpll_fbdiv_45": 4, + "c_cpll_refclk_div": 1, + "c_rxoutdiv": 2, + "c_txoutdiv": 2, + "user_interface": "AXI_4_Streaming", + "c_ufcbuswidthselect": 32, + "c_ufcrembuswidthselect": 2, + "c_ufcstrbbuswidthselect": 4, + "c_rembuswidthselect": 2, + "isv7gth": "false", + "gtquadcnt": 1, + "port7dmonitorout": 7, + "is_7series": "true", + "singleend_initclk": "false", + "singleend_gtrefclk": "false", + "c_double_gtrxreset": "false", + "c_doccport_enable": "false", + "is_board": "vc707", + "usdrpaddr_width": 8, + "usdmon_width": 16, + "txdiffctrl_width": 3, + "ins_loss_nyq": 14, + "rx_eq_mode": "AUTO", + "rx_coupling": "AC", + "rx_termination": "PROGRAMMABLE", + "rx_termination_prog_value": 800, + "rx_ppm_offset": 200, + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S01_AXIS", + "name": "USER_DATA_M_AXI_RX" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M01_AXIS", + "name": "USER_DATA_S_AXI_TX" + } + ] + }, + "aurora_8b10b_ch2": { + "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", + "parameters": { + "component_name": "design_1_aurora_8b10b_3_0", + "channel_enable": "X0Y0", + "c_refclk_loc_p": "BL8", + "c_refclk_loc_n": "BL7", + "c_column_used": "right", + "c_ucolumn_used": "right", + "c_family": "virtex7", + "c_device": "xc7vx485t", + "c_row_used": "None", + "c_xpackage": "ffg1761", + "c_xspeedgrade": -2, + "c_aurora_lanes": 1, + "c_lane_width": 4, + "c_active_transceiverquads": 1, + "c_start_quad": "X0Y0", + "c_start_lane": "X0Y0", + "c_refclk_source": "none", + "interface_mode": "Framing", + "c_stream": "false", + "dataflow_config": "Duplex", + "backchannel_mode": "Sidebands", + "c_simplex": "false", + "c_simplex_mode": "TX", + "flow_mode": "None", + "c_nfc": "false", + "c_nfc_mode": "IMM", + "c_ufc": "false", + "c_example_simulation": "false", + "c_gtwiz_out": "false", + "c_line_rate": 2, + "cc_line_rate": 2, + "c_refclk_frequency": "250.000", + "cc_refclk_frequency": "250.000", + "c_init_clk": "100.0", + "drp_freq": "100.0", + "c_gt_loc_1": "X", + "c_gt_loc_2": "X", + "c_gt_loc_3": "X", + "c_gt_loc_4": "X", + "c_gt_loc_5": "X", + "c_gt_loc_6": "X", + "c_gt_loc_7": "X", + "c_gt_loc_8": "X", + "c_gt_loc_9": "X", + "c_gt_loc_10": "X", + "c_gt_loc_11": "X", + "c_gt_loc_12": "X", + "c_gt_loc_13": "X", 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"c_use_byteswap": "false", + "c_cpll_fbdiv": 2, + "c_cpll_fbdiv_45": 4, + "c_cpll_refclk_div": 1, + "c_rxoutdiv": 2, + "c_txoutdiv": 2, + "user_interface": "AXI_4_Streaming", + "c_ufcbuswidthselect": 32, + "c_ufcrembuswidthselect": 2, + "c_ufcstrbbuswidthselect": 4, + "c_rembuswidthselect": 2, + "isv7gth": "false", + "gtquadcnt": 1, + "port7dmonitorout": 7, + "is_7series": "true", + "singleend_initclk": "false", + "singleend_gtrefclk": "false", + "c_double_gtrxreset": "false", + "c_doccport_enable": "false", + "is_board": "vc707", + "usdrpaddr_width": 8, + "usdmon_width": 16, + "txdiffctrl_width": 3, + "ins_loss_nyq": 14, + "rx_eq_mode": "AUTO", + "rx_coupling": "AC", + "rx_termination": "PROGRAMMABLE", + "rx_termination_prog_value": 800, + "rx_ppm_offset": 200, + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S02_AXIS", + "name": "USER_DATA_M_AXI_RX" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M02_AXIS", + "name": "USER_DATA_S_AXI_TX" + } + ] + }, + "aurora_8b10b_ch3": { + "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", + "parameters": { + "component_name": "design_1_aurora_8b10b_2_0", + "channel_enable": "X0Y0", + "c_refclk_loc_p": "BL8", + "c_refclk_loc_n": "BL7", + "c_column_used": "right", + "c_ucolumn_used": "right", + "c_family": "virtex7", + "c_device": "xc7vx485t", + "c_row_used": "None", + "c_xpackage": "ffg1761", + "c_xspeedgrade": -2, + "c_aurora_lanes": 1, + "c_lane_width": 4, + "c_active_transceiverquads": 1, + "c_start_quad": "X0Y0", + "c_start_lane": "X0Y0", + "c_refclk_source": "none", + "interface_mode": "Framing", + "c_stream": "false", + "dataflow_config": "Duplex", + "backchannel_mode": "Sidebands", + "c_simplex": "false", + "c_simplex_mode": "TX", + "flow_mode": "None", + "c_nfc": "false", + "c_nfc_mode": "IMM", + "c_ufc": "false", + "c_example_simulation": "false", + "c_gtwiz_out": "false", + "c_line_rate": 2, + "cc_line_rate": 2, + "c_refclk_frequency": "250.000", + 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"c_gt_loc_43": "X", + "c_gt_loc_44": "X", + "c_gt_loc_45": "X", + "c_gt_loc_46": "X", + "c_gt_loc_47": "X", + "c_gt_loc_48": "X", + "c_gt_clock_1": "GTXQ6", + "c_gt_clock_2": "None", + "c_use_scrambler": "false", + "c_use_chipscope": "false", + "c_drp_if": "false", + "transceivercontrol": "false", + "c_use_crc": "false", + "supportlevel": 0, + "c_use_byteswap": "false", + "c_cpll_fbdiv": 2, + "c_cpll_fbdiv_45": 4, + "c_cpll_refclk_div": 1, + "c_rxoutdiv": 2, + "c_txoutdiv": 2, + "user_interface": "AXI_4_Streaming", + "c_ufcbuswidthselect": 32, + "c_ufcrembuswidthselect": 2, + "c_ufcstrbbuswidthselect": 4, + "c_rembuswidthselect": 2, + "isv7gth": "false", + "gtquadcnt": 1, + "port7dmonitorout": 7, + "is_7series": "true", + "singleend_initclk": "false", + "singleend_gtrefclk": "false", + "c_double_gtrxreset": "false", + "c_doccport_enable": "false", + "is_board": "vc707", + "usdrpaddr_width": 8, + "usdmon_width": 16, + "txdiffctrl_width": 3, + "ins_loss_nyq": 14, + "rx_eq_mode": "AUTO", + "rx_coupling": "AC", + "rx_termination": "PROGRAMMABLE", + "rx_termination_prog_value": 800, + "rx_ppm_offset": 200, + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S03_AXIS", + "name": "USER_DATA_M_AXI_RX" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M03_AXIS", + "name": "USER_DATA_S_AXI_TX" + } + ] + }, + "axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "parameters": { + "c_s_axi_lite_addr_width": 10, + "c_s_axi_lite_data_width": 32, + "c_dlytmr_resolution": 125, + "c_prmry_is_aclk_async": 0, + "c_enable_multi_channel": 0, + "c_num_mm2s_channels": 1, + "c_num_s2mm_channels": 1, + "c_include_sg": 1, + "c_sg_include_stscntrl_strm": 0, + "c_sg_use_stsapp_length": 0, + "c_sg_length_width": 14, + "c_m_axi_sg_addr_width": 32, + "c_m_axi_sg_data_width": 32, + "c_m_axis_mm2s_cntrl_tdata_width": 32, + "c_s_axis_s2mm_sts_tdata_width": 32, + "c_micro_dma": 0, + "c_include_mm2s": 1, + "c_include_mm2s_sf": 1, + "c_mm2s_burst_size": 16, + "c_m_axi_mm2s_addr_width": 32, + "c_m_axi_mm2s_data_width": 32, + "c_m_axis_mm2s_tdata_width": 32, + "c_include_mm2s_dre": 0, + "c_include_s2mm": 1, + "c_include_s2mm_sf": 1, + "c_s2mm_burst_size": 16, + "c_m_axi_s2mm_addr_width": 32, + "c_m_axi_s2mm_data_width": 32, + "c_s_axis_s2mm_tdata_width": 32, + "c_include_s2mm_dre": 0, + "c_increase_throughput": 0, + "c_family": "virtex7", + "component_name": "design_1_axi_dma_0_0", + "c_addr_width": 32, + "c_single_interface": 0, + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 12288, + "c_highaddr": 13311 + }, + "memory-view": { + "M_AXI_SG": { + "axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + }, + "M_AXI_MM2S": { + "axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + }, + "M_AXI_S2MM": { + "axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + } + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S04_AXIS", + "name": "MM2S" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M04_AXIS", + "name": "S2MM" + } + ], + "irqs": { + "mm2s_introut": "axi_pcie_intc_0:0", + "s2mm_introut": "axi_pcie_intc_0:1" + } + }, + "axi_gpio_0": { + "vlnv": "xilinx.com:ip:axi_gpio:2.0", + "parameters": { + "c_family": "virtex7", + "c_s_axi_addr_width": 9, + "c_s_axi_data_width": 32, + "c_gpio_width": 8, + "c_gpio2_width": 32, + "c_all_inputs": 0, + "c_all_inputs_2": 0, + "c_all_outputs": 1, + "c_all_outputs_2": 0, + "c_interrupt_present": 0, + "c_dout_default": 0, + "c_tri_default": 4294967295, + "c_is_dual": 0, + "c_dout_default_2": 0, + "c_tri_default_2": 4294967295, + "component_name": "design_1_axi_gpio_0_0", + "use_board_flow": "false", + "gpio_board_interface": "led_8bits", + "gpio2_board_interface": "Custom", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 0, + "c_highaddr": 127 + } + }, + "axi_pcie_0": { + "vlnv": "xilinx.com:ip:axi_pcie:2.9", + "parameters": { + "c_family": "virtex7", + "c_instance": "design_1_axi_pcie_0_1", + "c_s_axi_id_width": 2, + "c_s_axi_addr_width": 32, + "c_s_axi_data_width": 64, + "c_m_axi_addr_width": 32, + "c_m_axi_data_width": 64, + "c_no_of_lanes": 1, + "c_max_link_speed": 1, + "c_pcie_use_mode": "3.0", + "c_device_id": 28705, + "c_vendor_id": 4334, + "c_class_code": 360448, + "c_ref_clk_freq": 0, + "c_rev_id": 0, + "c_subsystem_id": 7, + "c_subsystem_vendor_id": 4334, + "c_pcie_cap_slot_implemented": 0, + "c_slot_clock_config": "TRUE", + "c_msi_decode_enable": "TRUE", + "c_int_fifo_depth": 0, + "c_num_msi_req": 0, + "c_interrupt_pin": 0, + "c_comp_timeout": 0, + "c_include_rc": 0, + "c_s_axi_supports_narrow_burst": 0, + "c_include_baroffset_reg": 1, + "c_axibar_num": 1, + "c_axibar2pciebar_0": 0, + "c_axibar2pciebar_1": 0, + "c_axibar2pciebar_2": 0, + "c_axibar2pciebar_3": 0, + "c_axibar2pciebar_4": 0, + "c_axibar2pciebar_5": 0, + "c_axibar_as_0": 0, + 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"FALSE", + "c_device": "xc7vx485t", + "c_speed": -2, + "axi_aclk_loopback": "false", + "no_slv_err": "false", + "c_rp_bar_hide": "FALSE", + "enable_jtag_dbg": "false", + "c_axibar_chk_slv_err": "false", + "reduce_oob_freq": "false", + "component_name": "design_1_axi_pcie_0_1", + "include_rc": "PCI_Express_Endpoint_device", + "ref_clk_freq": "100_MHz", + "slot_clock_config": "true", + "pcie_use_mode": "GES_and_Production", + "no_of_lanes": "X1", + "max_link_speed": "5.0_GT/s", + "vendor_id": 4334, + "device_id": 28705, + "rev_id": 0, + "subsystem_vendor_id": 4334, + "subsystem_id": 7, + "enable_class_code": "true", + "class_code": 360448, + "base_class_menu": "Memory_controller", + "sub_class_interface_menu": "Other_memory_controller", + "bar0_enabled": "true", + "bar1_enabled": "false", + "bar2_enabled": "false", + "bar0_type": "Memory", + "bar1_type": "N/A", + "bar2_type": "N/A", + "bar0_scale": "Megabytes", + "bar1_scale": "N/A", + "bar2_scale": "N/A", + "bar0_size": 1, + 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"translation": 0, + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + }, + "pcie_bars": { + "BAR0": { + "translation": 0 + } + } + }, + "axi_pcie_intc_0": { + "vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0", + "parameters": { + "component_name": "design_1_axi_pcie_intc_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 8192, + "c_highaddr": 9215 + } + }, + "axis_interconnect_0_xbar": { + "vlnv": "xilinx.com:ip:axis_switch:1.1", + "parameters": { + "c_family": "virtex7", + "c_num_si_slots": 5, + "c_log_si_slots": 3, + "c_num_mi_slots": 5, + "c_axis_tdata_width": 32, + "c_axis_tid_width": 1, + "c_axis_tdest_width": 1, + "c_axis_tuser_width": 1, + "c_axis_signal_set": 27, + "c_arb_on_max_xfers": 1, + "c_arb_on_num_cycles": 0, + "c_arb_on_tlast": 0, + "c_include_arbiter": 1, + "c_arb_algorithm": 0, + "c_output_reg": 0, + "c_decoder_reg": 1, + "c_m_axis_connectivity_array": 33554431, + "c_m_axis_basetdest_array": 10, + "c_m_axis_hightdest_array": 10, + "c_routing_mode": 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