From 89f75c9a57879fd9b141302eb714a96ba4e9d613 Mon Sep 17 00:00:00 2001 From: Hatim Kanchwala Date: Tue, 30 Jun 2020 22:40:32 +0200 Subject: [PATCH] Remove old JSON config files --- fpga/etc/7aug.json | 420 ------------------------------------ fpga/etc/using-old-bit.json | 420 ------------------------------------ 2 files changed, 840 deletions(-) delete mode 100644 fpga/etc/7aug.json delete mode 100644 fpga/etc/using-old-bit.json diff --git a/fpga/etc/7aug.json b/fpga/etc/7aug.json deleted file mode 100644 index d833bff4d..000000000 --- a/fpga/etc/7aug.json +++ /dev/null @@ -1,420 +0,0 @@ -{ - "affinity": 1, - "stats": 3, - "name": "villas-acs", - "logging": { - "level": 5, - "faciltities": [ - "path", - "socket" - ], - "file": "/var/log/villas-node.log", - "syslog": true - }, - "http": { - "enabled": true, - "htdocs": "/villas/web/socket/", - "port": 80 - }, - "plugins": [ - "simple_circuit.so", - "example_hook.so" - ], - "fpgas": { - "vc707": { - "id": "10ee:7022", - "do_reset": true, - "ips": { - "hier_0_rtds_axis_0": { - "irqs": { - "irq_ts": "pcie_0_axi_pcie_intc_0:5", - "irq_case": "pcie_0_axi_pcie_intc_0:7", - "irq_overflow": "pcie_0_axi_pcie_intc_0:6" - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS", - "name": "m_axis" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS", - "name": "s_axis" - } - ], - "vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0" - }, - "pcie_0_axi_pcie_0": { - "axi_bars": { - "BAR0": { - "translation": 0, - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - }, - "memory-view": { - "M_AXI": { - "hier_0_rtds_axis_0": { - "reg0": { - "highaddr": 36863, - "baseaddr": 32768, - "size": 4096 - } - }, - "pcie_0_axi_pcie_0": { - "CTL0": { - "highaddr": 536870911, - "baseaddr": 268435456, - "size": 268435456 - } - }, - "hier_0_axi_fifo_mm_s_0": { - "Mem1": { - "highaddr": 57343, - "baseaddr": 49152, - "size": 8192 - }, - "Mem0": { - "highaddr": 28671, - "baseaddr": 24576, - "size": 4096 - } - }, - "hier_0_hls_dft_0": { - "Reg": { - "highaddr": 40959, - "baseaddr": 36864, - "size": 4096 - } - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "Reg": { - "highaddr": 24575, - "baseaddr": 20480, - "size": 4096 - } - }, - "hier_0_axi_dma_axi_dma_1": { - "Reg": { - "highaddr": 12287, - "baseaddr": 8192, - "size": 4096 - } - }, - "timer_0_axi_timer_0": { - "Reg": { - "highaddr": 20479, - "baseaddr": 16384, - "size": 4096 - } - }, - "hier_0_axi_dma_axi_dma_0": { - "Reg": { - "highaddr": 16383, - "baseaddr": 12288, - "size": 4096 - } - }, - "pcie_0_axi_reset_0": { - "Reg": { - "highaddr": 32767, - "baseaddr": 28672, - "size": 4096 - } - }, - "pcie_0_axi_pcie_intc_0": { - "Reg": { - "highaddr": 49151, - "baseaddr": 45056, - "size": 4096 - } - } - } - }, - "vlnv": "xilinx.com:ip:axi_pcie:2.8", - "pcie_bars": { - "BAR0": { - "translation": 0 - } - } - }, - "hier_0_axi_fifo_mm_s_0": { - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:2" - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS", - "name": "STR_TXD" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS", - "name": "STR_RXD" - } - ], - "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1" - }, - "hier_0_hls_dft_0": { - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:1" - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S05_AXIS", - "name": "output_r" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M05_AXIS", - "name": "input_r" - } - ], - "vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0" - }, - "hier_0_axi_dma_axi_dma_0": { - "irqs": { - "s2mm_introut": "pcie_0_axi_pcie_intc_0:4", - "mm2s_introut": "pcie_0_axi_pcie_intc_0:3" - }, - "memory-view": { - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_SG": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS", - "name": "MM2S" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS", - "name": "S2MM" - } - ], - "vlnv": "xilinx.com:ip:axi_dma:7.1" - }, - "hier_0_axi_dma_axi_dma_1": { - "irqs": { - "s2mm_introut": "pcie_0_axi_pcie_intc_0:4", - "mm2s_introut": "pcie_0_axi_pcie_intc_0:3" - }, - "memory-view": { - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S06_AXIS", - "name": "MM2S" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M06_AXIS", - "name": "S2MM" - } - ], - "vlnv": "xilinx.com:ip:axi_dma:7.1" - }, - "timer_0_axi_timer_0": { - "irqs": { - "generateout0": "pcie_0_axi_pcie_intc_0:0" - }, - "vlnv": "xilinx.com:ip:axi_timer:2.0" - }, - "hier_0_axis_data_fifo_1": { - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS", - "name": "AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS", - "name": "AXIS" - } - ], - "vlnv": "xilinx.com:ip:axis_data_fifo:1.1" - }, - "hier_0_axis_data_fifo_0": { - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS", - "name": "AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS", - "name": "AXIS" - } - ], - "vlnv": "xilinx.com:ip:axis_data_fifo:1.1" - }, - "pcie_0_axi_reset_0": { - "vlnv": "xilinx.com:ip:axi_gpio:2.0" - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "num_ports": 7, - "ports": [ - { - "role": "slave", - "target": "hier_0_rtds_axis_0:m_axis", - "name": "S00_AXIS" - }, - { - "role": "master", - "target": "hier_0_rtds_axis_0:s_axis", - "name": "M00_AXIS" - }, - { - "role": "target", - "target": "hier_0_axi_dma_axi_dma_0:MM2S", - "name": "S01_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axi_dma_axi_dma_0:S2MM", - "name": "M01_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_fifo_mm_s_0:STR_TXD", - "name": "S02_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_fifo_mm_s_0:STR_RXD", - "name": "M02_AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "S03_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "M03_AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "S04_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "M04_AXIS" - }, - { - "role": "slave", - "target": "hier_0_hls_dft_0:output_r", - "name": "S05_AXIS" - }, - { - "role": "master", - "target": "hier_0_hls_dft_0:input_r", - "name": "M05_AXIS" - }, - { - "role": "target", - "target": "hier_0_axi_dma_axi_dma_1:MM2S", - "name": "S06_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axi_dma_axi_dma_1:S2MM", - "name": "M06_AXIS" - } - ], - "vlnv": "xilinx.com:ip:axis_switch:1.1" - }, - "pcie_0_axi_pcie_intc_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0" - } - } - } - }, - "nodes": { - "dma_0": { - "type": "fpga", - "datamover": "dma_0", - "use_irqs": false - }, - "dma_1": { - "type": "fpga", - "datamover": "dma_1", - "use_irqs": false - }, - "fifo_0": { - "type": "fpga", - "datamover": "fifo_mm_s_0", - "use_irqs": false - }, - "simple_circuit": { - "type": "cbuilder", - "model": "simple_circuit", - "timestep": 2.5000000000000001e-5, - "parameters": [ - 1.0, - 0.001 - ] - } - }, - "paths": [ - { - "in": "dma_1", - "out": "simple_circuit", - "reverse": true - } - ] -} diff --git a/fpga/etc/using-old-bit.json b/fpga/etc/using-old-bit.json deleted file mode 100644 index d15565476..000000000 --- a/fpga/etc/using-old-bit.json +++ /dev/null @@ -1,420 +0,0 @@ -{ - "affinity": 1, - "stats": 3, - "name": "villas-acs", - "logging": { - "level": 5, - "faciltities": [ - "path", - "socket" - ], - "file": "/var/log/villas-node.log", - "syslog": true - }, - "http": { - "enabled": true, - "htdocs": "/villas/web/socket/", - "port": 80 - }, - "plugins": [ - "simple_circuit.so", - "example_hook.so" - ], - "fpgas": { - "vc707": { - "id": "10ee:7022", - "do_reset": true, - "ips": { - "hier_0_rtds_axis_0": { - "irqs": { - "irq_ts": "pcie_0_axi_pcie_intc_0:5", - "irq_case": "pcie_0_axi_pcie_intc_0:7", - "irq_overflow": "pcie_0_axi_pcie_intc_0:6" - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS", - "name": "m_axis" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS", - "name": "s_axis" - } - ], - "vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0" - }, - "pcie_0_axi_pcie_0": { - "axi_bars": { - "BAR0": { - "translation": 0, - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - }, - "memory-view": { - "M_AXI": { - "hier_0_rtds_axis_0": { - "reg0": { - "highaddr": 36863, - "baseaddr": 32768, - "size": 4096 - } - }, - "pcie_0_axi_pcie_0": { - "CTL0": { - "highaddr": 536870911, - "baseaddr": 268435456, - "size": 268435456 - } - }, - "hier_0_axi_fifo_mm_s_0": { - "Mem1": { - "highaddr": 57343, - "baseaddr": 49152, - "size": 8192 - }, - "Mem0": { - "highaddr": 28671, - "baseaddr": 24576, - "size": 4096 - } - }, - "hier_0_hls_dft_0": { - "Reg": { - "highaddr": 40959, - "baseaddr": 36864, - "size": 4096 - } - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "Reg": { - "highaddr": 24575, - "baseaddr": 20480, - "size": 4096 - } - }, - "hier_0_axi_dma_axi_dma_0": { - "Reg": { - "highaddr": 16383, - "baseaddr": 12288, - "size": 4096 - } - }, - "hier_0_axi_dma_axi_dma_1": { - "Reg": { - "highaddr": 12287, - "baseaddr": 8192, - "size": 4096 - } - }, - "timer_0_axi_timer_0": { - "Reg": { - "highaddr": 20479, - "baseaddr": 16384, - "size": 4096 - } - }, - "pcie_0_axi_reset_0": { - "Reg": { - "highaddr": 32767, - "baseaddr": 28672, - "size": 4096 - } - }, - "pcie_0_axi_pcie_intc_0": { - "Reg": { - "highaddr": 49151, - "baseaddr": 45056, - "size": 4096 - } - } - } - }, - "vlnv": "xilinx.com:ip:axi_pcie:2.8", - "pcie_bars": { - "BAR0": { - "translation": 0 - } - } - }, - "hier_0_axi_fifo_mm_s_0": { - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:2" - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS", - "name": "STR_TXD" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS", - "name": "STR_RXD" - } - ], - "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1" - }, - "hier_0_hls_dft_0": { - "irqs": { - "interrupt": "pcie_0_axi_pcie_intc_0:1" - }, - "ports": [ - { - "role": "master", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S05_AXIS", - "name": "output_r" - }, - { - "role": "slave", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M05_AXIS", - "name": "input_r" - } - ], - "vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0" - }, - "hier_0_axi_dma_axi_dma_0": { - "irqs": { - "s2mm_introut": "pcie_0_axi_pcie_intc_0:4", - "mm2s_introut": "pcie_0_axi_pcie_intc_0:3" - }, - "memory-view": { - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_SG": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS", - "name": "MM2S" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS", - "name": "S2MM" - } - ], - "vlnv": "xilinx.com:ip:axi_dma:7.1" - }, - "hier_0_axi_dma_axi_dma_1": { - "irqs": { - "s2mm_introut": "pcie_0_axi_pcie_intc_0:4", - "mm2s_introut": "pcie_0_axi_pcie_intc_0:3" - }, - "memory-view": { - "M_AXI_S2MM": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - }, - "M_AXI_MM2S": { - "pcie_0_axi_pcie_0": { - "BAR0": { - "highaddr": 4294967295, - "baseaddr": 0, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S06_AXIS", - "name": "MM2S" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M06_AXIS", - "name": "S2MM" - } - ], - "vlnv": "xilinx.com:ip:axi_dma:7.1" - }, - "timer_0_axi_timer_0": { - "irqs": { - "generateout0": "pcie_0_axi_pcie_intc_0:0" - }, - "vlnv": "xilinx.com:ip:axi_timer:2.0" - }, - "hier_0_axis_data_fifo_1": { - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS", - "name": "AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS", - "name": "AXIS" - } - ], - "vlnv": "xilinx.com:ip:axis_data_fifo:1.1" - }, - "hier_0_axis_data_fifo_0": { - "ports": [ - { - "role": "initiator", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS", - "name": "AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS", - "name": "AXIS" - } - ], - "vlnv": "xilinx.com:ip:axis_data_fifo:1.1" - }, - "pcie_0_axi_reset_0": { - "vlnv": "xilinx.com:ip:axi_gpio:2.0" - }, - "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": { - "num_ports": 7, - "ports": [ - { - "role": "slave", - "target": "hier_0_rtds_axis_0:m_axis", - "name": "S00_AXIS" - }, - { - "role": "master", - "target": "hier_0_rtds_axis_0:s_axis", - "name": "M00_AXIS" - }, - { - "role": "target", - "target": "hier_0_axi_dma_axi_dma_0:MM2S", - "name": "S01_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axi_dma_axi_dma_0:S2MM", - "name": "M01_AXIS" - }, - { - "role": "slave", - "target": "hier_0_axi_fifo_mm_s_0:STR_TXD", - "name": "S02_AXIS" - }, - { - "role": "master", - "target": "hier_0_axi_fifo_mm_s_0:STR_RXD", - "name": "M02_AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "S03_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axis_data_fifo_0:AXIS", - "name": "M03_AXIS" - }, - { - "role": "target", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "S04_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axis_data_fifo_1:AXIS", - "name": "M04_AXIS" - }, - { - "role": "slave", - "target": "hier_0_hls_dft_0:output_r", - "name": "S05_AXIS" - }, - { - "role": "master", - "target": "hier_0_hls_dft_0:input_r", - "name": "M05_AXIS" - }, - { - "role": "target", - "target": "hier_0_axi_dma_axi_dma_1:MM2S", - "name": "S06_AXIS" - }, - { - "role": "initiator", - "target": "hier_0_axi_dma_axi_dma_1:S2MM", - "name": "M06_AXIS" - } - ], - "vlnv": "xilinx.com:ip:axis_switch:1.1" - }, - "pcie_0_axi_pcie_intc_0": { - "vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0" - } - } - } - }, - "nodes": { - "dma_0": { - "type": "fpga", - "datamover": "dma_0", - "use_irqs": false - }, - "dma_1": { - "type": "fpga", - "datamover": "dma_1", - "use_irqs": false - }, - "fifo_0": { - "type": "fpga", - "datamover": "fifo_mm_s_0", - "use_irqs": false - }, - "simple_circuit": { - "type": "cbuilder", - "model": "simple_circuit", - "timestep": 2.5000000000000001e-5, - "parameters": [ - 1.0, - 0.001 - ] - } - }, - "paths": [ - { - "in": "dma_1", - "out": "simple_circuit", - "reverse": true - } - ] -}