diff --git a/fpga/include/villas/fpga/ips/pcie.hpp b/fpga/include/villas/fpga/ips/pcie.hpp index a63db2e20..290a8c577 100644 --- a/fpga/include/villas/fpga/ips/pcie.hpp +++ b/fpga/include/villas/fpga/ips/pcie.hpp @@ -48,6 +48,9 @@ public: friend class AxiPciExpressBridgeFactory; bool init(); + +private: + static constexpr char axiInterface[] = "M_AXI"; }; diff --git a/fpga/lib/ips/pcie.cpp b/fpga/lib/ips/pcie.cpp index df45d68cb..5b02f1261 100644 --- a/fpga/lib/ips/pcie.cpp +++ b/fpga/lib/ips/pcie.cpp @@ -38,12 +38,16 @@ static AxiPciExpressBridgeFactory factory; bool AxiPciExpressBridge::init() { + // Throw an exception if the is no bus master interface and thus no + // address space we can use for translation -> error + const MemoryManager::AddressSpaceId myAddrSpaceid = + busMasterInterfaces.at(axiInterface); + // Create an identity mapping from the FPGA card to this IP as an entry // point to all other IPs in the FPGA, because Vivado will generate a // memory view for this bridge that can see all others. - auto addrSpace = MemoryManager::get().findAddressSpace(getInstanceName()); MemoryManager::get().createMapping(0x00, 0x00, SIZE_MAX, "PCIeBridge", - card->addrSpaceId, addrSpace); + card->addrSpaceId, myAddrSpaceid); return true; }