diff --git a/etc/fpga/zcu106-smmu/zcu106-smmu.json b/etc/fpga/zcu106-smmu/zcu106-smmu.json new file mode 100644 index 000000000..7a124ea09 --- /dev/null +++ b/etc/fpga/zcu106-smmu/zcu106-smmu.json @@ -0,0 +1,509 @@ +{ + "axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "parameters": { + "c_s_axi_lite_addr_width": 10, + "c_s_axi_lite_data_width": 32, + "c_dlytmr_resolution": 125, + "c_prmry_is_aclk_async": 0, + "c_enable_multi_channel": 0, + "c_num_mm2s_channels": 1, + "c_num_s2mm_channels": 1, + "c_include_sg": 1, + "c_sg_include_stscntrl_strm": 0, + "c_sg_use_stsapp_length": 0, + "c_sg_length_width": 23, + "c_m_axi_sg_addr_width": 64, + "c_m_axi_sg_data_width": 32, + "c_m_axis_mm2s_cntrl_tdata_width": 32, + "c_s_axis_s2mm_sts_tdata_width": 32, + "c_micro_dma": 0, + "c_include_mm2s": 1, + "c_include_mm2s_sf": 1, + "c_mm2s_burst_size": 16, + "c_m_axi_mm2s_addr_width": 64, + "c_m_axi_mm2s_data_width": 128, + "c_m_axis_mm2s_tdata_width": 128, + "c_include_mm2s_dre": 0, + "c_include_s2mm": 1, + "c_include_s2mm_sf": 1, + "c_s2mm_burst_size": 16, + "c_m_axi_s2mm_addr_width": 64, + "c_m_axi_s2mm_data_width": 128, + "c_s_axis_s2mm_tdata_width": 128, + "c_include_s2mm_dre": 0, + "c_increase_throughput": 0, + "c_family": "zynquplus", + "component_name": "design_1_axi_dma_0_0", + "c_addr_width": 64, + "c_single_interface": 0, + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684354560, + "c_highaddr": 2684420095 + }, + "memory-view": { + "M_AXI_SG": { + "zynq_ultra_ps_e_0": { + "HPC1_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC1_QSPI": { + "baseaddr": 3221225472, + "highaddr": 3758096383, + "size": 536870912 + }, + "HPC1_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + }, + "M_AXI_MM2S": { + "zynq_ultra_ps_e_0": { + "HPC0_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC0_QSPI": { + "baseaddr": 3221225472, + "highaddr": 3758096383, + "size": 536870912 + }, + "HPC0_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + }, + "M_AXI_S2MM": { + "zynq_ultra_ps_e_0": { + "HPC0_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC0_QSPI": { + "baseaddr": 3221225472, + "highaddr": 3758096383, + "size": 536870912 + }, + "HPC0_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + } + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S00_AXIS", + "name": "MM2S" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M00_AXIS", + "name": "S2MM" + } + ] + }, + "axis_interconnect_0_xbar": { + "vlnv": "xilinx.com:ip:axis_switch:1.1", + "parameters": { + "c_family": "zynquplus", + "c_num_si_slots": 2, + "c_log_si_slots": 1, + "c_num_mi_slots": 2, + "c_axis_tdata_width": 128, + "c_axis_tid_width": 1, + "c_axis_tdest_width": 1, + "c_axis_tuser_width": 1, + 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"memory-view": { + "M_AXI_HPM0_FPD": { + "axi_dma_0": { + "Reg": { + "baseaddr": 2684354560, + "highaddr": 2684420095, + "size": 65536 + } + }, + "axis_interconnect_0_xbar": { + "Reg": { + "baseaddr": 2684420096, + "highaddr": 2684485631, + "size": 65536 + } + } + } + } + } +}