From bbff2c9a88a021596df2166b7473db7c2f180809 Mon Sep 17 00:00:00 2001 From: daniel-k Date: Tue, 23 Jan 2018 14:41:31 +0100 Subject: [PATCH] hwdef-parse: count total switch ports and populate property --- fpga/scripts/hwdef-parse.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fpga/scripts/hwdef-parse.py b/fpga/scripts/hwdef-parse.py index 98b569355..123ca3f9c 100755 --- a/fpga/scripts/hwdef-parse.py +++ b/fpga/scripts/hwdef-parse.py @@ -166,10 +166,13 @@ for mrange in mmap: # find AXI-Stream switch port mapping switch = root.find('.//MODULE[@MODTYPE="axis_switch"]') busifs = switch.find('.//BUSINTERFACES') +switch_ports = 0 for busif in busifs: if busif.get('VLNV') != 'xilinx.com:interface:axis:1.0': continue + switch_ports += 1 + busname = busif.get('BUSNAME') name = busif.get('NAME') type = busif.get('TYPE') @@ -193,6 +196,9 @@ for busif in busifs: if busif_ep: ports[-1]['name'] = sanitize_name(busif_ep.get('NAME')) +# set number of master/slave port pairs for switch +ips[switch.get('INSTANCE')]['num_ports'] = switch_ports / 2 + # find Interrupt assignments intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')