diff --git a/fpga/.gitignore b/fpga/.gitignore index 3d027958c..7097e8168 100644 --- a/fpga/.gitignore +++ b/fpga/.gitignore @@ -4,3 +4,6 @@ build/ *.o *.so *.user + +.vscode/ + diff --git a/fpga/include/villas/fpga/ips/aurora.hpp b/fpga/include/villas/fpga/ips/aurora.hpp index 202a14c7f..54484dd4f 100644 --- a/fpga/include/villas/fpga/ips/aurora.hpp +++ b/fpga/include/villas/fpga/ips/aurora.hpp @@ -39,7 +39,6 @@ public: static constexpr const char* slavePort = "s_axis"; void dump(); - double getDt(); std::list getMemoryBlocks() const { return { registerMemory }; } diff --git a/fpga/lib/CMakeLists.txt b/fpga/lib/CMakeLists.txt index 307b6f98c..c8efa2a09 100644 --- a/fpga/lib/CMakeLists.txt +++ b/fpga/lib/CMakeLists.txt @@ -34,6 +34,7 @@ set(SOURCES ips/dma.cpp ips/bram.cpp ips/rtds.cpp + ips/aurora.cpp ips/rtds2gpu/rtds2gpu.cpp ips/rtds2gpu/xrtds2gpu.c diff --git a/fpga/lib/ips/aurora.cpp b/fpga/lib/ips/aurora.cpp new file mode 100644 index 000000000..945f2bc7c --- /dev/null +++ b/fpga/lib/ips/aurora.cpp @@ -0,0 +1,64 @@ +/** Driver for wrapper around Aurora (acs.eonerc.rwth-aachen.de:user:aurora) + * + * @author Hatim Kanchwala + * @copyright 2020, Hatim Kanchwala + * @license GNU General Public License (version 3) + * + * VILLASfpga + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + *********************************************************************************/ + +#include + +#include + +#include +#include + + +/* Register offsets */ +#define AUR_AXIS_SR_OFFSET 0x00 /**< Status Register (read-only). See AUR_AXIS_SR_* constant. */ +#define AUR_AXIS_CR_OFFSET 0x04 /**< Control Register (read/write) */ + +/* Status register bits */ +#define AUR_AXIS_SR_LOOPBACK (1 << 0)/**< ‘1’ when Aurora IP is in loopback mode. */ + +/* Control register bits */ + +namespace villas { +namespace fpga { +namespace ip { + +static AuroraFactory auroraFactoryInstance; + + +void Aurora::dump() +{ + /* Check Aurora AXI4 registers */ + const uint32_t sr = readMemory(registerMemory, AUR_AXIS_SR_OFFSET); + + logger->info("Aurora-NovaCor AXI-Stream interface details:"); + logger->info("Aurora status: {:#x}", sr); + logger->info(" Loopback mode: {}", sr & AUR_AXIS_SR_LOOPBACK ? CLR_GRN("yes") : CLR_RED("no")); +} + +AuroraFactory::AuroraFactory() : + IpNodeFactory(getName()) +{ +} + +} // namespace ip +} // namespace fpga +} // namespace villas diff --git a/fpga/src/villas-fpga-pipe.cpp b/fpga/src/villas-fpga-pipe.cpp index ac2ff2e12..0f51abb76 100644 --- a/fpga/src/villas-fpga-pipe.cpp +++ b/fpga/src/villas-fpga-pipe.cpp @@ -39,6 +39,7 @@ #include #include #include +#include using namespace villas; @@ -145,17 +146,15 @@ int main(int argc, char* argv[]) auto card = setupFpgaCard(configFile, fpgaName); - auto rtds = dynamic_cast - (card->lookupIp(fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:"))); + auto aurora = dynamic_cast + (card->lookupIp(fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:aurora:"))); - //auto dma = dynamic_cast - // (card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:"))); auto dma = dynamic_cast (card->lookupIp("hier_0_axi_dma_axi_dma_1")); - if(rtds == nullptr) { - logger->error("No RTDS interface found on FPGA"); + if(aurora == nullptr) { + logger->error("No Aurora interface found on FPGA"); return 1; } @@ -164,13 +163,13 @@ int main(int argc, char* argv[]) return 1; } - rtds->dump(); + aurora->dump(); - rtds->connect(rtds->getMasterPort(rtds->masterPort), + aurora->connect(aurora->getMasterPort(aurora->masterPort), dma->getSlavePort(dma->s2mmPort)); dma->connect(dma->getMasterPort(dma->mm2sPort), - rtds->getSlavePort(rtds->slavePort)); + aurora->getSlavePort(aurora->slavePort)); auto &alloc = villas::HostRam::getAllocator(); auto mem = alloc.allocate(0x100 / sizeof(int32_t));