From bffb47dca8e0ed0081c8a36f51d3f0fff8c0406c Mon Sep 17 00:00:00 2001
From: Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
Date: Tue, 14 Jun 2016 01:19:17 +0200
Subject: [PATCH] added VILLASfpga code

---
 .gitignore                                    |    1 +
 config-fpga.h                                 |  111 +
 config.h                                      |    2 +-
 include/fpga-bench.h                          |   21 +
 include/fpga-tests.h                          |   29 +
 include/gtfpga.h                              |   79 -
 include/villas/fpga/dma.h                     |   42 +
 include/villas/fpga/fifo.h                    |   26 +
 include/villas/fpga/model.h                   |  100 +
 include/villas/fpga/rtds_axis.h               |   43 +
 include/villas/fpga/switch.h                  |   21 +
 include/villas/fpga/xsg.h                     |   54 +
 include/villas/kernel/pci.h                   |   21 +
 include/villas/kernel/vfio.h                  |  104 +
 include/villas/nodes/vfpga.h                  |  103 +
 lib/fpga/dma.c                                |  409 ++
 lib/fpga/fifo.c                               |   65 +
 lib/fpga/model.c                              |  136 +
 lib/fpga/rtds_axis.c                          |   49 +
 lib/fpga/switch.c                             |   49 +
 lib/fpga/xsg.c                                |  176 +
 lib/gtfpga.c                                  |  192 -
 lib/kernel/pci.c                              |   75 +
 lib/kernel/vfio.c                             |  625 ++
 lib/nodes/vfpga.c                             |  353 ++
 lib/utils.c                                   |   90 +
 src/fpga-bench.c                              |  159 +
 src/fpga-tests.c                              |  404 ++
 src/fpga.c                                    |  165 +
 src/server.c                                  |   13 +-
 thirdparty/opal/README.txt                    |    7 -
 thirdparty/opal/include_target/AsyncApi.h     |  670 ---
 .../include_target/OpalGenAsyncParamCtrl.h    |   96 -
 thirdparty/opal/include_target/OpalPrint.h    |  110 -
 thirdparty/opal/include_target/OpalTypes.h    |  734 ---
 thirdparty/xilinx/Makefile                    |   28 +
 thirdparty/xilinx/README.md                   |    1 +
 thirdparty/xilinx/include/xilinx/xaxidma.h    |  741 +++
 thirdparty/xilinx/include/xilinx/xaxidma_bd.h |  679 +++
 .../xilinx/include/xilinx/xaxidma_bdring.h    |  526 ++
 thirdparty/xilinx/include/xilinx/xaxidma_hw.h |  344 ++
 .../include/xilinx/xaxidma_porting_guide.h    |  254 +
 .../xilinx/include/xilinx/xaxis_switch.h      |  208 +
 .../xilinx/include/xilinx/xaxis_switch_hw.h   |  167 +
 .../xilinx/include/xilinx/xbasic_types.h      |  315 +
 thirdparty/xilinx/include/xilinx/xdebug.h     |   93 +
 thirdparty/xilinx/include/xilinx/xenv.h       |  191 +
 thirdparty/xilinx/include/xilinx/xenv_linux.h |  255 +
 thirdparty/xilinx/include/xilinx/xenv_none.h  |   55 +
 .../xilinx/include/xilinx/xenv_standalone.h   |  370 ++
 .../xilinx/include/xilinx/xenv_vxworks.h      |  272 +
 thirdparty/xilinx/include/xilinx/xil_assert.h |   85 +
 thirdparty/xilinx/include/xilinx/xil_cache.h  |   71 +
 thirdparty/xilinx/include/xilinx/xil_io.h     |  246 +
 thirdparty/xilinx/include/xilinx/xil_printf.h |   43 +
 thirdparty/xilinx/include/xilinx/xil_types.h  |  200 +
 thirdparty/xilinx/include/xilinx/xintc.h      |  370 ++
 thirdparty/xilinx/include/xilinx/xintc_l.h    |  330 +
 thirdparty/xilinx/include/xilinx/xllfifo.h    |  715 +++
 thirdparty/xilinx/include/xilinx/xllfifo_hw.h |  242 +
 .../xilinx/include/xilinx/xparameters.h       |   16 +
 thirdparty/xilinx/include/xilinx/xstatus.h    |  432 ++
 thirdparty/xilinx/include/xilinx/xstreamer.h  |  333 +
 thirdparty/xilinx/include/xilinx/xtmrctr.h    |  303 +
 thirdparty/xilinx/include/xilinx/xtmrctr_i.h  |   80 +
 thirdparty/xilinx/include/xilinx/xtmrctr_l.h  |  429 ++
 thirdparty/xilinx/include/xilinx/xutil.h      |  167 +
 thirdparty/xilinx/include/xilinx/xversion.h   |  111 +
 thirdparty/xilinx/orig/README.md              |    1 +
 .../xilinx/orig/axidma_v9_0/data/axidma.mdd   |   43 +
 .../xilinx/orig/axidma_v9_0/data/axidma.tcl   |  208 +
 .../orig/axidma_v9_0/data/axidma_header.h     |   41 +
 .../orig/axidma_v9_0/data/axidma_tapp.tcl     |  121 +
 .../axidma_v9_0/doc/html/api/HTML_custom.css  | 1430 +++++
 .../axidma_v9_0/doc/html/api/annotated.html   |   66 +
 .../axidma_v9_0/doc/html/api/classes.html     |   68 +
 .../orig/axidma_v9_0/doc/html/api/doc.png     |  Bin 0 -> 746 bytes
 .../axidma_v9_0/doc/html/api/dynsections.js   |   97 +
 .../orig/axidma_v9_0/doc/html/api/files.html  |   68 +
 .../axidma_v9_0/doc/html/api/functions.html   |  130 +
 .../doc/html/api/functions_vars.html          |  130 +
 .../axidma_v9_0/doc/html/api/globals.html     |  558 ++
 .../doc/html/api/globals_defs.html            |  456 ++
 .../doc/html/api/globals_func.html            |  162 +
 .../doc/html/api/globals_type.html            |   65 +
 .../doc/html/api/group__axidma__v9__0.html    | 5350 +++++++++++++++++
 .../orig/axidma_v9_0/doc/html/api/index.html  |  261 +
 .../orig/axidma_v9_0/doc/html/api/jquery.js   |   68 +
 .../axidma_v9_0/doc/html/api/modules.html     |   58 +
 .../doc/html/api/struct_x_axi_dma.html        |   78 +
 .../html/api/struct_x_axi_dma___bd_ring.html  |  398 ++
 .../html/api/struct_x_axi_dma___config.html   |   78 +
 .../orig/axidma_v9_0/doc/html/api/tab_a.png   |  Bin 0 -> 142 bytes
 .../orig/axidma_v9_0/doc/html/api/tab_b.png   |  Bin 0 -> 169 bytes
 .../orig/axidma_v9_0/doc/html/api/tab_h.png   |  Bin 0 -> 177 bytes
 .../orig/axidma_v9_0/doc/html/api/tab_s.png   |  Bin 0 -> 184 bytes
 .../orig/axidma_v9_0/doc/html/api/tabs.css    |   60 +
 .../axidma_v9_0/doc/html/api/xaxidma_8c.html  |   81 +
 .../axidma_v9_0/doc/html/api/xaxidma_8h.html  |  121 +
 .../doc/html/api/xaxidma__bd_8c.html          |   77 +
 .../doc/html/api/xaxidma__bd_8h.html          |  131 +
 .../doc/html/api/xaxidma__bdring_8c.html      |   91 +
 .../doc/html/api/xaxidma__bdring_8h.html      |  135 +
 .../doc/html/api/xaxidma__g_8c.html           |   57 +
 .../doc/html/api/xaxidma__hw_8h.html          |   95 +
 .../html/api/xaxidma__porting__guide_8h.html  |   57 +
 .../doc/html/api/xaxidma__selftest_8c.html    |   65 +
 .../doc/html/api/xaxidma__sinit_8c.html       |   65 +
 .../axidma_v9_0/doc/html/api/xlogo_bg.gif     |  Bin 0 -> 3154 bytes
 .../orig/axidma_v9_0/examples/index.html      |   22 +
 .../examples/xaxidma_example_selftest.c       |  147 +
 .../examples/xaxidma_example_sg_intr.c        | 1214 ++++
 .../examples/xaxidma_example_sg_poll.c        |  701 +++
 .../examples/xaxidma_example_simple_intr.c    |  753 +++
 .../examples/xaxidma_example_simple_poll.c    |  362 ++
 .../examples/xaxidma_multichan_sg_intr.c      | 1317 ++++
 .../examples/xaxidma_poll_multi_pkts.c        |  696 +++
 .../xilinx/orig/axidma_v9_0/src/Makefile      |   27 +
 .../xilinx/orig/axidma_v9_0/src/xaxidma.c     |  974 +++
 .../xilinx/orig/axidma_v9_0/src/xaxidma.h     |  741 +++
 .../xilinx/orig/axidma_v9_0/src/xaxidma_bd.c  |  354 ++
 .../xilinx/orig/axidma_v9_0/src/xaxidma_bd.h  |  679 +++
 .../orig/axidma_v9_0/src/xaxidma_bdring.c     | 1587 +++++
 .../orig/axidma_v9_0/src/xaxidma_bdring.h     |  526 ++
 .../xilinx/orig/axidma_v9_0/src/xaxidma_g.c   |   88 +
 .../xilinx/orig/axidma_v9_0/src/xaxidma_hw.h  |  344 ++
 .../axidma_v9_0/src/xaxidma_porting_guide.h   |  254 +
 .../orig/axidma_v9_0/src/xaxidma_selftest.c   |  115 +
 .../orig/axidma_v9_0/src/xaxidma_sinit.c      |   95 +
 .../axis_switch_v1_0/data/axis_switch.mdd     |   40 +
 .../axis_switch_v1_0/data/axis_switch.tcl     |   36 +
 .../doc/html/api/HTML_custom.css              | 1430 +++++
 .../doc/html/api/annotated.html               |   65 +
 .../doc/html/api/classes.html                 |   68 +
 .../axis_switch_v1_0/doc/html/api/doc.png     |  Bin 0 -> 746 bytes
 .../doc/html/api/dynsections.js               |   97 +
 .../axis_switch_v1_0/doc/html/api/files.html  |   63 +
 .../doc/html/api/functions.html               |   81 +
 .../doc/html/api/functions_vars.html          |   81 +
 .../doc/html/api/globals.html                 |  127 +
 .../doc/html/api/globals_defs.html            |  103 +
 .../doc/html/api/globals_func.html            |   82 +
 .../html/api/group__axis__switch__v1__0.html  |  786 +++
 .../axis_switch_v1_0/doc/html/api/index.html  |   76 +
 .../axis_switch_v1_0/doc/html/api/jquery.js   |   68 +
 .../doc/html/api/modules.html                 |   58 +
 .../doc/html/api/struct_x_axis___switch.html  |   94 +
 .../api/struct_x_axis___switch___config.html  |  122 +
 .../axis_switch_v1_0/doc/html/api/tab_a.png   |  Bin 0 -> 142 bytes
 .../axis_switch_v1_0/doc/html/api/tab_b.png   |  Bin 0 -> 169 bytes
 .../axis_switch_v1_0/doc/html/api/tab_h.png   |  Bin 0 -> 177 bytes
 .../axis_switch_v1_0/doc/html/api/tab_s.png   |  Bin 0 -> 184 bytes
 .../axis_switch_v1_0/doc/html/api/tabs.css    |   60 +
 .../doc/html/api/xaxis__switch_8c.html        |   75 +
 .../doc/html/api/xaxis__switch_8h.html        |   95 +
 .../doc/html/api/xaxis__switch__g_8c.html     |   57 +
 .../doc/html/api/xaxis__switch__hw_8h.html    |   71 +
 .../html/api/xaxis__switch__selftest_8c.html  |   65 +
 .../doc/html/api/xaxis__switch__sinit_8c.html |   65 +
 .../doc/html/api/xlogo_bg.gif                 |  Bin 0 -> 3154 bytes
 .../orig/axis_switch_v1_0/examples/index.html |   17 +
 .../examples/xaxis_switch_example.c           |  179 +
 .../xilinx/orig/axis_switch_v1_0/src/Makefile |   40 +
 .../orig/axis_switch_v1_0/src/xaxis_switch.c  |  313 +
 .../orig/axis_switch_v1_0/src/xaxis_switch.h  |  208 +
 .../axis_switch_v1_0/src/xaxis_switch_g.c     |   75 +
 .../axis_switch_v1_0/src/xaxis_switch_hw.h    |  167 +
 .../src/xaxis_switch_selftest.c               |  113 +
 .../axis_switch_v1_0/src/xaxis_switch_sinit.c |  118 +
 .../vxworks5_4/xtag_csp_common_v1_00_a.c      |   53 +
 .../orig/common_v1_00_a/data/common.mdd       |   41 +
 .../doc/html/api/HTML_custom.css              | 1430 +++++
 .../doc/html/api/annotated.html               |   63 +
 .../common_v1_00_a/doc/html/api/classes.html  |   67 +
 .../orig/common_v1_00_a/doc/html/api/doc.png  |  Bin 0 -> 746 bytes
 .../doc/html/api/dynsections.js               |   97 +
 .../common_v1_00_a/doc/html/api/files.html    |   70 +
 .../common_v1_00_a/doc/html/api/globals.html  |  210 +
 .../doc/html/api/globals_defs.html            |  120 +
 .../doc/html/api/globals_func.html            |   96 +
 .../doc/html/api/globals_type.html            |  100 +
 .../doc/html/api/globals_vars.html            |   67 +
 .../html/api/group__common__v1__00__a.html    | 1948 ++++++
 .../common_v1_00_a/doc/html/api/index.html    |   53 +
 .../common_v1_00_a/doc/html/api/jquery.js     |   68 +
 .../common_v1_00_a/doc/html/api/modules.html  |   58 +
 .../struct_x_e_n_v___t_i_m_e___s_t_a_m_p.html |   60 +
 .../common_v1_00_a/doc/html/api/tab_a.png     |  Bin 0 -> 142 bytes
 .../common_v1_00_a/doc/html/api/tab_b.png     |  Bin 0 -> 169 bytes
 .../common_v1_00_a/doc/html/api/tab_h.png     |  Bin 0 -> 177 bytes
 .../common_v1_00_a/doc/html/api/tab_s.png     |  Bin 0 -> 184 bytes
 .../orig/common_v1_00_a/doc/html/api/tabs.css |   60 +
 .../doc/html/api/xbasic__types_8c.html        |   77 +
 .../doc/html/api/xbasic__types_8h.html        |  109 +
 .../common_v1_00_a/doc/html/api/xenv_8h.html  |   57 +
 .../doc/html/api/xenv__linux_8h.html          |   81 +
 .../doc/html/api/xenv__none_8h.html           |   57 +
 .../doc/html/api/xenv__standalone_8h.html     |   81 +
 .../doc/html/api/xenv__vxworks_8h.html        |   81 +
 .../common_v1_00_a/doc/html/api/xlogo_bg.gif  |  Bin 0 -> 3154 bytes
 .../doc/html/api/xparameters_8h.html          |   57 +
 .../doc/html/api/xstatus_8h.html              |   57 +
 .../common_v1_00_a/doc/html/api/xutil_8h.html |   69 +
 .../doc/html/api/xutil__memtest_8c.html       |   69 +
 .../doc/html/api/xversion_8c.html             |   75 +
 .../doc/html/api/xversion_8h.html             |   75 +
 .../xilinx/orig/common_v1_00_a/src/Makefile   |   28 +
 .../orig/common_v1_00_a/src/xbasic_types.c    |  150 +
 .../orig/common_v1_00_a/src/xbasic_types.h    |  315 +
 .../xilinx/orig/common_v1_00_a/src/xenv.h     |  191 +
 .../orig/common_v1_00_a/src/xenv_linux.h      |  255 +
 .../orig/common_v1_00_a/src/xenv_none.h       |   55 +
 .../orig/common_v1_00_a/src/xenv_standalone.h |  370 ++
 .../orig/common_v1_00_a/src/xenv_vxworks.h    |  272 +
 .../orig/common_v1_00_a/src/xparameters.h     |  731 +++
 .../xilinx/orig/common_v1_00_a/src/xstatus.h  |  432 ++
 .../xilinx/orig/common_v1_00_a/src/xutil.h    |  167 +
 .../orig/common_v1_00_a/src/xutil_memtest.c   | 1186 ++++
 .../xilinx/orig/common_v1_00_a/src/xversion.c |  357 ++
 .../xilinx/orig/common_v1_00_a/src/xversion.h |  111 +
 .../xilinx/orig/intc_v3_4/data/intc.mdd       |   73 +
 .../xilinx/orig/intc_v3_4/data/intc.tcl       |  692 +++
 .../xilinx/orig/intc_v3_4/data/intc_header.h  |   42 +
 .../xilinx/orig/intc_v3_4/data/intc_tapp.tcl  |  206 +
 .../intc_v3_4/doc/html/api/HTML_custom.css    | 1430 +++++
 .../intc_v3_4/doc/html/api/annotated.html     |   65 +
 .../orig/intc_v3_4/doc/html/api/classes.html  |   68 +
 .../orig/intc_v3_4/doc/html/api/doc.png       |  Bin 0 -> 746 bytes
 .../intc_v3_4/doc/html/api/dynsections.js     |   97 +
 .../orig/intc_v3_4/doc/html/api/files.html    |   66 +
 .../intc_v3_4/doc/html/api/functions.html     |  103 +
 .../doc/html/api/functions_vars.html          |  103 +
 .../orig/intc_v3_4/doc/html/api/globals.html  |  157 +
 .../intc_v3_4/doc/html/api/globals_defs.html  |   86 +
 .../intc_v3_4/doc/html/api/globals_func.html  |  119 +
 .../intc_v3_4/doc/html/api/globals_vars.html  |   63 +
 .../doc/html/api/group__intc__v3__4.html      | 1343 +++++
 .../orig/intc_v3_4/doc/html/api/index.html    |  171 +
 .../orig/intc_v3_4/doc/html/api/jquery.js     |   68 +
 .../orig/intc_v3_4/doc/html/api/modules.html  |   58 +
 .../intc_v3_4/doc/html/api/struct_x_intc.html |  140 +
 .../doc/html/api/struct_x_intc___config.html  |  202 +
 .../orig/intc_v3_4/doc/html/api/tab_a.png     |  Bin 0 -> 142 bytes
 .../orig/intc_v3_4/doc/html/api/tab_b.png     |  Bin 0 -> 169 bytes
 .../orig/intc_v3_4/doc/html/api/tab_h.png     |  Bin 0 -> 177 bytes
 .../orig/intc_v3_4/doc/html/api/tab_s.png     |  Bin 0 -> 184 bytes
 .../orig/intc_v3_4/doc/html/api/tabs.css      |   60 +
 .../orig/intc_v3_4/doc/html/api/xintc_8c.html |   85 +
 .../orig/intc_v3_4/doc/html/api/xintc_8h.html |  116 +
 .../intc_v3_4/doc/html/api/xintc__g_8c.html   |   65 +
 .../intc_v3_4/doc/html/api/xintc__i_8h.html   |   65 +
 .../doc/html/api/xintc__intr_8c.html          |   65 +
 .../intc_v3_4/doc/html/api/xintc__l_8c.html   |   71 +
 .../intc_v3_4/doc/html/api/xintc__l_8h.html   |   87 +
 .../doc/html/api/xintc__options_8c.html       |   67 +
 .../doc/html/api/xintc__selftest_8c.html      |   67 +
 .../orig/intc_v3_4/doc/html/api/xlogo_bg.gif  |  Bin 0 -> 3154 bytes
 .../xilinx/orig/intc_v3_4/examples/index.html |   19 +
 .../orig/intc_v3_4/examples/xintc_example.c   |  348 ++
 .../examples/xintc_low_level_example.c        |  302 +
 .../intc_v3_4/examples/xintc_tapp_example.c   |  250 +
 thirdparty/xilinx/orig/intc_v3_4/src/Makefile |   28 +
 thirdparty/xilinx/orig/intc_v3_4/src/xintc.c  | 1081 ++++
 thirdparty/xilinx/orig/intc_v3_4/src/xintc.h  |  370 ++
 .../xilinx/orig/intc_v3_4/src/xintc_g.c       |  110 +
 .../xilinx/orig/intc_v3_4/src/xintc_i.h       |   93 +
 .../xilinx/orig/intc_v3_4/src/xintc_intr.c    |  176 +
 .../xilinx/orig/intc_v3_4/src/xintc_l.c       |  665 ++
 .../xilinx/orig/intc_v3_4/src/xintc_l.h       |  330 +
 .../xilinx/orig/intc_v3_4/src/xintc_options.c |  149 +
 .../orig/intc_v3_4/src/xintc_selftest.c       |  255 +
 .../xilinx/orig/llfifo_v5_0/data/llfifo.mdd   |   47 +
 .../xilinx/orig/llfifo_v5_0/data/llfifo.tcl   |   53 +
 .../llfifo_v5_0/doc/html/api/HTML_custom.css  | 1430 +++++
 .../llfifo_v5_0/doc/html/api/annotated.html   |   66 +
 .../llfifo_v5_0/doc/html/api/classes.html     |   68 +
 .../orig/llfifo_v5_0/doc/html/api/doc.png     |  Bin 0 -> 746 bytes
 .../llfifo_v5_0/doc/html/api/dynsections.js   |   97 +
 .../orig/llfifo_v5_0/doc/html/api/files.html  |   60 +
 .../llfifo_v5_0/doc/html/api/functions.html   |  116 +
 .../doc/html/api/functions_vars.html          |  116 +
 .../llfifo_v5_0/doc/html/api/globals.html     |  246 +
 .../doc/html/api/globals_defs.html            |  234 +
 .../doc/html/api/globals_func.html            |   68 +
 .../doc/html/api/globals_type.html            |   62 +
 .../doc/html/api/group__llfifo__v5__0.html    | 1623 +++++
 .../orig/llfifo_v5_0/doc/html/api/index.html  |  141 +
 .../orig/llfifo_v5_0/doc/html/api/jquery.js   |   68 +
 .../llfifo_v5_0/doc/html/api/modules.html     |   58 +
 .../doc/html/api/struct_x_ll_fifo.html        |  165 +
 .../api/struct_x_strm___rx_fifo_streamer.html |  158 +
 .../api/struct_x_strm___tx_fifo_streamer.html |  144 +
 .../orig/llfifo_v5_0/doc/html/api/tab_a.png   |  Bin 0 -> 142 bytes
 .../orig/llfifo_v5_0/doc/html/api/tab_b.png   |  Bin 0 -> 169 bytes
 .../orig/llfifo_v5_0/doc/html/api/tab_h.png   |  Bin 0 -> 177 bytes
 .../orig/llfifo_v5_0/doc/html/api/tab_s.png   |  Bin 0 -> 184 bytes
 .../orig/llfifo_v5_0/doc/html/api/tabs.css    |   60 +
 .../llfifo_v5_0/doc/html/api/xllfifo_8c.html  |   67 +
 .../llfifo_v5_0/doc/html/api/xllfifo_8h.html  |  117 +
 .../doc/html/api/xllfifo__hw_8h.html          |   74 +
 .../llfifo_v5_0/doc/html/api/xlogo_bg.gif     |  Bin 0 -> 3154 bytes
 .../orig/llfifo_v5_0/examples/index.html      |   18 +
 .../examples/xllfifo_interrupt_example.c      |  619 ++
 .../examples/xllfifo_polling_example.c        |  361 ++
 .../xilinx/orig/llfifo_v5_0/src/Makefile      |   27 +
 .../xilinx/orig/llfifo_v5_0/src/xllfifo.c     |  498 ++
 .../xilinx/orig/llfifo_v5_0/src/xllfifo.h     |  715 +++
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 .../xilinx/orig/llfifo_v5_0/src/xstreamer.c   |  516 ++
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 thirdparty/xilinx/src/xil_io.c                |  342 ++
 375 files changed, 79906 insertions(+), 1896 deletions(-)
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diff --git a/.gitignore b/.gitignore
index 616224223..c6ea066bb 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,5 +7,6 @@ node
 pipe
 test
 signal
+fpga
 
 thirdparty/
diff --git a/config-fpga.h b/config-fpga.h
new file mode 100644
index 000000000..5644204c9
--- /dev/null
+++ b/config-fpga.h
@@ -0,0 +1,111 @@
+/** Hardcoded configuration for VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _CONFIG_FPGA_H_
+#define _CONFIG_FPGA_H_
+
+#define AFFINITY		(1 << 3)
+#define PRIORITY		90
+
+#define RTDS_DM_FIFO		1
+#define RTDS_DM_DMA_SIMPLE	2
+#define RTDS_DM_DMA_SG		3
+#define DATAMOVER		RTDS_DM_DMA_SIMPLE
+
+/** PCIe BAR number of VILLASfpga registers */
+#define PCI_BAR			0
+
+/** AXI Bus frequency for all components
+ * except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
+#define AXI_HZ			125000000 // 125 MHz
+
+#define virt_to_axi(virt, map) ((char *) ((char *) virt - map))
+#define virt_to_dma(virt, dma) ((char *) ((char *) virt - dma) + BASEADDR_HOST)
+#define dma_to_virt(addr, dma) ((char *) ((char *) addr - BASEADDR_HOST) + dma)
+
+#if 0
+/** Base addresses in AXI bus of FPGA */
+enum {
+	BASEADDR_BRAM		= 0x0000, /* 8 KB Block RAM for DMA SG descriptors */
+	BASEADDR_XSG		= 0x2000, /* Xilinx System Generator Model */
+	BASEADDR_DMA_SG		= 0x3000, /* Scatter Gather DMA controller registers */
+	BASEADDR_TIMER		= 0x4000, /* Timer Counter registers */
+	BASEADDR_SWITCH		= 0x5000, /* AXI Stream switch registers */
+	BASEADDR_FIFO_MM	= 0x6000, /* Memory-mapped to AXI Stream FIFO */
+	BASEADDR_RESET		= 0x7000, /* Internal Reset register */
+	BASEADDR_RTDS		= 0x8000, /* RTDS to AXI Stream bridge */
+	BASEADDR_HLS		= 0x9000, /* High-level Synthesis model registers */
+	BASEADDR_DMA_SIMPLE	= 0xA000, /* Simple DMA controller registers */
+	BASEADDR_INTC		= 0xB000, /* PCIe MSI Interrupt controller registers */
+	BASEADDR_FIFO_MM_AXI4	= 0xC000, /* AXI4 (full) interface of AXI Stream FIFO */
+	BASEADDR_HOST		= 0x80000000 /* Start of host memory (0x0 of IOMMU) */
+};
+
+/** MSI vector table for VILLASfpga components */
+enum {
+	MSI_TMRCTR0		= 0, /* Sensivity: rising edge, synchronous: axi_clk */
+	MSI_TMRCTR1		= 1, /* Sensivity: rising edge, synchronous: axi_clk */
+	MSI_FIFO_MM		= 2, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_DMA_MM2S		= 3, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_DMA_S2MM		= 4, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_RTDS_TS		= 5, /* Sensivity: rising edge, synchronous: rtds_clk100m (New timestep started) */
+	MSI_RTDS_OVF		= 6, /* Sensivity: rising edge, synchronous: rtds_clk100m (UserTxInProgress overlapped with UserTStepPulse)*/
+	MSI_RTDS_CASE		= 7  /* Sensivity: rising edge, synchronous: rtds_clk100m (New RSCAD case started) */
+};
+
+/** Mapping of VILLASfpga components to AXI Stream interconnect ports */
+enum {
+	AXIS_SWITCH_RTDS	= 0,
+	AXIS_SWITCH_DMA_SG	= 1,
+	AXIS_SWITCH_FIFO_MM	= 2,
+	AXIS_SWITCH_FIFO0	= 3,
+	AXIS_SWITCH_XSG		= 4,
+	AXIS_SWITCH_HLS		= 5,
+	AXIS_SWITCH_FIFO1	= 6,
+	AXIS_SWITCH_DMA_SIMPLE	= 7,
+	AXI_SWITCH_NUM		= 8 /* Number of master and slave interfaces */
+};
+#else
+  #define HAS_DMA_SIMPLE	1
+  #define HAS_SWITCH		1
+  #define HAS_XSG		1
+
+/** Base addresses in AXI bus of FPGA */
+enum {
+	BASEADDR_SWITCH		= 0x0000, /* AXI Stream switch registers */
+	BASEADDR_DMA_SIMPLE	= 0x1000, /* Simple DMA controller registers */
+	BASEADDR_RESET		= 0x2000, /* Internal Reset register */
+	BASEADDR_RTDS		= 0x3000, /* RTDS to AXI Stream bridge */
+	BASEADDR_XSG		= 0x4000, /* Xilinx System Generator Model */
+	BASEADDR_INTC		= 0x5000, /* PCIe MSI Interrupt controller registers */
+	BASEADDR_PCIE		= 0x10000000, /* PCIe config space */
+	BASEADDR_HOST		= 0x80000000 /* Start of host memory (0x0 of IOMMU) */
+};
+
+/** MSI vector table for VILLASfpga components */
+enum {
+	MSI_DMA_MM2S		= 0, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_DMA_S2MM		= 1, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_RTDS_TS		= 2, /* Sensivity: rising edge, synchronous: rtds_clk100m (New timestep started) */
+	MSI_RTDS_OVF		= 3, /* Sensivity: rising edge, synchronous: rtds_clk100m (UserTxInProgress overlapped with UserTStepPulse)*/
+	MSI_RTDS_CASE		= 4  /* Sensivity: rising edge, synchronous: rtds_clk100m (New RSCAD case started) */
+};
+
+/** Mapping of VILLASfpga components to AXI Stream interconnect ports */
+enum {
+	AXIS_SWITCH_RTDS	= 0,
+	AXIS_SWITCH_XSG		= 1,
+	AXIS_SWITCH_DMA_SIMPLE	= 2,
+	AXI_SWITCH_NUM		= 3 /* Number of master and slave interfaces */
+};
+#endif
+
+#define PCI_VID_XILINX		0x10ee
+#define PCI_PID_VFPGA		0x7022
+
+#endif /* _CONFIG_FPGA_H_ */
\ No newline at end of file
diff --git a/config.h b/config.h
index 523adbcad..979a4d782 100644
--- a/config.h
+++ b/config.h
@@ -39,7 +39,7 @@
 
 /* Required kernel version */
 #define KERNEL_VERSION_MAJ	3
-#define KERNEL_VERSION_MIN	4
+#define KERNEL_VERSION_MIN	6
 	
 /** Coefficients for simple FIR-LowPass:
  *   F_s = 1kHz, F_pass = 100 Hz, F_block = 300
diff --git a/include/fpga-bench.h b/include/fpga-bench.h
new file mode 100644
index 000000000..a6a243a41
--- /dev/null
+++ b/include/fpga-bench.h
@@ -0,0 +1,21 @@
+/** Benchmarks for VILLASfpga
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _BENCH_H_
+#define _BENCH_H_
+
+#include "nodes/vfpga.h"
+
+int bench_memcpy(struct vfpga *f);
+
+int bench_memcpy(struct vfpga *f);
+
+int bench_dm(struct vfpga *f);
+
+#endif /* _BENCH_H_ */
\ No newline at end of file
diff --git a/include/fpga-tests.h b/include/fpga-tests.h
new file mode 100644
index 000000000..c79eadc62
--- /dev/null
+++ b/include/fpga-tests.h
@@ -0,0 +1,29 @@
+/** Test procedures for VILLASfpga
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#ifndef _TESTS_H_
+#define _TESTS_H_
+
+#include "nodes/vfpga.h"
+
+int test_intc(struct vfpga *f);
+
+int test_xsg(struct vfpga *f, const char *name);
+
+int test_fifo(struct vfpga *f);
+
+int test_dma(struct vfpga *f);
+
+int test_timer(struct vfpga *f);
+
+int test_rtds_rtt(struct vfpga *f);
+
+int test_rtds_cbuilder(struct vfpga *f);
+
+#endif /* _TESTS_H_ */
\ No newline at end of file
diff --git a/include/gtfpga.h b/include/gtfpga.h
deleted file mode 100644
index 68da628cc..000000000
--- a/include/gtfpga.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/** Node type: GTFPGA (Xilinx ML507)
- *
- * This file implements the gtfpga subtype for nodes.
- * It's based on the uio_pci_generic kernel module.
- * A detailed description of that module is available here:
- * http://www.hep.by/gnu/kernel/uio-howto/uio_pci_generic.html
- *
- * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
- * @copyright 2015-2016, Steffen Vogel
- *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
- *   Unauthorized copying of this file, via any medium is strictly prohibited. 
- */
-/**
- * @addtogroup gtfpga RTDS - PCIexpress Fiber interface node type
- * @ingroup node
- * @{
- *********************************************************************************/
-
-#ifndef _GTFPGA_H_
-#define _GTFPGA_H_
-
-#include <pci/pci.h>
-
-#include "node.h"
-
-#define GTFPGA_BAR	0	/**< The Base Address Register which is mmap()ed to the User Space */
-
-#define GTFPGA_MAX_TX	64	/**< The amount of values which is supported by the GTFPGA card */
-#define GTFPGA_MAX_RX	64	/**< The amount of values which is supported by the GTFPGA card */
-
-#define GTFPGA_VID	0x10ee	/**< The default vendor ID of the GTFPGA card */
-#define GTFPGA_DID	0x0007	/**< The default device ID of the GTFPGA card */
-
-struct gtfpga {
-	struct pci_filter filter;
-
-	int fd_irq;		/**< File descriptor for the timer. This is blocking when read(2) until a new IRQ / timer expiration. */
-
-	char *map_bar0;		/**< Memory-mapped address of BAR0 */
-	
-	enum {
-		GTFPGA_MODE_FIFO,
-		GTFPGA_MODE_DMA
-	} mode;
-
-	char *name;
-	double rate;
-
-	struct pci_dev *dev;
-};
-
-typedef void(*log_cb_t)(char *, ...);
-
-/** @see node_vtable::init */
-int gtfpga_init(int argc, char * argv[], config_setting_t *cfg);
-
-/** @see node_vtable::deinit */
-int gtfpga_deinit();
-
-/** @see node_vtable::parse */
-int gtfpga_parse(struct node *n, config_setting_t *cfg);
-
-/** @see node_vtable::print */
-char * gtfpga_print(struct node *n);
-
-/** @see node_vtable::open */
-int gtfpga_open(struct node *n);
-
-/** @see node_vtable::close */
-int gtfpga_close(struct node *n);
-
-/** @see node_vtable::read */
-int gtfpga_read(struct node *n, struct pool *pool, int cnt);
-
-/** @see node_vtable::write */
-int gtfpga_write(struct node *n, struct pool *pool, int cnt);
-
-#endif /** _GTFPGA_H_ @} */
diff --git a/include/villas/fpga/dma.h b/include/villas/fpga/dma.h
new file mode 100644
index 000000000..f60c27653
--- /dev/null
+++ b/include/villas/fpga/dma.h
@@ -0,0 +1,42 @@
+/** DMA related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' DMA driver (XAxiDma_*)
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _DMA_H_
+#define _DMA_H_
+ 
+#include <stdlib.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+#include <xilinx/xaxidma.h>
+
+#define XAXIDMA_SR_SGINCL_MASK	0x00000008
+
+enum dma_mode {
+	DMA_MODE_SIMPLE,
+	DMA_MODE_SG
+};
+
+struct dma_mem {
+	uint32_t base_virt;
+	uint32_t base_phys;
+	size_t len;
+};
+
+int dma_init(XAxiDma *xdma, char *baseaddr, enum dma_mode mode, struct dma_mem *bd, struct dma_mem *rx, size_t maxlen);
+
+ssize_t dma_write(XAxiDma *xdma, char *buf, size_t len, int irq);
+
+ssize_t dma_read(XAxiDma *xdma, char *buf, size_t len, int irq);
+
+ssize_t dma_ping_pong(XAxiDma *xdma, char *src, char *dst, size_t len, int s2mm_irq);
+
+#endif /* _DMA_H_ */
\ No newline at end of file
diff --git a/include/villas/fpga/fifo.h b/include/villas/fpga/fifo.h
new file mode 100644
index 000000000..13bbf3567
--- /dev/null
+++ b/include/villas/fpga/fifo.h
@@ -0,0 +1,26 @@
+/** FIFO related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _FIFO_H_
+#define _FIFO_H_
+
+#include <sys/types.h>
+
+#include <xilinx/xstatus.h>
+#include <xilinx/xllfifo.h>
+
+int fifo_init(XLlFifo *fifo, char *baseaddr, char *axi_baseaddr);
+
+ssize_t fifo_write(XLlFifo *fifo, char *buf, size_t len, int irq);
+
+ssize_t fifo_read(XLlFifo *fifo, char *buf, size_t len, int irq);
+
+#endif /* _FIFO_H_ */
\ No newline at end of file
diff --git a/include/villas/fpga/model.h b/include/villas/fpga/model.h
new file mode 100644
index 000000000..c11e4a066
--- /dev/null
+++ b/include/villas/fpga/model.h
@@ -0,0 +1,100 @@
+/** Interface to Xilinx System Generator Models via PCIe
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+ 
+#ifndef _MODEL_H_
+#define _MODEL_H_
+
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <villas/list.h>
+
+#include "xsg.h"
+
+enum model_type {
+	MODEL_TYPE_HLS,
+	MODEL_TYPE_XSG
+};
+
+struct model {
+	char *name;			/**< Name / Identifier of model */
+	void *baseaddr;			/**< Base of register map. */
+
+	enum model_type type;		/**< Model type. */
+
+	struct list parameters;		/**< List of model parameters. */
+
+	union {
+		struct xsg_model xsg;	/**< XSG specific model data */
+		//struct hls_model hls;	/**< HLS specific model data */
+	};
+};
+
+enum model_param_type {
+	MODEL_PARAM_TYPE_UFIX,
+	MODEL_PARAM_TYPE_FIX,
+	MODEL_PARAM_TYPE_FLOAT,
+	MODEL_PARAM_TYPE_BOOLEAN
+};
+
+enum model_param_direction {
+	MODEL_PARAM_IN,
+	MODEL_PARAM_OUT,
+	MODEL_PARAM_INOUT
+};
+
+union model_param_value {
+	uint32_t ufix;
+	int32_t  fix;
+	float    flt;
+	bool     bol;
+};
+
+struct model_param {
+	char *name;				/**< Name of the parameter */
+
+	enum model_param_direction direction;	/**< Read / Write / Read-write? */
+	enum model_param_type type;		/**< Data type. Integers are represented by MODEL_GW_TYPE_(U)FIX with model_gw::binpt == 0 */
+
+	int binpt;				/**< Binary point for type == MODEL_GW_TYPE_(U)FIX */
+	int offset;				/**< Register offset to model::baseaddress */
+
+	union model_param_value default_value;
+
+	struct model *model;			/**< A pointer to the model structure to which this parameters belongs to. */
+};
+
+int model_init(struct model *m, const char *xml);
+
+void model_destroy(struct model *m);
+
+void model_dump(struct model *m);
+
+void model_param_destroy(struct model_param *r);
+
+void model_param_add(struct model *m, const char *name, enum model_param_direction dir, enum model_param_type type);
+
+char * xsg_get_info(struct xsg_model *x, const char *key);
+
+/** Read a model parameter.
+ *
+ * Note: the data type of the register is taken into account.
+ * All datatypes are converted to double.
+ */
+int model_param_read(struct model_param *p, double *v);
+
+/** Update a model parameter.
+ *
+ * Note: the data type of the register is taken into account.
+ * The double argument will be converted to the respective data type of the
+ * GatewayIn/Out block.
+ */
+int model_param_write(struct model_param *p, double v);
+
+#endif /* _MODEL_H_ */
\ No newline at end of file
diff --git a/include/villas/fpga/rtds_axis.h b/include/villas/fpga/rtds_axis.h
new file mode 100644
index 000000000..ea2fea4d1
--- /dev/null
+++ b/include/villas/fpga/rtds_axis.h
@@ -0,0 +1,43 @@
+/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _RTDS_AXIS_H_
+#define _RTDS_AXIS_H_
+
+#define RTDS_HZ				100000000 // 100 MHz
+
+#define RTDS_AXIS_MAX_TX		64	/**< The amount of values which is supported by the vfpga card */
+#define RTDS_AXIS_MAX_RX		64	/**< The amount of values which is supported by the vfpga card */
+
+/* Register offsets */
+#define RTDS_AXIS_SR_OFFSET		0x00	/**< Status Register (read-only). See RTDS_AXIS_SR_* constant. */
+#define RTDS_AXIS_CR_OFFSET		0x04	/**< Control Register (read/write) */
+#define RTDS_AXIS_TSCNT_LOW_OFFSET	0x08	/**< Lower 32 bits of timestep counter (read-only). */
+#define RTDS_AXIS_TSCNT_HIGH_OFFSET	0x0C	/**< Higher 32 bits of timestep counter (read-only). */
+#define RTDS_AXIS_TS_PERIOD_OFFSET	0x10	/**< Period in clock cycles of previous timestep (read-only). */
+#define RTDS_AXIS_COALESC_OFFSET	0x14	/**< IRQ Coalescing register (read/write). */
+#define RTDS_AXIS_VERSION_OFFSET	0x18	/**< 16 bit version field passed back to the rack for version reporting (visible from “status� command, read/write). */
+#define RTDS_AXIS_MRATE_RTDS2AXIS	0x1C	/**< */
+#define RTDS_AXIS_MRATE_AXIS2RTDS	0x20	/**< */
+
+/* Status register bits */
+#define RTDS_AXIS_SR_CARDDETECTED	(1 << 0)/**< ‘1’ when RTDS software has detected and configured card. */
+#define RTDS_AXIS_SR_LINKUP		(1 << 1)/**< ‘1’ when RTDS communication link has been negotiated. */
+#define RTDS_AXIS_SR_TX_FULL		(1 << 2)/**< Tx buffer is full, writes that happen when UserTxFull=’1’ will be dropped (Throttling / buffering is performed by hardware). */
+#define RTDS_AXIS_SR_TX_INPROGRESS	(1 << 3)/**< Indicates when data is being put on link. */
+#define RTDS_AXIS_SR_CASE_RUNNING	(1 << 4)/**< There is currently a simulation running. */
+
+/* Control register bits */
+#define RTDS_AXIS_CR_DISABLE_LINK	0	/**< Disable SFP TX when set */
+
+void rtds_axis_dump(char *baseaddr);
+
+double rtds_axis_dt(char *baseaddr);
+
+#endif /* _RTDS_AXIS_H_ */
\ No newline at end of file
diff --git a/include/villas/fpga/switch.h b/include/villas/fpga/switch.h
new file mode 100644
index 000000000..59373dbaf
--- /dev/null
+++ b/include/villas/fpga/switch.h
@@ -0,0 +1,21 @@
+/** AXI Stream interconnect related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _SWITCH_H_
+#define _SWITCH_H_
+
+#include <xilinx/xaxis_switch.h>
+
+int switch_init(XAxis_Switch *sw, char *baseaddr, int micnt, int sicnt);
+
+int switch_connect(XAxis_Switch *sw, int mi, int si);
+
+#endif /* _SWITCH_H_ */
\ No newline at end of file
diff --git a/include/villas/fpga/xsg.h b/include/villas/fpga/xsg.h
new file mode 100644
index 000000000..0b5f8a31a
--- /dev/null
+++ b/include/villas/fpga/xsg.h
@@ -0,0 +1,54 @@
+/** Interface to Xilinx System Generator Models via VILLASfpga
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#ifndef _XSG_H_
+#define _XSG_H_
+
+#define XSG_MAGIC		0xDEADBABE
+
+/* Forward declaration */
+struct model;
+
+enum xsg_block_type {
+	XSG_BLOCK_GATEWAY_IN	= 0x1000,
+	XSG_BLOCK_GATEWAY_OUT	= 0x1001,
+	XSG_BLOCK_INFO		= 0x2000
+};
+
+struct xsg_model {
+	int version;
+
+	char *map;
+	size_t maplen;
+
+	struct list infos;
+};
+
+struct xsg_info {
+	char *field;
+	char *value;
+};
+
+int xsg_init_from_map(struct model *m);
+
+int xsg_init_from_xml(struct model *m, const char *xml);
+
+void xsg_destroy(struct xsg_model *x);
+
+void xsg_dump(struct xsg_model *x);
+
+void xsg_info_destroy(struct xsg_info *i);
+
+/** Read the XSG model information from ROM */
+int xsg_map_read(void *offset, void *dst, size_t len);
+
+/** Parse binary model information from ROM */
+int xsg_map_parse(uint32_t *map, size_t len, struct list *parameters, struct list *infos);
+
+#endif /* _XSG_H_ */
\ No newline at end of file
diff --git a/include/villas/kernel/pci.h b/include/villas/kernel/pci.h
new file mode 100644
index 000000000..1d6820991
--- /dev/null
+++ b/include/villas/kernel/pci.h
@@ -0,0 +1,21 @@
+/** Linux PCI helpers
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _PCI_H_
+#define _PCI_H_
+
+#include <pci/pci.h>
+
+struct pci_dev * pci_find_device(struct pci_access *pacc, struct pci_filter *f);
+
+int pci_attach_driver(struct pci_dev *d, const char *driver);
+
+int pci_get_iommu_group(struct pci_dev *pdev);
+
+#endif /* _PCI_H_ */
\ No newline at end of file
diff --git a/include/villas/kernel/vfio.h b/include/villas/kernel/vfio.h
new file mode 100644
index 000000000..c116d523e
--- /dev/null
+++ b/include/villas/kernel/vfio.h
@@ -0,0 +1,104 @@
+/** Virtual Function IO wrapper around kernel API
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#ifndef _VFIO_H_
+#define _VFIO_H_
+
+#include <stdbool.h>
+#include <pci/pci.h>
+
+#include <linux/vfio.h>
+#include <linux/pci_regs.h>
+
+#include <villas/list.h>
+
+#define VFIO_DEV(x)	"/dev/vfio/" x
+
+struct vfio_group {
+	int fd;						/**< VFIO group file descriptor */
+	int index;					/**< Index of the IOMMU group as listed under /sys/kernel/iommu_groups/ */
+
+	struct vfio_group_status status;		/**< Status of group */
+
+	struct list devices;
+
+	struct vfio_container *container;		/**< The VFIO container to which this group is belonging */
+};
+
+struct vfio_dev {
+	char *name;				/**< Name of the device as listed under /sys/kernel/iommu_groups/[vfio_group::index]/devices/ */
+	int fd;					/**< VFIO device file descriptor */
+
+	struct vfio_device_info info;
+	struct vfio_irq_info *irqs;
+	struct vfio_region_info *regions;
+	
+	void **mappings;
+	
+	int *msi_efds;				/**< Array of assigned eventfs for MSI handling */
+	int *msi_irqs;				/**< Linux assigned IRQ number for MSI (see /proc/interrupts) */
+
+	struct pci_dev *pdev;			/**< libpci handle of the device */
+	struct vfio_group *group;		/**< The VFIO group this device belongs to */
+};
+
+struct vfio_container {
+	int fd;
+	int version;
+	int extensions;
+
+	struct list groups;
+};
+
+/** Initialize a new VFIO container. */
+int vfio_init(struct vfio_container *c);
+
+/** Initialize a VFIO group and attach it to an existing VFIO container. */
+int vfio_group_attach(struct vfio_group *g, struct vfio_container *c, int index);
+
+/** Initialize a VFIO device, lookup the VFIO group it belongs to, create the group if not already existing. */
+int vfio_dev_attach(struct vfio_dev *d, struct vfio_container *c, const char *name, int index);
+
+/** Initialie a VFIO-PCI device (uses vfio_dev_attach() internally) */
+int vfio_pci_attach(struct vfio_dev *d, struct vfio_container *c, struct pci_dev *pdev);
+
+/** Hot resets a VFIO-PCI device */
+int vfio_pci_reset(struct vfio_dev *d);
+
+/** Create a new eventfd and binds it to the MSI irqs of the device */
+int vfio_pci_msi_fd(struct vfio_dev *d, uint32_t mask);
+
+/** Enable memory accesses and bus mastering for PCI device */
+int vfio_pci_enable(struct vfio_dev *d);
+
+/** Reset a VFIO device */
+int vfio_dev_reset(struct vfio_dev *d);
+
+/** Release memory and close container */
+int vfio_destroy(struct vfio_container *c);
+
+/** Release memory of group */
+void vfio_group_destroy(struct vfio_group *g);
+
+/** Release memory of device */
+void vfio_dev_destroy(struct vfio_dev *g);
+
+/** Print a dump of all attached groups and their devices including regions and IRQs */
+void vfio_dump(struct vfio_container *c);
+
+/** Map a device memory region to the application address space (e.g. PCI BARs) */
+void * vfio_map_region(struct vfio_dev *d, int idx);
+
+/** Allocate a virtual memory region and map it for DMA access from the devices */
+void * vfio_map_dma(struct vfio_container *c, size_t size, size_t pgsize, uint64_t phyaddr);
+
+/** munmap() a region which has been mapped by vfio_map_region() */
+int vfio_unmap_region(struct vfio_dev *d, int idx);
+
+#endif /* _VFIO_H_ */
diff --git a/include/villas/nodes/vfpga.h b/include/villas/nodes/vfpga.h
new file mode 100644
index 000000000..343d6ae80
--- /dev/null
+++ b/include/villas/nodes/vfpga.h
@@ -0,0 +1,103 @@
+/** Node type: VILLASfpga
+ *
+ * This file implements the vfpga node-type.
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited. 
+ */
+/**
+ * @addtogroup vfpga VILLASnode
+ * @ingroup node
+ * @{
+ *********************************************************************************/
+
+#ifndef _VFPGA_H_
+#define _VFPGA_H_
+
+#include <xilinx/xtmrctr.h>
+#include <xilinx/xintc.h>
+#include <xilinx/xllfifo.h>
+#include <xilinx/xaxis_switch.h>
+#include <xilinx/xaxidma.h>
+
+#include "kernel/vfio.h"
+
+#include "fpga/switch.h"
+#include "fpga/model.h"
+#include "fpga/dma.h"
+#include "fpga/fifo.h"
+#include "fpga/rtds_axis.h"
+
+#include <pci/pci.h>
+
+#include "nodes/vfpga.h"
+#include "node.h"
+#include "list.h"
+
+#define VFPGA_BAR		0	/**< The Base Address Register which is mmap()ed to the User Space */
+
+struct vfpga {
+	struct pci_filter filter;
+
+	enum {
+		vfpga_MODE_FIFO,
+		vfpga_MODE_DMA
+	} mode;
+
+	int features;
+
+	struct list models;		/**< List of XSG and HLS model blocks on FPGA. */
+	struct vfio_dev vd;		/**< VFIO device handle. */
+
+	/* Xilinx IP blocks */
+	XTmrCtr tmr;
+	XLlFifo fifo;
+	XAxiDma dma_simple;
+	XAxiDma dma_sg;
+	XAxis_Switch sw;
+
+	char *map;			/**< PCI BAR0 mapping for register access */
+	char *dma;			/**< DMA mapped memory */
+	
+	size_t maplen;
+	size_t dmalen;
+};
+
+/** @see node_vtable::init */
+int vfpga_init(int argc, char * argv[], config_setting_t *cfg);
+
+/** @see node_vtable::deinit */
+int vfpga_deinit();
+
+/** @see node_vtable::parse */
+int vfpga_parse(struct node *n, config_setting_t *cfg);
+
+/** @see node_vtable::print */
+char * vfpga_print(struct node *n);
+
+/** @see node_vtable::open */
+int vfpga_open(struct node *n);
+
+/** @see node_vtable::close */
+int vfpga_close(struct node *n);
+
+/** @see node_vtable::read */
+int vfpga_read(struct node *n, struct sample *smps[], unsigned cnt);
+
+/** @see node_vtable::write */
+int vfpga_write(struct node *n, struct sample *smps[], unsigned cnt);
+
+//////////
+
+int vfpga_init2(struct vfpga *f, struct vfio_container *vc, struct pci_dev *pdev);
+
+int vfpga_deinit2(struct vfpga *f);
+
+int vfpga_reset(struct vfpga *f);
+
+void vfpga_dump(struct vfpga *f);
+
+#endif /** _VFPGA_H_ @} */
diff --git a/lib/fpga/dma.c b/lib/fpga/dma.c
new file mode 100644
index 000000000..a57479c88
--- /dev/null
+++ b/lib/fpga/dma.c
@@ -0,0 +1,409 @@
+/** DMA related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' DMA driver (XAxiDma_*)
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASfpga. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <villas/log.h>
+
+#include "utils.h"
+#include "fpga/dma.h"
+
+int dma_write_complete(XAxiDma *xdma, int irq)
+{
+	int processed, ret;
+
+	XAxiDma_Bd *bd;
+	XAxiDma_BdRing *ring = XAxiDma_GetTxRing(xdma);
+
+	/* Wait until the one BD TX transaction is done */
+	while ((processed = XAxiDma_BdRingFromHw(ring, XAXIDMA_ALL_BDS, &bd)) == 0) {
+		if (irq >= 0)
+			wait_irq(irq);
+	}
+
+	/* Free all processed TX BDs for future transmission */
+	ret = XAxiDma_BdRingFree(ring, processed, bd);
+	if (ret != XST_SUCCESS) {
+		info("Failed to free %d tx BDs %d", processed, ret);
+		return -1;
+	}
+	
+	return processed;
+}
+
+int dma_read_complete(XAxiDma *xdma, int irq)
+{
+	return 0;
+}
+
+ssize_t dma_write(XAxiDma *xdma, char *buf, size_t len, int irq)
+{
+	int ret;
+	
+	if (xdma->HasSg) {
+
+		XAxiDma_BdRing *ring;
+		XAxiDma_Bd *bd;
+
+		ring = XAxiDma_GetTxRing(xdma);
+
+		ret = XAxiDma_BdRingAlloc(ring, 1, &bd);
+		if (ret != XST_SUCCESS)
+			return -1;
+
+		/* Set up the BD using the information of the packet to transmit */
+		ret = XAxiDma_BdSetBufAddr(bd, (uintptr_t) buf);
+		if (ret != XST_SUCCESS) {
+			info("Tx set buffer addr %p on BD %p failed %d", buf, bd, ret);
+			return -1;
+		}
+
+		ret = XAxiDma_BdSetLength(bd, len, ring->MaxTransferLen);
+		if (ret != XST_SUCCESS) {
+			info("Tx set length %zu on BD %p failed %d", len, bd, ret);
+			return -1;
+		}
+
+		/* Set SOF / EOF / ID */
+		XAxiDma_BdSetCtrl(bd, XAXIDMA_BD_CTRL_TXEOF_MASK | XAXIDMA_BD_CTRL_TXSOF_MASK);
+		XAxiDma_BdSetId(bd, (uintptr_t) buf);
+
+		/* Give the BD to DMA to kick off the transmission. */
+		ret = XAxiDma_BdRingToHw(ring, 1, bd);
+		if (ret != XST_SUCCESS) {
+			info("to hw failed %d", ret);
+			return -1;
+		}
+		
+		dma_write_complete(xdma, irq);
+	}
+	else {
+		ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) buf, len, XAXIDMA_DMA_TO_DEVICE);
+		if (ret != XST_SUCCESS) {
+			warn("Failed DMA transfer");
+			return -1;
+		}
+
+		if (irq >= 0) {
+			wait_irq(irq);
+			XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+		}
+		else {
+			while (XAxiDma_Busy(xdma, XAXIDMA_DMA_TO_DEVICE))
+				__asm__("nop");
+		}
+	}
+
+	return len;
+}
+
+ssize_t dma_read(XAxiDma *xdma, char *buf, size_t len, int irq)
+{
+	int ret;
+	
+	if (xdma->HasSg) {
+		int freecnt, processed;
+
+		XAxiDma_BdRing *ring;
+		XAxiDma_Bd *bd;
+
+		ring = XAxiDma_GetRxRing(xdma);
+
+		processed = 0;
+		do {
+			/* Wait until the data has been received by the Rx channel */
+			while (XAxiDma_BdRingFromHw(ring, 1, &bd) == 0) {
+				if (irq >= 0)
+					wait_irq(irq);
+			}
+			
+			//char *bdbuf = XAxiDma_BdGetBufAddr(bd);
+			//size_t bdlen = XAxiDma_BdGetActualLength(bd, XAXIDMA_MAX_TRANSFER_LEN);
+
+			//memcpy(buf, bdbuf, bdlen);
+			//buf += bdlen;
+
+			processed++;
+		} while (XAxiDma_BdGetSts(bd) & XAXIDMA_BD_STS_RXEOF_MASK);
+
+		/* Free all processed RX BDs for future transmission */
+		ret = XAxiDma_BdRingFree(ring, processed, bd);
+		if (ret != XST_SUCCESS) {
+			info("Failed to free %d rx BDs %d", processed, ret);
+			return XST_FAILURE;
+		}
+
+		/* Return processed BDs to RX channel so we are ready to receive new
+		 * packets:
+		 *    - Allocate all free RX BDs
+		 *    - Pass the BDs to RX channel
+		 */
+		freecnt = XAxiDma_BdRingGetFreeCnt(ring);
+		ret = XAxiDma_BdRingAlloc(ring, freecnt, &bd);
+		if (ret != XST_SUCCESS) {
+			info("bd alloc failed");
+			return -1;
+		}
+
+		ret = XAxiDma_BdRingToHw(ring, freecnt, bd);
+		if (ret != XST_SUCCESS) {
+			info("Submit %d rx BDs failed %d", freecnt, ret);
+			return -1;
+		}
+	}
+	else {
+		ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) buf, len, XAXIDMA_DEVICE_TO_DMA);
+		if (ret != XST_SUCCESS)
+			warn("Failed DMA transfer");
+
+		if (irq >= 0) {
+			wait_irq(irq);
+			XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+		}
+		else {
+			while (XAxiDma_Busy(xdma, XAXIDMA_DEVICE_TO_DMA))
+				__asm__("nop");
+		}
+	}
+
+	return len;
+}
+
+ssize_t dma_ping_pong(XAxiDma *xdma, char *src, char *dst, size_t len, int s2mm_irq)
+{
+	int ret;
+
+	/* Prepare S2MM transfer */
+	ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) dst, len, XAXIDMA_DEVICE_TO_DMA);
+	if (ret != XST_SUCCESS)
+		warn("Failed DMA transfer");
+
+	/* Start MM2S transfer */
+	ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) src, len, XAXIDMA_DMA_TO_DEVICE);
+	if (ret != XST_SUCCESS) {
+		warn("Failed DMA transfer");
+		return -1;
+	}
+
+	/* Wait for completion */
+	if (s2mm_irq >= 0) {
+		wait_irq(s2mm_irq);
+		XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+	}
+	else {
+		while (XAxiDma_Busy(xdma, XAXIDMA_DEVICE_TO_DMA))
+			__asm__("nop");
+	}
+	
+	return XAxiDma_ReadReg(xdma->RegBase + XAXIDMA_RX_OFFSET, XAXIDMA_BUFFLEN_OFFSET);
+}
+
+static int dma_setup_bdring(XAxiDma_BdRing *ring, struct dma_mem *bdbuf)
+{
+	int delay = 0;
+	int coalesce = 1;
+	int ret, cnt;
+
+	XAxiDma_Bd clearbd;
+
+	/* Disable all RX interrupts before RxBD space setup */
+	XAxiDma_BdRingIntDisable(ring, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set delay and coalescing */
+	XAxiDma_BdRingSetCoalesce(ring, coalesce, delay);
+
+	/* Setup Rx BD space */
+	cnt = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, bdbuf->len);
+	ret = XAxiDma_BdRingCreate(ring, bdbuf->base_phys, bdbuf->base_virt, XAXIDMA_BD_MINIMUM_ALIGNMENT, cnt);
+
+	if (ret != XST_SUCCESS) {
+		info("RX create BD ring failed %d", ret);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup an all-zero BD as the template for the Rx channel.
+	 */
+	XAxiDma_BdClear(&clearbd);
+	ret = XAxiDma_BdRingClone(ring, &clearbd);
+	if (ret != XST_SUCCESS) {
+		info("RX clone BD failed %d", ret);
+		return XST_FAILURE;
+	}
+	
+	return XST_SUCCESS;
+}
+
+static int dma_setup_rx(XAxiDma *AxiDmaInstPtr, struct dma_mem *bdbuf, struct dma_mem *rxbuf, size_t maxlen)
+{
+	int ret;
+	
+	XAxiDma_BdRing *ring;
+	XAxiDma_Bd *bd, *curbd;
+
+	uint32_t freecnt;
+	uintptr_t rxptr;
+
+	ring = XAxiDma_GetRxRing(AxiDmaInstPtr);
+	ret = dma_setup_bdring(ring, bdbuf);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+	/* Attach buffers to RxBD ring so we are ready to receive packets */
+	freecnt = XAxiDma_BdRingGetFreeCnt(ring);
+	ret = XAxiDma_BdRingAlloc(ring, freecnt, &bd);
+	if (ret != XST_SUCCESS) {
+		info("RX alloc BD failed %d", ret);
+		return XST_FAILURE;
+	}
+
+	curbd = bd;
+	rxptr = rxbuf->base_phys;
+	for (int i = 0; i < freecnt; i++) {
+		ret = XAxiDma_BdSetBufAddr(curbd, rxptr);
+
+		if (ret != XST_SUCCESS) {
+			info("Set buffer addr %#lx on BD %p failed %d", rxptr, curbd, ret);
+			return XST_FAILURE;
+		}
+
+		ret = XAxiDma_BdSetLength(curbd, maxlen, ring->MaxTransferLen);
+		if (ret != XST_SUCCESS) {
+			info("Rx set length %zu on BD %p failed %d", maxlen, curbd, ret);
+			return XST_FAILURE;
+		}
+
+		/* Receive BDs do not need to set anything for the control
+		 * The hardware will set the SOF/EOF bits per stream ret */
+		XAxiDma_BdSetCtrl(curbd, 0);
+		XAxiDma_BdSetId(curbd, rxptr);
+
+		rxptr += maxlen;
+		curbd = (XAxiDma_Bd *) XAxiDma_BdRingNext(ring, curbd);
+	}
+
+	/* Clear the receive buffer, so we can verify data */
+	memset((void *) (uintptr_t) rxbuf->base_virt, 0, rxbuf->len);
+
+	ret = XAxiDma_BdRingToHw(ring, freecnt, bd);
+	if (ret != XST_SUCCESS) {
+		info("RX submit hw failed %d", ret);
+		return XST_FAILURE;
+	}
+
+	/* Start RX DMA channel */
+	ret = XAxiDma_BdRingStart(ring);
+	if (ret != XST_SUCCESS) {
+		info("RX start hw failed %d", ret);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+static int dma_setup_tx(XAxiDma *AxiDmaInstPtr, struct dma_mem *bd)
+{
+	int ret;
+
+	XAxiDma_BdRing *ring;
+
+	ring = XAxiDma_GetTxRing(AxiDmaInstPtr);
+	ret = dma_setup_bdring(ring, bd);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+	/* Start the TX channel */
+	ret = XAxiDma_BdRingStart(ring);
+	if (ret != XST_SUCCESS) {
+		info("failed start bdring txsetup %d", ret);
+		return XST_FAILURE;
+	}
+	
+
+	return XST_SUCCESS;
+}
+
+int dma_init(XAxiDma *xdma, char *baseaddr, enum dma_mode mode, struct dma_mem *bd, struct dma_mem *rx, size_t maxlen)
+{
+	int ret, sgincld;
+
+	XAxiDma_Config xdma_cfg = {
+		.BaseAddr = (uintptr_t) baseaddr,
+		.HasStsCntrlStrm = 0,
+		.HasMm2S = 1,
+		.HasMm2SDRE = 0,
+		.Mm2SDataWidth = 32,
+		.HasS2Mm = 1,
+		.HasS2MmDRE = 0, /* Data Realignment Engine */
+		.S2MmDataWidth = 32,
+		.HasSg = (mode == DMA_MODE_SG) ? 1 : 0,
+		.Mm2sNumChannels = 1,
+		.S2MmNumChannels = 1,
+		.Mm2SBurstSize = 64,
+		.S2MmBurstSize = 64,
+		.MicroDmaMode = 0,
+		.AddrWidth = 32
+	};
+	
+	ret = XAxiDma_CfgInitialize(xdma, &xdma_cfg);
+	if (ret != XST_SUCCESS) {
+		info("Initialization failed %d", ret);
+		return -1;
+	}
+
+	/* Check if correct DMA type */
+	sgincld = XAxiDma_In32((uintptr_t) baseaddr + XAXIDMA_TX_OFFSET+ XAXIDMA_SR_OFFSET) &
+		  XAxiDma_In32((uintptr_t) baseaddr + XAXIDMA_RX_OFFSET+ XAXIDMA_SR_OFFSET) &
+		  XAXIDMA_SR_SGINCL_MASK;
+
+	if ((mode == DMA_MODE_SIMPLE && sgincld == XAXIDMA_SR_SGINCL_MASK) ||
+	    (mode == DMA_MODE_SG     && sgincld != XAXIDMA_SR_SGINCL_MASK)) {
+		info("This is not a %s DMA controller", (mode == DMA_MODE_SG) ? "SG" : "Simple");
+		return -1;
+	}
+
+	/* Perform selftest */
+	ret = XAxiDma_Selftest(xdma);
+	if (ret != XST_SUCCESS) {
+		info("DMA selftest failed");
+		return -1;
+	}
+
+	/* Setup Buffer Descriptor rings for SG DMA */
+	if (mode == DMA_MODE_SG) {
+		/* Split BD memory equally between Rx and Tx rings */
+		struct dma_mem bd_rx = {
+			.base_virt = bd->base_virt,
+			.base_phys = bd->base_phys,
+			.len = bd->len / 2
+		};
+		struct dma_mem bd_tx = {
+			.base_virt = bd->base_virt + bd_rx.len,
+			.base_phys = bd->base_phys + bd_rx.len,
+			.len = bd->len - bd_rx.len
+		};
+
+		ret = dma_setup_rx(xdma, &bd_rx, rx, maxlen);
+		if (ret != XST_SUCCESS)
+			return -1;
+
+		ret = dma_setup_tx(xdma, &bd_tx);
+		if (ret != XST_SUCCESS)
+			return -1;
+	}
+
+	/* Enable completion interrupts for both channels */
+	XAxiDma_IntrEnable(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+	XAxiDma_IntrEnable(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+
+	return 0;
+}
\ No newline at end of file
diff --git a/lib/fpga/fifo.c b/lib/fpga/fifo.c
new file mode 100644
index 000000000..6a389d58e
--- /dev/null
+++ b/lib/fpga/fifo.c
@@ -0,0 +1,65 @@
+/** FIFO related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASfpga. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <unistd.h>
+
+#include <villas/utils.h>
+
+#include "utils.h"
+#include "fpga/fifo.h"
+
+int fifo_init(XLlFifo *fifo, char *baseaddr, char *axi_baseaddr)
+{
+	int ret;
+
+	XLlFifo_Config fifo_cfg = {
+		.BaseAddress = (uintptr_t) baseaddr,
+		.Axi4BaseAddress = (uintptr_t) axi_baseaddr,
+		.Datainterface = (axi_baseaddr == NULL) ? 0 : 1 /* use AXI4 for Data, AXI4-Lite for control */
+	};
+	
+	ret = XLlFifo_CfgInitialize(fifo, &fifo_cfg, (uintptr_t) baseaddr);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+	XLlFifo_IntEnable(fifo, XLLF_INT_RC_MASK);
+
+	return 0;
+}
+
+ssize_t fifo_write(XLlFifo *fifo, char *buf, size_t len, int irq)
+{
+	XLlFifo_Write(fifo, buf, len);
+	XLlFifo_TxSetLen(fifo, len);
+
+	return len;
+}
+
+ssize_t fifo_read(XLlFifo *fifo, char *buf, size_t len, int irq)
+{
+	size_t nextlen = 0;
+
+	while (XLlFifo_RxOccupancy(fifo) == 0) {
+		if (irq >= 0)
+			wait_irq(irq);
+		else
+			__asm__("nop");
+	}
+
+	/* Get length of next frame */
+	nextlen = MIN(XLlFifo_RxGetLen(fifo), len);
+
+	/* Read from FIFO */
+	XLlFifo_Read(fifo, buf, nextlen);
+	
+	XLlFifo_IntClear(fifo, XLLF_INT_RC_MASK);
+
+	return nextlen;
+}
diff --git a/lib/fpga/model.c b/lib/fpga/model.c
new file mode 100644
index 000000000..855b2ebbe
--- /dev/null
+++ b/lib/fpga/model.c
@@ -0,0 +1,136 @@
+/** Interface to Xilinx System Generator Models via PCIe
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdint.h>
+#include <time.h>
+#include <string.h>
+#include <math.h>
+
+#include <villas/utils.h>
+#include <villas/log.h>
+
+#include "fpga/model.h"
+#include "fpga/xsg.h"
+
+int model_init(struct model *m, const char *xml)
+{
+	/** @todo: parse XML model descriptions */
+
+	list_init(&m->parameters);
+
+	return 0;
+}
+
+void model_destroy(struct model *m)
+{
+	list_destroy(&m->parameters, (dtor_cb_t) model_param_destroy, true);
+}
+
+void model_dump(struct model *m)
+{
+	const char *param_type[] = { "UFix", "Fix", "Float", "Boolean" };
+	const char *model_types[] = { "HLS", "XSG" };
+	const char *parameter_dirs[] = { "In", "Out", "In/Out" };
+
+	info("Model: %s (baseaddr=%p, type=%s)", m->name, m->baseaddr, model_types[m->type]);
+	
+	{ INDENT
+		info("Parameters:");
+		list_foreach(struct model_param *p, &m->parameters) { INDENT
+			if (p->direction == MODEL_PARAM_IN)
+				info("%#x: %s (%s) = %.3f %s %u",
+					p->offset,
+					p->name,
+					parameter_dirs[p->direction],
+					p->default_value.flt,
+					param_type[p->type],
+					p->binpt
+				);
+			else if (p->direction == MODEL_PARAM_OUT)
+				info("%#x: %s (%s)",
+					p->offset,
+					p->name,
+					parameter_dirs[p->direction]
+				);
+		}
+
+		switch (m->type) {
+			case MODEL_TYPE_HLS:
+				//hls_dump(&m->hls);
+				break;
+			case MODEL_TYPE_XSG:
+				xsg_dump(&m->xsg);
+				break;
+		}
+	}
+}
+
+int model_param_read(struct model_param *p, double *v)
+{
+	union model_param_value *ptr = p->offset + p->model->baseaddr;
+
+	switch (p->type) {
+		case MODEL_PARAM_TYPE_UFIX:
+			*v = (double) ptr->ufix / (1 << p->binpt);
+			break;
+
+		case MODEL_PARAM_TYPE_FIX:
+			*v = (double) ptr->fix / (1 << p->binpt);
+			break;
+
+		case MODEL_PARAM_TYPE_FLOAT:
+			*v = (double) ptr->flt;
+			break;
+			
+		case MODEL_PARAM_TYPE_BOOLEAN:
+			*v = (double) ptr->ufix ? 1 : 0;
+	}
+
+	return 0;
+}
+
+int model_param_write(struct model_param *p, double v)
+{
+	union model_param_value *ptr = p->offset + p->model->baseaddr;
+
+	switch (p->type) {
+		case MODEL_PARAM_TYPE_UFIX:
+			ptr->ufix = (uint32_t) (v * (1 << p->binpt));
+			break;
+
+		case MODEL_PARAM_TYPE_FIX:
+			ptr->fix = (int32_t) (v * (1 << p->binpt));
+			break;
+
+		case MODEL_PARAM_TYPE_FLOAT:
+			ptr->flt = (float) v;
+			break;
+			
+		case MODEL_PARAM_TYPE_BOOLEAN:
+			ptr->bol = (bool) v;
+			break;
+	}
+
+	return 0;
+}
+
+void model_param_add(struct model *m, const char *name, enum model_param_direction dir, enum model_param_type type)
+{
+	struct model_param *p = alloc(sizeof(struct model_param));
+	
+	p->name = strdup(name);
+	p->type = type;
+	p->direction = dir;
+	
+	list_push(&m->parameters, p);
+}
+
+void model_param_destroy(struct model_param *p)
+{
+	free(p->name);
+}
diff --git a/lib/fpga/rtds_axis.c b/lib/fpga/rtds_axis.c
new file mode 100644
index 000000000..6aade1cc5
--- /dev/null
+++ b/lib/fpga/rtds_axis.c
@@ -0,0 +1,49 @@
+/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <stdint.h>
+
+#include "log.h"
+#include "utils.h"
+
+#include "fpga/rtds_axis.h"
+
+void rtds_axis_dump(char *baseaddr)
+{
+	/* Check RTDS_Axis registers */
+	uint32_t *rtds = (uint32_t *) baseaddr;
+
+	uint32_t sr = rtds[RTDS_AXIS_SR_OFFSET/4];
+	info("RTDS AXI Stream interface details");
+	{ INDENT
+		info("RTDS status:  %#08x", sr);
+		{ INDENT
+			info("Card detected:  %s", sr & RTDS_AXIS_SR_CARDDETECTED ? GRN("yes") : RED("no"));
+			info("Link up:        %s", sr & RTDS_AXIS_SR_LINKUP ? GRN("yes") : RED("no"));
+			info("TX queue full:  %s", sr & RTDS_AXIS_SR_TX_FULL ? RED("yes") : GRN("no"));
+			info("TX in progress: %s", sr & RTDS_AXIS_SR_TX_INPROGRESS ? YEL("yes") : "no");
+			info("Case running:   %s", sr & RTDS_AXIS_SR_CASE_RUNNING ? GRN("yes") : RED("no"));
+		}
+
+		info("RTDS control: %#08x", rtds[RTDS_AXIS_CR_OFFSET/4]);
+		info("RTDS IRQ coalesc: %u", rtds[RTDS_AXIS_COALESC_OFFSET/4]);
+		info("RTDS IRQ version: %#06x", rtds[RTDS_AXIS_VERSION_OFFSET/4]);
+		info("RTDS IRQ multi-rate RTDS2AXIS: %u", rtds[RTDS_AXIS_MRATE_RTDS2AXIS/4]);
+		info("RTDS IRQ multi-rate AXIS2RTDS: %u", rtds[RTDS_AXIS_MRATE_AXIS2RTDS/4]);
+
+		info("RTDS timestep counter: %lu", (uint64_t) rtds[RTDS_AXIS_TSCNT_LOW_OFFSET/4] | (uint64_t) rtds[RTDS_AXIS_TSCNT_HIGH_OFFSET/4] << 32);
+		info("RTDS timestep period:  %.3f uS", rtds_axis_dt(baseaddr) * 1e6);
+	}
+}
+
+double rtds_axis_dt(char *baseaddr)
+{
+	uint32_t *rtds = (uint32_t *) baseaddr;
+
+	return (double) rtds[RTDS_AXIS_TS_PERIOD_OFFSET/4] / RTDS_HZ;
+}
\ No newline at end of file
diff --git a/lib/fpga/switch.c b/lib/fpga/switch.c
new file mode 100644
index 000000000..4acdfec01
--- /dev/null
+++ b/lib/fpga/switch.c
@@ -0,0 +1,49 @@
+/** AXI Stream interconnect related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include "fpga/switch.h"
+
+int switch_init(XAxis_Switch *sw, char *baseaddr, int micnt, int sicnt)
+{
+	int ret;
+
+	/* Setup AXI-stream switch */
+	XAxis_Switch_Config sw_cfg = {
+		.BaseAddress = (uintptr_t) baseaddr,
+		.MaxNumMI = micnt,
+		.MaxNumSI = sicnt
+	};
+	
+	ret = XAxisScr_CfgInitialize(sw, &sw_cfg, (uintptr_t) baseaddr);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+#if 0
+	ret = XAxisScr_SelfTest(sw);
+	if (ret != TRUE)
+		return -1;
+#endif
+
+	/* Disable all masters */
+	XAxisScr_RegUpdateDisable(sw);
+	XAxisScr_MiPortDisableAll(sw);
+	XAxisScr_RegUpdateEnable(sw);
+
+	return 0;
+}
+
+int switch_connect(XAxis_Switch *sw, int mi, int si)
+{
+	XAxisScr_RegUpdateDisable(sw);
+	XAxisScr_MiPortEnable(sw, mi, si);
+	XAxisScr_RegUpdateEnable(sw);
+
+	return 0;
+}
diff --git a/lib/fpga/xsg.c b/lib/fpga/xsg.c
new file mode 100644
index 000000000..61cd62b66
--- /dev/null
+++ b/lib/fpga/xsg.c
@@ -0,0 +1,176 @@
+/** Interface to Xilinx System Generator Models via VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdint.h>
+#include <string.h>
+#include <math.h>
+#include <sys/types.h>
+
+#include <villas/list.h>
+#include <villas/utils.h>
+#include <villas/log.h>
+
+#include "fpga/model.h"
+#include "fpga/xsg.h"
+#include "utils.h"
+
+int xsg_init_from_map(struct model *m)
+{
+	int ret;
+	struct xsg_model *x = &m->xsg;
+
+	list_init(&x->infos);
+
+	x->map = alloc(1024);
+
+	x->maplen = xsg_map_read(m->baseaddr, x->map, 1024 / 4);
+	if (x->maplen < 0)
+		return -1;
+
+	debug(5, "XSG: memory map length = %#zx", x->maplen);
+
+	ret = xsg_map_parse((uint32_t *) x->map, x->maplen, &m->parameters, &x->infos);
+	if (ret)
+		return -2;
+
+	m->name = xsg_get_info(x, "Name");
+
+	return 0;
+}
+
+int xsg_init_from_xml(struct model *m, const char *xml)
+{
+	/** @todo: parse Simulink .mdl file here (XML based) */
+
+	return -1;
+}
+
+void xsg_destroy(struct xsg_model *x)
+{
+	list_destroy(&x->infos, (dtor_cb_t) xsg_info_destroy, true);
+
+	free(x->map);
+}
+
+char * xsg_get_info(struct xsg_model *x, const char *key)
+{
+	struct xsg_info *info = list_lookup(&x->infos, key);
+
+	return info ? info->value : NULL;
+}
+
+void xsg_info_destroy(struct xsg_info *i)
+{
+	free(i->field);
+	free(i->value);
+}
+
+void xsg_dump(struct xsg_model *x)
+{
+	info("XSG Infos:");
+	list_foreach(struct xsg_info *i, &x->infos) { INDENT
+		info("%s: %s", i->field, i->value);
+	}
+}
+
+static uint32_t xsg_map_checksum(uint32_t *map, size_t len)
+{
+	uint32_t chks = 0;
+	for (int i = 2; i < len-1; i++)
+		chks += map[i];
+
+	return chks; /* moduluo 2^32 because of overflow */
+}
+
+int xsg_map_parse(uint32_t *map, size_t len, struct list *parameters, struct list *infos)
+{
+#define copy_string(off) strndup((char *) (data + (off)), (length - (off)) * 4);
+
+	struct model_param *p;
+	struct xsg_info *info;
+	
+	int i;
+	
+	if (map[0] != XSG_MAGIC)
+		error("Invalid magic: %#x", map[0]);
+
+	for (i = 2; i < len-1;) {
+		uint16_t type   = map[i] & 0xFFFF;
+		uint16_t length = map[i] >> 16;
+		uint32_t *data  = &map[i+1];
+		
+		switch (type) {
+			case XSG_BLOCK_GATEWAY_IN:
+			case XSG_BLOCK_GATEWAY_OUT:
+				if (length < 4)
+					break; /* block is to small to describe a gateway */
+			
+				p = alloc(sizeof(*p));
+
+				p->name          =  copy_string(3);
+				p->default_value.flt =  *((float *) &data[1]);
+				p->offset        = data[2];
+				p->direction     = type & 0x1;
+				p->type          = (data[0] >> 0) & 0xFF;
+				p->binpt         = (data[0] >> 8) & 0xFF;
+
+				list_push(parameters, p);
+				break;
+
+			case XSG_BLOCK_INFO:
+				info = alloc(sizeof(*info));
+
+				info->field = copy_string(0);
+				info->value = copy_string((int) ceil((double) (strlen(info->field) + 1) / 4))
+				
+				list_push(infos, info);
+				break;
+
+			default:
+				warn("Unknown block type: %#06x", type);
+		}
+		
+		i += length + 1;
+	}
+	
+	if (xsg_map_checksum(map, len) != map[i])
+		error("XSG: Invalid checksum");
+
+	return 0;
+
+#undef copy_string
+}
+
+int xsg_map_read(void *baseaddr, void *dst, size_t len)
+{
+#define get_word(a) ({ *addr = a; *data; })
+
+	volatile uint32_t *addr = baseaddr + 0x00;
+	volatile uint32_t *data = baseaddr + 0x04;
+
+	uint32_t *map = dst;
+	uint32_t  maplen, magic;
+
+	/* Check start DW */
+	magic = get_word(0);
+	if (magic != XSG_MAGIC)
+		return -1;
+
+	maplen = get_word(1);
+	if (maplen < 3)
+		return -2;
+
+	/* Read Data */
+	int i;
+	for (i = 0; i < MIN(maplen, len); i++)
+		map[i] = get_word(i);
+
+	return i;
+
+#undef get_word
+}
\ No newline at end of file
diff --git a/lib/gtfpga.c b/lib/gtfpga.c
deleted file mode 100644
index a173bbab6..000000000
--- a/lib/gtfpga.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/** Node type: GTFPGA (Xilinx ML507)
- *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
- * @copyright 2015-2016, Steffen Vogel
- *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
- *   Unauthorized copying of this file, via any medium is strictly prohibited.
- *********************************************************************************/
-
-#include <stdio.h>
-#include <inttypes.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <sys/mman.h>
-
-#include "gtfpga.h"
-#include "config.h"
-#include "utils.h"
-#include "timing.h"
-#include "utils.h"
-#include "kernel.h"
-
-static struct pci_access *pacc;
-
-static void gtfpga_debug(char *msg, ...) {
-	va_list ap;
-
-	va_start(ap, msg);
-	log_vprint(LOG_LVL_DEBUG, msg, ap);
-	va_end(ap);
-}
-
-int gtfpga_init(int argc, char * argv[], config_setting_t *cfg)
-{
-	if (getuid() != 0)
-		error("The gtfpga node-type requires superuser privileges!");
-
-	pacc = pci_alloc();		/* Get the pci_access structure */
-	if (!pacc)
-		error("Failed to allocate PCI access structure");
-
-	pci_init(pacc);			/* Initialize the PCI library */
-
-	pacc->error = (log_cb_t) error;	/* Replace logging and debug functions */
-	pacc->warning = (log_cb_t) warn;
-	pacc->debug = gtfpga_debug;
-
-	pci_scan_bus(pacc);		/* We want to get the list of devices */
-
-	return 0;
-}
-
-int gtfpga_deinit()
-{
-	pci_cleanup(pacc);
-
-	return 0;
-}
-
-int gtfpga_parse(struct node *n, config_setting_t *cfg)
-{
-	struct gtfpga *g = n->_vd;
-
-	const char *slot, *id, *err;
-	config_setting_t *cfg_slot, *cfg_id;
-
-	pci_filter_init(NULL, &g->filter);
-
-	cfg_slot = config_setting_get_member(cfg, "slot");
-	if (cfg_slot) {
-		slot = config_setting_get_string(cfg_slot);
-		if (slot) {
-			err = pci_filter_parse_slot(&g->filter, (char*) slot);
-			if (err)
-				cerror(cfg_slot, "%s", err);
-		}
-		else
-			cerror(cfg_slot, "Invalid slot format");
-	}
-
-	cfg_id = config_setting_get_member(cfg, "id");
-	if (cfg_id) {
-		id = config_setting_get_string(cfg_id);
-		if (id) {
-			err = pci_filter_parse_id(&g->filter, (char*) id);
-			if (err)
-				cerror(cfg_id, "%s", err);
-		}
-		else
-			cerror(cfg_slot, "Invalid id format");
-	}
-
-	if (!config_setting_lookup_float(cfg, "rate", &g->rate))
-		g->rate = 0;
-
-	return 0;
-}
-
-char * gtfpga_print(struct node *n)
-{
-	struct gtfpga *g = n->_vd;
-
-	if (g->dev) {
-		return strf("rate=%.1f slot=%04"PRIx16":%02"PRIx8":%02"PRIx8".%"PRIx8
-			" id=%04"PRIx16":%04"PRIx16" class=%04"PRIx16" irq=%d (%s)", g->rate,
-			g->dev->domain, g->dev->bus, g->dev->dev, g->dev->func, g->dev->vendor_id, g->dev->device_id,
-			g->dev->device_class, g->dev->irq, g->name);
-	}
-	else {
-		return strf("rate=%.1f slot=%02"PRIx8":%02"PRIx8".%"PRIx8" id=%04"PRIx16":%04"PRIx16, g->rate,
-			g->filter.bus, g->filter.device, g->filter.func,
-			g->filter.vendor, g->filter.device);
-	}
-}
-
-static struct pci_dev * gtfpga_find_device(struct pci_filter *f)
-{
-	struct pci_dev *d;
-
-	/* Iterate over all devices */
-	for (d = pacc->devices; d; d = d->next) {
-		if (pci_filter_match(f, d))
-			return d;
-	}
-
-	return NULL;
-}
-
-int gtfpga_open(struct node *n)
-{
-	struct gtfpga *g = n->_vd;
-	struct pci_dev *dev;
-
-	dev = gtfpga_find_device(&g->filter);
-	if (!dev)
-		error("No GTFPGA card found");
-
-	g->dev = dev;
-
-	/* @todo VFIO */
-
-	return 0;
-}
-
-int gtfpga_close(struct node *n)
-{
-	struct gtfpga *g = n->_vd;
-
-	/* @todo VFIO */
-
-	return 0;
-}
-
-int gtfpga_read(struct node *n, struct pool *pool, int cnt)
-{
-	struct gtfpga *g = n->_vd;
-
-	/* Wait for IRQ */
-	uint64_t fired;
-	read(g->fd_irq, &fired, sizeof(fired));
-
-	/* Copy memory mapped data */
-	/** @todo */
-
-	return 0;
-}
-
-/** @todo implement */
-int gtfpga_write(struct node *n, struct pool *pool, int cnt)
-{
-	struct gtfpga *g = n->_vd;
-
-	/* Copy memory mapped data */
-	/** @todo */
-
-	return 0;
-}
-
-static struct node_type vt = {
-	.name		= "gtfpga",
-	.description	= "GTFPGA PCIe card (libpci)",
-	.vectorize	= 0,
-	.parse		= gtfpga_parse,
-	.print		= gtfpga_print,
-	.open		= gtfpga_open,
-	.close		= gtfpga_close,
-	.read		= gtfpga_read,
-	.write		= gtfpga_write,
-	.init		= gtfpga_init,
-	.deinit		= gtfpga_deinit
-};
-
-REGISTER_NODE_TYPE(&vt)
\ No newline at end of file
diff --git a/lib/kernel/pci.c b/lib/kernel/pci.c
new file mode 100644
index 000000000..aaabaa1e2
--- /dev/null
+++ b/lib/kernel/pci.c
@@ -0,0 +1,75 @@
+/** Linux PCI helpers
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <libgen.h> 
+#include <unistd.h>
+
+#include "log.h"
+
+#include "kernel/pci.h"
+#include "config.h"
+
+struct pci_dev * pci_find_device(struct pci_access *pacc, struct pci_filter *f)
+{
+	struct pci_dev *d;
+
+	/* Iterate over all devices */
+	for (d = pacc->devices; d; d = d->next) {
+		if (pci_filter_match(f, d))
+			return d;
+	}
+
+	return NULL;
+}
+
+int pci_attach_driver(struct pci_dev *d, const char *driver)
+{
+	FILE *f;
+	char fn[256];
+
+	/* Add new ID to driver */
+	snprintf(fn, sizeof(fn), "%s/bus/pci/drivers/%s/new_id", SYSFS_PATH, driver);
+	f = fopen(fn, "w");
+	if (!f)
+		serror("Failed to add PCI id to %s driver (%s)", driver, fn);
+
+	debug(5, "Adding ID to %s module: %04x %04x", driver, d->vendor_id, d->device_id);
+	fprintf(f, "%04x %04x", d->vendor_id, d->device_id);
+	fclose(f);
+
+	/* Bind to driver */
+	snprintf(fn, sizeof(fn), "%s/bus/pci/drivers/%s/bind", SYSFS_PATH, driver);
+	f = fopen(fn, "w");
+	if (!f)
+		serror("Failed to bind PCI device to %s driver (%s)", driver, fn);
+
+	debug(5, "Bind device to %s driver", driver);
+	fprintf(f, "%04x:%02x:%02x.%x\n", d->domain, d->bus, d->dev, d->func);
+	fclose(f);
+
+	return 0;
+}
+
+int pci_get_iommu_group(struct pci_dev *pdev)
+{
+	int ret;
+	char *group, link[1024], sysfs[1024];
+
+	snprintf(sysfs, sizeof(sysfs), "%s/bus/pci/devices/%04x:%02x:%02x.%x/iommu_group", SYSFS_PATH,
+		pdev->domain, pdev->bus, pdev->dev, pdev->func);
+
+	ret = readlink(sysfs, link, sizeof(link));
+	if (ret < 0)
+		return -1;
+
+	group = basename(link);
+
+	return atoi(group);
+}
diff --git a/lib/kernel/vfio.c b/lib/kernel/vfio.c
new file mode 100644
index 000000000..d96f0927c
--- /dev/null
+++ b/lib/kernel/vfio.c
@@ -0,0 +1,625 @@
+/** Virtual Function IO wrapper around kernel API
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#define _DEFAULT_SOURCE
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <sys/eventfd.h>
+
+
+#include "utils.h"
+#include "log.h"
+
+#include "config.h"
+
+#include "kernel/kernel.h"
+#include "kernel/vfio.h"
+#include "kernel/pci.h"
+
+static const char *vfio_pci_region_names[] = {
+	"PCI_BAR0",		// VFIO_PCI_BAR0_REGION_INDEX,
+	"PCI_BAR1",		// VFIO_PCI_BAR1_REGION_INDEX,
+	"PCI_BAR2",		// VFIO_PCI_BAR2_REGION_INDEX,
+	"PCI_BAR3",		// VFIO_PCI_BAR3_REGION_INDEX,
+	"PCI_BAR4",		// VFIO_PCI_BAR4_REGION_INDEX,
+	"PCI_BAR5",		// VFIO_PCI_BAR5_REGION_INDEX,
+	"PCI_ROM",		// VFIO_PCI_ROM_REGION_INDEX,
+	"PCI_CONFIG",		// VFIO_PCI_CONFIG_REGION_INDEX,
+	"PCI_VGA"		//  VFIO_PCI_INTX_IRQ_INDEX,
+};
+
+static const char *vfio_pci_irq_names[] = {
+	"PCI_INTX",		// VFIO_PCI_INTX_IRQ_INDEX,
+	"PCI_MSI", 		// VFIO_PCI_MSI_IRQ_INDEX,
+	"PCI_MSIX",		// VFIO_PCI_MSIX_IRQ_INDEX,
+	"PCI_ERR", 		// VFIO_PCI_ERR_IRQ_INDEX,
+	"PCI_REQ"		// VFIO_PCI_REQ_IRQ_INDEX,
+};
+
+/* Helpers */
+int vfio_get_iommu_name(int index, char *buf, size_t len)
+{
+	FILE *f;
+	char fn[256];
+
+	snprintf(fn, sizeof(fn), "/sys/kernel/iommu_groups/%d/name", index);
+
+	f = fopen(fn, "r");
+	if (!f)
+		return -1;
+
+	int ret = fgets(buf, len, f) == buf ? 0 : -1;
+	
+	/* Remove trailing newline */
+	char *c = strrchr(buf, '\n');
+	if (c)
+		*c = 0;
+
+	fclose(f);
+
+	return ret;
+}
+
+/* Destructors */
+int vfio_destroy(struct vfio_container *v)
+{
+	int ret;
+
+	/* Release memory and close fds */
+	list_destroy(&v->groups, (dtor_cb_t) vfio_group_destroy, true);
+
+	/* Close container */
+	ret = close(v->fd);
+	if (ret < 0)
+		return -1;
+
+	debug(5, "VFIO: closed container: fd=%d", v->fd);
+
+	return 0;
+}
+
+void vfio_group_destroy(struct vfio_group *g)
+{
+	int ret;
+
+	list_destroy(&g->devices, (dtor_cb_t) vfio_dev_destroy, false);
+	
+	ret = ioctl(g->fd, VFIO_GROUP_UNSET_CONTAINER);
+	if (ret)
+		return;
+
+	debug(5, "VFIO: released group from container: group=%u", g->index);
+
+	ret = close(g->fd);
+	if (ret)
+		return;
+
+	debug(5, "VFIO: closed group: group=%u, fd=%d", g->index, g->fd);
+}
+
+void vfio_dev_destroy(struct vfio_dev *d)
+{
+	int ret;
+
+	for (int i = 0; i < d->info.num_regions; i++)
+		vfio_unmap_region(d, i);
+
+	/* Check if this is really a vfio-pci device */
+	if (d->info.flags & VFIO_DEVICE_FLAGS_PCI) {
+		for (int i = 0; i < d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++)
+			close(d->msi_efds[i]);
+
+		free(d->msi_efds);
+	}
+
+	ret = close(d->fd);
+	if (ret)
+		return;
+
+	debug(5, "VFIO: closed device: name=%s, fd=%d", d->name, d->fd);
+	
+	free(d->mappings);
+	free(d->name);
+}
+
+/* Constructors */
+int vfio_init(struct vfio_container *v)
+{
+	int ret;
+
+	/* Initialize datastructures */
+	memset(v, 0, sizeof(*v));
+	
+	list_init(&v->groups);
+
+	/* Load VFIO kernel module */
+	if (kernel_module_load("vfio"))
+		error("Failed to load kernel module: %s", "vfio");
+
+	/* Open VFIO API */
+	v->fd = open(VFIO_DEV("vfio"), O_RDWR);
+	if (v->fd < 0)
+		error("Failed to open VFIO container");
+
+	/* Check VFIO API version */
+	v->version = ioctl(v->fd, VFIO_GET_API_VERSION);
+	if (v->version < 0 || v->version != VFIO_API_VERSION)
+		error("Failed to get VFIO version");
+
+	/* Check available VFIO extensions (IOMMU types) */
+	v->extensions = 0;
+	for (int i = 1; i < VFIO_DMA_CC_IOMMU; i++) {
+		ret = ioctl(v->fd, VFIO_CHECK_EXTENSION, i);
+		if (ret < 0)
+			error("Failed to get VFIO extensions");
+		else if (ret > 0)
+			v->extensions |= (1 << i);
+	}
+
+	return 0;
+}
+
+int vfio_group_attach(struct vfio_group *g, struct vfio_container *c, int index)
+{
+	int ret;
+	char buf[128];
+
+	g->index = index;
+	g->container = c;
+	
+	list_init(&g->devices);
+	
+	/* Open group fd */
+	snprintf(buf, sizeof(buf), VFIO_DEV("%u"), g->index);
+	g->fd = open(buf, O_RDWR);
+	if (g->fd < 0)
+		serror("Failed to open VFIO group: %u", g->index);
+
+	/* Claim group ownership */
+	ret = ioctl(g->fd, VFIO_GROUP_SET_CONTAINER, &c->fd);
+	if (ret < 0)
+		serror("Failed to attach VFIO group to container");
+	
+	/* Set IOMMU type */
+	ret = ioctl(c->fd, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);
+	if (ret < 0)
+		serror("Failed to set IOMMU type of container");
+
+	/* Check group viability and features */
+	g->status.argsz = sizeof(g->status);
+
+	ret = ioctl(g->fd, VFIO_GROUP_GET_STATUS, &g->status);
+	if (ret < 0)
+		serror("Failed to get VFIO group status");
+	
+	if (!(g->status.flags & VFIO_GROUP_FLAGS_VIABLE))
+		error("VFIO group is not available: bind all devices to the VFIO driver!");
+	
+	list_push(&c->groups, g);
+
+	return 0;
+}
+
+int vfio_pci_attach(struct vfio_dev *d, struct vfio_container *c, struct pci_dev *pdev)
+{
+	char name[32];
+	int ret;
+	
+	/* Load PCI bus driver for VFIO */
+	if (kernel_module_load("vfio_pci"))
+		error("Failed to load kernel driver: %s", "vfio_pci");
+	
+	/* Bind PCI card to vfio-pci driver*/
+	ret = pci_attach_driver(pdev, "vfio-pci");
+	if (ret)
+		error("Failed to attach device to driver");
+
+	/* Get IOMMU group of device */
+	int index = pci_get_iommu_group(pdev);
+	if (index < 0)
+		error("Failed to get IOMMU group of device");
+
+	/* VFIO device name consists of PCI BDF */
+	snprintf(name, sizeof(name), "%04x:%02x:%02x.%x", pdev->domain, pdev->bus, pdev->dev, pdev->func);
+
+	ret = vfio_dev_attach(d, c, name, index);
+	if (ret < 0)
+		return ret;
+	
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI)) {
+		vfio_dev_destroy(d);
+		return -1;
+	}
+
+	d->pdev = pdev;
+
+	/* Initialize MSI irqs */
+	d->msi_efds = alloc(sizeof(int) * d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count);
+	d->msi_irqs = alloc(sizeof(int) * d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count);
+	for (int i = 0; i < d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
+		d->msi_efds[i] = -1;
+		d->msi_irqs[i] = -1;
+	}
+
+	return 0;
+}
+
+int vfio_dev_attach(struct vfio_dev *d, struct vfio_container *c, const char *name, int index)
+{
+	int ret;
+	struct vfio_group *g = NULL;
+	
+	/* Check if group already exists */
+	list_foreach(struct vfio_group *h, &c->groups) {
+		if (h->index == index)
+			g = h;
+	}
+	
+	if (!g) {
+		g = alloc(sizeof(struct vfio_group));
+
+		/* Aquire group ownership */
+		ret = vfio_group_attach(g, c, index);
+		if (ret)
+			error("Failed to attach to IOMMU group: %u", index);
+		
+		info("Attached new group %u to VFIO container", g->index);
+	}
+
+	d->group = g;
+	d->name = strdup(name);
+
+	/* Open device fd */
+	d->fd = ioctl(g->fd, VFIO_GROUP_GET_DEVICE_FD, d->name);
+	if (d->fd < 0)
+		serror("Failed to open VFIO device: %s", d->name);
+
+	/* Get device info */
+	d->info.argsz = sizeof(d->info);
+
+	ret = ioctl(d->fd, VFIO_DEVICE_GET_INFO, &d->info);
+	if (ret < 0)
+		serror("Failed to get VFIO device info for: %s", d->name);
+
+	d->irqs     = alloc(d->info.num_irqs    * sizeof(struct vfio_irq_info));
+	d->regions  = alloc(d->info.num_regions * sizeof(struct vfio_region_info));
+	d->mappings = alloc(d->info.num_regions * sizeof(void *));
+
+	/* Get device regions */
+	for (int i = 0; i < d->info.num_regions && i < 8; i++) {
+		struct vfio_region_info *region = &d->regions[i];
+
+		region->argsz = sizeof(*region);
+		region->index = i;
+
+		ret = ioctl(d->fd, VFIO_DEVICE_GET_REGION_INFO, region);
+		if (ret < 0)
+			serror("Failed to get regions of VFIO device: %s", d->name);
+	}
+
+	/* Get device irqs */
+	for (int i = 0; i < d->info.num_irqs; i++) {
+		struct vfio_irq_info *irq = &d->irqs[i];
+
+		irq->argsz = sizeof(*irq);
+		irq->index = i;
+
+		ret = ioctl(d->fd, VFIO_DEVICE_GET_IRQ_INFO, irq);
+		if (ret < 0)
+			serror("Failed to get IRQs of VFIO device: %s", d->name);
+	}
+	
+	list_push(&d->group->devices, d);
+
+	return 0;
+}
+
+int vfio_pci_reset(struct vfio_dev *d)
+{
+	int ret;
+
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI))
+		return -1;
+
+	size_t reset_infolen = sizeof(struct vfio_pci_hot_reset_info) + sizeof(struct vfio_pci_dependent_device) * 64;
+	size_t resetlen = sizeof(struct vfio_pci_hot_reset) + sizeof(int32_t) * 1;
+
+	struct vfio_pci_hot_reset_info *reset_info = alloc(reset_infolen);
+	struct vfio_pci_hot_reset *reset = alloc(resetlen);
+
+	reset_info->argsz = reset_infolen;
+	reset->argsz = resetlen;
+
+	ret = ioctl(d->fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, reset_info);
+	if (ret)
+		return ret;
+
+	debug(5, "VFIO: dependent devices for hot-reset:");
+	for (int i = 0; i < reset_info->count; i++) { INDENT
+		struct vfio_pci_dependent_device *dd = &reset_info->devices[i];
+		debug(5, "%04x:%02x:%02x.%01x: iommu_group=%u", dd->segment, dd->bus, PCI_SLOT(dd->devfn), PCI_FUNC(dd->devfn), dd->group_id);
+
+		if (dd->group_id != d->group->index)
+			return -3;
+	}
+
+	reset->count = 1;
+	reset->group_fds[0] = d->group->fd;
+
+	ret = ioctl(d->fd, VFIO_DEVICE_PCI_HOT_RESET, reset);
+
+	free(reset_info);
+
+	return ret;
+}
+
+int vfio_pci_msi_findirqs(struct vfio_dev *d)
+{
+	FILE *f;
+	char *end, *col, *last, line[1024];
+	int ret, vector;
+	
+	f = fopen("/proc/interrupts", "r");
+	if (!f)
+		return -1;
+
+	/* Ignore header line */
+	fgets(line, sizeof(line), f);
+
+	while (fgets(line, sizeof(line), f)) {
+		col = strtok(line, " ");
+
+		/* IRQ number is in first column */
+		int irq = strtol(col, &end, 10);
+		if (col == end)
+			continue;
+
+		/* Find last column of line */
+		while ((col = strtok(NULL, " ")))
+			last = col;
+
+		char name[13];
+		ret = sscanf(last, "vfio-msi[%u](%12[0-9:])", &vector, name);
+		if (ret == 2) { /* match was successful */
+			if (strstr(d->name, name) == d->name) /* device matches */
+				d->msi_irqs[vector] = irq;
+		}
+	}
+	
+	fclose(f);
+
+	return 0;
+}
+
+int vfio_pci_msi_fd(struct vfio_dev *d, uint32_t mask)
+{
+	int efd, ret;
+	struct vfio_irq_info *msi_irqs = &d->irqs[VFIO_PCI_MSI_IRQ_INDEX];
+	struct vfio_irq_set *irq_set;
+	size_t irq_setlen;
+	
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI))
+		return -1;
+
+	/* Check if already assigned */
+	for (int i = 0; i < MIN(sizeof(mask) * 8, msi_irqs->count); i++) {
+		if ((mask & (1 << i)) && (d->msi_efds[i] >= 0))
+			return -1;
+	}
+
+	/* Create new eventfd */
+	efd = eventfd(0, 0);
+	if (efd < 0)
+		return -3;
+
+	/* Assign new efd */
+	for (int i = 0; i < MIN(sizeof(mask) * 8, msi_irqs->count); i++) {
+		if (mask & (1 << i))
+			d->msi_efds[i] = efd;
+	}
+
+	irq_setlen = sizeof(struct vfio_irq_set) + msi_irqs->count * (sizeof(d->msi_efds[0]));
+	irq_set = alloc(irq_setlen);
+
+	irq_set->argsz = irq_setlen;
+	irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
+	irq_set->index = VFIO_PCI_MSI_IRQ_INDEX;
+	irq_set->count = msi_irqs->count;
+	irq_set->start = 0;
+	
+	/* We need to disable the complete MSI index first before adding new ones */
+	if (msi_irqs->flags & VFIO_IRQ_INFO_NORESIZE) {
+		memset(&irq_set->data[0], 0xFF, msi_irqs->count * sizeof(d->msi_efds[0]));
+
+		ret = ioctl(d->fd, VFIO_DEVICE_SET_IRQS, irq_set);
+		if (ret)
+			return -4;
+	}
+
+	memcpy(&irq_set->data[0], d->msi_efds, msi_irqs->count * sizeof(d->msi_efds[0]));
+
+	ret = ioctl(d->fd, VFIO_DEVICE_SET_IRQS, irq_set);
+	if (ret)
+		return -4;
+
+	/* Find corresponding Linux IRQ numbers */
+	ret = vfio_pci_msi_findirqs(d);
+	if (ret)
+		return -5;
+
+	free(irq_set);
+
+	return efd;
+}
+
+int vfio_pci_enable(struct vfio_dev *d)
+{
+	int ret;
+	uint32_t reg;
+	off_t offset = ((off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40) + PCI_COMMAND;
+
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI))
+		return -1;
+
+	ret = pread(d->fd, &reg, sizeof(reg), offset);
+	if (ret != sizeof(reg))
+		return -1;
+
+	/* Enable memory access and PCI bus mastering which is required for DMA */
+	reg |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+
+	ret = pwrite(d->fd, &reg, sizeof(reg), offset);
+	if (ret != sizeof(reg))
+		return -1;
+
+	return 0;
+}
+
+int vfio_dev_reset(struct vfio_dev *d)
+{
+	if (d->info.flags & VFIO_DEVICE_FLAGS_RESET)
+		return ioctl(d->fd, VFIO_DEVICE_RESET);
+	else
+		return -1; /* not supported by this device */
+}
+
+void vfio_dump(struct vfio_container *v)
+{
+	info("VFIO Version: %u", v->version);
+	info("VFIO Extensions: %#x", v->extensions);
+
+	list_foreach(struct vfio_group *g, &v->groups) {
+		info("VFIO Group %u, viable=%u, container=%d", g->index,
+			(g->status.flags & VFIO_GROUP_FLAGS_VIABLE) > 0,
+			(g->status.flags & VFIO_GROUP_FLAGS_CONTAINER_SET) > 0
+		);
+
+		list_foreach(struct vfio_dev *d, &g->devices) { INDENT
+			info("Device %s: regions=%u, irqs=%u, flags=%#x", d->name,
+				d->info.num_regions,
+				d->info.num_irqs,
+				d->info.flags
+			);
+
+			for (int i = 0; i < d->info.num_regions && i < 8; i++) { INDENT
+				struct vfio_region_info *region = &d->regions[i];
+
+				if (region->size > 0)
+					info("Region %u %s: size=%#llx, offset=%#llx, flags=%u",
+						region->index, (d->info.flags & VFIO_DEVICE_FLAGS_PCI) ? vfio_pci_region_names[i] : "",
+						region->size,
+						region->offset,
+						region->flags
+					);
+			}
+			
+			for (int i = 0; i < d->info.num_irqs; i++) { INDENT
+				struct vfio_irq_info *irq = &d->irqs[i];
+
+				if (irq->count > 0)
+					info("IRQ %u %s: count=%u, flags=%u",
+						irq->index, (d->info.flags & VFIO_DEVICE_FLAGS_PCI ) ? vfio_pci_irq_names[i] : "",
+						irq->count,
+						irq->flags
+				);
+			}
+		}
+	}
+}
+
+void * vfio_map_region(struct vfio_dev *d, int idx)
+{
+	struct vfio_region_info *r = &d->regions[idx];
+
+	if (!(r->flags & VFIO_REGION_INFO_FLAG_MMAP))
+		return MAP_FAILED;
+
+	d->mappings[idx] = mmap(NULL, r->size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_32BIT, d->fd, r->offset);
+	
+	return d->mappings[idx];
+}
+
+void * vfio_map_dma(struct vfio_container *c, size_t size, size_t pgsize, uint64_t phyaddr)
+{
+	void *vaddr;
+	int ret, pgbits, flags;
+	size_t defpgsize;
+
+	defpgsize = sysconf(_SC_PAGESIZE);
+	if (!pgsize)
+		pgsize = defpgsize;
+
+	pgbits = 8 * sizeof(unsigned long long) - __builtin_clzll((unsigned long long) pgsize) - 1;
+
+	debug(3, "pgsize = %#zx", pgsize);
+	debug(3, "defpgsize = %#zx", defpgsize);
+
+	flags = MAP_PRIVATE | MAP_ANONYMOUS | MAP_32BIT;
+	if (pgsize != defpgsize) /* Map as Hugepages */
+		flags |= MAP_HUGETLB | (pgbits << MAP_HUGE_SHIFT);
+
+	vaddr = mmap(0, size, PROT_READ | PROT_WRITE, flags, 0, 0);
+	if (vaddr == MAP_FAILED)
+		return MAP_FAILED;
+
+	debug(3, "Allocated VM for DMA mapping at: %p", vaddr);
+	
+	struct vfio_iommu_type1_dma_map dma_map = {
+		.argsz = sizeof(struct vfio_iommu_type1_dma_map),
+		.vaddr = (uint64_t) vaddr,
+		.size = size,
+		.iova = phyaddr,
+		.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE
+	};
+
+	ret = ioctl(c->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
+	if (ret)
+		serror("Failed to create DMA mapping");
+
+	info("DMA map size=%#llx, iova=%#llx, vaddr=%#llx", dma_map.size, dma_map.iova, dma_map.vaddr);
+
+	return vaddr;
+}
+
+int vfio_unmap_region(struct vfio_dev *d, int idx)
+{
+	struct vfio_region_info *r = &d->regions[idx];
+	
+	if (!d->mappings[idx])
+		return -1; /* was not mapped */
+	
+	debug(3, "VFIO: unmap region %u from device", idx);
+	
+	return munmap(d->mappings[idx], r->size);
+}
+
+int vfio_unmap_dma(struct vfio_container *c)
+{
+	struct vfio_iommu_type1_dma_unmap dma_unmap = {
+		.argsz = sizeof(struct vfio_iommu_type1_dma_unmap),
+		.flags = 0,
+		.iova = 0, /* IO virtual address */
+		.size = 0  /* Size of mapping (bytes) */
+	};
+
+	debug(3, "VFIO: unmap DMA region from device");
+	
+	return ioctl(c->fd, VFIO_IOMMU_UNMAP_DMA, &dma_unmap);
+}
diff --git a/lib/nodes/vfpga.c b/lib/nodes/vfpga.c
new file mode 100644
index 000000000..0c78e1da0
--- /dev/null
+++ b/lib/nodes/vfpga.c
@@ -0,0 +1,353 @@
+/** Node type: VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/mman.h>
+
+#include "kernel/kernel.h"
+#include "kernel/pci.h"
+
+#include "nodes/vfpga.h"
+
+#include "config.h"
+#include "config-fpga.h"
+#include "utils.h"
+#include "timing.h"
+
+static struct pci_access *pacc;
+
+typedef void(*log_cb_t)(char *, ...);
+
+int vfpga_init2(struct vfpga *f, struct vfio_container *vc, struct pci_dev *pdev)
+{
+	int ret;
+
+	list_init(&f->models);
+	
+	f->features = 0;
+
+	if (pdev->vendor_id != PCI_VID_XILINX)
+		error("This is not a Xilinx FPGA board!");
+
+	/* Attach PCIe card to VFIO container */
+	ret = vfio_pci_attach(&f->vd, vc, pdev);
+	if (ret)
+		error("Failed to attach VFIO device");
+
+	/* Setup IRQs */
+	for (int i = 0; i < f->vd.irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
+		ret = vfio_pci_msi_fd(&f->vd, (1 << i));
+		if (ret < 0)
+			serror("Failed to create eventfd for IRQ: ret=%d", f->vd.msi_efds[i]);
+	}
+
+	/* Map PCIe BAR */
+	f->map = vfio_map_region(&f->vd, VFIO_PCI_BAR0_REGION_INDEX);
+	if (f->map == MAP_FAILED)
+		serror("Failed to mmap() BAR0");
+	
+	/* Map DMA accessible memory */
+	f->dma = vfio_map_dma(f->vd.group->container, 0x10000, 0x1000, 0x0);
+	if (f->dma == MAP_FAILED)
+		serror("Failed to mmap() DMA");
+
+	/* Enable memory access and PCI bus mastering for DMA */
+	ret = vfio_pci_enable(&f->vd);
+	if (ret)
+		serror("Failed to enable PCI device");
+	
+#if 1
+	/* Trigger internal reset of fpga card / PCIe endpoint */
+	ret = vfpga_reset(f);
+	if (ret)
+		serror("Failed to reset fpga card");
+#endif
+
+	/* Reset / detect PCI device */
+	ret = vfio_pci_reset(&f->vd);
+	if (ret)
+		serror("Failed to reset PCI device");
+
+	/* Initialize Interrupt controller */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IMR_OFFSET, 0);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IAR_OFFSET, 0xFFFFFFFF); /* Acknowlege all pending IRQs */
+	usleep(1000);
+
+	/* Setup Vectors */
+	for (int i = 0; i < 16; i++)
+		XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IVAR_OFFSET + i * sizeof(uint32_t), i);
+
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IMR_OFFSET, 0xFFFFFFFF); /* Use fast acknowlegement for all IRQs */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, 0x00000000);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_MER_OFFSET, XIN_INT_HARDWARE_ENABLE_MASK | XIN_INT_MASTER_ENABLE_MASK);
+
+#ifdef HAS_SWITCH
+	/* Initialize AXI4-Sream crossbar switch */
+	ret = switch_init(&f->sw, f->map + BASEADDR_SWITCH, AXI_SWITCH_NUM, AXI_SWITCH_NUM);
+	if (ret)
+		error("Failed to initialize switch");
+#endif
+
+#ifdef HAS_XSG
+	/* Initialize System Generator model */
+	struct model *m = alloc(sizeof(struct model));
+	m->baseaddr = f->map + BASEADDR_XSG;
+	m->type = MODEL_TYPE_XSG;
+
+	ret = model_init(m, NULL);
+	if (ret)
+		error("Failed to init model: %d", ret);
+
+	ret = xsg_init_from_map(m);
+	if (ret)
+		error("Failed to init XSG model: %d", ret);
+	
+	list_push(&f->models, m);
+#endif
+
+#ifdef HAS_FIFO_MM
+	/* Initialize AXI4-Stream Memory Mapped FIFO */
+	ret = fifo_init(&f->fifo, f->map + BASEADDR_FIFO_MM, f->map + BASEADDR_FIFO_MM_AXI4);
+	if (ret)
+		error("Failed to initialize FIFO");
+#endif
+
+#ifdef HAS_DMA_SG
+	/* Initialize Scatter Gather DMA controller */
+	struct dma_mem bd = {
+		.base_virt = (uintptr_t) f->map + BASEADDR_BRAM,
+		.base_phys = BASEADDR_BRAM,
+		.len = 0x2000
+	};
+	struct dma_mem rx = {
+		.base_virt = (uintptr_t) f->dma,
+		.base_phys = BASEADDR_HOST,
+		.len = 0x10000
+	};
+
+	ret = dma_init(&f->dma_sg, f->map + BASEADDR_DMA_SG, DMA_MODE_SG, &bd, &rx, sizeof(uint32_t) * 64);
+	if (ret)
+		return -1;
+#endif
+
+#ifdef HAS_DMA_SIMPLE
+	/* Initialize Simple DMA controller */
+	ret = dma_init(&f->dma_simple, f->map + BASEADDR_DMA_SIMPLE, DMA_MODE_SIMPLE, 0, 0, 0);
+	if (ret)
+		return -1;
+#endif
+
+#ifdef HAS_TIMER
+	/* Initialize timer */
+	XTmrCtr_Config tmr_cfg = {
+		.BaseAddress = (uintptr_t) f->map + BASEADDR_TIMER,
+		.SysClockFreqHz = AXI_HZ
+	};
+
+	XTmrCtr_CfgInitialize(&f->tmr, &tmr_cfg, (uintptr_t) f->map + BASEADDR_TIMER);
+	XTmrCtr_InitHw(&f->tmr);
+#endif
+
+	return 0;
+}
+
+int vfpga_deinit2(struct vfpga *f)
+{
+	list_destroy(&f->models, (dtor_cb_t) model_destroy, true);
+
+	return 0;
+}
+
+int vfpga_reset(struct vfpga *f)
+{
+	int ret;
+	char state[4096];
+
+	/* Save current state of PCI configuration space */
+	ret = pread(f->vd.fd, state, sizeof(state), (off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40);
+	if (ret != sizeof(state))
+		return -1;
+
+	uint32_t *rst_reg = (uint32_t *) (f->map + BASEADDR_RESET);
+
+	info("Reset fpga");
+	rst_reg[0] = 1;
+
+	usleep(100000);
+
+	/* Restore previous state of PCI configuration space */
+	ret = pwrite(f->vd.fd, state, sizeof(state), (off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40);
+	if (ret != sizeof(state))
+		return -1;
+
+	info("Reset status = %#x", *rst_reg);
+
+	return 0;
+}
+
+/* Dump some details about the fpga card */
+void vfpga_dump(struct vfpga *f)
+{
+	char namebuf[128];
+	char *name;
+
+	name = pci_lookup_name(pacc, namebuf, sizeof(namebuf), PCI_LOOKUP_DEVICE, f->vd.pdev->vendor_id, f->vd.pdev->device_id);
+	pci_fill_info(f->vd.pdev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);	/* Fill in header info we need */
+
+	info("Found fpga card: %s", name);
+	{ INDENT
+		info("slot=%04x:%02x:%02x.%d", f->vd.pdev->domain, f->vd.pdev->bus, f->vd.pdev->dev, f->vd.pdev->func);
+		info("vendor=%04x", f->vd.pdev->vendor_id);
+		info("device=%04x", f->vd.pdev->device_id);
+		info("class=%04x", f->vd.pdev->device_class);
+	}
+	info("BAR0 mapped at %p", f->map);
+
+	vfio_dump(f->vd.group->container);
+}
+
+static void vfpga_debug(char *msg, ...) {
+	va_list ap;
+
+	va_start(ap, msg);
+	log_vprint(LOG_LVL_DEBUG, msg, ap);
+	va_end(ap);
+}
+
+int vfpga_init(int argc, char * argv[], config_setting_t *cfg)
+{
+	if (getuid() != 0)
+		error("The vfpga node-type requires superuser privileges!");
+
+	pacc = pci_alloc();		/* Get the pci_access structure */
+	if (!pacc)
+		error("Failed to allocate PCI access structure");
+
+	pci_init(pacc);			/* Initialize the PCI library */
+
+	pacc->error = (log_cb_t) error;	/* Replace logging and debug functions */
+	pacc->warning = (log_cb_t) warn;
+	pacc->debug = vfpga_debug;
+
+	pci_scan_bus(pacc);		/* We want to get the list of devices */
+
+	return 0;
+}
+
+int vfpga_deinit()
+{
+	pci_cleanup(pacc);
+
+	return 0;
+}
+
+int vfpga_parse(struct node *n, config_setting_t *cfg)
+{
+	struct vfpga *v = n->_vd;
+
+	const char *slot, *id, *err;
+	config_setting_t *cfg_slot, *cfg_id;
+
+	pci_filter_init(NULL, &v->filter);
+
+	cfg_slot = config_setting_get_member(cfg, "slot");
+	if (cfg_slot) {
+		slot = config_setting_get_string(cfg_slot);
+		if (slot) {
+			err = pci_filter_parse_slot(&v->filter, (char*) slot);
+			if (err)
+				cerror(cfg_slot, "%s", err);
+		}
+		else
+			cerror(cfg_slot, "Invalid slot format");
+	}
+
+	cfg_id = config_setting_get_member(cfg, "id");
+	if (cfg_id) {
+		id = config_setting_get_string(cfg_id);
+		if (id) {
+			err = pci_filter_parse_id(&v->filter, (char*) id);
+			if (err)
+				cerror(cfg_id, "%s", err);
+		}
+		else
+			cerror(cfg_slot, "Invalid id format");
+	}
+
+	return 0;
+}
+
+char * vfpga_print(struct node *n)
+{
+	struct vfpga *v = n->_vd;
+
+	return strf("slot=%02"PRIx8":%02"PRIx8".%"PRIx8" id=%04"PRIx16":%04"PRIx16,
+		v->filter.bus, v->filter.device, v->filter.func,
+		v->filter.vendor, v->filter.device);
+}
+
+int vfpga_open(struct node *n)
+{
+	struct vfpga *v = n->_vd;
+	struct pci_dev *dev;
+
+	dev = pci_find_device(pacc, &v->filter);
+	if (!dev)
+		error("No vfpga card found");
+
+	/* @todo */
+
+	return 0;
+}
+
+int vfpga_close(struct node *n)
+{
+//	struct vfpga *v = n->_vd;
+
+	/* @todo */
+
+	return 0;
+}
+
+int vfpga_read(struct node *n, struct sample *smps[], unsigned cnt)
+{
+//	struct vfpga *v = n->_vd;
+
+	/** @todo */
+
+	return 0;
+}
+
+/** @todo implement */
+int vfpga_write(struct node *n, struct sample *smps[], unsigned cnt)
+{
+//	struct vfpga *v = n->_vd;
+
+	/** @todo */
+
+	return 0;
+}
+
+static struct node_type vt = {
+	.name		= "vfpga",
+	.description	= "VILLASfpga PCIe card (libpci)",
+	.vectorize	= 0,
+	.parse		= vfpga_parse,
+	.print		= vfpga_print,
+	.open		= vfpga_open,
+	.close		= vfpga_close,
+	.read		= vfpga_read,
+	.write		= vfpga_write,
+	.init		= vfpga_init,
+	.deinit		= vfpga_deinit
+};
+
+REGISTER_NODE_TYPE(&vt)
\ No newline at end of file
diff --git a/lib/utils.c b/lib/utils.c
index ac5b0a1f6..1fa4bbb91 100644
--- a/lib/utils.c
+++ b/lib/utils.c
@@ -202,4 +202,94 @@ void * memdup(const void *src, size_t bytes)
 	memcpy(dst, src, bytes);
 	
 	return dst;
+}
+
+#include <stdio.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <ctype.h>
+
+#include "utils.h"
+
+uint64_t wait_irq(int irq)
+{
+	ssize_t ret;
+	uint64_t cnt;
+
+	ret = read(irq, &cnt, sizeof(cnt));
+	if (ret != sizeof(cnt))
+		return 0;
+
+	return cnt;
+}
+
+int read_random(char *buf, size_t len)
+{
+	int ret, fd;
+	
+	fd = open("/dev/urandom", O_RDONLY);
+	if (fd < 0)
+		return -1;
+	
+	ret = read(fd, buf, len);
+	if (ret != len)
+		ret = -1;
+	else
+		ret = 0;
+
+	close(fd);
+
+	return ret;
+}
+
+void printb(void *mem, size_t len)
+{
+	uint8_t *mem8 = (uint8_t *) mem;
+
+	for (int i = 0; i < len; i++) {
+		printf("%02hx ", mem8[i]);
+
+		if (i % 16 == 15)
+			printf("\n");
+	}
+}
+
+void printdw(void *mem, size_t len)
+{
+	int columns = 4;
+
+	uint32_t *mem32 = (uint32_t *) mem;
+
+	for (int i = 0; i < len; i++) {
+		if (i % columns == 0)
+			printf("%#x: ", i * 4);
+
+		printf("%08x ", mem32[i]);
+		
+		char *memc = (char *) &mem32[i];
+		printf("%c%c%c%c ",
+			isprint(memc[0]) ? memc[0] : ' ',
+			isprint(memc[1]) ? memc[1] : ' ',
+			isprint(memc[2]) ? memc[2] : ' ',
+			isprint(memc[3]) ? memc[3] : ' '
+		);
+
+		if ((i+1) % columns == 0)
+			printf("\n");
+	}
+}
+
+void rdtsc_sleep(uint64_t nanosecs, uint64_t start)
+{
+	uint64_t cycles;
+
+	cycles = (double) nanosecs / (1e9 / 3392389000);
+	
+	if (start == 0)
+		start = rdtscp();
+	
+	do {
+		__asm__("nop");
+	} while (rdtscp() - start < cycles);
 }
\ No newline at end of file
diff --git a/src/fpga-bench.c b/src/fpga-bench.c
new file mode 100644
index 000000000..31e7df764
--- /dev/null
+++ b/src/fpga-bench.c
@@ -0,0 +1,159 @@
+/** Benchmarks for VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <villas/utils.h>
+#include <villas/hist.h>
+#include <villas/log.h>
+#include <villas/nodes/vfpga.h>
+
+#include "config.h"
+#include "config-fpga.h"
+
+#define BENCH_EXP_MIN	2	// 1 << 2 = 4 Bytes
+#define BENCH_EXP_MAX	17	// 1 << 17 = 128 MiB
+
+#define BENCH_ROUNDS	10000
+#define BENCH_WARMUP	2000
+
+/* List of available benchmarks */
+enum benchmarks {
+	BENCH_FIFO,
+	BENCH_DMA_SIMPLE,
+	BENCH_DMA_SG,
+	MAX_BENCHS
+};
+
+static int bench_run(struct vfpga *f, int polling, int bench)
+{
+	struct hist hist;
+	uint64_t start, stop;
+	
+	hist_create(&hist, 0, 0, 1);
+
+	int irq_fifo     = polling ? -1 : f->vd.msi_efds[MSI_FIFO_MM];
+	int irq_dma_mm2s = polling ? -1 : f->vd.msi_efds[MSI_DMA_MM2S];
+	int irq_dma_s2mm = polling ? -1 : f->vd.msi_efds[MSI_DMA_S2MM];
+	
+	char *src, *dst;
+	size_t len;
+
+	for (int exp = BENCH_EXP_MIN; exp < BENCH_EXP_MAX; exp++) {
+		size_t sz = 1 << exp;
+		
+		hist_reset(&hist);
+		read_random(src, len);
+		memset(dst, 0, len);
+
+		info("Running bench with size: %#zx", sz);
+
+		for (int i = 0; i < BENCH_ROUNDS + BENCH_WARMUP; i++) {
+			start = rdtscp();
+
+			switch (bench) {
+				case BENCH_FIFO:
+					fifo_write(&f->fifo, src, len, irq_fifo);
+					fifo_read(&f->fifo, src, len, irq_fifo);
+					break;
+				case BENCH_DMA_SG:
+					dma_write(&f->dma_sg, src, len, irq_dma_mm2s);
+					dma_read(&f->dma_sg, src, len, irq_dma_s2mm);
+					break;
+				case BENCH_DMA_SIMPLE:
+					dma_write(&f->dma_simple, src, len, irq_dma_mm2s);
+					dma_read(&f->dma_simple, src, len, irq_dma_s2mm);
+					break;
+			}
+			
+			stop = rdtscp();
+
+			if (memcmp(src, dst, len))
+				warn("Compare failed");
+
+			if (i > BENCH_WARMUP)
+				hist_put(&hist, stop - start);
+		}
+
+		hist_dump(&hist);
+	}
+
+	hist_destroy(&hist);
+}
+
+int bench_dm(struct vfpga *f)
+{
+	int irq_fifo, irq_dma_mm2s, irq_dma_s2mm;
+	int polling = true;
+	int ret;
+
+	/* Loopback all datamovers */
+	switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_DMA_SIMPLE);
+	switch_connect(&f->sw, AXIS_SWITCH_DMA_SG, AXIS_SWITCH_DMA_SG);
+	switch_connect(&f->sw, AXIS_SWITCH_FIFO_MM, AXIS_SWITCH_FIFO_MM);
+
+	for (polling = 0; polling <= 1; polling++) {
+		for (int i = 0; i < MAX_BENCHS; i++)
+			bench_run(f, polling, i);
+	}
+
+	return 0;
+}
+
+int bench_memcpy(struct vfpga *f)
+{
+	uint64_t start, end, total = 0;
+
+#if 1
+	char *src = f->map;
+	char *dst = alloc(1 << 13);
+#else
+	char *dst = f->map;
+	char *src = alloc(1 << 13);
+	read_random(src, 1 << 13);
+#endif
+
+	char *srcb = src;
+	for (int i = 0; i < 1 << 13; i++)
+		srcb[i] = i;
+
+	unsigned long long runs = 10000;
+	
+	fgetc(stdin);
+	
+	//memcpy(dst, src, 0xFF);
+	
+	for (int i = 0; i < 64; i++)
+		dst[i] = src[i];
+	
+	fgetc(stdin);
+
+	for (int exp = 0; exp < 14; exp++) {
+		size_t len = 1 << exp;
+
+		for (int i = 0; i < runs; i++) {
+			/* Clear cache */
+			for (char *p = src; p < src + len; p += 64)
+				__builtin_ia32_clflush(p);
+
+	//		for (char *p = f->dma; p < src + len; p += 64)
+	//			__builtin_ia32_clflush(p);
+
+			/* Start measurement */
+			start = rdtscp();
+			memcpy(dst, src, len);
+			end = rdtscp();
+		
+			total += end - start;
+		}
+		
+		info("avg. clk cycles for %u bytes = %u", len, total / runs);
+		usleep(100000);
+	}
+}
\ No newline at end of file
diff --git a/src/fpga-tests.c b/src/fpga-tests.c
new file mode 100644
index 000000000..3384e9d1e
--- /dev/null
+++ b/src/fpga-tests.c
@@ -0,0 +1,404 @@
+/** Test procedures for VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <fcntl.h>
+#include <poll.h>
+#include <time.h>
+
+#include <villas/utils.h>
+#include <villas/nodes/vfpga.h>
+
+#include "fpga-tests.h"
+#include "config.h"
+#include "config-fpga.h"
+
+//#include "cbuilder/cbmodel.h"
+
+#define TEST_LEN 0x1000
+
+#define CPU_HZ 3392389000
+
+int test_intc(struct vfpga *f)
+{
+	uint32_t ier, isr;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | 0xFF00);
+
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_ISR_OFFSET, 0xFF00);
+
+	debug(3, "Wait for 8 SW triggerd interrupts");
+	for (int i = 0; i < 8; i++)
+		wait_irq(f->vd.msi_efds[i+8]);
+
+	isr = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_ISR_OFFSET);
+	
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return (isr & 0xFF00) ? -1 : 0; /* ISR should get cleared by MSI_Grant_signal */
+}
+
+#ifdef HAS_XSG
+int test_xsg(struct vfpga *f, const char *name)
+{
+	struct model *m;
+
+	m = list_lookup(&f->models, name);
+	if (m) {
+		model_dump(m);
+
+		list_foreach(struct model_param *p, &m->parameters) {
+			if (p->direction == MODEL_PARAM_IN) {
+				model_param_write(p, p->default_value.flt);
+				info("Param '%s' updated to: %f", p->name, p->default_value.flt);
+			}
+		}
+
+		if (strcmp(m->name, "xsg_multiply_add") == 0) {
+			switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_XSG);
+			switch_connect(&f->sw, AXIS_SWITCH_XSG, AXIS_SWITCH_DMA_SIMPLE);
+
+			float *src = (float *) f->dma;
+			float *dst = (float *) f->dma + TEST_LEN;
+			
+			for (int i = 0; i < 6; i++)
+				src[i] = 1.1 * (i+1);
+
+			ssize_t len = dma_ping_pong(&f->dma_simple, virt_to_dma(src, f->dma), virt_to_dma(dst, f->dma), 6 * sizeof(float), -1);
+			if (len != 6 * sizeof(float))
+				error("Failed to to ping pong DMA transfer: %zd", len);
+
+			for (int i = 0; i < 6; i++)
+				info("src[%d] = %f", i, src[i]);
+			for (int i = 0; i < 6; i++)
+				info("dst[%d] = %f", i, dst[i]);
+		}
+	}
+	else
+		warn("There is no model named '%s'", name);
+
+	return 0;
+}
+#endif
+
+#ifdef HAS_FIFO_MM
+int test_fifo(struct vfpga *f)
+{
+	int ret;
+	ssize_t len;
+	uintptr_t baseaddr = (uintptr_t) (f->map + BASEADDR_FIFO_MM);
+	char src[255], dst[255];
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_FIFO_MM));
+
+	/* Get some random data to compare */
+	memset(dst, 0, sizeof(dst));
+	ret = read_random((char *) src, sizeof(src));
+	if (ret)
+		error("Failed to get random data");
+
+	ret = switch_connect(&f->sw, AXIS_SWITCH_FIFO_MM, AXIS_SWITCH_FIFO_MM);
+	if (ret)
+		error("Failed to configure switch");
+
+	len = fifo_write(&f->fifo, (char *) src, sizeof(src), f->vd.msi_efds[MSI_FIFO_MM]);
+	if (len != sizeof(src))
+		error("Failed to send to FIFO");
+
+	len = fifo_read(&f->fifo, (char *) dst, sizeof(dst), f->vd.msi_efds[MSI_FIFO_MM]);
+	if (len != sizeof(dst))
+		error("Failed to read from FIFO");
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	/* Compare data */
+	return memcmp(src, dst, sizeof(src));
+}
+#endif
+
+#if defined(HAS_DMA_SG) || defined(HAS_DMA_SIMPLE)
+int test_dma(struct vfpga *f)
+{
+	int ret;
+	ssize_t len;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_DMA_MM2S) | (1 << MSI_DMA_S2MM));
+
+	ret = switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_DMA_SIMPLE);
+	if (ret)
+		error("Failed to configure switch");
+
+#ifdef HAS_DMA_SG
+	/* Memory for buffer descriptors and RX */
+	struct dma_mem bd = {
+		.base_virt = (uintptr_t) f->map + BASEADDR_BRAM,
+		.base_phys = BASEADDR_BRAM,
+		.len = 8 * 1024
+	};
+	
+	struct dma_mem rx = {
+		.base_virt = (uintptr_t) f->dma + TEST_LEN,
+		.base_phys = BASEADDR_HOST + TEST_LEN,
+		.len = TEST_LEN
+	};
+#endif
+
+	/* Get some random data to compare */
+	char *src = f->dma;
+	char *dst = f->dma + TEST_LEN;
+
+	ret = read_random(src, TEST_LEN);
+	if (ret)
+		error("Failed to get random data");
+
+#if 0
+	len = dma_write(&f->dma_simple, virt_to_dma(src, f->dma), TEST_LEN, -1);//f->vd.msi_efds[MSI_DMA_MM2S]);
+	if (len != TEST_LEN)
+		error("Failed to send to DMAC: %zd", len);
+
+	len = dma_read(&f->dma_simple, virt_to_dma(dst, f->dma), TEST_LEN, -1);//f->vd.msi_efds[MSI_DMA_S2MM]);
+	if (len != TEST_LEN)
+		error("Failed to send to DMAC: %zd", len);
+#else
+	len = dma_ping_pong(&f->dma_simple, virt_to_dma(src, f->dma), virt_to_dma(dst, f->dma), TEST_LEN, f->vd.msi_efds[MSI_DMA_S2MM]);
+	if (len != TEST_LEN)
+		error("Failed to to ping pong DMA transfer: %zd", len);
+#endif
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	/* Check received data */
+	return memcmp(src, dst, TEST_LEN);
+}
+#endif
+
+#ifdef HAS_TIMER
+int test_timer(struct vfpga *f)
+{
+	int ret;
+	bool success;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_TMRCTR0));
+
+	XTmrCtr_SetOptions(&f->tmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
+	XTmrCtr_SetResetValue(&f->tmr, 0, AXI_HZ / 125);
+	XTmrCtr_Start(&f->tmr, 0);
+
+	struct pollfd pfd = {
+		.fd = f->vd.msi_efds[MSI_TMRCTR0],
+		.events = POLLIN
+	};
+
+	ret = poll(&pfd, 1, 1000);
+	if (ret == 1) {
+		uint64_t counter = wait_irq(f->vd.msi_efds[MSI_TMRCTR0]);
+
+		info("Got IRQ: counter = %llu", counter);
+
+		if (counter == 1)
+			return 0;
+		else
+			warn("Counter was not 1");
+	}
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return -1;
+}
+#endif
+
+#ifdef HAS_RTDS_AXIS
+int test_rtds_cbuilder(struct vfpga *f)
+{
+	int ret;
+	int values_tx = 1;
+	int values_rx;
+	uint32_t tsc = 0, ovfl = 0;
+	ssize_t len;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+//	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_DMA_MM2S) | (1 << MSI_DMA_S2MM));
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_RTDS_OVF));
+
+	/* Dump RTDS AXI Stream state */
+	rtds_axis_dump(f->map + BASEADDR_RTDS);
+
+	/* Get some random data to compare */
+	float *data_rx = (uint32_t *) (f->dma);
+	float *data_tx = (uint32_t *) (f->dma + 0x1000);
+
+	/* Setup crossbar switch */
+	switch_connect(&f->sw, AXIS_SWITCH_RTDS, AXIS_SWITCH_DMA_SIMPLE);
+	switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_RTDS);
+
+	/* Disable blocking Overflow status */
+	int flags = fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_GETFL, 0);
+	fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_SETFL, flags | O_NONBLOCK);
+	
+	/* Initialize CBuilder model */
+	double mdl_dt = rtds_axis_dt(f->map + BASEADDR_RTDS);
+	double mdl_params[] = {
+		1,	/**< R2 = 1 Ohm */
+		0.001	/**< C2 = 1000 uF */
+	};
+	double mdl_inputs[1];
+	double mdl_outputs[1];
+
+	cbmodel_init(&mdl_params, mdl_dt);
+
+	while (1) {
+		/* Check for overflow */
+		ovfl += wait_irq(f->vd.msi_efds[MSI_RTDS_OVF]);
+		if (tsc % (int) (1.0 / mdl_dt) == 0)
+			warn("Missed %u timesteps", ovfl);
+		
+		break;
+
+		/* Read data from RTDS */
+		len = dma_read(&f->dma_simple, virt_to_dma(data_rx, f->dma), 0x1000, -1);
+		uint64_t start = rdtscp();
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+
+		values_rx = len / sizeof(uint32_t);
+
+		mdl_inputs[0] = data_rx[0]; /* cast to double */
+		
+		/* Run CBuilder model */
+		cbmodel_step(mdl_inputs, mdl_outputs);
+		
+		data_tx[0] = mdl_outputs[0]; /* cast to float */
+
+		/* Send data to RTDS */
+		len = dma_write(&f->dma_simple, virt_to_dma(data_tx, f->dma), sizeof(uint32_t) * values_tx, -1);
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+	}
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return 0;
+}
+
+int test_rtds_rtt(struct vfpga *f)
+{
+	int ret;
+	int values_tx = 64;
+	int values_rx;
+	uint32_t tsc = 0, ovfl = 0;
+	ssize_t len;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+//	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_DMA_MM2S) | (1 << MSI_DMA_S2MM));
+
+	/* Dump RTDS AXI Stream state */
+	rtds_axis_dump(f->map + BASEADDR_RTDS);
+
+	/* Get some random data to compare */
+	uint32_t *data_rx = (uint32_t *) (f->dma);
+	uint32_t *data_tx = (uint32_t *) (f->dma + 0x1000);
+
+	int switch_port;
+#if DATAMOVER == RTDS_DM_FIFO
+	switch_port = AXIS_SWITCH_FIFO_MM;
+#elif DATAMOVER == RTDS_DM_DMA_SIMPLE
+	switch_port = AXIS_SWITCH_DMA_SIMPLE;
+#elif DATAMOVER == RTDS_DM_DMA_SG
+	switch_port = AXIS_SWITCH_DMA_SG;
+#endif
+
+	/* Setup crossbar switch */
+	switch_connect(&f->sw, AXIS_SWITCH_RTDS, switch_port);
+	switch_connect(&f->sw, switch_port, AXIS_SWITCH_RTDS);
+
+	/* Disable blocking Overflow status */
+	int flags = fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_GETFL, 0);
+	fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_SETFL, flags | O_NONBLOCK);
+
+	int irq_fifo = f->vd.msi_efds[MSI_FIFO_MM];
+	int rtt2_prev, rtt2;
+
+	while (1) {
+#if 0		/* Wait for TS */
+		tsc += wait_irq(f->vd.msi_efds[MSI_RTDS_TS]);
+#else
+		tsc++;
+#endif
+
+#if 0		/* Check for overflow */
+		ovfl += wait_irq(f->vd.msi_efds[MSI_RTDS_OVF]);
+		if (tsc % 20000 == 0)
+			warn("Missed %u timesteps", ovfl);
+#endif
+
+#if DATAMOVER == RTDS_DM_FIFO
+retry:		len = fifo_read(&f->fifo, (char *) data_rx, 0x1000, irq_fifo);
+		if (XLlFifo_RxOccupancy(&f->fifo) > 0 )
+			goto retry;
+#elif DATAMOVER == RTDS_DM_DMA_SIMPLE
+		len = dma_read(&f->dma_simple, virt_to_dma(data_rx, f->dma), 0x1000, -1);//f->vd.msi_efds[MSI_DMA_S2MM]);
+		uint64_t start = rdtscp();
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+#elif DATAMOVER == RTDS_DM_DMA_SG
+		len = dma_read(&f->dma_sg, virt_to_dma(data_rx, f->dma), 0x1000, f->vd.msi_efds[MSI_DMA_S2MM]);
+#endif
+		values_rx = len / sizeof(uint32_t);
+
+		for (int i = 0; i < values_tx; i++)
+			data_tx[i] = data_rx[i];
+		
+		data_tx[3] = tsc;
+
+		if (data_rx[3] == 0)
+			tsc = 0;
+		
+		int rtt = tsc - data_rx[3];
+		
+		rtt2_prev = rtt2;
+		rtt2 = tsc - data_rx[0];
+
+		rdtsc_sleep(30000, start);
+
+#if DATAMOVER == RTDS_DM_FIFO
+		len = fifo_write(&f->fifo, (char *) data_tx, sizeof(uint32_t) * values_tx, irq_fifo);
+		if (len != sizeof(uint32_t) * values_tx)
+			error("Failed to send to FIFO");
+#elif DATAMOVER == RTDS_DM_DMA_SIMPLE
+		len = dma_write(&f->dma_simple, virt_to_dma(data_tx, f->dma), sizeof(uint32_t) * values_tx, -1);//f->vd.msi_efds[MSI_DMA_MM2S]);
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+#elif DATAMOVER == RTDS_DM_DMA_SG
+		len = dma_write(&f->dma_sg, virt_to_dma(data_tx, f->dma), sizeof(uint32_t) * values_tx, f->vd.msi_efds[MSI_DMA_MM2S]);
+#endif
+	}
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return 0;
+}
+#endif
\ No newline at end of file
diff --git a/src/fpga.c b/src/fpga.c
new file mode 100644
index 000000000..db1fbbbe7
--- /dev/null
+++ b/src/fpga.c
@@ -0,0 +1,165 @@
+/** VILLASfpga utility for tests and benchmarks
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+ 
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <dirent.h>
+#include <errno.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <sched.h>
+
+#include <villas/log.h>
+#include <villas/timing.h>
+#include <villas/utils.h>
+#include <villas/nodes/vfpga.h>
+#include <villas/kernel/pci.h>
+#include <villas/kernel/kernel.h>
+
+#include "config.h"
+#include "config-fpga.h"
+
+#include "fpga-tests.h"
+#include "fpga-bench.h"
+
+static struct pci_access *pacc;
+
+void usage(char *name)
+{
+	printf("Usage: %s [ARGS]\n", name);
+	printf("  -d    Set log level\n");
+	printf("  -i    ID pair of PCI device: [vendor]:[device][:class]\n");
+	printf("  -s    Slot of PCI device: [[[domain]:][bus]:][slot][.[func]]\n\n");
+	printf("fpga PCIutil %s (built on %s %s)\n",
+		VERSION, __DATE__, __TIME__);
+	printf(" copyright 2014-2015, Institute for Automation of Complex Power Systems, EONERC\n");
+	printf(" Steffen Vogel <StVogel@eonerc.rwth-aachen.de>\n");
+}
+
+int main(int argc, char *argv[])
+{
+	int ret;
+	char *err;
+
+	struct vfpga fpga;
+	struct vfio_container vc;
+	struct pci_dev *pdev;
+	struct pci_filter filter;
+
+	/* Init libpci */
+	pacc = pci_alloc();		/* Get the pci_access structure */
+	pci_init(pacc);			/* Initialize the PCI library */
+	pci_scan_bus(pacc);		/* We want to get the list of devices */
+	pci_filter_init(pacc, &filter);
+
+	/* Default filter */
+	filter.vendor = PCI_VID_XILINX;
+	filter.device = PCI_PID_VFPGA;
+	
+	/* Parse arguments */
+	char c, *endptr;
+	while ((c = getopt (argc, argv, "i:s:d:")) != -1) {
+		switch (c) {
+			case 's':
+				err = pci_filter_parse_slot(&filter, optarg);
+				if (err)
+					error("Failed to parse slot: %s", err);
+				break;
+
+			case 'i':
+				err = pci_filter_parse_id(&filter, optarg);
+				if (err)
+					error("Failed to parse ID: %s", err);
+				break;
+			
+			case 'd':
+				log_setlevel(strtoul(optarg, &endptr, 10), ~0);
+				break;	
+
+			case '?':
+			default:
+				usage(argv[0]);
+		}
+	}
+
+	/* Search for fpga card */
+	pdev = pci_find_device(pacc, &filter);
+	if (!pdev)
+		error("Failed to find PCI device");
+
+	/* Get VFIO handles and details */
+	ret = vfio_init(&vc);
+	if (ret)
+		serror("Failed to initialize VFIO");
+
+	/* Initialize fpga card */
+	ret = vfpga_init2(&fpga, &vc, pdev);
+	if (ret)
+		error("Failed to initialize fpga card");
+
+	vfpga_dump(&fpga);
+
+	/* Setup scheduler */
+	cpu_set_t set = integer_to_cpuset(AFFINITY);
+
+	ret = sched_setaffinity(0, sizeof(set), &set);
+	if (ret)
+		serror("Failed to pin thread");
+
+	ret = sched_setscheduler(0, SCHED_FIFO, &(struct sched_param) { .sched_priority = PRIORITY });
+	if (ret)
+		serror("Failed to change scheduler");
+
+	for (int i = 0; i < fpga.vd.irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
+		ret = kernel_irq_setaffinity(fpga.vd.msi_irqs[i], AFFINITY, NULL);
+		if (ret)
+			serror("Failed to change affinity of VFIO-MSI interrupt");
+	}
+
+	/* Start tests */
+	ret = test_intc(&fpga);
+	info("INTC Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+	ret = test_xsg(&fpga, "xsg_multiply_add");
+	info("XSG Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_timer(&fpga);
+//	info("Timer Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_fifo(&fpga);
+//	info("FIFO Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+	ret = test_dma(&fpga);
+	info("DMA Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_rtds_rtt(&fpga);
+//	info("RTDS RTT Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_rtds_cbuilder(&fpga);
+//	info("RTDS RTT Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+	/* Start benchmarks */
+#if 0
+	ret = bench_memcpy(&fpga);
+#endif
+
+	/* Shutdown */
+	ret = vfpga_deinit2(&fpga);
+	if (ret)
+		error("Failed to de-initialize fpga card");
+
+	ret = vfio_destroy(&vc);
+	if (ret)
+		error("Failed to deinitialize VFIO module");
+
+	pci_cleanup(pacc);
+
+	return 0;
+}
diff --git a/src/server.c b/src/server.c
index 579b3d25f..864d777d8 100644
--- a/src/server.c
+++ b/src/server.c
@@ -8,18 +8,17 @@
 
 #include <stdlib.h>
 #include <string.h>
-
 #include <signal.h>
 #include <unistd.h>
-
 #include <sched.h>
 
 #include "config.h"
-#include "utils.h"
-#include "cfg.h"
-#include "path.h"
-#include "node.h"
-#include "kernel.h"
+
+#include <villas/utils.h>
+#include <villas/cfg.h>
+#include <villas/path.h>
+#include <villas/node.h>
+#include <villas/kernel/kernel.h>
 
 #ifdef ENABLE_OPAL_ASYNC
   #include "opal.h"
diff --git a/thirdparty/opal/README.txt b/thirdparty/opal/README.txt
deleted file mode 100644
index a2ea5e86d..000000000
--- a/thirdparty/opal/README.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-This directory contains the libOpalAsyncApi library and
-several smaller OPAL-RT related dependencies.
-
-It's included for testing purposes.
-
-The contents of this directory are a subset of the libraries which are
-on the OPAL simulators itself at: /usr/opalrt/common/
\ No newline at end of file
diff --git a/thirdparty/opal/include_target/AsyncApi.h b/thirdparty/opal/include_target/AsyncApi.h
deleted file mode 100644
index bbea71101..000000000
--- a/thirdparty/opal/include_target/AsyncApi.h
+++ /dev/null
@@ -1,670 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
- *
- *	File name =			$Workfile: AsyncApi.h $
- *	SourceSafe path =	$Logfile: /SIMUPAR/soft/common/include_target/AsyncApi.h $
- *	SourceSafe rev. =	$Revision: 2.14 $
- *	Last checked in =	$Date: 2009/06/04 01:39:35 $
- *	Last updated =		$Modtime: 8/14/02 3:43p $
- *	Last modified by =	$Author: irenep $
- *
- *-----------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------
- *
- *  Abstract:
- *
- *-----------------------------------------------------------------*/
-
-#ifndef OPAL_ASYNC_MEM_H
-
-#define OPAL_ASYNC_MEM_H
-
-#if defined(__QNXNTO__)
-	#include <semaphore.h>
-	#include <inttypes.h>
-#endif
-#include <math.h>
-
-//typedef unsigned char byte;
-//typedef unsigned short word;
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-// NOTE : Copié du fichier OpalRtMain.h
-typedef enum
-{
-/*	0	*/	STATE_ERROR,
-/*	1	*/	STATE_PAUSE,
-/*	2	*/	STATE_LOAD,
-/*	3	*/	STATE_RUN,
-/*	4	*/	STATE_SINGLE_STEP,
-/*	5	*/	STATE_RESET,
-/*	6	*/	STATE_STOP,
-/*	7	*/	STATE_WAIT_SC
-} RUN_STATE;
-
-
-typedef enum
-{
-	OP_ASYNC_WAIT_FOR_DATA,
-	OP_ASYNC_PREPARE_DATA,
-	OP_ASYNC_DATA_READY
-} OpalAsyncStatusCode;
-
-
-/* Send icon mode actually supported */
-#define	NEED_REPLY_BEFORE_NEXT_SEND	0
-#define	NEED_REPLY_NOW				1
-#define	DONT_NEED_REPLY				2
-
-/* Define to support multi-plateforme */
-# ifndef UINT64_T
-#  if defined(__i386__) && defined(__linux__)
-#    define UINT64_T unsigned long long
-#  endif
-#  if defined(_MSC_VER)
-#    define UINT64_T unsigned __int64
-#  endif
-#  if defined(__QNXNTO__)
-#    define UINT64_T uint64_t
-#  endif
-# endif
-# ifdef UINT64_T
-#  if defined(__i386__) && defined(__linux__)
- __extension__
-#  endif
-# endif /* UINT64_T */
-
-
-/****************************************************************************************
-*
-* Name :	OpalOpenAsyncMem
-*
-* Input Parameters :
-*		sizeOfMemory :	the size in bytes of the shared memory.
-*							
-*		mem_name :		the name of shared memory.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			ENOMEM	Insufficient memory available.
-*			EIO		Cannot open shared memory.
-* 
-* Description :	Open the shared memory for futur acces.
-*
-*****************************************************************************************/
-int	OpalOpenAsyncMem(int	sizeOfMemory,const char *mem_name);
-
-
-/****************************************************************************************
-*
-* Name :	OpalCloseAsyncMem
-*
-* Input Parameters :
-*		sizeOfMemory :	Size of the shared memory.
-*							
-*		mem_name :		Name of shared memory.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EIO		Cannot close shared memory.
-* 
-* Description :	Close the shared memory
-*
-*****************************************************************************************/
-int	OpalCloseAsyncMem(int	sizeOfMemory,const char *mem_name);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetNbAsyncSendIcon
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	
-*		nbIcon :	pointer to a integer variable
-*		
-* Return :	EOK		success
-* 
-* Description :	Gives the number of send icon registered to the controller.
-*
-*****************************************************************************************/
-int	OpalGetNbAsyncSendIcon(int	*nbIcon);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetNbAsyncRecvIcon
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :
-*		nbIcon :	pointer to a integer variable
-*
-* Return :	EOK		success
-* 
-* Description :	Gives the number of receive icon registered to the controller.
-*
-*****************************************************************************************/
-int	OpalGetNbAsyncRecvIcon(int	*nbIcon);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncCtrlParameters
-*
-* Input Parameters :
-*		size :		the size in bytes of the parameters structure.
-*
-* Output Parameters :	
-*		ParamPtr :	pointer to a parameters structure.
-*		
-* Return :	EOK		success
-*			E2BIG	size parameter are too big.
-*			ENOEXEC pointer error, version error or shmem error
-* 
-* Description :	Give all the parameters of the controller icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncCtrlParameters(void	*ParamPtr,int	size);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIconDataLength
-*
-* Input Parameters :	
-*		SendID	:	ID of the icon
-*
-* Output Parameters :
-*		length	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*  
-* Description :	Gives the data length of the send icon specified with SendID parameter.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIconDataLength(int	*length, unsigned int SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIconMode
-*
-* Input Parameters :	
-*		SendID	:	ID of the icon
-*
-* Output Parameters :
-*		mode	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*  
-* Description :	Gives the mode of the send icon specified with SendID parameter.
-*				(See at the top of this file for mode definition)
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIconMode(int	*mode, unsigned int SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvIconDataLength
-*
-* Input Parameters :	
-*		RecvID	:	ID of the icon
-*
-* Output Parameters :
-*		length	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*  
-* Description :	Gives the data length of the recv icon specified with RecvID parameter.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvIconDataLength(int	*length, unsigned int RecvID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalWaitForAsyncSendRequest
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :
-*		SendID	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			ENODEV	No send icon registered.
-*  
-* Description :	Gives the ID of the icon who call a send request.
-*
-*****************************************************************************************/
-int	OpalWaitForAsyncSendRequest(unsigned int	*SendID);
-
-/****************************************************************************************
-*
-* Name :	OpalAsyncSendRequestDone
-*
-* Input Parameters :	
-*		SendID	:	ID of the icon
-*
-* Output Parameters :	nil
-*		
-* Return :	EOK		success
-*			ENODEV	No send icon registered.
-*			EINVAL	invalid ID
-*  
-* Description :	Reply to a specific send icon.
-*
-*****************************************************************************************/
-int	OpalAsyncSendRequestDone(unsigned int	SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIconData
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Get the data for the specific send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIconData(void	*dataPtr, int size, unsigned int SendID);
-
-/****************************************************************************************
-* Name :	OpalGetSubsetAsyncSendIconData
-*
-* Input Parameters :	
-*		offset	:	offset in bytes of the data buffer to be get
-*		size	:	size in bytes of the data buffer to get.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		succes
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Get one subset of the data for the specific send icon.
-*               OpalGetSubsetAsyncSendIconData(buf,0,size,sendId) 
-*				is the same as OpalGetAsyncSendIconData(buf,size,sendId) 
-*
-*****************************************************************************************/
-
-int OpalGetSubsetAsyncSendIconData(double *dataPtr, int offset, int size, unsigned int SendID);
-
-
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconData
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Set the data for the specific recv icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconData(void	*dataPtr, int size, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalSetSubsetAsyncRecvIconData
-*
-* Input Parameters :	
-*		offset	:	offset in bytes of the data buffer to be set
-*		size	:	size in bytes of the data buffer.to be set
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		succes
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Set one subset of the data for the specific recv icon.
-*               OpalSetSubsetAsyncRecvIconData(buf,0,size,recvId) 
-*				is the same as OpalSetAsyncRecvIconData(buf,size,recvId) 
-*
-*****************************************************************************************/
-int	OpalSetSubsetAsyncRecvIconData(double *dataPtr,int offset,int size, unsigned int RecvID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncSendIconError
-*
-* Input Parameters :	
-*		Error	:	error code returned to the send icon.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*  
-* Description :	Set the error code for the specific send icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncSendIconError(double Error, unsigned int SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconError
-*
-* Input Parameters :	
-*		Error	:	error code returned to the receive icon.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no receive icon registered
-*  
-* Description :	Set the error code for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconError(double Error, unsigned int RecvID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconStatus
-*
-* Input Parameters :	
-*		Status	:	status code returned to the recveive icon.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no receive icon registered
-*  
-* Description :	Set the status code for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconStatus(double Status, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconStatus
-*
-* Input Parameters :	
-*		Status	:	status code returned to the recveive icon.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no receive icon registered
-*  
-* Description :	Set the status code for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconStatusMult(double Status, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvIconTimeout
-*
-* Input Parameters :	
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		timeout	:	pointer to a double.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no recv icon registered
-*  
-* Description :	Get the timout for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvIconTimeout(double	*timeout, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIDList
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			ENODEV	no send icon registered
-*			E2BIG	invalid size.
-*  
-* Description :	Get the ID list of all Send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIDList(void	*dataPtr, int size);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvIDList
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			ENODEV	no Recv icon registered
-*			E2BIG	invalid size.
-*  
-* Description :	Get the ID list of all Recv icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvIDList(void	*dataPtr, int size);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*  
-* Description :	Get all parameters of the specific Send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendParameters(void	*dataPtr, int size, unsigned int SendID);
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendExtFloatParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the exterended is to be stored.
-*		
-* Return :	number of parameters
-*  
-* Description :	Get all extended parameters of the specific Send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendExtFloatParameters(void	*dataPtr, int size, unsigned int SendID);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*  
-* Description :	Get all parameters of the specific Recv icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvParameters(void	*dataPtr, int size, unsigned int RecvID);
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvExtFloatParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the exterended is to be stored.
-*		
-* Return :	number of parameters
-*  
-* Description :	Get all extended parameters of the specific recv icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvExtFloatParameters(void	*dataPtr, int size, unsigned int RecvID);
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncCtrlExtFloatParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the exterended is to be stored.
-*		
-* Return :	number of parameters
-*  
-* Description :	Get all extended parameters of the specific ctrl icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncCtrlExtFloatParameters(void	*dataPtr, int size);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncModelState 
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		STATE_ERROR			
-*				STATE_PAUSE			
-*				STATE_LOAD			
-*				STATE_RUN			
-*				STATE_SINGLE_STEP	
-*				STATE_RESET			
-*				STATE_STOP			
-*				STATE_WAIT_SC		
-*  
-* Description :	Returns the state of the model
-*
-*****************************************************************************************/
-int OpalGetAsyncModelState (void);
-
-// RT is defined coz these prototypes are reuired only on target site
-// and long long are not supported on Windows
-#if defined(RT)
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncStartExecCpuTime 
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		
-* Description :	This function returns the cuurent CPU time counter read at start of execution
-*
-*****************************************************************************************/
-int OpalGetAsyncStartExecCpuTime( void * ParamPtr, UINT64_T * time );
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncStartPauseCpuTime 
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		
-* Description :	This function returns the cuurent CPU time counter read at start of execution
-*
-*****************************************************************************************/
-int OpalGetAsyncStartPauseCpuTime( void * ParamPtr, UINT64_T * time );
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncModelTime
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		
-* Description :	This function get a CPU time close to model sync, and the current modelTime
-*
-*****************************************************************************************/
-int OpalGetAsyncModelTime( void * ParamPtr, unsigned long long * CPUtime, double * modelTime);
-#endif
-
-unsigned atoh (const char * ptr);
-unsigned ascii_to_hexa (char * str);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif  // #ifndef OPAL_ASYNC_MEM_H
-
diff --git a/thirdparty/opal/include_target/OpalGenAsyncParamCtrl.h b/thirdparty/opal/include_target/OpalGenAsyncParamCtrl.h
deleted file mode 100644
index 3dc446ec3..000000000
--- a/thirdparty/opal/include_target/OpalGenAsyncParamCtrl.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
- *
- *	File name =			$Workfile: OpalGenAsyncParamCtrl.h $
- *	SourceSafe path =	$Logfile: /SIMUPAR/soft/common/include_target/OpalGenAsyncParamCtrl.h $
- *	SourceSafe rev. =	$Revision: 2.8 $
- *	Last checked in =	$Date: 2009/12/15 14:42:27 $
- *	Last updated =		$Modtime: 7/31/02 10:25a $
- *	Last modified by =	$Author: AntoineKeirsbulck $
- *
- *-----------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------
- *
- *  Abstract:
- *
- *-----------------------------------------------------------------*/
-
-#include "OpalTypes.h"
-
-#ifndef OPAL_GENASYCPARAM_CTRL_H
-#define OPAL_GENASYCPARAM_CTRL_H
-
-#define	SENDASYNC_NB_FLOAT_PARAM		5
-#define	SENDASYNC_NB_STRING_PARAM		5
-#define	SENDASYNC_MAX_STRING_LENGTH		1000
-
-#define	RECVASYNC_NB_FLOAT_PARAM		5
-#define	RECVASYNC_NB_STRING_PARAM		5
-#define	RECVASYNC_MAX_STRING_LENGTH		1000
-
-#define	GENASYNC_NB_FLOAT_PARAM			12
-#define	GENASYNC_NB_STRING_PARAM		12
-#define	GENASYNC_MAX_STRING_LENGTH		1000
-
-
-// Align bytes
-#if defined(__GNUC__)
-#	undef	GNUPACK
-#	define	GNUPACK(x)		__attribute__ ((aligned(x),packed))
-#else
-#	undef	GNUPACK
-#	define	GNUPACK(x)
-#	if defined(__sgi)
-#		pragma pack(1)
-#	else
-#		pragma pack (push, 1)
-#	endif
-#endif
-
-
-//------------ LocalData ---------------
-typedef struct
-{
-	unsigned char	controllerID														;// ignored GNUPACK(1);
-	double			FloatParam[GENASYNC_NB_FLOAT_PARAM]									GNUPACK(1);
-	char			StringParam[GENASYNC_NB_STRING_PARAM][GENASYNC_MAX_STRING_LENGTH]	;// ignored GNUPACK(1);
-	UINT64_T		execStartCpuTime													GNUPACK(1);
-	UINT64_T		pauseStartCpuTime													GNUPACK(1);
-#ifdef RT
-	unsigned long long	modelSyncCpuTime												GNUPACK(1);
-#else
-	UINT64_T		modelSyncCpuTime													GNUPACK(1);
-#endif
-	double			modelTime															GNUPACK(1);
-
-} Opal_GenAsyncParam_Ctrl;
-
-
-typedef struct
-{
-	double			FloatParam[SENDASYNC_NB_FLOAT_PARAM]								GNUPACK(1);
-	char			StringParam[SENDASYNC_NB_STRING_PARAM][SENDASYNC_MAX_STRING_LENGTH]	;// ignored GNUPACK(1);
-
-} Opal_SendAsyncParam;
-
-typedef struct
-{
-	double			FloatParam[RECVASYNC_NB_FLOAT_PARAM]								GNUPACK(1);
-	char			StringParam[RECVASYNC_NB_STRING_PARAM][RECVASYNC_MAX_STRING_LENGTH]	;// ignored GNUPACK(1);
-
-} Opal_RecvAsyncParam;
-
-#if defined(__GNUC__)
-#	undef	GNUPACK
-#else
-#	if defined(__sgi)
-#		pragma pack(0)
-#	else
-#		pragma pack (pop)
-#	endif
-#endif
-
-#endif  // #ifndef OPAL_GENASYCPARAM_CTRL_H
diff --git a/thirdparty/opal/include_target/OpalPrint.h b/thirdparty/opal/include_target/OpalPrint.h
deleted file mode 100644
index da4cc3ba8..000000000
--- a/thirdparty/opal/include_target/OpalPrint.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
- *
- *	File name =			$Workfile: OpalPrint.h $
- *	SourceSafe path =	$Logfile: /SIMUPAR/soft/common/include_target/OpalPrint.h $
- *	SourceSafe rev. =	$Revision: 2.3 $
- *	Last checked in =	$Date: 2004/08/13 19:35:48 $
- *	Last updated =		$Modtime: 03-10-14 16:58 $Author: djibriln $
- *
- *-----------------------------------------------------------------*/
-
-#ifndef OPALPRINT_H
-#define OPALPRINT_H
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-#if defined (RTLAB) && !defined(IS_COMPILED_IN_CONTROLLER)  && !defined(IS_COMPILED_IN_METACONTROLLER)
-	int	OpalPrint(const char *format, ... );
-#else
-	#define OpalPrint printf
-#endif
-
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSystemCtrl_Register
-	*
-	* Input Parameters :
-	*		sysShMemName :	The name of shared memory.
-	*							
-	* Output Parameters :	NIL
-	*		
-	* Return :	EOK		Succes
-	*			-1		Cannot open shared memory.
-	* 
-	* Description :	Enable the OpalPrint function to send message via the OpalDisplay by opening a shared memory.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/	
-	int	OpalSystemCtrl_Register(char *sysShMemName); 
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSystemCtrl_UnRegister
-	*
-	* Input Parameters :
-	*		sysShMemName :	The name of shared memory.
-	*							
-	* Output Parameters :	NIL
-	*		
-	* Return :	EOK		Succes
-	* 
-	* Description :	Close the OpalPrint shared memory.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/	
-	int OpalSystemCtrl_UnRegister(char *sysMemName);
-
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSendFileName
-	*
-	* Input Parameters :
-	*		fileName :	Name of the file to be retrieved on reset
-	*		fileMode :  Specify 'a' for "Ascii", 'b' for "Binary"
-	*		fileType :  Set to 0. For internal use only.
-	*							
-	* Output Parameters :	NIL
-	*		
-	* Return :	EOK		Succes
-	* 
-	* Description :	Sends the name and type of a file so that RT-LAB retrieves it on reset.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/	
-	int	OpalSendFileName(char *fileName, char fileMode, int fileType);
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSendClosedFileName
-	*
-	* Input Parameters :
-	*		fileName :	Name of the file to be retrieved
-	*
-	* Output Parameters :	NIL
-	*
-	* Return :	EOK		Succes
-	*
-	* Description :	Sends the name of a file ready to be retrieved.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/
-	int	OpalSendClosedFileName(char *fileName);
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif
diff --git a/thirdparty/opal/include_target/OpalTypes.h b/thirdparty/opal/include_target/OpalTypes.h
deleted file mode 100644
index c07923ed0..000000000
--- a/thirdparty/opal/include_target/OpalTypes.h
+++ /dev/null
@@ -1,734 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
-
- *	File name =			$RCSfile: OpalTypes.h,v $
- *	CVS  path =			$Source: /git/RT-LAB/RT-LAB/soft/common/include_target/OpalTypes.h,v $
- *	CVS  rev. =			$Revision: 1.8 $
- *	Last checked in =	$Date: 2010/07/07 15:53:08 $
- *	Last modified by =	$Author: AntoineKeirsbulck $
- *
- *-----------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------
- *
- *  Abstract:
- *      Data types for use with MATLAB/SIMULINK and the Real-Time Workshop.
- *      Data types for use with XMATH/SYSTEMBUILD and AutoCode.
- *
- *      When compiling stand-alone model code, data types can be overridden
- *      via compiler switches.
- *
- *-----------------------------------------------------------------*/
-
-#ifndef __OPALTYPES__
-#define __OPALTYPES__
-
-#ifdef _WIN32
-	#ifndef WIN32
-	#define WIN32
-	#endif
-#endif
-
-#if defined(__QNXNTO__)
-#	include <inttypes.h>
-#endif
-
-/* =========================================================================
-	MATLAB
-	Inclure les types de tmwtypes.h (de Matlab) seulement si ce dernier
-	n'a pas déjà été inclus, sinon on a des erreurs de redefinition
-	avec gcc. Tous ce qui est inclus entre le #if qui suit et le #endif
-	correspondant est une copie du contenu de tmwtypes.h. Pour inclure
-	d'autre types, s'assurer de les mettre en dehors de la région délimitée
-	par ces #if __TMWTYPES__ / #endif
-*/
-#if ! defined(__TMWTYPES__)
-#include <limits.h>
-
-#ifndef __MWERKS__
-# ifdef __STDC__
-#  include <float.h>
-# else
-#  define FLT_MANT_DIG 24
-#  define DBL_MANT_DIG 53
-# endif
-#endif
-
-/*
- *      The following data types cannot be overridden when building MEX files.
- */
-#ifdef MATLAB_MEX_FILE
-# undef CHARACTER_T
-# undef INTEGER_T
-# undef BOOLEAN_T
-# undef REAL_T
-# undef TIME_T
-#endif
-
-/*
- *      The following define is used to emulate when all integer types are
- *      32-bits.  This is the case for TI C30/C40 DSPs which are RTW targets.
- */
-#ifdef DSP32
-# define INT8_T    int
-# define UINT8_T   unsigned int
-# define INT16_T   int
-# define UINT16_T  unsigned int
-#endif
-
-/*
- * The uchar_T, ushort_T and ulong_T types are needed for compilers which do
- * not allow defines to be specified, at the command line, with spaces in them.
- */
-
-typedef unsigned char  uchar_T;
-typedef unsigned short ushort_T;
-typedef unsigned long  ulong_T;
-
-
-
-/*=======================================================================*
- * Fixed width word size data types:                                     *
- *   int8_T, int16_T, int32_T     - signed 8, 16, or 32 bit integers     *
- *   uint8_T, uint16_T, uint32_T  - unsigned 8, 16, or 32 bit integers   *
- *   real32_T, real64_T           - 32 and 64 bit floating point numbers *
- *=======================================================================*/
-
-#ifndef INT8_T
-# if CHAR_MIN == -128
-#   define INT8_T char
-# elif SCHAR_MIN == -128
-#   define INT8_T signed char
-# endif
-#endif
-#ifdef INT8_T
-  typedef INT8_T int8_T;
-# ifndef UINT8_T
-#   define UINT8_T unsigned char
-# endif
-  typedef UINT8_T uint8_T;
-#endif
-
-
-#ifndef INT16_T
-# if SHRT_MAX == 0x7FFF
-#  define INT16_T short
-# elif INT_MAX == 0x7FFF
-#  define INT16_T int
-# endif
-#endif
-#ifdef INT16_T
- typedef INT16_T int16_T;
-#endif
-
-
-#ifndef UINT16_T
-# if SHRT_MAX == 0x7FFF    /* can't compare with USHRT_MAX on some platforms */
-#  define UINT16_T unsigned short
-# elif INT_MAX == 0x7FFF
-#  define UINT16_T unsigned int
-# endif
-#endif
-#ifdef UINT16_T
-  typedef UINT16_T uint16_T;
-#endif
-
-
-#ifndef INT32_T
-# if INT_MAX == 0x7FFFFFFF
-#  define INT32_T int
-# elif LONG_MAX == 0x7FFFFFFF
-#  define INT32_T long
-# endif
-#endif
-#ifdef INT32_T
- typedef INT32_T int32_T;
-#endif
-
-
-#ifndef UINT32_T
-# if INT_MAX == 0x7FFFFFFF
-#  define UINT32_T unsigned int
-# elif LONG_MAX == 0x7FFFFFFF
-#  define UINT32_T unsigned long
-# endif
-#endif
-#ifdef UINT32_T
- typedef UINT32_T uint32_T;
-#endif
-
-
-#ifndef REAL32_T
-# ifndef __MWERKS__
-#  if FLT_MANT_DIG >= 23
-#    define REAL32_T float
-#  endif
-# else
-#    define REAL32_T float
-# endif
-#endif
-#ifdef REAL32_T
-typedef REAL32_T real32_T;
-#endif
-
-#ifndef REAL64_T
-# ifndef __MWERKS__
-#  if DBL_MANT_DIG >= 52
-#    define REAL64_T double
-#  endif
-# else
-#    define REAL64_T double
-# endif
-#endif
-#ifdef REAL64_T
-  typedef REAL64_T real64_T;
-#endif
-
-/*=======================================================================*
- * Fixed width word size data types:                                     *
- *   int64_T                      - signed 64 bit integers               *
- *   uint64_T                     - unsigned 64 bit integers             *
- *=======================================================================*/
-
-#ifndef INT64_T
-# if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#   define INT64_T long
-#   define FMT64 ""
-# endif
-# if defined(__LP64__)
-#   define INT64_T long
-#   define FMT64 "L"
-# endif
-# if defined(__i386__) && defined(__linux__)
-#   define INT64_T long long
-#   define FMT64 "L"
-# endif
-# if defined(_MSC_VER)
-#   define INT64_T __int64
-#   define FMT64 "I64"
-# endif
-# if defined(__QNXNTO__)
-#   define INT64_T int64_t
-#  endif
-#endif
-#ifdef INT64_T
-# if defined(__i386__) && defined(__linux__)
- __extension__
-# endif
- typedef INT64_T int64_T;
-#endif
-
-
-#ifndef UINT64_T
-# if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#   define UINT64_T unsigned long
-# endif
-# if defined(__LP64__)
-#   define UINT64_T unsigned long
-# endif
-# if defined(__i386__) && defined(__linux__)
-#   define UINT64_T unsigned long long
-# endif
-# if defined(_MSC_VER)
-#   define UINT64_T unsigned __int64
-# endif
-# if defined(__QNXNTO__)
-#   define UINT64_T uint64_t
-#endif
-#endif
-#ifdef UINT64_T
-# if defined(__i386__) && defined(__linux__)
- __extension__
-# endif
- typedef UINT64_T uint64_T;
-#endif
-
-
-/*================================================================*
- *  Fixed-point data types:                                       *
- *     fixpoint_T     - 16 or 32-bit unsigned integers            *
- *     sgn_fixpoint_T - 16 or 32-bit signed integers              *
- *  Note, when building fixed-point applications, real_T is equal *
- *  to fixpoint_T and time_T is a 32-bit unsigned integer.        *
- *================================================================*/
-
-#ifndef FIXPTWS
-# define FIXPTWS 32
-#endif
-#if FIXPTWS != 16 && FIXPTWS != 32
-  "--> fixed-point word size (FIXPTWS) must be 16 or 32 bits"
-#endif
-
-#if FIXPTWS == 16
-  typedef uint16_T fixpoint_T;
-  typedef int16_T  sgn_fixpoint_T;
-#else
-  typedef uint32_T fixpoint_T;
-  typedef int32_T  sgn_fixpoint_T;
-#endif
-
-#ifdef FIXPT
-# define REAL_T fixpoint_T
-# define TIME_T uint32_T
-#endif
-
-
-
-/*===========================================================================*
- * General or logical data types where the word size is not guaranteed.      *
- *  real_T     - possible settings include real32_T, real64_T, or fixpoint_T *
- *  time_T     - possible settings include real64_T or uint32_T              *
- *  boolean_T                                                                *
- *  char_T                                                                   *
- *  int_T                                                                    *
- *  uint_T                                                                   *
- *  byte_T                                                                   *
- *===========================================================================*/
-
-#ifndef REAL_T
-# ifdef REAL64_T
-#   define REAL_T real64_T
-# else
-#   ifdef REAL32_T
-#     define REAL_T real32_T
-#   endif
-# endif
-#endif
-#ifdef REAL_T
-  typedef REAL_T real_T;
-#endif
-
-#ifndef TIME_T
-#  ifdef REAL_T
-#    define TIME_T real_T
-#  endif
-#endif
-#ifdef TIME_T
-  typedef TIME_T time_T;
-#endif
-
-#ifndef BOOLEAN_T
-# if defined(UINT8_T)
-#   define BOOLEAN_T UINT8_T
-# else
-#   define BOOLEAN_T unsigned int
-# endif
-#endif
-typedef BOOLEAN_T boolean_T;
-
-
-#ifndef CHARACTER_T
-#define CHARACTER_T char
-#endif
-typedef CHARACTER_T char_T;
-
-
-#ifndef INTEGER_T
-#define INTEGER_T int
-#endif
-typedef INTEGER_T int_T;
-
-
-#ifndef UINTEGER_T
-#define UINTEGER_T unsigned
-#endif
-typedef UINTEGER_T uint_T;
-
-
-#ifndef BYTE_T
-#define BYTE_T unsigned char
-#endif
-typedef BYTE_T byte_T;
-
-
-/*===========================================================================*
- * Define Complex Structures                                                 *
- *===========================================================================*/
-
-#ifndef CREAL32_T
-#  ifdef REAL32_T
-    typedef struct {
-      real32_T re, im;
-    } creal32_T;
-#    define CREAL32_T creal32_T
-#  endif
-#endif
-
-#ifndef CREAL64_T
-#  ifdef REAL64_T
-    typedef struct {
-      real64_T re, im;
-    } creal64_T;
-#    define CREAL64_T creal64_T
-#  endif
-#endif
-
-#ifndef CREAL_T
-#  ifdef REAL_T
-    typedef struct {
-      real_T re, im;
-    } creal_T;
-#    define CREAL_T creal_T
-#  endif
-#endif
-
-#ifndef CINT8_T
-#  ifdef INT8_T
-    typedef struct {
-      int8_T re, im;
-    } cint8_T;
-#    define CINT8_T cint8_T
-#  endif
-#endif
-
-#ifndef CUINT8_T
-#  ifdef UINT8_T
-    typedef struct {
-      uint8_T re, im;
-    } cuint8_T;
-#    define CUINT8_T cuint8_T
-#  endif
-#endif
-
-#ifndef CINT16_T
-#  ifdef INT16_T
-    typedef struct {
-      int16_T re, im;
-    } cint16_T;
-#    define CINT16_T cint16_T
-#  endif
-#endif
-
-#ifndef CUINT16_T
-#  ifdef UINT16_T
-    typedef struct {
-      uint16_T re, im;
-    } cuint16_T;
-#    define CUINT16_T cuint16_T
-#  endif
-#endif
-
-#ifndef CINT32_T
-#  ifdef INT32_T
-    typedef struct {
-      int32_T re, im;
-    } cint32_T;
-#    define CINT32_T cint32_T
-#  endif
-#endif
-
-#ifndef CUINT32_T
-#  ifdef UINT32_T
-    typedef struct {
-      uint32_T re, im;
-    } cuint32_T;
-#    define CUINT32_T cuint32_T
-#  endif
-#endif
-
-#else /* defined(__TMWTYPES__) */
-
-#ifdef OP_MATLABR12
-
-#ifndef INT64_T
-# if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#   define INT64_T long
-#   define FMT64 ""
-# endif
-# if defined(__LP64__)
-#   define INT64_T long
-#   define FMT64 "L"
-# endif
-# if defined(__i386__) && defined(__linux__)
-#   define INT64_T long long
-#   define FMT64 "L"
-# endif
-# if defined(_MSC_VER)
-#   define INT64_T __int64
-#   define FMT64 "I64"
-# endif
-# if defined(__QNXNTO__)
-#   define INT64_T int64_t
-#  endif
-#endif
-#ifdef INT64_T
-# if defined(__i386__) && defined(__linux__)
- __extension__
-# endif
- typedef INT64_T int64_T;
-#endif
-
-# ifndef UINT64_T
-#  if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#    define UINT64_T unsigned long
-#  endif
-# if defined(__LP64__)
-#   define UINT64_T unsigned long
-# endif
-#  if defined(__i386__) && defined(__linux__)
-#    define UINT64_T unsigned long long
-#  endif
-#  if defined(_MSC_VER)
-#    define UINT64_T unsigned __int64
-#  endif
-#  if defined(__QNXNTO__)
-#    define UINT64_T uint64_t
-#  endif
-# endif
-# ifdef UINT64_T
-#  if defined(__i386__) && defined(__linux__)
- __extension__
-#  endif
-typedef UINT64_T uint64_T;
-# endif /* UINT64_T */
-#endif /* OP_MATLABR12 */
-
-#endif /* ! defined(_	__) */
-/*
-  MATLAB
-  ===========================================================================
-*/
-
-/*=======================================================================*
- * Min and Max:                                                          *
- *   int8_T, int16_T, int32_T     - signed 8, 16, or 32 bit integers     *
- *   uint8_T, uint16_T, uint32_T  - unsigned 8, 16, or 32 bit integers   *
- *=======================================================================*/
-
-#define  OP_MAX_int8_T      ((int8_T)(127))            /* 127  */
-#define  OP_MIN_int8_T      ((int8_T)(-128))           /* -128 */
-#define  OP_MAX_uint8_T     ((uint8_T)(255))           /* 255  */
-#define  OP_MIN_uint8_T     ((uint8_T)(0))
-
-#define  OP_MAX_int16_T     ((int16_T)(32767))         /* 32767 */
-#define  OP_MIN_int16_T     ((int16_T)(-32768))        /* -32768 */
-#define  OP_MAX_uint16_T    ((uint16_T)(65535))        /* 65535 */
-#define  OP_MIN_uint16_T    ((uint16_T)(0))
-
-#define  OP_MAX_int32_T     ((int32_T)(2147483647))    /* 2147483647  */
-#define  OP_MIN_int32_T     ((int32_T)(-2147483647-1)) /* -2147483648 */
-#define  OP_MAX_uint32_T    ((uint32_T)(0xFFFFFFFFU))  /* 4294967295  */
-#define  OP_MIN_uint32_T    ((uint32_T)(0))
-
-#ifdef INT64_T
-#define  OP_MAX_int64_T     ((int64_T)(9223372036854775807))
-#define  OP_MIN_int64_T     ((int64_T)(-9223372036854775807-1))
-#endif
-#ifdef UINT64_T
-#define  OP_MAX_uint64_T    ((uint64_T)(0xFFFFFFFFFFFFFFFFULL))
-#define  OP_MIN_uint64_T    ((uint64_T)(0))
-#endif
-
-/*
-*
-*	Equivalent type between SIMULINK and SYSTEMBUILD
-*
-*/
-#ifndef _SA_TYPES
-#define _SA_TYPES
-	typedef	real_T		RT_FLOAT;
-	typedef int_T		RT_INTEGER;
-	typedef boolean_T	RT_BOOLEAN;
-	typedef time_T		RT_DURATION;
-#endif	/* _SA_TYPES */
-
-
-#ifndef FALSE
-	#define FALSE       0
-#endif
-#ifndef TRUE
-	#define TRUE        1
-#endif
-
-
-#ifdef INT64_T
-#	if ! defined(LONGLONG_MAX)
-#		define LONGLONG_MAX		OP_MAX_int64_T
-#	endif
-#	if ! defined(LONGLONG_MIN)
-#		define LONGLONG_MIN		OP_MIN_int64_T
-#	endif
-#endif
-#ifdef UINT64_T
-#	if ! defined(ULONGLONG_MAX)
-#		define ULONGLONG_MAX	OP_MAX_uint64_T
-#	endif
-#endif
-
-
-// Some define for partability
-#if defined(WIN32)	/* =============================================================== */
-
-	typedef unsigned int		pid_t;
-	typedef int					pthread_t;
-#	ifndef PATH_MAX
-#		define PATH_MAX (MAX_PATH)
-#	endif
-#	define OP_SLEEP( msec )		Sleep( msec )
-#	define pthread_self			GetCurrentThreadId
-#	define vsnprintf			_vsnprintf
-#	define snprintf				_snprintf
-#	define FILE_ALL_RW_PERMS	(_S_IWRITE | _S_IREAD)
-
-#elif defined(__QNX__)	/* =========================================================== */
-
-#	if ! defined(_IEEE1394_H_)
-	typedef int				HANDLE;
-#	endif /*  ! _IEEE1394_H_ */
-	typedef int				HMODULE;
-
-#	if defined(__QNXNTO__)
-
-#		define _MAX_PATH	(PATH_MAX)
-//#ifndef _strdup
-//#		define _strdup(s)	strdup(s)
-//#endif
-#		define _strlwr(s)	strlwr(s)
-
-#	else /*  ! __QNXNTO  */
-
-		typedef int				pthread_t;
-#		define pthread_self		getpid
-
-#	endif /* __QNXNTO__  */
-
-#	define MAX_PATH (PATH_MAX)
-#	define OP_SLEEP( msec )		delay( msec )
-//#	define _getcwd(b,l)			getcwd(b,l)
-
-#	define FILE_ALL_RW_PERMS	(S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH)
-
-
-#elif defined(__linux__)	/* ======================================================= */
-
-	typedef int				HANDLE;
-	typedef int				HMODULE;
-#	define MAX_PATH (PATH_MAX)
-#	define _MAX_PATH (PATH_MAX)
-
-#	include <sys/time.h>
-#	define OP_SLEEP( msec )						\
-	{	struct timeval tv;						\
-		tv.tv_sec = (msec) / 1000;				\
-		tv.tv_usec = ((msec) % 1000) * 1000;	\
-		select(0, NULL, NULL, NULL, &tv);		\
-	}
-
-//#ifndef _strdup
-//#	define _strdup(s)			strdup(s)
-//#endif
-//#	define _getcwd(b,l)			getcwd(b,l)
-//#	define _access(s1,s2)		access(s1,s2)
-//#	define _alloca(s)			alloca(s)
-//#	define _mkdir(s)			mkdir(s)
-#	define stricmp(s1,s2)		strcasecmp(s1,s2)
-#	define strnicmp(s1,s2,n)	strncasecmp(s1,s2,n)
-#	define FILE_ALL_RW_PERMS	(S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH)
-
-#elif defined(__sun__) || defined(__sgi)
-	typedef int HANDLE;
-	typedef int	HMODULE;
-#	define MAX_PATH (PATH_MAX)
-#	define _MAX_PATH (PATH_MAX)
-
-#	define	stricmp(s1, s2)			strcasecmp(s1, s2)
-#	define	strnicmp(s1, s2, len)	strncasecmp(s1, s2, len)
-//#	define	_strdup(s)				strdup(s)
-//#	define _getcwd(b,l)				getcwd(b,l)
-//#	define _alloca(s)				alloca(s)
-
-#endif /*  WIN32  /  __QNX__  /  __linux__  //  __sun__  // __sgi  //======================================= */
-
-//#ifndef WIN32
-//#include <string.h>
-//#include <strings.h>
-//#include <sys/stat.h>
-//#include <unistd.h>
-
-//#ifdef _strdup
-//#undef _strdup
-//#warning _strdup should not be #defined!
-//#endif
-//
-//# ifndef __QNX__
-//	static inline int stricmp(char const * s1, char const *s2) {
-//		return strcasecmp(s1,s2);
-//	}
-//	static inline int strnicmp(char const * s1, char const *s2, size_t l) {
-//		return strncasecmp(s1,s2,l);
-//	}
-//// QDT: Not possible due o libOpalCore and libOpalOhci depending on each other
-////	static inline int _stricmp(char const * s1, char const *s2) {
-////		return strcasecmp(s1,s2);
-////	}
-//#  ifndef _stricmp
-//#	define _stricmp stricmp
-//#  endif
-//	static inline int _strnicmp(char const * s1, char const *s2, size_t l) {
-//		return strncasecmp(s1,s2,l);
-//	}
-//	static inline char * _strdup(const char * s) {
-//		return strdup(s);
-//	}
-////	static inline void * _alloca(size_t size) {
-////		return alloca(size);
-////	}
-//# endif
-//	static inline pid_t _getpid() {
-//		return getpid();
-//	}
-//	static inline char * _getcwd(char * buffer, size_t size) {
-//		return getcwd(buffer, size);
-//	}
-//	static inline int _mkdir(const char *path, mode_t mode) {
-//		return mkdir(path, mode);
-//	}
-//	static inline int _access(const char *pathname, int mode) {
-//		return access(pathname, mode);
-//	}
-//	static inline int _close(int fildes) {
-//		return close(fildes);
-//	}
-//#endif
-
-typedef struct
-{
-	union
-	{
-		struct { unsigned char s_b1,s_b2,s_b3,s_b4; } S_un_b;
-		uint32_T	S_addr;
-	} S_un;
-} OP_IN_ADDR;
-
-
-typedef enum
-{
-	TR_PRIORITY_NORMAL = 0,
-	TR_PRIORITY_HIGH,
-	TR_MAX_PRIORITY
-
-}	TR_PRIORITY;
-
-#define ROUND_ST(x)	(int)((x)+0.5)
-#define FLOAT_EQU(x,y) (((((x)-(y)) >= 0) && (((x)-(y)) < 0.0000001)) || ((((y)-(x)) >= 0) && (((y)-(x)) < 0.0000001))  )
-
-#if ! defined(OP_API_H)
-typedef	unsigned short	OP_API_INSTANCE_ID;
-typedef unsigned long OP_LOAD_ID;
-#endif
-
-#if ! defined(EOK)
-#	define	EOK	0
-#else
-#	if EOK != 0
-	Generated error: EOK should be 0
-#	endif
-#endif
-
-#define NUM_MODEL_ARGS	8
-
-typedef unsigned long OP_FULL_MODEL_ID;
-
-#endif  /* __OPALTYPES__ */
diff --git a/thirdparty/xilinx/Makefile b/thirdparty/xilinx/Makefile
new file mode 100644
index 000000000..9bd95f430
--- /dev/null
+++ b/thirdparty/xilinx/Makefile
@@ -0,0 +1,28 @@
+LIB = libxil.so
+
+PREFIX ?= /usr/local
+
+SRCS  = $(wildcard src/*.c)
+SRCS += $(wildcard orig/*/src/*.c)
+OBJS  = $(SRCS:c=o)
+
+CC = gcc
+CFLAGS = -O3 -fPIC -Iinclude/xilinx -Iorig/common_v1_00_a/src -Wno-int-conversion -Wno-pointer-to-int-cast -Wno-int-to-pointer-cast
+
+ifdef DEBUG
+	CFLAGS += -DDEBUG -DXDEBUG_WARNING -g
+endif
+
+all: $(LIB)
+
+$(LIB): $(OBJS)
+	$(CC) -shared -o $@ $^
+
+clean:
+	rm -f $(LIB) $(OBJS)
+
+install: $(LIB)
+	mkdir -p $(PREFIX)/include/xilinx
+	install -m 0644 $(LIB) $(PREFIX)/lib
+	install -m 0644 include/xilinx/*.h $(PREFIX)/include/xilinx
+	ldconfig
diff --git a/thirdparty/xilinx/README.md b/thirdparty/xilinx/README.md
new file mode 100644
index 000000000..c42363e74
--- /dev/null
+++ b/thirdparty/xilinx/README.md
@@ -0,0 +1 @@
+These drivers are taken from https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers
\ No newline at end of file
diff --git a/thirdparty/xilinx/include/xilinx/xaxidma.h b/thirdparty/xilinx/include/xilinx/xaxidma.h
new file mode 100644
index 000000000..86f62dd65
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxidma.h
@@ -0,0 +1,741 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma.h
+* @addtogroup axidma_v9_0
+* @{
+* @details
+*
+* This is the driver API for the AXI DMA engine.
+*
+* For a full description of DMA features, please see the hardware spec. This
+* driver supports the following features:
+*
+*   - Scatter-Gather DMA (SGDMA)
+*   - Simple DMA
+*   - Interrupts
+*   - Programmable interrupt coalescing for SGDMA
+*   - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA
+*     engine
+*
+* <b>Simple DMA</b>
+*
+* Simple DMA allows the application to define a single transaction between DMA
+* and Device. It has two channels: one from the DMA to Device and the other
+* from Device to DMA. Application has to set the buffer address and
+* length fields to initiate the transfer in respective channel.
+*
+* <b>Transactions</b>
+*
+* The object used to describe a transaction is referred to as a Buffer
+* Descriptor (BD). Buffer descriptors are allocated in the user application.
+* The user application needs to set buffer address, transfer length, and
+* control information for this transfer. The control information includes
+* SOF and EOF. Definition of those masks are in xaxidma_hw.h
+*
+* <b>Scatter-Gather DMA</b>
+*
+* SGDMA allows the application to define a list of transactions in memory which
+* the hardware will process without further application intervention. During
+* this time, the application is free to continue adding more work to keep the
+* Hardware busy.
+*
+* User can check for the completion of transactions through polling the
+* hardware, or interrupts.
+*
+* SGDMA processes whole packets. A packet is defined as a series of
+* data bytes that represent a message. SGDMA allows a packet of data to be
+* broken up into one or more transactions. For example, take an Ethernet IP
+* packet which consists of a 14 byte header followed by a 1 or more bytes of
+* payload. With SGDMA, the application may point a BD to the header and another
+* BD to the payload, then transfer them as a single message. This strategy can
+* make a TCP/IP stack more efficient by allowing it to keep packet header and
+* data in different memory regions instead of assembling packets into
+* contiguous blocks of memory.
+*
+* <b>BD Ring Management</b>
+*
+* BD rings are shared by the software and the hardware.
+*
+* The hardware expects BDs to be setup as a linked list. The DMA hardware walks
+* through the list by following the next pointer field of a completed BD.
+* The hardware stops processing when the just completed BD is the same as the
+* BD specified in the Tail Ptr register in the hardware.
+*
+* The last BD in the ring is linked to the first BD in the ring.
+*
+* All BD management are done inside the driver. The user application should not
+* directly modify the BD fields. Modifications to the BD fields should always
+* go through the specific API functions.
+*
+* Within the ring, the driver maintains four groups of BDs. Each group consists
+* of 0 or more adjacent BDs:
+*
+*   - Free: The BDs that can be allocated by the application with
+*     XAxiDma_BdRingAlloc().
+*
+*   - Pre-process: The BDs that have been allocated with
+*     XAxiDma_BdRingAlloc(). These BDs are under application control. The
+*     application modifies these BDs through driver API to prepare them
+*     for DMA transactions.
+*
+*   - Hardware: The BDs that have been enqueued to hardware with
+*     XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a
+*     state of awaiting hardware processing, in process, or processed by
+*     hardware. It is considered an error for the application to change BDs
+*     while they are in this group. Doing so can cause data corruption and lead
+*     to system instability.
+*
+*   - Post-process: The BDs that have been processed by hardware and have
+*     been extracted from the Hardware group with XAxiDma_BdRingFromHw().
+*     These BDs are under application control. The application can check the
+*     transfer status of these BDs. The application use XAxiDma_BdRingFree()
+*     to put them into the Free group.
+*
+* BDs are expected to transition in the following way for continuous
+* DMA transfers:
+* <pre>
+*
+*         XAxiDma_BdRingAlloc()                   XAxiDma_BdRingToHw()
+*   Free ------------------------> Pre-process ----------------------> Hardware
+*                                                                      |
+*    /|\                                                               |
+*     |   XAxiDma_BdRingFree()                  XAxiDma_BdRingFromHw() |
+*     +--------------------------- Post-process <----------------------+
+*
+* </pre>
+*
+* When a DMA transfer is to be cancelled before enqueuing to hardware,
+* application can return the requested BDs to the Free group using
+* XAxiDma_BdRingUnAlloc(), as shown below:
+* <pre>
+*
+*         XAxiDma_BdRingUnAlloc()
+*   Free <----------------------- Pre-process
+*
+* </pre>
+*
+* The API provides functions for BD list traversal:
+* - XAxiDma_BdRingNext()
+* - XAxiDma_BdRingPrev()
+*
+* These functions should be used with care as they do not understand where
+* one group ends and another begins.
+*
+* <b>SGDMA Descriptor Ring Creation</b>
+*
+* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring
+* is allocated by the application, and it has to be contiguous. Physical
+* address is required to setup the BD ring.
+*
+* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of
+* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be
+* used to find out how many BDs can be allocated for certain amount of memory.
+*
+* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if
+* the BDs have same types of controls, for example, SOF and EOF. After
+* using the XAxiDma_BdRingClone(), the application only needs to setup the
+* buffer address and transfer length. Note that certain BDs in one packet,
+* for example, the first BD and the last BD, may need to setup special
+* control information.
+*
+* <b>Descriptor Ring State Machine</b>
+*
+* There are two states of the BD ring:
+*
+*   - HALTED (H), where hardware is not running
+*
+*   - NOT HALTED (NH), where hardware is running
+*
+* The following diagram shows the state transition for the DMA engine:
+*
+* <pre>
+*   _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(),   ______
+*   |   |               or XAxiDma_Resume()                    |    |
+*   | H |----------------------------------------------------->| NH |
+*   |   |<-----------------------------------------------------|    |
+*   -----   XAxiDma_Pause() or XAxiDma_Reset()                 ------
+* </pre>
+*
+* <b>Interrupt Coalescing</b>
+*
+* SGDMA provides control over the frequency of interrupts through interrupt
+* coalescing. The DMA engine provides two ways to tune the interrupt
+* coalescing:
+*
+* - The packet threshold counter. Interrupt will fire once the
+*   programmable number of packets have been processed by the engine.
+*
+* - The packet delay timer counter. Interrupt will fire once the
+*   programmable amount of time has passed after processing the last packet,
+*   and no new packets to process. Note that the interrupt will only fire if
+*   at least one packet has been processed.
+*
+* <b> Interrupt </b>
+*
+* Interrupts are handled by the user application. Each DMA channel has its own
+* interrupt ID. The driver provides APIs to enable/disable interrupt,
+* and tune the interrupt frequency regarding to packet processing frequency.
+*
+* <b> Software Initialization </b>
+*
+*
+* To use the Simple mode DMA engine for transfers, the following setup is
+* required:
+*
+* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
+*   initializes a driver instance for the given DMA engine and resets the
+*   engine.
+*
+* - Enable interrupts if chosen to use interrupt mode. The application is
+*   responsible for setting up the interrupt system, which includes providing
+*   and connecting interrupt handlers and call back functions, before
+*   enabling the interrupts.
+*
+* - Set the buffer address and length field in respective channels to start
+*   the DMA transfer
+*
+* To use the SG mode DMA engine for transfers, the following setup are
+* required:
+*
+* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
+*   initializes a driver instance for the given DMA engine and resets the
+*   engine.
+*
+* - BD Ring creation. A BD ring is needed per DMA channel and can be built by
+*   calling XAxiDma_BdRingCreate().
+*
+* - Enable interrupts if chose to use interrupt mode. The application is
+*   responsible for setting up the interrupt system, which includes providing
+*   and connecting interrupt handlers and call back functions, before
+*   enabling the interrupts.
+*
+* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for
+*   the first time or after a reset, and XAxiDma_BdRingToHw() if the channel
+*   is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not
+*   running will not put the BDs to the hardware, and the BDs will be processed
+*   later when the DMA channel is started through XAxiDma_BdRingStart().
+*
+* <b> How to start DMA transactions </b>
+*
+* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware
+* to start DMA transfers.
+*
+* For both channels, if the DMA engine is currently stopped (using
+* XAxiDma_Pause()), the newly added BDs will be accepted but not processed
+* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed,
+* using XAxiDma_Resume().
+*
+* <b> Software Post-Processing on completed DMA transactions </b>
+*
+* If the interrupt system has been set up and the interrupts are enabled,
+* a DMA channels notifies the software about the completion of a transfer
+* through interrupts. Otherwise, the user application can poll for
+* completions of the BDs, using XAxiDma_BdRingFromHw() or
+* XAxiDma_BdHwCompleted().
+*
+* - Once BDs are finished by a channel, the application first needs to fetch
+*   them from the channel using XAxiDma_BdRingFromHw().
+*
+* - On the TX side, the application now could free the data buffers attached to
+*   those BDs as the data in the buffers has been transmitted.
+*
+* - On the RX side, the application now could use the received data in the
+*	buffers attached to those BDs.
+*
+* - For both channels, completed BDs need to be put back to the Free group
+*   using XAxiDma_BdRingFree(), so they can be used for future transactions.
+*
+* - On the RX side, it is the application's responsibility to have BDs ready
+*   to receive data at any time. Otherwise, the RX channel refuses to
+*   accept any data if it has no RX BDs.
+*
+* <b> Examples </b>
+*
+* We provide five examples to show how to use the driver API:
+* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer
+* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.
+* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer
+* - One for simple polling mode (xaxidma_example_simple_poll.c)
+* - One for simple Interrupt mode (xaxidma_example_simple_intr.c)
+*
+* <b> Address Translation </b>
+*
+* All buffer addresses and BD addresses for the hardware are physical
+* addresses. The user application is responsible to provide physical buffer
+* address for the BD upon BD ring creation. The user application accesses BD
+* through its virtual addess. The driver maintains the address translation
+* between the physical and virtual address for BDs.
+*
+* <b> Cache Coherency </b>
+*
+* This driver expects all application buffers attached to BDs to be in cache
+* coherent memory. If cache is used in the system, buffers for transmit MUST
+* be flushed from the cache before passing the associated BD to this driver.
+* Buffers for receive MUST be invalidated before accessing the data.
+*
+* <b> Alignment </b>
+*
+* For BDs:
+*
+* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT.
+* This is the smallest alignment allowed by both hardware and software for them
+* to properly work.
+*
+* If the descriptor ring is to be placed in cached memory, alignment also MUST
+* be at least the processor's cache-line size. Otherwise, system instability
+* occurs. For alignment larger than the cache line size, multiple cache line
+* size alignment is required.
+*
+* Aside from the initial creation of the descriptor ring (see
+* XAxiDma_BdRingCreate()), there are no other run-time checks for proper
+* alignment of BDs.
+*
+* For application data buffers:
+*
+* Application data buffers may reside on any alignment if DRE is built into the
+* hardware. Otherwise, application data buffer must be word-aligned. The word
+* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and
+* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.
+*
+* For scatter gather transfers that have more than one BDs in the chain of BDs,
+* Each BD transfer length must be multiple of word too. Otherwise, internal
+* error happens in the hardware.
+*
+* <b> Error Handling </b>
+*
+* The DMA engine will halt on all error conditions. It requires the software
+* to do a reset before it can start process new transfer requests.
+*
+* <b> Restart After Stopping </b>
+*
+* After the DMA engine has been stopped (through reset or reset after an error)
+* the software keeps track of the current BD pointer when reset happens, and
+* processing of BDs can be resumed through XAxiDma_BdRingStart().
+*
+* <b> Limitations </b>
+*
+* This driver does not have any mechanisms for mutual exclusion. It is up to
+* the application to provide this protection.
+*
+* <b> Hardware Defaults & Exclusive Use </b>
+*
+* After the initialization or reset, the DMA engine is in the following
+* default mode:
+* - All interrupts are disabled.
+*
+* - Interrupt coalescing counter is 1.
+*
+* - The DMA engine is not running (halted). Each DMA channel is started
+*   separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer
+*   yet, or XAxiDma_BdRingStart() otherwise.
+*
+* The driver has exclusive use of the registers and BDs. All accesses to the
+* registers and BDs should go through the driver interface.
+*
+* <b> Debug Print </b>
+*
+* To see the debug print for the driver, please put "-DDEBUG" as the extra
+* compiler flags in software platform settings. Also comment out the line in
+* xdebug.h: "#undef DEBUG".
+*
+* <b>Changes From v1.00a</b>
+*
+* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int
+* . We added XAxiDma_LookupConfig() so that user does not need to look for the
+* hardware settings anymore.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+*		      New API added for simple DMA mode are
+*			- XAxiDma_Busy
+*			- XAxiDma_SimpleTransfer
+*		      New Macros added for simple DMA mode are
+* 			- XAxiDma_HasSg
+* 			- XAxiDma_IntrEnable
+* 			- XAxiDma_IntrGetEnabled
+* 			- XAxiDma_IntrDisable
+* 			- XAxiDma_IntrGetIrq
+* 			- XAxiDma_IntrAckIrq
+* 5.00a srt  08/25/11  Added support for memory barrier and modified
+*			Cache Macros to have a common API for Microblaze
+*			and Zynq.
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode.
+*		      - Changed APIs:
+*			* XAxiDma_GetRxRing(InstancePtr, RingIndex)
+*			* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*        					u32 BuffAddr, u32 Length,
+*						int Direction, int RingIndex)
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+*					u32 LenBytes, u32 LengthMask)
+*       		* XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+*			* XAxiDma_BdGetLength(BdPtr, LengthMask)
+*		       - New APIs
+*			* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*			- New API:
+*			  XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
+* 7.01a srt  10/26/12  - Fixed issue with driver as it fails with IP version
+*		         < 6.00a as the parameter C_NUM_*_CHANNELS is not
+*			 applicable.
+*		       - Changed the logic of MCDMA BD fields Set APIs, to
+*			 clear the field first and then set it.
+* 7.02a srt  01/23/13  Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
+*		       (CR 691867)
+*		       Updated DDR base address for IPI designs (CR 703656).
+* 8.0   adk  19/12/13  Updated as per the New Tcl API's
+*	srt  01/29/14  Added support for Micro DMA Mode and cyclic mode of
+*		       operations.
+*		      - New APIs:
+*			* XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+ *			* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
+* 8.1   adk  20/01/15  Added support for peripheral test. Created the self
+*		       test example to include it on peripheral test's(CR#823144).
+* 8.1   adk  29/01/15  Added the sefltest api (XAxiDma_Selftest) to the driver source files
+* 		      (xaxidma_selftest.c) and called this from the selftest example
+* 9.0 	adk  27/07/15  Added support for 64-bit Addressing.
+* 9.0   adk  19/08/15  Fixed CR#873125 DMA SG Mode example tests are failing on
+*		       HW in 2015.3.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XAXIDMA_H_   /* prevent circular inclusions */
+#define XAXIDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xaxidma_bdring.h"
+#ifdef __MICROBLAZE__
+#include "xenv.h"
+#else
+#include <string.h>
+#include "xil_cache.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The XAxiDma driver instance data. An instance must be allocated for each DMA
+ * engine in use.
+ */
+typedef struct XAxiDma {
+	u32 RegBase;		/* Virtual base address of DMA engine */
+
+	int HasMm2S;		/* Has transmit channel */
+	int HasS2Mm;		/* Has receive channel */
+	int Initialized;	/* Driver has been initialized */
+	int HasSg;
+
+	XAxiDma_BdRing TxBdRing;     /* BD container management for TX channel */
+	XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
+	int TxNumChannels;
+	int RxNumChannels;
+	int MicroDmaMode;
+	int AddrWidth;		  /**< Address Width */
+} XAxiDma;
+
+/**
+ * The configuration structure for AXI DMA engine
+ *
+ * This structure passes the hardware building information to the driver
+ */
+typedef struct {
+	u32 DeviceId;
+	u32 BaseAddr;
+
+	int HasStsCntrlStrm;
+	int HasMm2S;
+	int HasMm2SDRE;
+	int Mm2SDataWidth;
+	int HasS2Mm;
+	int HasS2MmDRE;
+	int S2MmDataWidth;
+	int HasSg;
+	int Mm2sNumChannels;
+	int S2MmNumChannels;
+	int Mm2SBurstSize;
+	int S2MmBurstSize;
+	int MicroDmaMode;
+	int AddrWidth;		  /**< Address Width */
+} XAxiDma_Config;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/*****************************************************************************/
+/**
+* Get Transmit (Tx) Ring ptr
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	Pointer to the Tx Ring
+*
+* @note		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr)
+* 		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetTxRing(InstancePtr) \
+			(&((InstancePtr)->TxBdRing))
+
+/*****************************************************************************/
+/**
+* Get Receive (Rx) Ring ptr
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	Pointer to the Rx Ring
+*
+* @note
+* 		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetRxRing(InstancePtr) \
+			(&((InstancePtr)->RxBdRing[0]))
+
+/*****************************************************************************/
+/**
+* Get Receive (Rx) Ring ptr of a Index
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+* @param	RingIndex is the channel Index.
+*
+* @return	Pointer to the Rx Ring
+*
+* @note
+* 		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr,
+						int RingIndex)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \
+			(&((InstancePtr)->RxBdRing[RingIndex]))
+
+/*****************************************************************************/
+/**
+* This function checks whether system is configured as Simple or
+* Scatter Gather mode
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+*		- TRUE if configured as SG mode
+*		- FALSE if configured as simple mode
+*
+* @note		None
+*
+*****************************************************************************/
+#define XAxiDma_HasSg(InstancePtr)	((InstancePtr)->HasSg) ? TRUE : FALSE
+
+/*****************************************************************************/
+/**
+ * This function enables interrupts specified by the Mask in specified
+ * direction, Interrupts that are not in the mask are not affected.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be enabled
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @return	None
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrEnable(InstancePtr, Mask, Direction) 	\
+	XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
+			| (Mask & XAXIDMA_IRQ_ALL_MASK))
+
+
+/*****************************************************************************/
+/**
+ * This function gets the mask for the interrupts that are currently enabled
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	The bit mask for the interrupts that are currently enabled
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define   XAxiDma_IntrGetEnabled(InstancePtr, Direction)	\
+			XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
+							XAXIDMA_IRQ_ALL_MASK)
+
+
+
+/*****************************************************************************/
+/**
+ * This function disables interrupts specified by the Mask. Interrupts that
+ * are not in the mask are not affected.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be disabled
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @return	None
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+ #define XAxiDma_IntrDisable(InstancePtr, Mask, Direction)	\
+		XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
+			& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
+
+
+/*****************************************************************************/
+/**
+ * This function gets the interrupts that are asserted.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	The bit mask for the interrupts asserted.
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrGetIrq(InstancePtr, Direction)	\
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
+							XAXIDMA_IRQ_ALL_MASK)
+
+/*****************************************************************************/
+/**
+ * This function acknowledges the interrupts that are specified in Mask
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be acknowledge
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	None
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction)	\
+			XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
+			(Mask) & XAXIDMA_IRQ_ALL_MASK)
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization and control functions in xaxidma.c
+ */
+XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
+int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
+void XAxiDma_Reset(XAxiDma * InstancePtr);
+int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
+int XAxiDma_Pause(XAxiDma * InstancePtr);
+int XAxiDma_Resume(XAxiDma * InstancePtr);
+u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
+u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
+	int Direction);
+int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select);
+int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select);
+int XAxiDma_Selftest(XAxiDma * InstancePtr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xaxidma_bd.h b/thirdparty/xilinx/include/xilinx/xaxidma_bd.h
new file mode 100644
index 000000000..0b8879ce1
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxidma_bd.h
@@ -0,0 +1,679 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_bd.h
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Buffer descriptor (BD) management API.
+ *
+ * <b> Buffer Descriptors </b>
+ *
+ * A BD defines a DMA transaction (see "Transaction" section in xaxidma.h).
+ * All accesses to a BD go through this set of API.
+ *
+ * The XAxiDma_Bd structure defines a BD. The first XAXIDMA_BD_HW_NUM_BYTES
+ * are shared between hardware and software.
+ *
+ * <b> Actual Transfer Length </b>
+ *
+ * The actual transfer length for receive could be smaller than the requested
+ * transfer length. The hardware sets the actual transfer length in the
+ * completed BD. The API to retrieve the actual transfer length is
+ * XAxiDma_GetActualLength().
+ *
+ * <b> User IP words </b>
+ *
+ * There are 5 user IP words in each BD.
+ *
+ * If hardware does not have the StsCntrl stream built in, then these words
+ * are not usable. Retrieving these words get a NULL pointer and setting
+ * these words results an error.
+ *
+ * <b> Performance </b>
+ *
+ * BDs are typically in a non-cached memory space. Reducing the number of
+ * I/O operations to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 5.00a srt  08/25/11 Changed Cache Macros to have a common API for Zynq
+ *		           and Microblaze.
+ * 6.00a srt  01/24/12 Added APIs to support Multi-Channel DMA:
+ *			XAxiDma_BdSetTId()
+ *			XAxiDma_BdGetTId()
+ *			XAxiDma_BdSetTDest()
+ *			XAxiDma_BdGetTDest()
+ *			XAxiDma_BdSetTUser()
+ *			XAxiDma_BdGetTUser()
+ *			XAxiDma_BdSetARCache()
+ *			XAxiDma_BdGetARCache()
+ *			XAxiDma_BdSetARUser()
+ *			XAxiDma_BdGetARUser()
+ *			XAxiDma_BdSetStride()
+ *			XAxiDma_BdGetStride()
+ *			XAxiDma_BdSetVSize()
+ *			XAxiDma_BdGetVSize()
+ *			- Changed APIs
+ *			XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+ *			XAxiDma_BdGetLength(BdPtr, LengthMask)
+ *			XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr,
+ *					u32 LenBytes, u32 LengthMask)
+ * 7.01a srt  10/26/12  Changed the logic of MCDMA BD fields Set APIs, to
+ *			clear the field first and set it.
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode.
+ *
+ * </pre>
+ *****************************************************************************/
+
+#ifndef XAXIDMA_BD_H_    /* To prevent circular inclusions */
+#define XAXIDMA_BD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xaxidma_hw.h"
+#include "xstatus.h"
+#include "xdebug.h"
+#include "xil_cache.h"
+
+#ifdef __MICROBLAZE__
+#include "xenv.h"
+#else
+#include <string.h>
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The XAxiDma_Bd is the type for a buffer descriptor (BD).
+ */
+
+typedef UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ * Define methods to flush and invalidate cache for BDs should they be
+ * located in cached memory.
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XAXIDMA_CACHE_FLUSH(BdPtr)
+#define XAXIDMA_CACHE_INVALIDATE(BdPtr)
+#else
+#define XAXIDMA_CACHE_FLUSH(BdPtr) \
+	Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
+
+#define XAXIDMA_CACHE_INVALIDATE(BdPtr) \
+	Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param	BaseAddress is the base address of the BD to read
+* @param	Offset is the word offset to be read
+*
+* @return	The 32-bit value of the field
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset)
+*
+******************************************************************************/
+#define XAxiDma_BdRead(BaseAddress, Offset)				\
+	(*(u32 *)((UINTPTR)((void *)(BaseAddress)) + (u32)(Offset)))
+
+/*****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param	BaseAddress is the base address of the BD to write
+* @param	Offset is the word offset to be written
+* @param	Data is the 32-bit value to write to the field
+*
+* @return	None.
+*
+* @note
+* 		C-style signature:
+*		void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XAxiDma_BdWrite(BaseAddress, Offset, Data)			\
+	(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)
+
+/*****************************************************************************/
+/**
+ * Zero out BD specific fields. BD fields that are for the BD ring or for the
+ * system hardware build information are not touched.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdClear(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdClear(BdPtr)                    \
+  memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \
+    XAXIDMA_BD_BYTES_TO_CLEAR)
+
+/*****************************************************************************/
+/**
+ * Get the control bits for the BD
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	The bit mask for the control of the BD
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetCtrl(BdPtr)				\
+		(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET)	\
+		& XAXIDMA_BD_CTRL_ALL_MASK)
+/*****************************************************************************/
+/**
+ * Retrieve the status of a BD
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_***
+ *		values defined in xaxidma_hw.h to interpret the returned value
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetSts(BdPtr)              \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		XAXIDMA_BD_STS_ALL_MASK)
+/*****************************************************************************/
+/**
+ * Retrieve the length field value from the given BD.  The returned value is
+ * the same as what was written with XAxiDma_BdSetLength(). Note that in the
+ * this value does not reflect the real length of received data.
+ * See the comments of XAxiDma_BdSetLength() for more details. To obtain the
+ * actual transfer length, use XAxiDma_BdGetActualLength().
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	LengthMask is the Maximum Transfer Length.
+ *
+ * @return	The length value set in the BD.
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetLength(BdPtr, LengthMask)                \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
+		LengthMask)
+
+
+/*****************************************************************************/
+/**
+ * Set the ID field of the given BD. The ID is an arbitrary piece of data the
+ * application can associate with a specific BD.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Id is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetId(BdPtr, Id)                                      \
+	(XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (u32)(Id)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))
+
+/*****************************************************************************/
+/**
+ * Get the BD's buffer address
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetBufAddr(BdPtr)                     \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))
+
+/*****************************************************************************/
+/**
+ * Check whether a BD has completed in hardware. This BD has been submitted
+ * to hardware. The application can use this function to poll for the
+ * completion of the BD.
+ *
+ * This function may not work if the BD is in cached memory.
+ *
+ * @param	BdPtr is the BD to check on
+ *
+ * @return
+ *		- 0 if not complete
+ *		- XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain
+ * 		XAXIDMA_BD_STS_*_ERR_MASK bits.
+ *
+ * @note
+ * 		C-style signature:
+ *		int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdHwCompleted(BdPtr)                     \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		XAXIDMA_BD_STS_COMPLETE_MASK)
+
+/*****************************************************************************/
+/**
+ * Get the actual transfer length of a BD. The BD has completed in hw.
+ *
+ * This function may not work if the BD is in cached memory.
+ *
+ * @param	BdPtr is the BD to check on
+ * @param	LengthMask is the Maximum Transfer Length.
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetActualLength(BdPtr, LengthMask)      \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		LengthMask)
+
+/*****************************************************************************/
+/**
+ * Set the TID field of the TX BD.
+ * Provides a stream identifier and can be used to differentiate between
+ * multiple streams of data that are being transferred across the same
+ * interface.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TId is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTId(BdPtr, TId) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TID_FIELD_MASK); \
+	val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTId(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TID_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the TDEST field of the TX BD.
+ * Provides coarse routing information for the data stream.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TDest is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTDest(BdPtr, TDest) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TDEST_FIELD_MASK); \
+	val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TDest field of the RX BD previously set with i
+ * XAxiDma_BdSetTDest.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTDest(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TDEST_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the TUSER field of the TX BD.
+ * User defined sideband signaling.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TUser is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTUser(BdPtr, TUser)	\
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TUSER_FIELD_MASK); \
+	val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TUSER field of the RX BD previously set with
+ * XAxiDma_BdSetTUser.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTUser(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TUSER_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the ARCACHE field of the given BD.
+ * This signal provides additional information about the cacheable
+ * characteristics of the transfer.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	ARCache is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetARCache(BdPtr, ARCache) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_ARCACHE_FIELD_MASK); \
+	val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the ARCACHE field of the given BD previously set with
+ * XAxiDma_BdSetARCache.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetARCache(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) &  \
+		XAXIDMA_BD_ARCACHE_FIELD_MASK)
+
+
+/*****************************************************************************/
+/**
+ * Set the ARUSER field of the given BD.
+ * Sideband signals used for user defined information.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	ARUser is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetARUser(BdPtr, ARUser) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_ARUSER_FIELD_MASK); \
+	val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the ARUSER field of the given BD previously set with
+ * XAxiDma_BdSetARUser.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetARUser(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) &  \
+		XAXIDMA_BD_ARUSER_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the STRIDE field of the given BD.
+ * It is the address distance between the first address of successive
+ * horizontal reads.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Stride is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetStride(BdPtr, Stride) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
+		~XAXIDMA_BD_STRIDE_FIELD_MASK); \
+	val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the STRIDE field of the given BD previously set with
+ * XAxiDma_BdSetStride.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetStride(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) &  \
+		XAXIDMA_BD_STRIDE_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the VSIZE field of the given BD.
+ * Number of horizontal lines for strided access.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	VSize is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetVSize(BdPtr, VSize) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
+		~XAXIDMA_BD_VSIZE_FIELD_MASK); \
+	val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the STRIDE field of the given BD previously set with
+ * XAxiDma_BdSetVSize.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetVSize(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) &  \
+		XAXIDMA_BD_VSIZE_FIELD_MASK)
+
+/*****************************************************************************/
+
+/************************** Function Prototypes ******************************/
+
+int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask);
+u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr);
+u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr);
+int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
+u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
+void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+
+/* Debug utility
+ */
+void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xaxidma_bdring.h b/thirdparty/xilinx/include/xilinx/xaxidma_bdring.h
new file mode 100644
index 000000000..351f65827
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxidma_bdring.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_bdring.h
+* @addtogroup axidma_v9_0
+* @{
+*
+* This file contains DMA channel related structure and constant definition
+* as well as function prototypes. Each DMA channel is managed by a Buffer
+* Descriptor ring, and XAxiDma_BdRing is chosen as the symbol prefix used in
+* this file. See xaxidma.h for more information on how a BD ring is managed.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA.
+*		      - New API
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+*		      - Changed APIs
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XAXIDMA_BDRING_H_	/* prevent circular inclusions */
+#define XAXIDMA_BDRING_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xaxidma_bd.h"
+
+
+
+/************************** Constant Definitions *****************************/
+/* State of a DMA channel
+ */
+#define AXIDMA_CHANNEL_NOT_HALTED	1
+#define AXIDMA_CHANNEL_HALTED		2
+
+/* Argument constant to simplify argument setting
+ */
+#define XAXIDMA_NO_CHANGE		0xFFFFFFFF
+#define XAXIDMA_ALL_BDS			0x0FFFFFFF /* 268 Million */
+
+/**************************** Type Definitions *******************************/
+
+/** Container structure for descriptor storage control. If address translation
+ * is enabled, then all addresses and pointers excluding FirstBdPhysAddr are
+ * expressed in terms of the virtual address.
+ */
+typedef struct {
+	u32 ChanBase;		/**< physical base address*/
+
+	int IsRxChannel;	/**< Is this a receive channel */
+	volatile int RunState;	/**< Whether channel is running */
+	int HasStsCntrlStrm; 	/**< Whether has stscntrl stream */
+	int HasDRE;
+	int DataWidth;
+	int Addr_ext;
+	u32 MaxTransferLen;
+
+	UINTPTR FirstBdPhysAddr;	/**< Physical address of 1st BD in list */
+	UINTPTR FirstBdAddr;	/**< Virtual address of 1st BD in list */
+	UINTPTR LastBdAddr;		/**< Virtual address of last BD in the list */
+	u32 Length;		/**< Total size of ring in bytes */
+	UINTPTR Separation;		/**< Number of bytes between the starting
+				     address of adjacent BDs */
+	XAxiDma_Bd *FreeHead;	/**< First BD in the free group */
+	XAxiDma_Bd *PreHead;	/**< First BD in the pre-work group */
+	XAxiDma_Bd *HwHead;	/**< First BD in the work group */
+	XAxiDma_Bd *HwTail;	/**< Last BD in the work group */
+	XAxiDma_Bd *PostHead;	/**< First BD in the post-work group */
+	XAxiDma_Bd *BdaRestart;	/**< BD to load when channel is started */
+	int FreeCnt;		/**< Number of allocatable BDs in free group */
+	int PreCnt;		/**< Number of BDs in pre-work group */
+	int HwCnt;		/**< Number of BDs in work group */
+	int PostCnt;		/**< Number of BDs in post-work group */
+	int AllCnt;		/**< Total Number of BDs for channel */
+	int RingIndex;		/**< Ring Index */
+} XAxiDma_BdRing;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* within the given memory constraints.
+*
+* The results of this macro can be provided to XAxiDma_BdRingCreate().
+*
+* @param	Alignment specifies what byte alignment the BDs must fall
+*		on and must be a power of 2 to get an accurate calculation
+*		(32, 64, 126,...)
+* @param	Bytes is the number of bytes to be used to store BDs.
+*
+* @return	Number of BDs that can fit in the given memory area
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*		This function is used only when system is configured as SG mode
+*
+******************************************************************************/
+#define XAxiDma_BdRingCntCalc(Alignment, Bytes)                           \
+	(uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* are required to contain a given number of BDs at a given alignment.
+*
+* @param	Alignment specifies what byte alignment the BDs must fall on.
+*		This parameter must be a power of 2 to get an accurate
+*		calculation (32, 64,128,...)
+* @param	NumBd is the number of BDs to calculate memory size
+*		requirements
+*
+* @return	The number of bytes of memory required to create a BD list
+*		with the given memory constraints.
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*		This function is used only when system is configured as SG mode
+*
+******************************************************************************/
+#define XAxiDma_BdRingMemCalc(Alignment, NumBd)			\
+	(int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XAxiDma_BdRingCreate().
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The total number of BDs allocated for this channel.
+*
+* @note
+* 		C-style signature:
+*		int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre-
+* processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The number of BDs currently allocatable.
+*
+* @note
+* 		C-style signature:
+*		int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetFreeCnt(RingPtr)  ((RingPtr)->FreeCnt)
+
+
+/****************************************************************************/
+/**
+* Snap shot the latest BD a BD ring is processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	None
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingSnapShotCurrBd(RingPtr)				  \
+	{								  \
+		if (!RingPtr->IsRxChannel) {				  \
+			(RingPtr)->BdaRestart = (XAxiDma_Bd *)		  \
+				XAxiDma_ReadReg((RingPtr)->ChanBase,	  \
+					XAXIDMA_CDESC_OFFSET);		  \
+		} else {						  \
+			if (!RingPtr->RingIndex) {			  \
+				(RingPtr)->BdaRestart =	(XAxiDma_Bd *)	  \
+				XAxiDma_ReadReg(			  \
+					(RingPtr)->ChanBase,		  \
+					XAXIDMA_CDESC_OFFSET);		  \
+			} else {					  \
+				(RingPtr)->BdaRestart =	(XAxiDma_Bd *)	  \
+				XAxiDma_ReadReg(			  \
+				(RingPtr)->ChanBase,			  \
+				(XAXIDMA_RX_CDESC0_OFFSET +		  \
+				(RingPtr->RingIndex - 1) * 		  \
+					XAXIDMA_RX_NDESC_OFFSET));	  \
+			}						  \
+		}							  \
+	}
+
+/****************************************************************************/
+/**
+* Get the BD a BD ring is processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The current BD that the BD ring is working on
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetCurrBd(RingPtr)               \
+	(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \
+					XAXIDMA_CDESC_OFFSET)              \
+
+/****************************************************************************/
+/**
+* Return the next BD in the ring.
+*
+* @param	RingPtr is the BD ring to operate on.
+* @param	BdPtr is the current BD.
+*
+* @return	The next BD in the ring relative to the BdPtr parameter.
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr,
+*							XAxiDma_Bd *BdPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingNext(RingPtr, BdPtr)			\
+		(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ?	\
+			(UINTPTR)(RingPtr)->FirstBdAddr :	\
+			(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD in the ring.
+*
+* @param	RingPtr is the DMA channel to operate on.
+* @param	BdPtr is the current BD.
+*
+* @return	The previous BD in the ring relative to the BdPtr parameter.
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr,
+*		XAxiDma_Bd *BdPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingPrev(RingPtr, BdPtr)				\
+		(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ?		\
+			(XAxiDma_Bd*)(RingPtr)->LastBdAddr :		\
+			(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Retrieve the contents of the channel status register
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Current contents of status register
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetSr(RingPtr)				\
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get error bits of a DMA channel
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Rrror bits in the status register, they should be interpreted
+*		with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetError(RingPtr)				\
+		(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_ERR_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Check whether a DMA channel is started, meaning the channel is not halted.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return
+*		- 1 if channel is started
+*		- 0 otherwise
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XAxiDma_BdRingHwIsStarted(RingPtr)				\
+		((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_HALTED_MASK) ? FALSE : TRUE)
+
+/****************************************************************************/
+/**
+* Check if the current DMA channel is busy with a DMA operation.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return
+*		- 1 if the DMA is busy.
+*		- 0 otherwise
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingBusy(RingPtr)					 \
+		(XAxiDma_BdRingHwIsStarted(RingPtr) &&		\
+		((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_IDLE_MASK) ? FALSE : TRUE))
+
+/****************************************************************************/
+/**
+* Set interrupt enable bits for a channel. This operation will modify the
+* XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @param	Mask consists of the interrupt signals to enable.Bits not
+*		specified in the mask are not affected.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntEnable(RingPtr, Mask)			\
+		(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
+			| ((Mask) & XAXIDMA_IRQ_ALL_MASK)))
+
+/****************************************************************************/
+/**
+* Get enabled interrupts of a channel. It is in XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @return	Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in
+*		xaxidma_hw.h to interpret this returned value.
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntGetEnabled(RingPtr)				\
+	(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
+		& XAXIDMA_IRQ_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Clear interrupt enable bits for a channel. It modifies the
+* XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @param	Mask consists of the interrupt signals to disable.Bits not
+*		specified in the Mask are not affected.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr,
+*								u32 Mask)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntDisable(RingPtr, Mask)				\
+		(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \
+			~((Mask) & XAXIDMA_IRQ_ALL_MASK)))
+
+/****************************************************************************/
+/**
+* Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. This
+* operation can be used to see which interrupts are pending.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Current contents of the IRQ_OFFSET register. Use
+*		XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret
+*		the returned value.
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetIrq(RingPtr)				\
+		(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_IRQ_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Acknowledge asserted interrupts. It modifies XAXIDMA_SR_OFFSET register.
+* A mask bit set for an unasserted interrupt has no effect.
+*
+* @param 	RingPtr is the channel instance to operate on.
+* @param	Mask are the interrupt signals to acknowledge
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingAckIrq(RingPtr, Mask)				\
+		XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\
+			(Mask) & XAXIDMA_IRQ_ALL_MASK)
+
+/************************* Function Prototypes ******************************/
+
+/*
+ * Descriptor ring functions xaxidma_bdring.c
+ */
+int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
+int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr);
+u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr,
+		UINTPTR VirtAddr, u32 Alignment, int BdCount);
+int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr);
+int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd ** BdSetPtr);
+int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit,
+		XAxiDma_Bd ** BdSetPtr);
+int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr);
+int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, u32 Timer);
+void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr,
+		u32 *CounterPtr, u32 *TimerPtr);
+
+/* The following functions are for debug only
+ */
+int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr);
+void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xaxidma_hw.h b/thirdparty/xilinx/include/xilinx/xaxidma_hw.h
new file mode 100644
index 000000000..cc467a83b
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxidma_hw.h
@@ -0,0 +1,344 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *  @file xaxidma_hw.h
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Hardware definition file. It defines the register interface and Buffer
+ * Descriptor (BD) definitions.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 4.00a rkv  02/22/11 Added support for simple DMA mode
+ * 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode and Cyclic mode of
+ *		       operations.
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+
+#ifndef XAXIDMA_HW_H_    /* prevent circular inclusions */
+#define XAXIDMA_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name DMA Transfer Direction
+ *  @{
+ */
+#define XAXIDMA_DMA_TO_DEVICE		0x00
+#define XAXIDMA_DEVICE_TO_DMA		0x01
+
+
+/** @name Buffer Descriptor Alignment
+ *  @{
+ */
+#define XAXIDMA_BD_MINIMUM_ALIGNMENT	0x40	/**< Minimum byte alignment
+						requirement for descriptors to
+						satisfy both hardware/software
+						needs */
+/*@}*/
+
+/** @name Micro DMA Buffer Address Alignment
+ *  @{
+ */
+#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN	0xFFF	/**< Minimum byte alignment
+						requirement for buffer address
+						in Micro DMA mode */
+/*@}*/
+
+/** @name Maximum transfer length
+ *	This is determined by hardware
+ * @{
+ */
+#define XAXIDMA_MAX_TRANSFER_LEN	0x7FFFFF  /* Max length hw supports */
+#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN	0x00FFFF  /* Max length MCDMA
+						     hw supports */
+/*@}*/
+
+/* Register offset definitions. Register accesses are 32-bit.
+ */
+/** @name Device registers
+ *  Register sets on TX and RX channels are identical
+ *  @{
+ */
+#define XAXIDMA_TX_OFFSET	0x00000000 /**< TX channel registers base
+					     *  offset */
+#define XAXIDMA_RX_OFFSET	0x00000030 /**< RX channel registers base
+					     * offset */
+
+/* This set of registers are applicable for both channels. Add
+ * XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX
+ * channel
+ */
+#define XAXIDMA_CR_OFFSET	 0x00000000   /**< Channel control */
+#define XAXIDMA_SR_OFFSET	 0x00000004   /**< Status */
+#define XAXIDMA_CDESC_OFFSET	 0x00000008   /**< Current descriptor pointer */
+#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C   /**< Current descriptor pointer */
+#define XAXIDMA_TDESC_OFFSET	 0x00000010   /**< Tail descriptor pointer */
+#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014   /**< Tail descriptor pointer */
+#define XAXIDMA_SRCADDR_OFFSET	 0x00000018   /**< Simple mode source address
+						pointer */
+#define XAXIDMA_SRCADDR_MSB_OFFSET	0x0000001C  /**< Simple mode source address
+						pointer */
+#define XAXIDMA_DESTADDR_OFFSET		0x00000018   /**< Simple mode destination address pointer */
+#define XAXIDMA_DESTADDR_MSB_OFFSET	0x0000001C   /**< Simple mode destination address pointer */
+#define XAXIDMA_BUFFLEN_OFFSET		0x00000028   /**< Tail descriptor pointer */
+#define XAXIDMA_SGCTL_OFFSET		0x0000002c   /**< SG Control Register */
+
+/** Multi-Channel DMA Descriptor Offsets **/
+#define XAXIDMA_RX_CDESC0_OFFSET	0x00000040   /**< Rx Current Descriptor 0 */
+#define XAXIDMA_RX_CDESC0_MSB_OFFSET	0x00000044   /**< Rx Current Descriptor 0 */
+#define XAXIDMA_RX_TDESC0_OFFSET	0x00000048   /**< Rx Tail Descriptor 0 */
+#define XAXIDMA_RX_TDESC0_MSB_OFFSET	0x0000004C   /**< Rx Tail Descriptor 0 */
+#define XAXIDMA_RX_NDESC_OFFSET		0x00000020   /**< Rx Next Descriptor Offset */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_CR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /**< Start/stop DMA channel */
+#define XAXIDMA_CR_RESET_MASK	0x00000004 /**< Reset DMA engine */
+#define XAXIDMA_CR_KEYHOLE_MASK	0x00000008 /**< Keyhole feature */
+#define XAXIDMA_CR_CYCLIC_MASK	0x00000010 /**< Cyclic Mode */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_SR_OFFSET register
+ *
+ * This register reports status of a DMA channel, including
+ * run/stop/idle state, errors, and interrupts (note that interrupt
+ * masks are shared with XAXIDMA_CR_OFFSET register, and are defined
+ * in the _IRQ_ section.
+ *
+ * The interrupt coalescing threshold value and delay counter value are
+ * also shared with XAXIDMA_CR_OFFSET register, and are defined in a
+ * later section.
+ * @{
+ */
+#define XAXIDMA_HALTED_MASK		0x00000001  /**< DMA channel halted */
+#define XAXIDMA_IDLE_MASK		0x00000002  /**< DMA channel idle */
+#define XAXIDMA_ERR_INTERNAL_MASK	0x00000010  /**< Datamover internal
+						      *  err */
+#define XAXIDMA_ERR_SLAVE_MASK		0x00000020  /**< Datamover slave err */
+#define XAXIDMA_ERR_DECODE_MASK		0x00000040  /**< Datamover decode
+						      *  err */
+#define XAXIDMA_ERR_SG_INT_MASK		0x00000100  /**< SG internal err */
+#define XAXIDMA_ERR_SG_SLV_MASK		0x00000200  /**< SG slave err */
+#define XAXIDMA_ERR_SG_DEC_MASK		0x00000400  /**< SG decode err */
+#define XAXIDMA_ERR_ALL_MASK		0x00000770  /**< All errors */
+
+/** @name Bitmask for interrupts
+ * These masks are shared by XAXIDMA_CR_OFFSET register and
+ * XAXIDMA_SR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_IRQ_IOC_MASK		0x00001000 /**< Completion intr */
+#define XAXIDMA_IRQ_DELAY_MASK		0x00002000 /**< Delay interrupt */
+#define XAXIDMA_IRQ_ERROR_MASK		0x00004000 /**< Error interrupt */
+#define XAXIDMA_IRQ_ALL_MASK		0x00007000 /**< All interrupts */
+/*@}*/
+
+/** @name Bitmask and shift for delay and coalesce
+ * These masks are shared by XAXIDMA_CR_OFFSET register and
+ * XAXIDMA_SR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_DELAY_MASK		0xFF000000 /**< Delay timeout
+						     *  counter */
+#define XAXIDMA_COALESCE_MASK		0x00FF0000 /**< Coalesce counter */
+
+#define XAXIDMA_DELAY_SHIFT		24
+#define XAXIDMA_COALESCE_SHIFT		16
+/*@}*/
+
+
+/* Buffer Descriptor (BD) definitions
+ */
+
+/** @name Buffer Descriptor offsets
+ *  USR* fields are defined by higher level IP.
+ *  setup for EMAC type devices. The first 13 words are used by hardware.
+ *  All words after the 13rd word are for software use only.
+ *  @{
+ */
+#define XAXIDMA_BD_NDESC_OFFSET		0x00  /**< Next descriptor pointer */
+#define XAXIDMA_BD_NDESC_MSB_OFFSET	0x04  /**< Next descriptor pointer */
+#define XAXIDMA_BD_BUFA_OFFSET		0x08  /**< Buffer address */
+#define XAXIDMA_BD_BUFA_MSB_OFFSET	0x0C  /**< Buffer address */
+#define XAXIDMA_BD_MCCTL_OFFSET		0x10  /**< Multichannel Control Fields */
+#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET	0x14  /**< 2D Transfer Sizes */
+#define XAXIDMA_BD_CTRL_LEN_OFFSET	0x18  /**< Control/buffer length */
+#define XAXIDMA_BD_STS_OFFSET		0x1C  /**< Status */
+
+#define XAXIDMA_BD_USR0_OFFSET		0x20  /**< User IP specific word0 */
+#define XAXIDMA_BD_USR1_OFFSET		0x24  /**< User IP specific word1 */
+#define XAXIDMA_BD_USR2_OFFSET		0x28  /**< User IP specific word2 */
+#define XAXIDMA_BD_USR3_OFFSET		0x2C  /**< User IP specific word3 */
+#define XAXIDMA_BD_USR4_OFFSET		0x30  /**< User IP specific word4 */
+
+#define XAXIDMA_BD_ID_OFFSET		0x34  /**< Sw ID */
+#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET	0x38  /**< Whether has stscntrl strm */
+#define XAXIDMA_BD_HAS_DRE_OFFSET	0x3C  /**< Whether has DRE */
+#define XAXIDMA_BD_ADDRLEN_OFFSET	0x40  /**< Check for BD Addr */
+
+#define XAXIDMA_BD_HAS_DRE_MASK		0xF00 /**< Whether has DRE mask */
+#define XAXIDMA_BD_WORDLEN_MASK		0xFF  /**< Whether has DRE mask */
+
+#define XAXIDMA_BD_HAS_DRE_SHIFT	8     /**< Whether has DRE shift */
+#define XAXIDMA_BD_WORDLEN_SHIFT	0     /**< Whether has DRE shift */
+
+#define XAXIDMA_BD_START_CLEAR		8   /**< Offset to start clear */
+#define XAXIDMA_BD_BYTES_TO_CLEAR	48  /**< BD specific bytes to be
+					      *  cleared */
+
+#define XAXIDMA_BD_NUM_WORDS		20U  /**< Total number of words for
+					       * one BD*/
+#define XAXIDMA_BD_HW_NUM_BYTES		52  /**< Number of bytes hw used */
+
+/* The offset of the last app word.
+ */
+#define XAXIDMA_LAST_APPWORD		4
+
+/*@}*/
+#define XAXIDMA_DESC_LSB_MASK	(0xFFFFFFC0U)	/**< LSB Address mask */
+
+/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /**< First tx packet */
+#define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /**< Last tx packet */
+#define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /**< All control bits */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_STS_COMPLETE_MASK	0x80000000 /**< Completed */
+#define XAXIDMA_BD_STS_DEC_ERR_MASK	0x40000000 /**< Decode error */
+#define XAXIDMA_BD_STS_SLV_ERR_MASK	0x20000000 /**< Slave error */
+#define XAXIDMA_BD_STS_INT_ERR_MASK	0x10000000 /**< Internal err */
+#define XAXIDMA_BD_STS_ALL_ERR_MASK	0x70000000 /**< All errors */
+#define XAXIDMA_BD_STS_RXSOF_MASK	0x08000000 /**< First rx pkt */
+#define XAXIDMA_BD_STS_RXEOF_MASK	0x04000000 /**< Last rx pkt */
+#define XAXIDMA_BD_STS_ALL_MASK		0xFC000000 /**< All status bits */
+/*@}*/
+
+/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_TDEST_FIELD_MASK	0x0000000F
+#define XAXIDMA_BD_TID_FIELD_MASK	0x00000F00
+#define XAXIDMA_BD_TUSER_FIELD_MASK	0x000F0000
+#define XAXIDMA_BD_ARCACHE_FIELD_MASK	0x0F000000
+#define XAXIDMA_BD_ARUSER_FIELD_MASK	0xF0000000
+
+#define XAXIDMA_BD_TDEST_FIELD_SHIFT	0
+#define XAXIDMA_BD_TID_FIELD_SHIFT    	8
+#define XAXIDMA_BD_TUSER_FIELD_SHIFT	16
+#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT	24
+#define XAXIDMA_BD_ARUSER_FIELD_SHIFT	28
+
+/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_STRIDE_FIELD_MASK	0x0000FFFF
+#define XAXIDMA_BD_VSIZE_FIELD_MASK	0xFFF80000
+
+#define XAXIDMA_BD_STRIDE_FIELD_SHIFT	0
+#define XAXIDMA_BD_VSIZE_FIELD_SHIFT   	19
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XAxiDma_In32	Xil_In32
+#define XAxiDma_Out32	Xil_Out32
+
+/*****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XAxiDma_ReadReg(BaseAddress, RegOffset)             \
+    XAxiDma_In32((BaseAddress) + (RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)          \
+    XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xaxidma_porting_guide.h b/thirdparty/xilinx/include/xilinx/xaxidma_porting_guide.h
new file mode 100644
index 000000000..ff10ddc7c
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxidma_porting_guide.h
@@ -0,0 +1,254 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_porting_guide.h
+* @addtogroup axidma_v9_0
+* @{
+*
+* This is a guide on how to move from using the xlldma driver to use xaxidma
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+* 6.00a srt  03/27/12 Added support for MCDMA mode
+* 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+*
+* </pre>
+*
+* <b>Overview</b>
+*
+* The API for xaxidma driver is similar to xlldma driver. The prefix for the
+* API functions and structures is XAxiDma_ for the xaxidma driver.
+*
+* Due to hardware feature changes, signatures of some API functions are a
+* little bit different from the xlldma API functions.
+*
+* We present API functions:
+* - That only have prefix changes
+* - That have different return type
+* - That are new API functions
+* - That have been removed
+*
+* Note that data structures have different prefix of XAxiDma_. Those API
+* functions, that have data structures with prefix change, are considered as
+* prefix change.
+*
+* <b>API Functions That Only Have Prefix Changes</b>
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver (upto v5_00_a)
+* -----------------------------------------------------------------------
+*    XLlDma_Reset(...)               |  XAxiDma_Reset(...)
+*    XLlDma_BdRingSnapShotCurrBd(...)|  XAxiDma_BdRingSnapShotCurrBd(...)
+*    XLlDma_BdRingNext(...)          |  XAxiDma_BdRingNext(...)
+*    XLlDma_BdRingPrev(...)          |  XAxiDma_BdRingPrev(...)
+*    XLlDma_BdRingGetSr(...)         |  XAxiDma_BdRingGetSr(...)
+*    XLlDma_BdRingBusy(...)          |  XAxiDma_BdRingBusy(...)
+*    XLlDma_BdRingIntEnable(...)     |  XAxiDma_BdRingIntEnable(...)
+*    XLlDma_BdRingIntDisable(...)    |  XAxiDma_BdRingIntDisable(...)
+*    XLlDma_BdRingIntGetEnabled(...) |  XAxiDma_BdRingIntGetEnabled(...)
+*    XLlDma_BdRingGetIrq(...)        |  XAxiDma_BdRingGetIrq(...)
+*    XLlDma_BdRingAckIrq(...)        |  XAxiDma_BdRingAckIrq(...)
+*    XLlDma_BdRingCreate(...)        |  XAxiDma_BdRingCreate(...)
+*    XLlDma_BdRingClone(...)         |  XAxiDma_BdRingClone(...)
+*    XLlDma_BdRingAlloc(...)         |  XAxiDma_BdRingAlloc(...)
+*    XLlDma_BdRingUnAlloc(...)       |  XAxiDma_BdRingUnAlloc(...)
+*    XLlDma_BdRingToHw(...)          |  XAxiDma_BdRingToHw(...)
+*    XLlDma_BdRingFromHw(...)        |  XAxiDma_BdRingFromHw(...)
+*    XLlDma_BdRingFree(...)          |  XAxiDma_BdRingFree(...)
+*    XLlDma_BdRingStart(...)         |  XAxiDma_BdRingStart(...)
+*    XLlDma_BdRingCheck(...)         |  XAxiDma_BdRingCheck(...)
+*    XLlDma_BdRingSetCoalesce(...)   |  XAxiDma_BdRingSetCoalesce(...)
+*    XLlDma_BdRingGetCoalesce(...)   |  XAxiDma_BdRingGetCoalesce(...)
+*    XLlDma_BdRead(...)              |  XAxiDma_BdRead(...)
+*    XLlDma_BdWrite(...)             |  XAxiDma_BdWrite(...)
+*    XLlDma_BdClear(...)             |  XAxiDma_BdClear(...)
+*    XLlDma_BdSetId(...)             |  XAxiDma_BdSetId(...)
+*    XLlDma_BdGetId(...)             |  XAxiDma_BdGetId(...)
+*    XLlDma_BdGetLength(...)         |  XAxiDma_BdGetLength(...)
+*    XLlDma_BdGetBufAddr(...)        |  XAxiDma_BdGetBufAddr(...)
+*
+*</pre>
+*
+* <b>API Functions That Have Different Return Type</b>
+*
+* Due to possible hardware failures, The caller should check the return value
+* of the following functions.
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver
+* -----------------------------------------------------------------------
+* void XLlDma_Pause(...)             | int XAxiDma_Pause(...)
+* void XLlDma_Resume(...)            | int XAxiDma_Resume(...)
+* </pre>
+*
+* The following functions have return type changed:
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver
+* -----------------------------------------------------------------------
+* XLlDma_BdRing XLlDma_GetRxRing(...)| XAxiDma_BdRing * XAxiDma_GetRxRing(...)
+* XLlDma_BdRing XLlDma_GetTxRing(...)| XAxiDma_BdRing * XAxiDma_GetTxRing(...)
+* u32 XLlDma_BdRingMemCalc(...)      | int XAxiDma_BdRingMemCalc(...)
+* u32 XLlDma_BdRingCntCalc(...)      | int XAxiDma_BdRingCntCalc(...)
+* u32 XLlDma_BdRingGetCnt(...)       | int XAxiDma_BdRingGetCnt(...)
+* u32 XLlDma_BdRingGetFreeCnt(...)   | int XAxiDma_BdRingGetFreeCnt(...)
+* void XLlDma_BdSetLength(...)       | int XAxiDma_BdSetLength(...)
+* void XLlDma_BdSetBufAddr(...)      | int XAxiDma_BdSetBufAddr(...)
+*</pre>
+*
+* <b>API Functions That Are New API Functions</b>
+*
+* Now that the AXI DMA core is a standalone core, some new API are intrduced.
+* Some other functions are added due to hardware interface change, so to
+* replace old API functions.
+*
+* - XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
+* - int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
+* - int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
+* - XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr);
+* - int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr);
+* - void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
+* - int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
+* - void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+* - u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr);
+* - u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
+* - u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
+*
+* <b>API Functions That Have Been Removed</b>
+*
+* Please see individual function comments for how to replace the removed API
+* function with new API functions.
+*
+* - void XLlDma_Initialize(XLlDma * InstancePtr, u32 BaseAddress).
+*   This function is replaced by XAxiDma_LookupConfig()/XAxiDma_CfgInitialize()
+*
+* - u32 XLlDma_BdRingGetCr(XLlDma_BdRing* RingPtr).
+*   This is replaced by XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
+*
+* - u32 XLlDma_BdRingSetCr(XLlDma_BdRing* RingPtr, u32 Data).
+*   This function is covered by other API functions:
+*      - void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*      - void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*      - int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter,
+*            u32 Timer)
+*
+* - u32 XLlDma_BdSetStsCtrl(XLlDma_Bd* BdPtr, u32 Data).
+*   Replaced by XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+*
+* - u32 XLlDma_BdGetStsCtrl(XLlDma_Bd* BdPtr).
+*   Replaced by XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) and
+*   XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr).
+*
+* <b>API Functions That Have Been Added to support simple DMA mode</b>
+*
+* - u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
+* - int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, int Length,
+*	int Direction);
+* - XAxiDma_HasSg(InstancePtr);
+* - XAxiDma_IntrEnable(InstancePtr,Mask,Direction);
+* - XAxiDma_IntrGetEnabled(InstancePtr, Direction);
+* - XAxiDma_IntrDisable(InstancePtr, Mask, Direction);
+* - XAxiDma_IntrGetIrq(InstancePtr, Direction);
+* - XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction);
+*
+* <b> For xaxidma driver v6_00_a Multiple Channel Support
+*     ---------------------------------------------------
+* This driver supports Multi-channel mode and accordingly some APIs are
+* changed to index multiple channels. Few new APIs are added.
+*  - Changed APIs
+*	* XAxiDma_GetRxRing(InstancePtr, RingIndex)
+* 	* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*			u32 BuffAddr, u32 Length,
+*			int Direction, int RingIndex)
+*	* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*			int RingIndex)
+*	* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*      			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*	* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+*			u32 LenBytes, u32 LengthMask)
+*       * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+*	* XAxiDma_BdGetLength(BdPtr, LengthMask)
+*
+*  - New APIs
+*	* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*			int Direction, int Select)
+*	* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*			int RingIndex)
+*	* XAxiDma_BdSetTId()
+*	* XAxiDma_BdGetTId()
+*	* XAxiDma_BdSetTDest()
+*	* XAxiDma_BdGetTDest()
+*	* XAxiDma_BdSetTUser()
+*	* XAxiDma_BdGetTUser()
+*	* XAxiDma_BdSetARCache()
+*	* XAxiDma_BdGetARCache()
+*	* XAxiDma_BdSetARUser()
+*	* XAxiDma_BdGetARUser()
+*	* XAxiDma_BdSetStride()
+*	* XAxiDma_BdGetStride()
+*	* XAxiDma_BdSetVSize()
+*	* XAxiDma_BdGetVSize()
+* <b> For xaxidma driver v7_00_a
+*     ---------------------------------------------------
+*  - New API
+*	* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
+*
+*  - Changed APIs
+*	All the APIs changed in v6_00_a are reverted back for backward
+*	compatibility.
+*</pre>
+*
+******************************************************************************/
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xaxis_switch.h b/thirdparty/xilinx/include/xilinx/xaxis_switch.h
new file mode 100644
index 000000000..604760916
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxis_switch.h
@@ -0,0 +1,208 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch.h
+* @addtogroup axis_switch_v1_0
+* @{
+* @details
+*
+* This is the main header file for Xilinx AXI4-Stream Switch Control Router
+* core. It is used for routing streams where masters in the system do not know
+* final destination address.
+*
+* <b>Core Features </b>
+*
+* For a full description of AXI4-Stream Switch Control Router, please see the
+* hardware specification.
+*
+* <b>Software Initialization & Configuration</b>
+*
+* The application needs to do following steps in order for preparing the
+* AXI4-Stream Switch Control Router core to be ready.
+*
+* - Call XAxisScr_LookupConfig using a device ID to find the core
+*   configuration.
+* - Call XAxisScr_CfgInitialize to initialize the device and the driver
+*   instance associated with it.
+*
+* <b>Interrupts </b>
+*
+* This driver does not have interrupt mechanism.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XAXI4-Stream Switch driver is composed of several source files. This
+* allows the user to build and link only those parts of the driver that are
+* necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XAXIS_SWITCH_H_
+#define XAXIS_SWITCH_H_		/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xaxis_switch_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+* This typedef contains configuration information for the AXI4-Stream Switch
+* core. Each AXI4-Stream Switch device should have a configuration structure
+* associated.
+*/
+typedef struct {
+	u16 DeviceId;		/**< DeviceId is the unique ID of the AXI4-
+				  *  Stream Switch core */
+	u32 BaseAddress;	/**< BaseAddress is the physical base address
+				  *  of the core's registers */
+	u8 MaxNumSI;		/**< Maximum number of Slave interfaces */
+	u8 MaxNumMI;		/**< Maximum number of Master interfaces */
+} XAxis_Switch_Config;
+
+/**
+* The AXI4-Stream Switch driver instance data. An instance must be allocated
+* for each core in use.
+*/
+typedef struct {
+	XAxis_Switch_Config Config;	/**< Hardware Configuration */
+	u32 IsReady;			/**< Core and the driver instance are
+					  *  initialized */
+} XAxis_Switch;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This macro enables register updates.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_RegUpdateEnable(XAxis_Switch *InstancePtr)
+*
+******************************************************************************/
+#define XAxisScr_RegUpdateEnable(InstancePtr) \
+	XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XAXIS_SCR_CTRL_OFFSET, \
+		XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAXIS_SCR_CTRL_OFFSET) | \
+				XAXIS_SCR_CTRL_REG_UPDATE_MASK)
+
+/*****************************************************************************/
+/**
+*
+* This macro disables register updates.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_RegUpdateDisable(XAxis_Switch *InstancePtr)
+*
+******************************************************************************/
+#define XAxisScr_RegUpdateDisable(InstancePtr) \
+	XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XAXIS_SCR_CTRL_OFFSET, \
+		XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAXIS_SCR_CTRL_OFFSET) & \
+				(~XAXIS_SCR_CTRL_REG_UPDATE_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization function in xaxis_switch_sinit.c */
+XAxis_Switch_Config *XAxisScr_LookupConfig(u16 DeviceId);
+
+/* Initialization and control functions in xaxis_switch.c */
+s32 XAxisScr_CfgInitialize(XAxis_Switch *InstancePtr,
+			XAxis_Switch_Config *CfgPtr, u32 EffectiveAddr);
+
+void XAxisScr_MiPortEnable(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex);
+void XAxisScr_MiPortDisable(XAxis_Switch *InstancePtr, u8 MiIndex);
+s32 XAxisScr_IsMiPortEnabled(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex);
+s32 XAxisScr_IsMiPortDisabled(XAxis_Switch *InstancePtr, u8 MiIndex);
+void XAxisScr_MiPortDisableAll(XAxis_Switch *InstancePtr);
+
+/* Self test function in xaxis_switch_selftest.c */
+s32 XAxisScr_SelfTest(XAxis_Switch *InstancePtr);
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xaxis_switch_hw.h b/thirdparty/xilinx/include/xilinx/xaxis_switch_hw.h
new file mode 100644
index 000000000..f98227e19
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xaxis_switch_hw.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_hw.h
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This header file contains identifiers and register-level core functions (or
+* macros) that can be used to access the Xilinx AXI4-Stream Switch Control
+* Router core.
+*
+* For more information about the operation of this core see the hardware
+* specification and documentation in the higher level driver
+* xaxis_switch.h file.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XAXIS_SWITCH_HW_H_
+#define XAXIS_SWITCH_HW_H_	/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name MI MUX register offsets
+*
+* @{
+*/
+#define XAXIS_SCR_CTRL_OFFSET		0x000	/**< Control Register offset */
+#define XAXIS_SCR_MI_MUX_START_OFFSET	0x040	/**< Start of MI MUX Register
+						  *  offset */
+#define XAXIS_SCR_MI_MUX_END_OFFSET	0x07C	/**< End of MI MUX Register
+						  *  offset */
+
+/*@}*/
+
+/** @name MI MUX Control register mask
+* @{
+*/
+#define XAXIS_SCR_CTRL_REG_UPDATE_MASK	0x02	/**< Register Update
+						  *  mask */
+/*@}*/
+
+/** @name MI MUX register mask
+*
+* It is applicable for MI[0...15] registers.
+* @{
+*/
+#define XAXIS_SCR_MI_X_MUX_MASK		0x0F		/**< MI MUX mask */
+#define XAXIS_SCR_MI_X_DISABLE_MASK	0x80000000	/**< MI Disable mask */
+#define XAXIS_SCR_MI_X_DISABLE_SHIFT	31	/**< MI Disable shift */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/** @name Register access macro definition
+* @{
+*/
+#define XAxisScr_In32		Xil_In32	/**< Input Operations */
+#define XAxisScr_Out32		Xil_Out32	/**< Output Operations */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads a value from a AXI4-Stream Switch register. A 32 bit read
+* is performed. If the component is implemented in a smaller width, only the
+* least significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param	BaseAddress is the base address of the XAxis_Switch core
+*		instance.
+* @param	RegOffset is the register offset of the register (defined at
+*		the top of this file).
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XAxisScr_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XAxisScr_ReadReg(BaseAddress, RegOffset) \
+	XAxisScr_In32((BaseAddress) + ((u32)RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes a value to a AXI4-Stream Switch register. A 32 bit write
+* is performed. If the component is implemented in a smaller width, only the
+* least significant data is written.
+*
+* @param	BaseAddress is the base address of the XAxis_Switch core
+*		instance.
+* @param	RegOffset is the register offset of the register (defined at
+*		the top of this file) to be written.
+* @param	Data is the 32-bit value to write into the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_WriteReg(u32 BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+******************************************************************************/
+#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data) \
+	XAxisScr_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
+/*@}*/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
\ No newline at end of file
diff --git a/thirdparty/xilinx/include/xilinx/xbasic_types.h b/thirdparty/xilinx/include/xilinx/xbasic_types.h
new file mode 100644
index 000000000..7213c7bcc
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xbasic_types.h
@@ -0,0 +1,315 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains basic types for Xilinx software IP.  These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*       rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*                     compiler warnings
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* 1.00a rpm  07/21/04 Added XExceptionHandler typedef for processor exceptions
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a wre  01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE
+* 1.00a rpm  04/02/07 Added ifndef KERNEL around u32, u16, u8 data types
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1
+#endif
+
+#ifndef FALSE
+#  define FALSE		0
+#endif
+
+#ifndef NULL
+#define NULL		0
+#endif
+
+/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+
+#define XCOMPONENT_IS_READY     0x11111111  /**< component has been initialized */
+#define XCOMPONENT_IS_STARTED   0x22222222  /**< component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED    0
+#define XTEST_FAILED    1
+
+#define XASSERT_NONE     0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+#include <stdint.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t		Xuint8;		/**< unsigned 8-bit */
+typedef int8_t		Xint8;		/**< signed 8-bit */
+typedef uint16_t	Xuint16;	/**< unsigned 16-bit */
+typedef int16_t		Xint16;		/**< signed 16-bit */
+typedef uint32_t	Xuint32;	/**< unsigned 32-bit */
+typedef int32_t		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the XWaitInAssert variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression)                   \
+{                                                  \
+    if (expression)                                \
+    {                                              \
+        XAssertStatus = XASSERT_NONE;              \
+    }                                              \
+    else                                           \
+    {                                              \
+        XAssert(__FILE__, __LINE__);               \
+                XAssertStatus = XASSERT_OCCURRED;  \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the XWaitInAssert variable is true, in which case
+*           no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression)                \
+{                                                  \
+    if (expression)                                \
+    {                                              \
+        XAssertStatus = XASSERT_NONE;              \
+    }                                              \
+    else                                           \
+    {                                              \
+        XAssert(__FILE__, __LINE__);               \
+                XAssertStatus = XASSERT_OCCURRED;  \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+*         no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS()                      \
+{                                                  \
+   XAssert(__FILE__, __LINE__);                    \
+           XAssertStatus = XASSERT_OCCURRED;       \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+*         no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS()                   \
+{                                                  \
+   XAssert(__FILE__, __LINE__);                    \
+           XAssertStatus = XASSERT_OCCURRED;       \
+   return 0;                                       \
+}
+
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+void XNullHandler(void *NullParameter);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xdebug.h b/thirdparty/xilinx/include/xilinx/xdebug.h
new file mode 100644
index 000000000..e8047e275
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xdebug.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef _XDEBUG_H
+#define _XDEBUG_H
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#include <stdio.h>
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+#define XDBG_DEBUG_ERROR             0x00000001    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFF    /* all debugging data */
+
+#define XDBG_DEBUG_FIFO_REG          0x00000100    /* display register reads/writes */
+#define XDBG_DEBUG_FIFO_RX           0x00000101    /* receive debug messages */
+#define XDBG_DEBUG_FIFO_TX           0x00000102    /* transmit debug messages */
+#define XDBG_DEBUG_FIFO_ALL          0x0000010F    /* all fifo debug messages */
+
+#define XDBG_DEBUG_TEMAC_REG         0x00000400    /* display register reads/writes */
+#define XDBG_DEBUG_TEMAC_RX          0x00000401    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_TX          0x00000402    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ALL         0x0000040F    /* all temac  debug messages */
+
+#define XDBG_DEBUG_TEMAC_ADPT_RX     0x00000800    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_TX     0x00000801    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_IOCTL  0x00000802    /* ioctl debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_MISC   0x00000803    /* debug msg for other routines */
+#define XDBG_DEBUG_TEMAC_ADPT_ALL    0x0000080F    /* all temac adapter debug messages */
+
+#define xdbg_current_types (XDBG_DEBUG_ERROR)
+
+#define xdbg_stmnt(x)  x
+
+/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
+ * macros that accept variable number of arguments
+ */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
+
+#else /* ANSI Syntax */
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+#endif
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+/* See VxWorks comments above */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...)
+#else /* ANSI Syntax */
+#define xdbg_printf(...)
+#endif
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* _XDEBUG_H */
diff --git a/thirdparty/xilinx/include/xilinx/xenv.h b/thirdparty/xilinx/include/xilinx/xenv.h
new file mode 100644
index 000000000..54d24f476
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xenv.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xenv_linux.h b/thirdparty/xilinx/include/xilinx/xenv_linux.h
new file mode 100644
index 000000000..e1edc618a
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xenv_linux.h
@@ -0,0 +1,255 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_linux.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a ch   10/24/02 First release
+* 1.10a wgr  03/22/07 Converted to new coding style.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_LINUX_H
+#define XENV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include <asm/cache.h>
+#include <asm/cacheflush.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * Those macros are defined to catch legacy code in Xilinx drivers. The
+ * XENV_MEM_COPY and XENV_MEM_FILL macros were used in early Xilinx driver
+ * code. They are being replaced by memcpy() and memset() function calls. These
+ * macros are defined to catch any remaining occurences of those macros.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+		memcpy(DestPtr, SrcPtr, Bytes)
+/*		do_not_use_XENV_MEM_COPY_use_memcpy_instead */
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+		memset(DestPtr, Data, Bytes)
+/*		do_not_use_XENV_MEM_FILL_use_memset_instead */
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ * @note	XENV_USLEEP is deprecated. Use udelay() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_USLEEP(delay)	udelay(delay)
+/*		do_not_use_XENV_MEM_COPY_use_memcpy_instead */
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ * The implementation of the cache handling functions can be found in
+ * arch/microblaze.
+ *
+ * These #defines are simple mappings to the Linux API.
+ *
+ * The underlying Linux implementation will take care of taking the right
+ * actions depending on the configuration of the MicroBlaze processor in the
+ * system.
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_DCACHE()		__enable_dcache()
+#define XCACHE_DISABLE_DCACHE()		__disable_dcache()
+#define XCACHE_ENABLE_ICACHE()		__enable_icache()
+#define XCACHE_DISABLE_ICACHE()		__disable_icache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) invalidate_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)      flush_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
+
+#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) "XCACHE_INVALIDATE_ICACHE_RANGE unsupported"
+#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len)      flush_icache_range(Addr, Len)
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xenv_none.h b/thirdparty/xilinx/include/xilinx/xenv_none.h
new file mode 100644
index 000000000..e0ff47a01
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xenv_none.h
@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_none.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This is a legacy file kept for backwards compatibility.
+*
+* Please modify your code to #include "xenv_standalone.h" instead.
+*
+*
+******************************************************************************/
+
+#warning ********************************************************************
+#warning *
+#warning * Use of xenv_none.h deprecated.
+#warning * Please include the new xenv_standalone.h file instead.
+#warning *
+#warning ********************************************************************
+
+#include "xenv_standalone.h"
+
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xenv_standalone.h b/thirdparty/xilinx/include/xilinx/xenv_standalone.h
new file mode 100644
index 000000000..14a83b05c
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xenv_standalone.h
@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((int)(Addr), (int)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
+
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xenv_vxworks.h b/thirdparty/xilinx/include/xilinx/xenv_vxworks.h
new file mode 100644
index 000000000..1254a6bdc
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xenv_vxworks.h
@@ -0,0 +1,272 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_vxworks.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+*       rmm  09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL
+*       rmm  10/24/02 Added XENV_USLEEP macro
+* 1.00a rmm  07/16/01 First release
+* 1.10a wgr  03/22/07 Converted to new coding style.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_VXWORKS_H
+#define XENV_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+#include <string.h>
+
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note	XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note	XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+#if (CPU_FAMILY==PPC)
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef struct
+{
+	u32 TimeBaseUpper;
+	u32 TimeBaseLower;
+} XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)                   \
+{                                                       \
+    vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper,  \
+                  (UINT32*)&(StampPtr)->TimeBaseLower); \
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note    None.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * None.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+
+/* For non-PPC systems the above macros are not defined. Generate a error to
+ * make the developer aware of the problem.
+ */
+#else
+#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting."
+#endif
+
+
+/*****************************************************************************/
+/**
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_USLEEP(delay)	sysUsDelay(delay)
+
+#define udelay(delay)	sysUsDelay(delay)
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ ******************************************************************************/
+
+#if (CPU_FAMILY==PPC)
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+#define XCACHE_ENABLE_DCACHE()		cacheEnable(DATA_CACHE)
+#define XCACHE_DISABLE_DCACHE()		cacheDisable(DATA_CACHE)
+#define XCACHE_ENABLE_ICACHE()		cacheEnable(INSTRUCTION_CACHE)
+#define XCACHE_DISABLE_ICACHE()		cacheDisable(INSTRUCTION_CACHE)
+
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \
+		cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifdef XENV_VXWORKS_H */
+
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xil_assert.h b/thirdparty/xilinx/include/xilinx/xil_assert.h
new file mode 100644
index 000000000..7ce034201
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xil_assert.h
@@ -0,0 +1,85 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include <assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define Xil_AssertVoid(expr)                                            \
+  ((expr)                                                               \
+   ? __ASSERT_VOID_CAST (0)                                             \
+   : __assert_fail (__STRING(expr), __FILE__, __LINE__, __ASSERT_FUNCTION))
+#define Xil_AssertNonvoid(expr)                                         \
+  ((expr)                                                               \
+   ? __ASSERT_VOID_CAST (0)                                             \
+   : __assert_fail (__STRING(expr), __FILE__, __LINE__, __ASSERT_FUNCTION))
+#define Xil_AssertVoidAlways()                                          \
+  __assert_fail ("always", __FILE__, __LINE__, __ASSERT_FUNCTION)
+#define Xil_AssertNonvoidAlways()                                       \
+  __assert_fail ("always", __FILE__, __LINE__, __ASSERT_FUNCTION)
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/thirdparty/xilinx/include/xilinx/xil_cache.h b/thirdparty/xilinx/include/xilinx/xil_cache.h
new file mode 100644
index 000000000..a1b68faf0
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xil_cache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* Contains dummies for cache related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define Xil_DCacheEnable()
+#define Xil_DCacheDisable()
+#define Xil_DCacheInvalidateRange(Addr, Len)
+#define Xil_DCacheFlushRange(Addr, Len)
+#define Xil_ICacheEnable()
+#define Xil_ICacheDisable()
+#define Xil_ICacheInvalidateRange(Addr, Len)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/thirdparty/xilinx/include/xilinx/xil_io.h b/thirdparty/xilinx/include/xilinx/xil_io.h
new file mode 100644
index 000000000..ae35ff60b
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xil_io.h
@@ -0,0 +1,246 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 1.00a sdm      07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
+* 3.07a asa	     08/31/12 Added xil_printf.h include
+* 3.08a sgd	     11/05/12 Reverted SYNC macros definitions
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+//#include "xpseudo_asm.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if 0
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+#else
+#  define SYNCHRONIZE_IO
+#  define INST_SYNC
+#  define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/thirdparty/xilinx/include/xilinx/xil_printf.h b/thirdparty/xilinx/include/xilinx/xil_printf.h
new file mode 100644
index 000000000..a3ecfea50
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xil_printf.h
@@ -0,0 +1,43 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "xil_types.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+#define xil_printf(fmt, ...)	printf(fmt, ##__VA_ARGS__)
+#define print(ptr)		printf("%s", ptr)
+
+#define outbyte(byte)		putc(byte, stdout)
+#define inbyte();		getc(stdin)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/thirdparty/xilinx/include/xilinx/xil_types.h b/thirdparty/xilinx/include/xilinx/xil_types.h
new file mode 100644
index 000000000..e8b78b7c6
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xil_types.h
@@ -0,0 +1,200 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * UPPER_32_BITS - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * LOWER_32_BITS - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
diff --git a/thirdparty/xilinx/include/xilinx/xintc.h b/thirdparty/xilinx/include/xilinx/xintc.h
new file mode 100644
index 000000000..080f01b51
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xintc.h
@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc.h
+* @addtogroup intc_v3_4
+* @{
+* @details
+*
+* The Xilinx interrupt controller driver component. This component supports the
+* Xilinx interrupt controller.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 0 and 31 inclusive with
+* 0 being the highest priority interrupt source.
+*
+* The Xilinx interrupt controller supports the following features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - master enable/disable
+*   - single callback per interrupt or all pending interrupts handled for
+*     each interrupt of the processor
+*
+* The acknowledgement of the interrupt within the interrupt controller is
+* selectable, either prior to the device's handler being called or after
+* the handler is called. This is necessary to support interrupt signal inputs
+* which are either edge or level signals.  Edge driven interrupt signals
+* require that the interrupt is acknowledged prior to the interrupt being
+* serviced in order to prevent the loss of interrupts which are occurring
+* extremely close together.  A level driven interrupt input signal requires
+* the interrupt to acknowledged after servicing the interrupt to ensure that
+* the interrupt only generates a single interrupt condition.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xintc_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The interrupt vector table for each interrupt controller device is declared
+* statically in xintc_g.c within the configuration data for each instance.
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table - to retrieve the vector table
+* for an instance of the interrupt controller. The user should populate the
+* vector table with handlers and callbacks at run-time using the XIntc_Connect()
+* and XIntc_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an argument
+* to be passed to the handler when an interrupt occurs.  The tools default this
+* argument to the base address of the interrupting device.  Note that the
+* device driver interrupt handlers given in this file do not take a base
+* address as an argument, but instead take a pointer to the driver instance.
+* This means that although the table is created statically, the user must still
+* use XIntc_Connect() when the interrupt handler takes an argument other than
+* the base address. This is only to say that the existence of the static vector
+* tables should not mislead the user into thinking they no longer need to
+* register/connect interrupt handlers with this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00a rpm  01/09/02 Removed the AckLocation argument from XIntc_Connect().
+*                     This information is now internal in xintc_g.c.
+* 1.00b jhl  02/13/02 Repartitioned the driver for smaller files
+* 1.00b jhl  04/24/02 Made LookupConfig function global and relocated config
+*                     data type
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table. Moved vector
+*                     table and options out of instance structure and into
+*                     the configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and _m is removed from
+*		      all the macro names/definitions.
+* 2.01a sdm  04/27/10 Updated the tcl so that the defintions are generated in
+*		      the xparameters.h to know whether the optional registers
+*		      SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
+*		      This driver doesnot make use of these definitions and does
+*		      not use the optional registers.
+* 2.03a hvm  05/24/11 Updated the tcl to generate vector Ids for external
+*		      interrupts. CR565336
+* 2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
+*		      and XIntc_SetNormalIntrMode for setting to normal
+*		      interrupt mode.
+* 2.04a asa  03/19/12 Changed the XIntc_Config struct. The order of entries
+*		      declared in the structure now matches with the
+*		      XIntc_ConfigTable generated by the driver tcl.
+* 2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
+*		      added IntVectorAddr to XIntc_Config for this.
+*		      Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.06a bss  01/28/13 To support Cascade mode:
+* 		      Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
+*		      XIN_INTC_SECONDARY,XIN_INTC_LAST and
+*		      XIN_CONTROLLER_MAX_INTRS  macros
+*		      Added NumberofIntrs and IntcType fields in XIntc_Config
+*		      structure.
+*		      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
+*		      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
+*		      XIntc_Acknowledge,XIntc_ConnectFastHandler and
+*		      XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
+*		      API in xintc.c
+*  		      Modified XIntc_DeviceInterruptHandler,
+*  		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
+*		      XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
+*		      API in xintc_l.c.
+*		      Modified XIntc_SetOptions API in xintc_options.c.
+*		      Modified XIntc_SimulateIntr API in xintc_selftest.c.
+*		      Modified driver tcl:
+*			to check for Cascade mode and generate XPAR_INTC_TYPE
+*			for each controller.
+*			Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
+*			interrupt sources of all Controllers in Cascade mode.
+* 2.07a bss  10/18/13 To support Nested interrupts:
+*		      Modified XIntc_DeviceInterruptHandler API.
+*		      Added XIN_ILR_OFFSET macro in xintc_l.h.
+*		      Modified driver tcl to generate HAS_ILR parameter in
+*		      xparameters.h
+* 3.0   bss  01/28/13 Modified xintc.c to initialize IVAR register with
+*		      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
+*		      CR#765931.
+*		      Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
+*		      correctly(CR#764865).
+*
+* @note
+*		For Cascade mode, Interrupt IDs are generated in xparameters.h
+*		as shown below:
+*
+*	    Master/Primary INTC
+*		 ______
+*		|      |-0      Secondary INTC
+*		|      |-.         ______
+*		|      |-.        |      |-32        Last INTC
+*		|      |-.        |      |-.          ______
+*		|______|<-31------|      |-.         |      |-64
+*			          |      |-.         |      |-.
+*			          |______|<-63-------|      |-.
+*                                                    |      |-.
+*                                                    |______|-95
+*
+*		All driver functions has to be called using DeviceId/
+*		InstancePtr/BaseAddress of Primary/Master Controller and
+*		Interrupts IDs generated in xparameters.h only.
+*		Driver functions takes care of Slave Controllers based on
+*		Interrupt ID passed. User must not use Interrupt source/ID
+*		31 of Primary and Secondary controllers to call driver
+*		functions.
+*
+*		For nested interrupts, XIntc_DeviceInterruptHandler saves
+*		microblaze r14 register on entry and restores on exit. This is
+*		required since compiler does not support nesting. It enables
+*		Microblaze interrupts after blocking further interrupts from
+*		the current interrupt number and interrupts below current
+*		interrupt proirity by writing to Interrupt Level Register of
+*		INTC on entry. On exit, it disables microblaze interrupts and
+*		restores ILR register default value(0xFFFFFFFF)back. It is
+*		recommended to increase STACK_SIZE in linker script for nested
+*		interrupts.
+* 3.0     adk    12/10/13  Updated as per the New Tcl API's
+* 3.0 	  adk 	 17/02/14  Fixed the CR:771287 Changes are made in the intc
+* 		           driver tcl.
+* 3.1     adk    8/4/14    Fixed the CR:783248 Changes are made in
+*			   the test-app tcl
+* 3.2     bss    4/8/14    Fixed driver tcl to handle external interrupt pins
+*			   correctly (CR#799609).
+* 3.3     adk    11/3/14   added generation of C_HAS_ILR parameter to
+*			   xparameters.h.Changes are made in the driver tcl file
+*			   (CR#828046).
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_H			/* prevent circular inclusions */
+#define XINTC_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xintc_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Configuration options
+ * These options are used in XIntc_SetOptions() to configure the device.
+ * @{
+ */
+/**
+ * <pre>
+ * XIN_SVC_SGL_ISR_OPTION	Service the highest priority pending interrupt
+ *				and then return.
+ * XIN_SVC_ALL_ISRS_OPTION	Service all of the pending interrupts and then
+ *				return.
+ * </pre>
+ */
+#define XIN_SVC_SGL_ISR_OPTION  1UL
+#define XIN_SVC_ALL_ISRS_OPTION 2UL
+/*@}*/
+
+/**
+ * @name Start modes
+ * One of these values is passed to XIntc_Start() to start the device.
+ * @{
+ */
+/** Simulation only mode, no hardware interrupts recognized */
+#define XIN_SIMULATION_MODE     0
+/** Real mode, no simulation allowed, hardware interrupts recognized */
+#define XIN_REAL_MODE           1
+/*@}*/
+
+/**
+ * @name Masks to specify Interrupt Controller Mode
+ * @{
+ */
+#define XIN_INTC_NOCASCADE     	0	/* Normal - No Cascade Mode */
+#define XIN_INTC_PRIMARY     	1	/* Master/Primary controller */
+#define XIN_INTC_SECONDARY     	2	/* Secondary Slave Controllers */
+#define XIN_INTC_LAST     	3	/* Last Slave Controller */
+
+/*@}*/
+
+/**
+ * @name Mask to specify maximum number of interrupt sources per controller
+ * @{
+ */
+#define XIN_CONTROLLER_MAX_INTRS	32  /* Each Controller has 32
+					       interrupt pins */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	u32 AckBeforeService;	/**< Ack location per interrupt */
+	int FastIntr;		/**< Fast Interrupt enabled */
+	u32 IntVectorAddr;	/**< Interrupt Vector Address */
+	int NumberofIntrs;      /**< Number of Interrupt sources */
+	u32 Options;		/**< Device options */
+	int IntcType;		/**< Intc type 0 - No Cascade Mode
+				               1 - primary instance
+				               2 - secondary instance
+				               3 - last instance */
+
+/** Static vector table of interrupt handlers */
+#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
+	XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
+#else
+	XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
+#endif
+
+} XIntc_Config;
+
+/**
+ * The XIntc driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	u32 BaseAddress;	 /**< Base address of registers */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 IsStarted;		 /**< Device has been started */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+	XIntc_Config *CfgPtr;	 /**< Pointer to instance config entry */
+
+} XIntc;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xintc.c
+ */
+int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
+
+int XIntc_Start(XIntc * InstancePtr, u8 Mode);
+void XIntc_Stop(XIntc * InstancePtr);
+
+int XIntc_Connect(XIntc * InstancePtr, u8 Id,
+		  XInterruptHandler Handler, void *CallBackRef);
+void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
+
+void XIntc_Enable(XIntc * InstancePtr, u8 Id);
+void XIntc_Disable(XIntc * InstancePtr, u8 Id);
+
+void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
+
+XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
+
+int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
+				XFastInterruptHandler Handler);
+void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
+
+/*
+ * Interrupt functions in xintr_intr.c
+ */
+void XIntc_VoidInterruptHandler(void);
+void XIntc_InterruptHandler(XIntc * InstancePtr);
+
+/*
+ * Options functions in xintc_options.c
+ */
+int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
+u32 XIntc_GetOptions(XIntc * InstancePtr);
+
+/*
+ * Self-test functions in xintc_selftest.c
+ */
+int XIntc_SelfTest(XIntc * InstancePtr);
+int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xintc_l.h b/thirdparty/xilinx/include/xilinx/xintc_l.h
new file mode 100644
index 000000000..9d9c9eaff
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xintc_l.h
@@ -0,0 +1,330 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_l.h
+* @addtogroup intc_v3_4
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+*
+* Note that users of the driver interface given in this file can register
+* an interrupt handler dynamically (at run-time) using the
+* XIntc_RegisterHandler() function.
+* User of the driver interface given in xintc.h should still use
+* XIntc_Connect(), as always.
+* Also see the discussion of the interrupt vector tables in xintc.h.
+*
+* There are currently two interrupt handlers specified in this interface.
+*
+* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
+*   is used in cases where there is a single interrupt controller device in
+*   the system and the handler cannot be passed an argument. This function is
+*   provided mostly for backward compatibility.
+*
+* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
+*   argument, indicating which interrupt controller device in the system is
+*   causing the interrupt - thereby supporting multiple interrupt controllers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs. _m is removed from all
+*		      the macro definitions.
+* 2.04a bss  01/13/12 Updated for adding defines for IMR and IVAR for
+*                     the FAST Interrupt
+* 2.05a bss  08/18/12 Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.07a bss  10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_L_H		/* prevent circular inclusions */
+#define XINTC_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xil_io.h"
+
+/*
+ * XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
+ * accessed through a DCR bus connected to a bridge.
+ */
+#define XPAR_XINTC_USE_DCR_BRIDGE 0
+
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+#include "xio_dcr.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* define the offsets from the base address for all the registers of the
+ * interrupt controller, some registers may be optional in the hardware device
+ */
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+
+#define XIN_ISR_OFFSET      0	/* Interrupt Status Register */
+#define XIN_IPR_OFFSET      1	/* Interrupt Pending Register */
+#define XIN_IER_OFFSET      2	/* Interrupt Enable Register */
+#define XIN_IAR_OFFSET      3	/* Interrupt Acknowledge Register */
+#define XIN_SIE_OFFSET      4	/* Set Interrupt Enable Register */
+#define XIN_CIE_OFFSET      5	/* Clear Interrupt Enable Register */
+#define XIN_IVR_OFFSET      6	/* Interrupt Vector Register */
+#define XIN_MER_OFFSET      7	/* Master Enable Register */
+#define XIN_IMR_OFFSET      8	/* Interrupt Mode Register , this is present
+				 *  only for Fast Interrupt */
+#define XIN_IVAR_OFFSET     64  /* Interrupt Vector Address Register
+				 * Interrupt 0 Offest, this is present
+				 * only for Fast Interrupt */
+
+#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
+
+#define XIN_ISR_OFFSET      0	/* Interrupt Status Register */
+#define XIN_IPR_OFFSET      4	/* Interrupt Pending Register */
+#define XIN_IER_OFFSET      8	/* Interrupt Enable Register */
+#define XIN_IAR_OFFSET      12	/* Interrupt Acknowledge Register */
+#define XIN_SIE_OFFSET      16	/* Set Interrupt Enable Register */
+#define XIN_CIE_OFFSET      20	/* Clear Interrupt Enable Register */
+#define XIN_IVR_OFFSET      24	/* Interrupt Vector Register */
+#define XIN_MER_OFFSET      28	/* Master Enable Register */
+#define XIN_IMR_OFFSET      32	/* Interrupt Mode Register , this is present
+				 *  only for Fast Interrupt */
+#define XIN_ILR_OFFSET      36  /* Interrupt level register */
+#define XIN_IVAR_OFFSET     0x100 /* Interrupt Vector Address Register
+				   * Interrupt 0 Offest, this is present
+				   * only for Fast Interrupt */
+
+
+
+#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
+
+/* Bit definitions for the bits of the MER register */
+
+#define XIN_INT_MASTER_ENABLE_MASK      0x1UL
+#define XIN_INT_HARDWARE_ENABLE_MASK    0x2UL	/* once set cannot be cleared */
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the driver interface given in this file and an instance pointer for the
+ * driver interface given in xintc.h file.
+ */
+typedef struct {
+	XInterruptHandler Handler;
+	void *CallBackRef;
+} XIntc_VectorTableEntry;
+
+typedef void (*XFastInterruptHandler) (void);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Define the appropriate I/O access method to memory mapped I/O or DCR.
+ */
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+
+#define XIntc_In32  XIo_DcrIn
+#define XIntc_Out32 XIo_DcrOut
+
+#else
+
+#define XIntc_In32  Xil_In32
+#define XIntc_Out32 Xil_Out32
+
+#endif
+
+/****************************************************************************/
+/**
+*
+* Enable all interrupts in the Master Enable register of the interrupt
+* controller.  The interrupt controller defaults to all interrupts disabled
+* from reset such that this macro must be used to enable interrupts.
+*
+* @param	BaseAddress is the base address of the device.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_MasterEnable(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_MasterEnable(BaseAddress) \
+	XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
+	XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable all interrupts in the Master Enable register of the interrupt
+* controller.
+*
+* @param	BaseAddress is the base address of the device.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_MasterDisable(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_MasterDisable(BaseAddress) \
+	XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	EnableMask is the 32-bit value to write to the enable register.
+*		Each bit of the mask corresponds to an interrupt input signal
+*		that is connected to the interrupt controller (INT0 = LSB).
+*		Only the bits which are set in the mask will enable interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
+*
+*****************************************************************************/
+#define XIntc_EnableIntr(BaseAddress, EnableMask) \
+	XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	DisableMask is the 32-bit value to write to the enable register.
+*		Each bit of the mask corresponds to an interrupt input signal
+*		that is connected to the interrupt controller (INT0 = LSB).
+*		Only the bits which are set in the mask will disable interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
+*
+*****************************************************************************/
+#define XIntc_DisableIntr(BaseAddress, DisableMask) \
+	XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
+
+/****************************************************************************/
+/**
+*
+* Acknowledge specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	AckMask is the 32-bit value to write to the acknowledge
+*		register. Each bit of the mask corresponds to an interrupt input
+*		signal that is connected to the interrupt controller (INT0 =
+*		LSB).  Only the bits which are set in the mask will acknowledge
+*		interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
+*
+*****************************************************************************/
+#define XIntc_AckIntr(BaseAddress, AckMask) \
+	XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
+
+/****************************************************************************/
+/**
+*
+* Get the interrupt status from the interrupt controller which indicates
+* which interrupts are active and enabled.
+*
+* @param	BaseAddress is the base address of the device
+*
+* @return	The 32-bit contents of the interrupt status register. Each bit
+*		corresponds to an interrupt input signal that is connected to
+*		the interrupt controller (INT0 = LSB). Bits which are set
+*		indicate an active interrupt which is also enabled.
+*
+* @note		C-style signature:
+*		u32 XIntc_GetIntrStatus(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_GetIntrStatus(BaseAddress) \
+	(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
+	XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Interrupt controller handlers, to be connected to processor exception
+ * handling code.
+ */
+void XIntc_LowLevelInterruptHandler(void);
+void XIntc_DeviceInterruptHandler(void *DeviceId);
+
+/* Various configuration functions */
+void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option);
+
+void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
+			   XInterruptHandler Handler, void *CallBackRef);
+
+void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
+					XFastInterruptHandler FastHandler);
+
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xllfifo.h b/thirdparty/xilinx/include/xilinx/xllfifo.h
new file mode 100644
index 000000000..0afb38281
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xllfifo.h
@@ -0,0 +1,715 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xllfifo.h
+* @addtogroup llfifo_v5_0
+* @{
+* @details
+ *
+ * The Xilinx Dual Channel Fifo driver component. This driver supports the
+ * Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.
+ *
+ * For a full description of the bridge features, please see the HW spec. This
+ * driver supports the following features:
+ *   - Memory mapped access to host interface registers
+ *   - API for polled frame transfers
+ *   - API for interrupt driven frame transfers
+ *   - Virtual memory support
+ *   - Full duplex operation
+ *
+ * <h2>Driver Description</h2>
+ *
+ * This driver enables higher layer software to access the XPS_llFifo core
+ * using any alignment in the data buffers.
+ *
+ * This driver supports send and receive channels in the same instance
+ * structure in the same fashion as the hardware core.
+ *
+ * <h2>Initialization</h2>
+ *
+ * An instance of this driver is initialized using a call to Initialize().
+ *
+ * <h2>Usage</h2>
+ *
+ * It is fairly simple to use the API provided by this FIFO driver. The
+ * only somewhat tricky part is that the calling code must correctly call
+ * a couple routines in the right sequence for receive and transmit.
+ *
+ * This sequence is described here. Check the routine functional
+ * descriptions for information on how to use a specific API routine.
+ *
+ * <h3>Receive</h3>
+ *
+ * A frame is received by using the following sequence:<br>
+ * 1) call XLlFifo_RxOccupancy() to check the occupancy count<br>
+ * 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame<br>
+ * 3) call XLlFifo_Read() one or more times to read the number of bytes
+ *    reported by XLlFifo_RxGetLen().<br>
+ *
+ * For example:
+ * <pre>
+ * 	while (XLlFifo_RxOccupancy(&RxInstance)) {
+ * 		frame_len = XLlFifo_RxGetLen(&RxInstance);
+ *		while (frame_len) {
+ * 			unsigned bytes = min(sizeof(buffer), frame_len);
+ * 			XLlFifo_Read(&RxInstance, buffer, bytes);
+ * 			// ********
+ * 			// do something with buffer here
+ * 			// ********
+ * 			frame_len -= bytes;
+ *		}
+ * 	}
+ * </pre>
+ *
+ * This FIFO hardware core does <b>not</b> support a sequence where the
+ * calling code calls RxGetLen() twice in a row and then receive the data
+ * for two frames. Each frame must be read in by calling RxGetLen() just
+ * prior to reading the data.
+ *
+ * <h3>Transmit</h3>
+ * A frame is transmittted by using the following sequence:<br>
+ * 1) call XLlFifo_Write() one or more times to write all the of bytes in
+ *    the next frame.<br>
+ * 2) call XLlFifo_TxSetLen() to begin the transmission of frame just
+ *    written.<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_left = frame_len;
+ * 	while (frame_left) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_left);
+ * 		XLlFifo_Write(&TxInstance, buffer, bytes);
+ * 		// ********
+ * 		// do something here to refill buffer
+ * 		// ********
+ * 		frame_left -= bytes;
+ * 	}
+ * 	XLlFifo_TxSetLen(&RxInstance, frame_len);
+ * </pre>
+ *
+ * This FIFO hardware core does <b>not</b> support a sequence where the
+ * calling code writes the data for two frames and then calls TxSetLen()
+ * twice in a row. Each frame must be written by writting the data for one
+ * frame and then calling TxSetLen().
+ *
+ * <h2>Interrupts</h2>
+ * This driver does not handle interrupts from the FIFO hardware. The
+ * software layer above may make use of the interrupts by setting up its
+ * own handlers for the interrupts.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/12/06 First release
+ * 1.01a sdm  08/22/08 Removed support for static interrupt handlers from the
+ *		       MDD file
+ * 1.02a jz   12/04/09 Hal phase 1 support
+ * 2.01a asa  09/17/10 Added code for resetting Local Link/AXI Streaming
+ *		       interface for CR574868
+ * 2.02a asa  12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
+ *		       HeadIndex to zero when all bytes have been read.
+ *		       Changed the macro XStrm_IsRxInternalEmpty in file
+ *		       xtreamer.h to use FrmByteCnt instead of HeadIndex.
+ *		       When FrmByteCnt is zero, this means all internal buffers
+ *		       in streamer are empty. Earlier implementation using
+ *		       HeadIndex was not very clear and could give improper
+ *		       results for some cases.
+ *		       Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
+ *		       These changes are done to fix the CR 604650.
+  * 2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+ *		         defines for the new registers, and XLLF_INT_TFPF_MASK,
+ *		         XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+ *		         XLLF_INT_RFPE_MASK for the new version of the
+ *		         AXI4-Stream FIFO core (v2.01a and later)
+ *
+ * 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
+ * 		      In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
+ * 		      In XLlfifo.h file updated XLlfifo structure for
+ * 		      Axi4BaseAddress and for Datainterface type provided
+ *		      polling and interrupt examples. XLlfifo_IsRxDone Macro
+ *		      Is added in the XLlfifo.h file for polledmode exmaple.
+ *		      Added Static initialzation for the driver.
+ *		      XLlFifo_Initialize is still used to make the driver
+ *		      backward compatible.
+ * 4.0   adk  19/12/13 Updated as per the New Tcl API's
+ * 5.0   adk  15/05/15 Updated the register offsets in the AXI4 data path
+ *		       as per latest IP version(v4.1)(CR:860254).
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+#ifndef XLLFIFO_H		/* prevent circular inclusions */
+#define XLLFIFO_H		/* by using preprocessor symbols */
+
+/* force C linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+/* This order needs to be kept this way to avoid xstatus/xil_types conflict */
+#include "xstreamer.h"
+#include "xllfifo_hw.h"
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines a run-time instance of an XLlFifo device.
+ */
+typedef struct XLlFifo {
+	u32 BaseAddress;  /**< BaseAddress is the physical base address of the
+	                   *   device's registers
+	                   */
+
+	u32 IsReady;           /**< IsReady is non-zero if the driver instance
+	                        *   has been initialized.
+	                        */
+
+	u32 Axi4BaseAddress;	/**< BaseAddress if the FIFO Data interface is
+				 *	AXI4 this address should use for FIFO
+				 *	access
+				 */
+	u32 Datainterface;	/**< Data interface of the FIFO. This value is zero
+				 *	if the Datainterface is AXI4-lite.
+				 */
+	XStrm_RxFifoStreamer RxStreamer; /**< RxStreamer is the byte streamer
+	                                  *   instance for the receive channel.
+	                                  */
+	XStrm_TxFifoStreamer TxStreamer; /**< TxStreamer is the byte streamer
+	                                  *   instance for the transmit channel.
+	                                  */
+} XLlFifo;
+
+typedef struct XLlFifo_Config {
+	u32 DeviceId;		/**< Deviceid of the AXI FIFO */
+	u32 BaseAddress;	/**< Base Address of the AXI FIFO */
+	u32 Axi4BaseAddress;    /**< Axi4 interface Base address */
+	u32 Datainterface;	/**< Type of Datainterface */
+}XLlFifo_Config;
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_Reset resets both the Tx and Rx channels and the local link interface
+* the FIFO specified by <i>InstancePtr</i>. XLlFifo_TxReset resets also sends a
+* reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any
+* bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO
+* not yet transmitted.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_Reset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Reset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \
+			XLLF_LLR_RESET_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_Status returns a bit mask of the interrupt status register (ISR)
+* for the FIFO specified by <i>InstancePtr</i>. XLlFifo_Status can be used
+* to query the status of the FIFO without having to have interrupts enabled.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IntStatus returns a bit mask of the status conditions.
+*           The mask will be a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Status(InstancePtr) \
+	 XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntEnable enables the interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
+* set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the interrupts to enable. The mask
+*           can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntEnable(InstancePtr, Mask) \
+{ \
+	u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+			XLLF_IER_OFFSET); \
+	Reg |= ((Mask) & XLLF_INT_ALL_MASK);                    \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+			Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntDisable disables the interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
+* set to 1 in <i>Mask</i>, will be disabled. In other words, XLlFifo_IntDisable
+* uses the "set a bit to clear it" scheme.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the interrupts to disable. The mask
+*           can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntDisable(InstancePtr, Mask) \
+{ \
+	u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+			XLLF_IER_OFFSET); \
+	Reg &= ~((Mask) & XLLF_INT_ALL_MASK);  \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+			Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntPending returns a bit mask of the pending interrupts for the
+* FIFO specified by <i>InstancePtr</i>. Each bit set to 1 in the return value
+* represents a pending interrupt.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IntPending returns a bit mask of the interrupts that are
+*           pending. The mask will be a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_ipie_value;
+extern u32 _xllfifo_ipis_value;
+#define XLlFifo_IntPending(InstancePtr) \
+	(_xllfifo_ipie_value = XLlFifo_ReadReg( \
+		(InstancePtr)->BaseAddress, XLLF_IER_OFFSET),  \
+	_xllfifo_ipis_value = XLlFifo_ReadReg( \
+		(InstancePtr)->BaseAddress, XLLF_ISR_OFFSET),  \
+	(_xllfifo_ipie_value & _xllfifo_ipis_value))
+#else
+#define XLlFifo_IntPending(InstancePtr) \
+	(XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) &  \
+	 XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntClear clears pending interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding pending interrupt for
+* each bit set to 1 in <i>Mask</i>, will be cleared. In other words,
+* XLlFifo_IntClear uses the "set a bit to clear it" scheme.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the pending interrupts to clear. The
+*           mask can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntClear(InstancePtr, Mask) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
+			((Mask) & XLLF_INT_ALL_MASK))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_RxReset resets the receive channel of the FIFO specified by
+* <i>InstancePtr</i>. XLlFifo_RxReset drops any bytes in the FIFO not yet
+* retrieved.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Rx Reset
+* complete (RRC) bit.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_RxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_RxReset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
+			XLLF_RDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified
+* by <i>InstancePtr</i>, is empty.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsRxEmpty returns TRUE when the receive channel of the
+*           FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxEmpty(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
+							? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the receive channel of the FIFO, specified by <i>InstancePtr</i>.
+*
+* The xps_ll_fifo core uses the same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_RxOccupancy will give the value of
+* 1, which means one length value (a reserved fifo location) and no data
+* values.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxOccupancy returns the occupancy count for the specified
+*           packet FIFO.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxOccupancy(InstancePtr) \
+	XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxGetLen notifies the hardware that the program is ready to receive
+* the next frame from the receive channel of the FIFO, specified by
+* <i>InstancePtr</i>.
+*
+* Note that the program must first call XLlFifo_RxGetLen before pulling data
+* out of the receive channel of the FIFO with XLlFifo_Read.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxGetLen returns the number of bytes available in the next
+*           frame.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxGetLen(InstancePtr) \
+	XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Read reads <i>Bytes</i> bytes from the receive channel of the FIFO
+* referenced by <i>InstancePtr</i> to the block of memory, referenced by
+* <i>BufPtr</i>.
+*
+* Care must be taken to ensure that the number of bytes read with one or more
+* calls to XLlFifo_Read() does not exceed the number of bytes available given
+* from the last call to XLlFifo_RxGetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address to place the data read.
+*
+* @param    Bytes specifies the number of bytes to read.
+*
+* @return   N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Read(InstancePtr, BufPtr, Bytes) \
+	XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxReset resets the transmit channel of the FIFO specified by
+* <i>InstancePtr</i>. XLlFifo_TxReset drops any bytes in the FIFO not yet
+* transmitted.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Tx Reset
+* complete (TRC) bit.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_TxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxReset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
+			XLLF_TDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsTxDone returns true if the transmission in the transmit channel
+* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsTxDone
+* works only if the TC bit in the IS register is cleared before sending a
+* frame.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsTxDone returns TRUE when the transmit channel of the
+*           FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsTxDone(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+		XLLF_INT_TC_MASK) \
+		? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxDone returns true if the reception in the receive channel
+* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsRxDone
+* works only if the RC bit in the ISR register is cleared before receiving a
+* frame.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsRxDone returns TRUE when the receive channel of the
+*           FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxDone(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+		XLLF_INT_RC_MASK) \
+		? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxVacancy returns the number of unused 32 bit words available
+* (vacancy) in the send channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_TxVacancy will give the value of
+* FIFO_WIDTH - 1, which means one length value used (a reserved fifo location)
+* and no data values yet present.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_TxVacancy returns the vacancy count in 32-bit words for
+*           the specified FIFO.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxVacancy(InstancePtr) \
+	XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_TxSetLen begins a hardware transfer of <i>Bytes</i> bytes out of the
+* transmit channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Bytes specifies the frame length in bytes.
+*
+* @return   N/A
+*
+* @note
+*
+* C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)
+*
+******************************************************************************/
+#define XLlFifo_TxSetLen(InstancePtr, Bytes) \
+	XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
+* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
+* <i>InstancePtr</i>.
+*
+* Care must be taken to ensure that the number of bytes written with one or
+* more calls to XLlFifo_Write() matches the number of bytes given in the next
+* call to XLlFifo_TxSetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address of data to write.
+*
+* @param    Bytes specifies the number of bytes to write.
+*
+* @return   N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Write(InstancePtr, BufPtr, Bytes) \
+	XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)
+*
+* The TDR stores the destination address corresponding to the packet to  be
+* transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core
+* the following sequence should be followed
+*  - Write the destination address into TDR first,
+*  - Write the packet data to the Transmit Data FIFO next
+*  - Write the length of the packet into the Transmit Length Register.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+* @param    Tdest is the Transmit Destination address to be written to TDR.
+*
+* @return   N/A
+*
+* @note		C Signature:
+*		void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
+*
+******************************************************************************/
+#define XLlFifo_WriteTdr(InstancePtr, Tdest) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
+			  Tdest & 0xF)
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).
+*
+* The RDR contains destination address corresponding to the valid packet that
+* is received. The RDR should only be read when a receive packet is available
+* for processing (the receive occupancy is not zero).
+* Once the RDR is read, the receive packet data should be read from the receive
+* data FIFO before the RDR is read again. The RDR values are stored in the
+* receive data FIFO by the AXI4-Stream FIFO core with the data of each packet.
+* The RDR value for the subsequent packet to be processed is moved to the RDR
+* when the previous RDR value has been read.
+*
+* @param    	InstancePtr references the FIFO on which to operate.
+*
+* @return   	The Receive Destination address  read from the RDR.
+*
+* @note		C Signature:
+*		u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_ReadRdr(InstancePtr) 				\
+	XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+/*
+ * Initialization functions xllfifo.c
+ */
+int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
+			XLlFifo_Config *Config, u32 EffectiveAddress);
+void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress);
+XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId);
+u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr);
+u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr);
+u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr);
+void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes);
+u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr);
+void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XLLFIFO_H  end of preprocessor protection symbols */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xllfifo_hw.h b/thirdparty/xilinx/include/xilinx/xllfifo_hw.h
new file mode 100644
index 000000000..694dd358e
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xllfifo_hw.h
@@ -0,0 +1,242 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xllfifo_hw.h
+* @addtogroup llfifo_v5_0
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the xps_ll_fifo core.
+* High-level driver functions are defined in xpfifo.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jvb  10/16/06 First release.
+* 1.02a jz   12/04/09  Hal phase 1 support
+* 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+* 2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+*		       defines for the new registers, and XLLF_INT_TFPF_MASK,
+*		       XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+*		       XLLF_INT_RFPE_MASK for the new version of the
+*		       AXI4-Stream FIFO core (v2.01a and later)
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XLLFIFO_HW_H		/* prevent circular inclusions */
+#define XLLFIFO_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xdebug.h"
+#include "xil_io.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit.
+ */
+
+/** @name Registers
+ *  @{
+ */
+#define XLLF_ISR_OFFSET  0x00000000  /**< Interrupt Status */
+#define XLLF_IER_OFFSET  0x00000004  /**< Interrupt Enable */
+
+#define XLLF_TDFR_OFFSET 0x00000008  /**< Transmit Reset */
+#define XLLF_TDFV_OFFSET 0x0000000c  /**< Transmit Vacancy */
+#define XLLF_TDFD_OFFSET 0x00000010  /**< Transmit Data */
+#define XLLF_AXI4_TDFD_OFFSET   0x00000000  /**< Axi4 Transmit Data */
+#define XLLF_TLF_OFFSET  0x00000014  /**< Transmit Length */
+
+#define XLLF_RDFR_OFFSET 0x00000018  /**< Receive Reset */
+#define XLLF_RDFO_OFFSET 0x0000001c  /**< Receive Occupancy */
+#define XLLF_RDFD_OFFSET 0x00000020  /**< Receive Data */
+#define XLLF_AXI4_RDFD_OFFSET 	0x00001000  /**< Axi4 Receive Data */
+#define XLLF_RLF_OFFSET  0x00000024  /**< Receive Length */
+#define XLLF_LLR_OFFSET  0x00000028  /**< Local Link Reset */
+#define XLLF_TDR_OFFSET  0x0000002C  /**< Transmit Destination  */
+#define XLLF_RDR_OFFSET  0x00000030  /**< Receive Destination  */
+
+/*@}*/
+
+/* Register masks. The following constants define bit locations of various
+ * control bits in the registers. Constants are not defined for those registers
+ * that have a single bit field representing all 32 bits. For further
+ * information on the meaning of the various bit masks, refer to the HW spec.
+ */
+
+/** @name Interrupt bits
+ *  These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET
+ *  registers.
+ * @{
+ */
+#define XLLF_INT_RPURE_MASK       0x80000000 /**< Receive under-read */
+#define XLLF_INT_RPORE_MASK       0x40000000 /**< Receive over-read */
+#define XLLF_INT_RPUE_MASK        0x20000000 /**< Receive underrun (empty) */
+#define XLLF_INT_TPOE_MASK        0x10000000 /**< Transmit overrun */
+#define XLLF_INT_TC_MASK          0x08000000 /**< Transmit complete */
+#define XLLF_INT_RC_MASK          0x04000000 /**< Receive complete */
+#define XLLF_INT_TSE_MASK         0x02000000 /**< Transmit length mismatch */
+#define XLLF_INT_TRC_MASK         0x01000000 /**< Transmit reset complete */
+#define XLLF_INT_RRC_MASK         0x00800000 /**< Receive reset complete */
+#define XLLF_INT_TFPF_MASK        0x00400000 /**< Tx FIFO Programmable Full,
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_TFPE_MASK        0x00200000 /**< Tx FIFO Programmable Empty
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_RFPF_MASK        0x00100000 /**< Rx FIFO Programmable Full
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_RFPE_MASK        0x00080000 /**< Rx FIFO Programmable Empty
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_ALL_MASK         0xfff80000 /**< All the ints */
+#define XLLF_INT_ERROR_MASK       0xf2000000 /**< Error status ints */
+#define XLLF_INT_RXERROR_MASK     0xe0000000 /**< Receive Error status ints */
+#define XLLF_INT_TXERROR_MASK     0x12000000 /**< Transmit Error status ints */
+/*@}*/
+
+/** @name Reset register values
+ *  These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET
+ *  reset registers.
+ * @{
+ */
+#define XLLF_RDFR_RESET_MASK        0x000000a5 /**< receive reset value */
+#define XLLF_TDFR_RESET_MASK        0x000000a5 /**< Transmit reset value */
+#define XLLF_LLR_RESET_MASK         0x000000a5 /**< Local Link reset value */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**** debug macros ****/
+#define XLlFifo_reg_name(RegOffset) \
+	(((RegOffset) == XLLF_ISR_OFFSET) ? "ISR": \
+	((RegOffset) == XLLF_IER_OFFSET) ? "IER": \
+	((RegOffset) == XLLF_TDFR_OFFSET) ? "TDFR {tx reset}": \
+	((RegOffset) == XLLF_TDFV_OFFSET) ? "TDFV {tx vacancy}": \
+	((RegOffset) == XLLF_TDFD_OFFSET) ? "TDFD {tx data}": \
+	((RegOffset) == XLLF_TLF_OFFSET) ? "TLF {tx length}": \
+	((RegOffset) == XLLF_RDFR_OFFSET) ? "RDFR {rx reset}": \
+	((RegOffset) == XLLF_RDFO_OFFSET) ? "RDFO {rx occupancy}": \
+	((RegOffset) == XLLF_RDFD_OFFSET) ? "RDFD {rx data}": \
+	((RegOffset) == XLLF_RLF_OFFSET) ? "RLF {rx length}": \
+	"unknown")
+
+#define XLlFifo_print_reg_o(BaseAddress, RegOffset, Value) \
+	 xdbg_printf(XDBG_DEBUG_FIFO_REG, "0x%08x -> %s(0x%08x)\n", (Value), \
+			  XLlFifo_reg_name(RegOffset), \
+			 (RegOffset) + (BaseAddress))
+
+#define XLlFifo_print_reg_i(BaseAddress, RegOffset, Value) \
+	xdbg_printf(XDBG_DEBUG_FIFO_REG, "%s(0x%08x) -> 0x%08x\n", \
+			 XLlFifo_reg_name(RegOffset), \
+			(RegOffset) + (BaseAddress), (Value))
+/**** end debug macros ****/
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_ReadReg returns the value of the register at the offet,
+* <i>RegOffset</i>, from the memory mapped base address, <i>BaseAddress</i>.
+*
+* @param    BaseAddress specifies the base address of the device.
+*
+* @param    RegOffset specifies the offset from BaseAddress.
+*
+* @return   XLlFifo_ReadReg returns the value of the specified register.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_rr_value;
+#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
+	((((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
+		"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
+		(RegOffset)) : 0), \
+	_xllfifo_rr_value = Xil_In32((BaseAddress) + (RegOffset)), \
+	XLlFifo_print_reg_i((BaseAddress), (RegOffset), _xllfifo_rr_value), \
+	_xllfifo_rr_value)
+#else
+#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_WriteReg writes the value, <i>Value</i>, to the register at the
+* offet, <i>RegOffset</i>, from the memory mapped base address,
+* <i>BaseAddress</i>.
+*
+* @param    BaseAddress specifies the base address of the device.
+*
+* @param    RegOffset specifies the offset from BaseAddress.
+*
+* @param    Value is value to write to the register.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)
+*
+*****************************************************************************/
+#ifdef DEBUG
+#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
+	(((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
+		"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
+		(RegOffset)) : 0), \
+	XLlFifo_print_reg_o((BaseAddress), (RegOffset), (Value)), \
+	(Xil_Out32((BaseAddress) + (RegOffset), (Value)))
+#else
+#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
+	((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XLLFIFO_HW_H  end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xparameters.h b/thirdparty/xilinx/include/xilinx/xparameters.h
new file mode 100644
index 000000000..279ab6a47
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xparameters.h
@@ -0,0 +1,16 @@
+#ifndef _X_PARAMETERS_H_
+#define _X_PARAMETERS_H_
+
+/* We set all instance counters to zero
+ * to avoid the generation of configuration tables
+ * See: *_g.c, *_sinit.c source files
+ */
+#define XPAR_XLLFIFO_NUM_INSTANCES 0
+#define XPAR_XTMRCTR_NUM_INSTANCES 0
+#define XPAR_XAXIDMA_NUM_INSTANCES 0
+#define XPAR_XAXIS_SWITCH_NUM_INSTANCES 0
+
+#define XPAR_XINTC_NUM_INSTANCES 0
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 0
+
+#endif
\ No newline at end of file
diff --git a/thirdparty/xilinx/include/xilinx/xstatus.h b/thirdparty/xilinx/include/xilinx/xstatus.h
new file mode 100644
index 000000000..a8caf2f4e
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xstatus.h
@@ -0,0 +1,432 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xstreamer.h b/thirdparty/xilinx/include/xilinx/xstreamer.h
new file mode 100644
index 000000000..bbb65f0e9
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xstreamer.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*
+ *
+ * @file xstreamer.h
+* @addtogroup llfifo_v5_0
+* @{
+ *
+ * The Xilinx byte streamer for packet FIFOs.
+ *
+ * <h2>Driver Description</h2>
+ *
+ * This driver enables higher layer software to access a hardware FIFO using
+ * any alignment in the data buffers while preserving alignment for the hardware
+ * FIFO access.
+ *
+ * This driver treats send and receive channels separately, using different
+ * types of instance objects for each.
+ *
+ * This driver makes use of another FIFO driver to access the specific FIFO
+ * hardware through use of the routines passed into the Tx/RxInitialize
+ * routines.
+ *
+ * <h2>Initialization</h2>
+ *
+ * Send and receive channels are intialized separately. The receive channel is
+ * initiailzed using XStrm_RxInitialize(). The send channel is initialized
+ * using XStrm_TxInitialize().
+ *
+ *
+ * <h2>Usage</h2>
+ * It is fairly simple to use the API provided by this byte streamer
+ * driver. The only somewhat tricky part is that the calling code must
+ * correctly call a couple routines in the right sequence for receive and
+ * transmit.
+ *
+ * 	This sequence is described here. Check the routine functional
+ * descriptions for information on how to use a specific API routine.
+ *
+ * <h3>Receive</h3>
+ * A frame is received by using the following sequence:<br>
+ * 1) call XStrm_RxGetLen() to get the length of the next incoming frame.<br>
+ * 2) call XStrm_Read() one or more times to read the number of bytes
+ * 	   reported by XStrm_RxGetLen().<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_len = XStrm_RxGetLen(&RxInstance);
+ * 	while (frame_len) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_len);
+ * 		XStrm_Read(&RxInstance, buffer, bytes);
+ * 		// do something with buffer here
+ * 		frame_len -= bytes;
+ * 	}
+ * </pre>
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * <h3>Transmit</h3>
+ * A frame is transmittted by using the following sequence:<br>
+ * 1) call XStrm_Write() one or more times to write all the of bytes in
+ *    the next frame.<br>
+ * 2) call XStrm_TxSetLen() to begin the transmission of frame just
+ *    written.<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_left = frame_len;
+ * 	while (frame_left) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_left);
+ * 		XStrm_Write(&TxInstance, buffer, bytes);
+ * 		// do something here to refill buffer
+ * 	}
+ * 	XStrm_TxSetLen(&RxInstance, frame_len);
+ * </pre>
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/12/06 First release
+ * 1.02a jz   12/04/09  Hal phase 1 support
+ * 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+ * 2.02a asa  12/28/11  The macro XStrm_IsRxInternalEmpty is changed to use
+ *			FrmByteCnt instead of HeadIndex.
+ * </pre>
+ *
+ *****************************************************************************/
+#ifndef XSTREAMER_H		/* prevent circular inclusions */
+#define XSTREAMER_H		/* by using preprocessor symbols */
+
+/* force C linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xenv.h"
+#include "xdebug.h"
+#include "xil_types.h"
+
+/*
+ * key hole size in 32 bit words
+ */
+#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS 4
+
+/*
+ * This union is used simply to force a 32bit alignment on the
+ * buffer. Only the 'bytes' member is really used.
+ */
+union XStrm_AlignedBufferType {
+	u32 _words[LARGEST_FIFO_KEYHOLE_SIZE_WORDS];
+	char bytes[LARGEST_FIFO_KEYHOLE_SIZE_WORDS * 4];
+};
+
+typedef int(*XStrm_XferFnType) (void *FifoInstance, void *BufPtr,
+                                    unsigned WordCount);
+typedef u32 (*XStrm_GetLenFnType) (void *FifoInstance);
+typedef void (*XStrm_SetLenFnType) (void *FifoInstance,
+                                    u32 ByteCount);
+typedef u32 (*XStrm_GetOccupancyFnType) (void *FifoInstance);
+typedef u32 (*XStrm_GetVacancyFnType) (void *FifoInstance);
+
+/**
+ * This typedef defines a run-time instance of a receive byte-streamer.
+ */
+typedef struct XStrm_RxFifoStreamer {
+	union XStrm_AlignedBufferType AlignedBuffer;
+	unsigned HeadIndex;  /**< HeadIndex is the index to the AlignedBuffer
+	                      *   as bytes.
+                              */
+	unsigned FifoWidth;  /**< FifoWidth is the FIFO key hole width in bytes.
+	                      */
+	unsigned FrmByteCnt; /**< FrmByteCnt is the number of bytes in the next
+			      *   Frame.
+			      */
+	void *FifoInstance;  /**< FifoInstance is the FIFO driver instance to
+	                      *   pass to ReadFn, GetLenFn, and GetOccupancyFn
+	                      *   routines.
+	                      */
+	XStrm_XferFnType ReadFn;     /**< ReadFn is the routine the streamer
+	                              *   uses to receive bytes from the Fifo.
+	                              */
+	XStrm_GetLenFnType GetLenFn; /**< GetLenFn is the routine the streamer
+	                              *   uses to initiate receive operations
+	                              *   on the FIFO.
+                                      */
+	XStrm_GetOccupancyFnType GetOccupancyFn; /**< GetOccupancyFn is the
+	                                          *   routine the streamer uses
+	                                          *   to get the occupancy from
+	                                          *   the FIFO.
+	                                          */
+} XStrm_RxFifoStreamer;
+
+/**
+ * This typedef defines a run-time instance of a transmit byte-streamer.
+ */
+typedef struct XStrm_TxFifoStreamer {
+	union XStrm_AlignedBufferType AlignedBuffer;
+	unsigned TailIndex; /**< TailIndex is the index to the AlignedBuffer
+	                     *   as bytes
+                             */
+	unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes.
+	                     */
+
+	void *FifoInstance; /**< FifoInstance is the FIFO driver instance to
+	                     *   pass to WriteFn, SetLenFn, and GetVacancyFn
+	                     *   routines.
+	                     */
+	XStrm_XferFnType WriteFn; /**< WriteFn is the routine the streamer
+	                           *   uses to transmit bytes to the Fifo.
+	                           */
+	XStrm_SetLenFnType SetLenFn; /**< SetLenFn is the routine the streamer
+	                              *   uses to initiate transmit operations
+	                              *   on the FIFO.
+                                      */
+	XStrm_GetVacancyFnType GetVacancyFn; /**< GetVaccancyFn is the routine
+	                                      *   the streamer uses to get the
+	                                      *   vacancy from the FIFO.
+	                                      */
+} XStrm_TxFifoStreamer;
+
+/*****************************************************************************/
+/*
+*
+* XStrm_TxVacancy returns the number of unused 32-bit words available (vacancy)
+* between the streamer, specified by <i>InstancePtr</i>, and the FIFO this
+* streamer is using.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_TxVacancy returns the vacancy count in number of 32 bit words.
+*
+* @note
+*
+* C Signature: u32 XStrm_TxVacancy(XStrm_TxFifoStreamer *InstancePtr)
+*
+* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
+* is subtracted from the vacancy value of FIFO this streamer is using. This is
+* to ensure the caller can write the number words given in the return value and
+* not overflow the FIFO.
+*
+******************************************************************************/
+#define XStrm_TxVacancy(InstancePtr) \
+	(((*(InstancePtr)->GetVacancyFn)((InstancePtr)->FifoInstance)) - \
+			(((InstancePtr)->TailIndex + 3) / 4))
+
+/*****************************************************************************/
+/*
+*
+* XStrm_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the streamer, specified by <i>InstancePtr</i>, and FIFO this
+* steamer is using.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_RxOccupancy returns the occupancy count in number of 32 bit
+*           words.
+*
+* @note
+*
+* C Signature: u32 XStrm_RxOccupancy(XStrm_RxFifoStreamer *InstancePtr)
+*
+* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
+* is added to the occupancy value of FIFO this streamer is using. This is to
+* ensure the caller will get a little more accurate occupancy value.
+*
+******************************************************************************/
+#ifdef DEBUG
+extern u32 _xstrm_ro_value;
+extern u32 _xstrm_buffered;
+#define XStrm_RxOccupancy(InstancePtr) \
+        (_xstrm_ro_value = ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "reg: %d; frmbytecnt: %d\n", \
+		_xstrm_ro_value, (InstancePtr)->FrmByteCnt), \
+	(((InstancePtr)->FrmByteCnt) ? \
+		_xstrm_buffered = ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+		0), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered_bytes: %d\n", _xstrm_buffered), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered (rounded): %d\n", _xstrm_buffered), \
+	(_xstrm_ro_value + _xstrm_buffered))
+#else
+#define XStrm_RxOccupancy(InstancePtr) \
+	( \
+	  ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)) + \
+	  ( \
+	    ((InstancePtr)->FrmByteCnt) ? \
+	      ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+	      0 \
+	  ) \
+	)
+#endif
+
+/****************************************************************************/
+/*
+*
+* XStrm_IsRxInternalEmpty returns true if the streamer, specified by
+* <i>InstancePtr</i>, is not holding any bytes in it's  internal buffers. Note
+* that this routine does not reflect information about the state of the
+* FIFO used by this streamer.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_IsRxInternalEmpty returns TRUE when the streamer is not
+*           holding any bytes in it's internal buffers. Otherwise,
+*           XStrm_IsRxInternalEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XStrm_IsRxInternalEmpty(XStrm_RxFifoStreamer *InstancePtr)
+*
+*****************************************************************************/
+#define XStrm_IsRxInternalEmpty(InstancePtr) \
+	(((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE)
+
+void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr,
+                        unsigned FifoWidth, void *FifoInstance,
+                        XStrm_XferFnType ReadFn,
+                        XStrm_GetLenFnType GetLenFn,
+                        XStrm_GetOccupancyFnType GetOccupancyFn);
+
+void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr,
+                        unsigned FifoWidth, void *FifoInstance,
+                        XStrm_XferFnType WriteFn,
+                        XStrm_SetLenFnType SetLenFn,
+                        XStrm_GetVacancyFnType GetVacancyFn);
+
+void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes);
+void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr,
+                    unsigned bytes);
+
+u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr);
+void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr,
+                   unsigned bytes);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XSTREAMER_H  end of preprocessor protection symbols */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xtmrctr.h b/thirdparty/xilinx/include/xilinx/xtmrctr.h
new file mode 100644
index 000000000..5b8238043
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xtmrctr.h
@@ -0,0 +1,303 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr.h
+* @addtogroup tmrctr_v4_0
+* @{
+* @details
+*
+* The Xilinx timer/counter component. This component supports the Xilinx
+* timer/counter. More detailed description of the driver operation can
+* be found in the xtmrctr.c file.
+*
+* The Xilinx timer/counter supports the following features:
+*   - Polled mode.
+*   - Interrupt driven mode
+*   - enabling and disabling specific timers
+*   - PWM operation
+*   - Cascade Operation (This is to be used for getting a 64 bit timer and this
+*     feature is present in the latest versions of the axi_timer IP)
+*
+* The driver does not currently support the PWM operation of the device.
+*
+* The timer counter operates in 2 primary modes, compare and capture. In
+* either mode, the timer counter may count up or down, with up being the
+* default.
+*
+* Compare mode is typically used for creating a single time period or multiple
+* repeating time periods in the auto reload mode, such as a periodic interrupt.
+* When started, the timer counter loads an initial value, referred to as the
+* compare value, into the timer counter and starts counting down or up. The
+* timer counter expires when it rolls over/under depending upon the mode of
+* counting. An external compare output signal may be configured such that a
+* pulse is generated with this signal when it hits the compare value.
+*
+* Capture mode is typically used for measuring the time period between
+* external events. This mode uses an external capture input signal to cause
+* the value of the timer counter to be captured. When started, the timer
+* counter loads an initial value, referred to as the compare value,
+
+* The timer can be configured to either cause an interrupt when the count
+* reaches the compare value in compare mode or latch the current count
+* value in the capture register when an external input is asserted
+* in capture mode. The external capture input can be enabled/disabled using the
+* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
+* drive an external output when the compare value is reached in the count
+* register The external compare output can be enabled/disabled using the
+* XTmrCtr_SetOptions function.
+*
+* <b>Interrupts</b>
+*
+* It is the responsibility of the application to connect the interrupt
+* handler of the timer/counter to the interrupt source. The interrupt
+* handler function, XTmrCtr_InterruptHandler, is visible such that the user
+* can connect it to the interrupt source. Note that this interrupt handler
+* does not provide interrupt context save and restore processing, the user
+* must perform this processing.
+*
+* The driver services interrupts and passes timeouts to the upper layer
+* software through callback functions. The upper layer software must register
+* its callback functions during initialization. The driver requires callback
+* functions for timers.
+*
+* @note
+* The default settings for the timers are:
+*   - Interrupt generation disabled
+*   - Count up mode
+*   - Compare mode
+*   - Hold counter (will not reload the timer)
+*   - External compare output disabled
+*   - External capture input disabled
+*   - Pulse width modulation disabled
+*   - Timer disabled, waits for Start function to be called
+* <br><br>
+* A timer counter device may contain multiple timer counters. The symbol
+* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
+* The device currently contains 2 timer counters.
+* <br><br>
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.10b mta  03/21/07 Updated to new coding style.
+* 1.11a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+*		      file
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+*		      for naming consistency (CR 559142).
+* 2.02a sdm  09/28/10 Updated the driver tcl to generate the xparameters
+*		      for the timer clock frequency (CR 572679).
+* 2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
+*		      processing for CR 584557.
+* 2.04a sdm  07/12/11 Added support for cascade mode operation.
+* 		      The cascade mode of operation is present in the latest
+*		      versions of the axi_timer IP. Please check the HW
+*		      Datasheet to see whether this feature is present in the
+*		      version of the IP that you are using.
+* 2.05a adk  15/05/13 Fixed the CR:693066
+*		      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
+*		      XTmrCtr instance structure.
+*		      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
+*		      the XTmrCtr_Start function.
+*		      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
+*		      There will be no Initialization done in the
+*		      XTmrCtr_Initialize if both the timers have already started and
+*		      the XST_DEVICE_IS_STARTED Status is returned.
+*		      Removed the logic in the XTmrCtr_Initialize function
+*		      which was checking the Register Value to know whether
+*		      a timer has started or not.
+* 3.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.0   als  09/30/15 Updated initialization API.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_H		/* prevent circular inclusions */
+#define XTMRCTR_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xtmrctr_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Configuration options
+ * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
+ * @{
+ */
+/**
+ * Used to configure the timer counter device.
+ * <pre>
+ * XTC_CASCADE_MODE_OPTION	Enables the Cascade Mode only valid for TCSRO.
+ * XTC_ENABLE_ALL_OPTION	Enables all timer counters at once.
+ * XTC_DOWN_COUNT_OPTION	Configures the timer counter to count down from
+ *				start value, the default is to count up.
+ * XTC_CAPTURE_MODE_OPTION	Configures the timer to capture the timer
+ *				counter value when the external capture line is
+ *				asserted. The default mode is compare mode.
+ * XTC_INT_MODE_OPTION		Enables the timer counter interrupt output.
+ * XTC_AUTO_RELOAD_OPTION	In compare mode, configures the timer counter to
+ *				reload from the compare value. The default mode
+ *				causes the timer counter to hold when the
+ *				compare value is hit.
+ *				In capture mode, configures the timer counter to
+ *				not hold the previous capture value if a new
+ *				event occurs. The default mode cause the timer
+ *				counter to hold the capture value until
+ *				recognized.
+ * XTC_EXT_COMPARE_OPTION	Enables the external compare output signal.
+ * </pre>
+ */
+#define XTC_CASCADE_MODE_OPTION		0x00000080UL
+#define XTC_ENABLE_ALL_OPTION		0x00000040UL
+#define XTC_DOWN_COUNT_OPTION		0x00000020UL
+#define XTC_CAPTURE_MODE_OPTION		0x00000010UL
+#define XTC_INT_MODE_OPTION		0x00000008UL
+#define XTC_AUTO_RELOAD_OPTION		0x00000004UL
+#define XTC_EXT_COMPARE_OPTION		0x00000002UL
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	u32 SysClockFreqHz;	/**< The AXI bus clock frequency */
+} XTmrCtr_Config;
+
+/**
+ * Signature for the callback function.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions, and passed back to the
+ *		upper layer when the callback is invoked. Its type is
+ *		 unimportant to the driver, so it is a void pointer.
+ * @param 	TmrCtrNumber is the number of the timer/counter within the
+ *		device. The device typically contains at least two
+ *		timer/counters. The timer number is a zero based number with a
+ *		range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
+ */
+typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
+
+
+/**
+ * Timer/Counter statistics
+ */
+typedef struct {
+	u32 Interrupts;	 /**< The number of interrupts that have occurred */
+} XTmrCtrStats;
+
+/**
+ * The XTmrCtr driver instance data. The user is required to allocate a
+ * variable of this type for every timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XTmrCtr_Config Config;   /**< Core configuration. */
+	XTmrCtrStats Stats;	 /**< Component Statistics */
+	u32 BaseAddress;	 /**< Base address of registers */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 IsStartedTmrCtr0;	 /**< Is Timer Counter 0 started */
+	u32 IsStartedTmrCtr1;	 /**< Is Timer Counter 1 started */
+
+	XTmrCtr_Handler Handler; /**< Callback function */
+	void *CallBackRef;	 /**< Callback reference for handler */
+} XTmrCtr;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* Required functions, in file xtmrctr.c */
+void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
+		u32 EffectiveAddr);
+int XTmrCtr_InitHw(XTmrCtr *InstancePtr);
+int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
+void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
+			   u32 ResetValue);
+u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Lookup configuration in xtmrctr_sinit.c */
+XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
+
+/* Functions for options, in file xtmrctr_options.c */
+void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
+u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Functions for statistics, in file xtmrctr_stats.c */
+void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
+void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
+
+/* Functions for self-test, in file xtmrctr_selftest.c */
+int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Functions for interrupts, in file xtmrctr_intr.c */
+void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
+			void *CallBackRef);
+void XTmrCtr_InterruptHandler(void *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xtmrctr_i.h b/thirdparty/xilinx/include/xilinx/xtmrctr_i.h
new file mode 100644
index 000000000..6cbbc0a46
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xtmrctr_i.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_i.h
+* @addtogroup tmrctr_v3_0
+* @{
+*
+* This file contains data which is shared between files internal to the
+* XTmrCtr component. It is intended for internal use only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 _m is removed from all the macro definitions.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_I_H		/* prevent circular inclusions */
+#define XTMRCTR_I_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern u8 XTmrCtr_Offsets[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xtmrctr_l.h b/thirdparty/xilinx/include/xilinx/xtmrctr_l.h
new file mode 100644
index 000000000..f5fd773ee
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xtmrctr_l.h
@@ -0,0 +1,429 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_l.h
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* High-level driver functions are defined in xtmrctr.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+*		      for naming consistency (CR 559142).
+* 2.04a sdm  07/12/11 Added the CASC mode bit in the TCSRO register for the
+*		      cascade mode operation.
+*		      The cascade mode of operation is present in the latest
+*		      versions of the axi_timer IP. Please check the HW
+*		      Datasheet to see whether this feature is present in the
+*		      version of the IP that you are using.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_L_H		/* prevent circular inclusions */
+#define XTMRCTR_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * Defines the number of timer counters within a single hardware device. This
+ * number is not currently parameterized in the hardware but may be in the
+ * future.
+ */
+#define XTC_DEVICE_TIMER_COUNT		2
+
+/* Each timer counter consumes 16 bytes of address space */
+
+#define XTC_TIMER_COUNTER_OFFSET	16
+
+/** @name Register Offset Definitions
+ * Register offsets within a timer counter, there are multiple
+ * timer counters within a single device
+ * @{
+ */
+
+#define XTC_TCSR_OFFSET		0	/**< Control/Status register */
+#define XTC_TLR_OFFSET		4	/**< Load register */
+#define XTC_TCR_OFFSET		8	/**< Timer counter register */
+
+/* @} */
+
+/** @name Control Status Register Bit Definitions
+ * Control Status Register bit masks
+ * Used to configure the timer counter device.
+ * @{
+ */
+
+#define XTC_CSR_CASC_MASK		0x00000800 /**< Cascade Mode */
+#define XTC_CSR_ENABLE_ALL_MASK		0x00000400 /**< Enables all timer
+							counters */
+#define XTC_CSR_ENABLE_PWM_MASK		0x00000200 /**< Enables the Pulse Width
+							Modulation */
+#define XTC_CSR_INT_OCCURED_MASK	0x00000100 /**< If bit is set, an
+							interrupt has occured.
+							If set and '1' is
+							written to this bit
+							position, bit is
+							cleared. */
+#define XTC_CSR_ENABLE_TMR_MASK		0x00000080 /**< Enables only the
+							specific timer */
+#define XTC_CSR_ENABLE_INT_MASK		0x00000040 /**< Enables the interrupt
+							output. */
+#define XTC_CSR_LOAD_MASK		0x00000020 /**< Loads the timer using
+							the load value provided
+							earlier in the Load
+							Register,
+							XTC_TLR_OFFSET. */
+#define XTC_CSR_AUTO_RELOAD_MASK	0x00000010 /**< In compare mode,
+							configures
+							the timer counter to
+							reload  from the
+							Load Register. The
+							default  mode
+							causes the timer counter
+							to hold when the compare
+							value is hit. In capture
+							mode, configures  the
+							timer counter to not
+							hold the previous
+							capture value if a new
+							event occurs. The
+							default mode cause the
+							timer counter to hold
+							the capture value until
+							recognized. */
+#define XTC_CSR_EXT_CAPTURE_MASK	0x00000008 /**< Enables the
+							external input
+							to the timer counter. */
+#define XTC_CSR_EXT_GENERATE_MASK	0x00000004 /**< Enables the
+							external generate output
+							for the timer. */
+#define XTC_CSR_DOWN_COUNT_MASK		0x00000002 /**< Configures the timer
+							counter to count down
+							from start value, the
+							default is to count
+							up.*/
+#define XTC_CSR_CAPTURE_MODE_MASK	0x00000001 /**< Enables the timer to
+							capture the timer
+							counter value when the
+							external capture line is
+							asserted. The default
+							mode is compare mode.*/
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+extern u8 XTmrCtr_Offsets[];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Read one of the timer counter registers.
+*
+* @param	BaseAddress contains the base address of the timer counter
+*		device.
+* @param	TmrCtrNumber contains the specific timer counter within the
+*		device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegOffset contains the offset from the 1st register of the timer
+*		counter to select the specific register of the timer counter.
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
+					unsigned RegOffset);
+******************************************************************************/
+#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
+			(RegOffset))
+
+#ifndef XTimerCtr_ReadReg
+#define XTimerCtr_ReadReg XTmrCtr_ReadReg
+#endif
+
+/*****************************************************************************/
+/**
+* Write a specified value to a register of a timer counter.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegOffset contain the offset from the 1st register of the timer
+*		counter to select the specific register of the timer counter.
+* @param	ValueToWrite is the 32 bit value to be written to the register.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
+*					unsigned RegOffset, u32 ValueToWrite);
+******************************************************************************/
+#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (RegOffset)), (ValueToWrite))
+
+/****************************************************************************/
+/**
+*
+* Set the Control Status Register of a timer counter to the specified value.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegisterValue is the 32 bit value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
+*					u8 TmrCtrNumber,u32 RegisterValue);
+*****************************************************************************/
+#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the Control Status Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
+*						u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Get the Timer Counter Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
+*						u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber)		  \
+	XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
+
+/****************************************************************************/
+/**
+*
+* Set the Load Register of a timer counter to the specified value.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegisterValue is the 32 bit value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
+*						  u32 RegisterValue);
+*****************************************************************************/
+#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue)	 \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
+					   (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the Load Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber)	\
+XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable a timer counter such that it starts running.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber)			    \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
+			(XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
+			XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable a timer counter such that it stops running.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber)			  \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
+			XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
+
+/****************************************************************************/
+/**
+*
+* Enable the interrupt for a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber)			    \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),  \
+			XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the interrupt for a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber)			   \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,  \
+	(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),		   \
+		XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK))
+
+/****************************************************************************/
+/**
+*
+* Cause the timer counter to load it's Timer Counter Register with the value
+* in the Load Register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		   zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
+					u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber)		  \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
+			XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Determine if a timer counter event has occurred.  Events are defined to be
+* when a capture has occurred or the counter has roller over.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @note		C-Style signature:
+* 		int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber)		\
+		((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),	\
+		XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) ==		\
+		XTC_CSR_INT_OCCURED_MASK)
+
+/************************** Function Prototypes ******************************/
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xutil.h b/thirdparty/xilinx/include/xilinx/xutil.h
new file mode 100644
index 000000000..082738e34
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xutil.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xutil.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains utility functions such as memory test functions.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* <pre>
+* XUT_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XUT_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing
+*       value as the test value for memory.
+*
+* XUT_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XUT_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XUT_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XUT_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* </pre>
+*
+* <i>WARNING</i>
+*
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+*
+* The address, Addr, provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
+* boundry of a power of two making it more difficult to detect addressing
+* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
+* problem. Ideally, if large blocks of memory are to be tested, break
+* them up into smaller regions of memory to allow the test patterns used
+* not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  11/01/01 First release
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XUTIL_H			/* prevent circular inclusions */
+#define XUTIL_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XUT_MEMTEST_INIT_VALUE  1
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XUT_ALLMEMTESTS     0
+#define XUT_INCREMENT       1
+#define XUT_WALKONES        2
+#define XUT_WALKZEROS       3
+#define XUT_INVERSEADDR     4
+#define XUT_FIXEDPATTERN    5
+#define XUT_MAXTEST         XUT_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_memtest prototypes */
+
+int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/include/xilinx/xversion.h b/thirdparty/xilinx/include/xilinx/xversion.h
new file mode 100644
index 000000000..8dad9824c
--- /dev/null
+++ b/thirdparty/xilinx/include/xilinx/xversion.h
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xversion.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains the interface for the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XVERSION_H		/* prevent circular inclusions */
+#define XVERSION_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+typedef char XVersion[6];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion);
+
+int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion);
+
+int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr);
+
+void XVersion_ToString(XVersion *InstancePtr, char *StringPtr);
+
+int XVersion_FromString(XVersion *InstancePtr, char *StringPtr);
+
+void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/README.md b/thirdparty/xilinx/orig/README.md
new file mode 100644
index 000000000..16edb5122
--- /dev/null
+++ b/thirdparty/xilinx/orig/README.md
@@ -0,0 +1 @@
+Those drivers are taken from https://github.com/Xilinx/embeddedsw
\ No newline at end of file
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/data/axidma.mdd b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma.mdd
new file mode 100644
index 000000000..773a39d3c
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma.mdd
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Copyright (C) 2010 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+##############################################################################
+
+OPTION psf_version = 2.1;
+
+BEGIN driver axidma
+
+  OPTION supported_peripherals = (axi_dma_v[3-9]_[0-9][0-9]_[a-z] axi_dma_v[3-9]_[0-9]);
+  OPTION driver_state = ACTIVE;
+  OPTION copyfiles = all;
+  OPTION VERSION = 9.0;
+  OPTION NAME = axidma;
+
+END driver
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/data/axidma.tcl b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma.tcl
new file mode 100644
index 000000000..f0f806f76
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma.tcl
@@ -0,0 +1,208 @@
+###############################################################################
+#
+# Copyright (C) 2010 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ----------------------------------------------------
+#  8.0     adk    12/10/13 Updated as per the New Tcl API's
+##############################################################################
+
+#uses "xillib.tcl"
+
+set periph_ninstances    0
+
+proc generate {drv_handle} {
+  ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxiDma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S_DRE" "C_INCLUDE_S2MM_DRE" "C_INCLUDE_MM2S" "C_INCLUDE_S2MM" "C_M_AXI_MM2S_DATA_WIDTH" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width"
+  ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "AxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width"
+  ::hsi::utils::define_config_file  $drv_handle "xaxidma_g.c" "XAxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width"
+}
+
+#
+# Given a list of arguments, define them all in an include file.
+# Handles mpd and mld parameters, as well as the special parameters NUM_INSTANCES,
+# DEVICE_ID
+# Will not work for a processor.
+#
+
+proc xdefine_dma_include_file {drv_handle file_name drv_string args} {
+    # Open include file
+    set file_handle [xopen_include_file $file_name]
+
+    # Get all peripherals connected to this driver
+    set periphs [xget_sw_iplist_for_driver $drv_handle]
+
+    # Handle special cases
+    set arg "NUM_INSTANCES"
+    set posn [lsearch -exact $args $arg]
+    if {$posn > -1} {
+	puts $file_handle "/* Definitions for driver [string toupper [get_property NAME $drv_handle]] */"
+	# Define NUM_INSTANCES
+	puts $file_handle "#define [xget_dname $drv_string $arg] [llength $periphs]"
+	set args [lreplace $args $posn $posn]
+    }
+    # Check if it is a driver parameter
+
+    lappend newargs
+    foreach arg $args {
+	set value [get_property CONFIG.$arg $drv_handle]
+	if {[llength $value] == 0} {
+	    lappend newargs $arg
+	} else {
+	    puts $file_handle "#define [xget_dname $drv_string $arg] [get_property CONFIG.$arg $drv_handle]"
+	}
+    }
+    set args $newargs
+
+    # Print all parameters for all peripherals
+    set device_id 0
+    foreach periph $periphs {
+	puts $file_handle ""
+	puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */"
+	foreach arg $args {
+	    if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
+		set value $device_id
+		incr device_id
+	    } else {
+		set value [xget_param_value $periph $arg]
+		if {[string compare -nocase $arg "C_INCLUDE_SG"] == 0} {
+			if {[llength $value] == 0} {
+				set value 1
+			}
+		} else {
+	                if {[llength $value] == 0} {
+	                    set value 0
+	                }
+	        }
+		if {[string compare -nocase $arg "C_MICRO_DMA"] == 0} {
+			if {[llength $value] == 0} {
+				set value 1
+			}
+		} else {
+	                if {[llength $value] == 0} {
+	                    set value 0
+	                }
+	        }
+	    }
+
+	    set value [xformat_addr_string $value $arg]
+	    if {[string compare -nocase "HW_VER" $arg] == 0} {
+                puts $file_handle "#define [xget_name $periph $arg] \"$value\""
+	    } else {
+                puts $file_handle "#define [xget_name $periph $arg] $value"
+            }
+	}
+	puts $file_handle ""
+    }
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+#-----------------------------------------------------------------------------
+# ::hsi::utils::define_canonical_xpars - Used to print out canonical defines for a driver.
+# Given a list of arguments, define each as a canonical constant name, using
+# the driver name, in an include file.
+#-----------------------------------------------------------------------------
+proc xdefine_axidma_canonical_xpars {drv_handle file_name drv_string args} {
+    # Open include file
+    set file_handle [xopen_include_file $file_name]
+
+    # Get all the peripherals connected to this driver
+    set periphs [xget_sw_iplist_for_driver $drv_handle]
+
+    # Get the names of all the peripherals connected to this driver
+    foreach periph $periphs {
+        set peripheral_name [string toupper [get_property NAME $periph]]
+        lappend peripherals $peripheral_name
+    }
+
+    # Get possible canonical names for all the peripherals connected to this
+    # driver
+    set device_id 0
+    foreach periph $periphs {
+        set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]]
+        lappend canonicals $canonical_name
+
+        # Create a list of IDs of the peripherals whose hardware instance name
+        # doesn't match the canonical name. These IDs can be used later to
+        # generate canonical definitions
+        if { [lsearch $peripherals $canonical_name] < 0 } {
+            lappend indices $device_id
+        }
+        incr device_id
+    }
+
+    set i 0
+    foreach periph $periphs {
+        set periph_name [string toupper [get_property NAME $periph]]
+
+        # Generate canonical definitions only for the peripherals whose
+        # canonical name is not the same as hardware instance name
+        if { [lsearch $canonicals $periph_name] < 0 } {
+            puts $file_handle "/* Canonical definitions for peripheral $periph_name */"
+            set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]]
+
+            foreach arg $args {
+                set lvalue [xget_dname $canonical_name $arg]
+                # The commented out rvalue is the name of the instance-specific constant
+                # set rvalue [xget_name $periph $arg]
+                # The rvalue set below is the actual value of the parameter
+                set rvalue [xget_param_value $periph $arg]
+
+		if {[string compare -nocase $arg "C_INCLUDE_SG"] == 0} {
+			if {[llength $rvalue] == 0} {
+				set rvalue 1
+			}
+		} else {
+	                if {[llength $rvalue] == 0} {
+	                    set rvalue 0
+	                }
+	        }
+		if {[string compare -nocase $arg "C_MICRO_DMA"] == 0} {
+			if {[llength $rvalue] == 0} {
+				set rvalue 1
+			}
+		} else {
+	                if {[llength $rvalue] == 0} {
+	                    set rvalue 0
+	                }
+	        }
+                set rvalue [xformat_addr_string $rvalue $arg]
+
+                puts $file_handle "#define $lvalue $rvalue"
+
+            }
+            puts $file_handle ""
+            incr i
+        }
+    }
+
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/data/axidma_header.h b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma_header.h
new file mode 100644
index 000000000..fe4fab014
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma_header.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef AXIDMA_HEADER_H		/* prevent circular inclusions */
+#define AXIDMA_HEADER_H		/* by using protection macros */
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+int AxiDMASelfTestExample(u16 DeviceId);
+
+#endif
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/data/axidma_tapp.tcl b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma_tapp.tcl
new file mode 100644
index 000000000..865d9d319
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/data/axidma_tapp.tcl
@@ -0,0 +1,121 @@
+###############################################################################
+#
+# Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+##############################################################################
+# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
+
+# -----------------------------------------------------------------
+# Software Project Types (swproj):
+#   0 : MemoryTest - Calls basic  memorytest routines from common driver dir
+#   1 : PeripheralTest - Calls any existing polled_example and/or selftest
+# -----------------------------------------------------------------
+
+# -----------------------------------------------------------------
+# TCL Procedures:
+# -----------------------------------------------------------------
+
+proc gen_include_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {axidma_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_src_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {examples/xaxidma_example_selftest.c data/axidma_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_testfunc_def {swproj mhsinst} {
+  return ""
+}
+
+proc gen_init_code {swproj mhsinst} {
+  return ""
+}
+
+proc gen_testfunc_call {swproj mhsinst} {
+
+  if {$swproj == 0} {
+    return ""
+  }
+
+  set ipname [get_property NAME $mhsinst]
+  set deviceid [::hsi::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
+   set stdout [get_property CONFIG.STDOUT [get_os]]
+   if { $stdout == "" || $stdout == "none" } {
+       set hasStdout 0
+   } else {
+       set hasStdout 1
+   }
+
+  set testfunc_call ""
+
+  if {${hasStdout} == 0} {
+
+      append testfunc_call "
+
+   {
+      int status;
+
+      status = AxiDMASelfTestExample(${deviceid});
+
+   }"
+  } else {
+
+      append testfunc_call "
+
+   {
+      int status;
+
+
+      print(\"\\r\\n Running AxiDMASelfTestExample() for ${ipname}...\\r\\n\");
+
+      status = AxiDMASelfTestExample(${deviceid});
+
+      if (status == 0) {
+         print(\"AxiDMASelfTestExample PASSED\\r\\n\");
+      }
+      else {
+         print(\"AxiDMASelfTestExample FAILED\\r\\n\");
+      }
+   }"
+  }
+
+  return $testfunc_call
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/HTML_custom.css b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/HTML_custom.css
new file mode 100644
index 000000000..26defe1a8
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/HTML_custom.css
@@ -0,0 +1,1430 @@
+/* The standard CSS for doxygen 1.8.5 */
+
+body{
+	background: none repeat scroll 0 0 #FFFFFF;
+	color: #51626F;
+	font-family: arial,sans-serif !important;
+    	font-size: 75% !important;
+    	font-weight: normal !important;
+    	margin-left: 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+.contents, .textblock {
+font: 400 12px/15px arial,sans-serif;
+}
+.textblock ul, .contents ul{ 
+	margin: 5px 0;
+	padding: 0;
+}
+.textblockol {
+	margin:5px 15px; 
+	padding:0;
+	list-style-image: none; 
+}
+.textblock li, .contents li {
+	margin: 0 0 2px 15px;
+    	padding: 0 0 2px 2px;
+}
+
+/* For hiding RHS TOC 
+.toc{
+display:none;
+}*/
+/* For hiding RHS TOC*/ 
+
+For hiding Nav Bar
+.navpath, #nav-path{
+display:none;
+}
+/* For hiding Nav Bar*/
+/* For hiding extra navrows */
+#navrow2, #navrow3, #navrow4, #navrow5 {
+display:none;
+}
+/* @group Heading Levels */
+
+.title {
+	font: 400 14px/28px arial,sans-serif;
+	font-size: 150%;
+	font-weight: bold;
+	margin: 9px 2px;
+	text-align: left;
+}
+
+h2, h3 {
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+    text-indent: 0 !important;
+}
+h4, h5{
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+}
+h5{
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+h6{
+    color: #E66A08 !important;
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+p {
+    padding-bottom: 0px !important;
+	font: 400 12px/15px arial,sans-serif;
+}
+li p {
+    padding-bottom: 0px !important;
+	margin: 0px;
+}
+
+h1, h2.groupheader {
+    clear: both !important;
+    color: #627178 !important;
+    font-size: 1.4em !important;
+    font-weight: bold !important;
+    line-height: 28px !important;
+    margin-top: 0.6em !important;
+}
+
+h1, h2, h3, h4, h5, h6 {
+	-webkit-transition: text-shadow 0.5s linear;
+	-moz-transition: text-shadow 0.5s linear;
+	-ms-transition: text-shadow 0.5s linear;
+	-o-transition: text-shadow 0.5s linear;
+	transition: text-shadow 0.5s linear;
+	margin-right: 15px;
+}
+
+h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {
+	text-shadow: 0 0 15px cyan;
+}
+
+dt {
+	font-weight: bold;
+}
+
+
+/*Hiding Tabs - Tushar
+div.tabs 
+{ 
+    visibility: hidden; 
+} */
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #017bba;
+	font-weight: normal;
+	text-decoration: none;
+	/*font: 400 12px/15px;*/
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code, a.code:visited, a.line, a.line:visited {
+	color: #4665A2;
+}
+
+a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {
+	color: #4665A2; 
+	/*font: 400 12px/15px;*/
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+pre.fragment {
+        border: 0px solid #C4CFE5;
+        background-color: #FFFFFF;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        font-size:  9pt;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 105%;
+}
+
+div.fragment {
+        padding: 0px;
+        margin: 0px;
+	background-color: #FFFFFF;
+	border: 0px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 13px;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+div.line.glow {
+	background-color: cyan;
+	box-shadow: 0 0 10px cyan;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #51626F
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: cyan;
+	box-shadow: 0 0 15px cyan;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
+        border-bottom: 1px solid #DEE4F0;
+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+	font-size: 80%;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+        -webkit-transition: box-shadow 0.5s linear;
+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
+        display: table !important;
+        width: 100%;
+}
+
+.memitem.glow {
+         box-shadow: 0 0 15px cyan;
+}
+
+.memname {
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memname td {
+	vertical-align: bottom;
+}
+
+.memproto, dl.reflist dt {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #E66A08 !important;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+.memdoc, dl.reflist dd {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 6px 10px 2px 10px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        background-image:url('nav_g.png');
+        background-repeat:repeat-x;
+        background-color: #FFFFFF;
+        /* opera specific markup */
+        border-bottom-left-radius: 4px;
+        border-bottom-right-radius: 4px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 4px;
+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 4px;
+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
+        margin: 0px 0px 10px 0px;
+        padding: 5px;
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+.paramname code {
+        line-height: 14px;
+}
+
+.params, .retval, .exception, .tparams {
+        margin-left: 0px;
+        padding-left: 0px;
+		font: 400 12px/15px arial,sans-serif;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+table.mlabels {
+	border-spacing: 0px;
+}
+
+td.mlabels-left {
+	width: 100%;
+	padding: 0px;
+}
+
+td.mlabels-right {
+	vertical-align: bottom;
+	padding: 0px;
+	white-space: nowrap;
+}
+
+span.mlabels {
+        margin-left: 8px;
+}
+
+span.mlabel {
+        background-color: #728DC1;
+        border-top:1px solid #5373B4;
+        border-left:1px solid #5373B4;
+        border-right:1px solid #C4CFE5;
+        border-bottom:1px solid #C4CFE5;
+	text-shadow: none;
+	color: white;
+	margin-right: 4px;
+	padding: 2px 3px;
+	border-radius: 3px;
+	font-size: 7pt;
+	white-space: nowrap;
+	vertical-align: middle;
+}
+
+
+
+/* @end */
+
+/* these are for tree view when not used as main index */
+
+div.directory {
+        margin: 10px 0px;
+        border-top: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        width: 100%;
+}
+
+.directory table {
+        border-collapse:collapse;
+}
+
+.directory td {
+        margin: 0px;
+        padding: 0px;
+	vertical-align: top;
+}
+
+.directory td.entry {
+        white-space: nowrap;
+        padding-right: 6px;
+	padding-top: 3px;
+}
+
+.directory td.entry a {
+        outline:none;
+}
+
+.directory td.entry a img {
+        border: none;
+}
+
+.directory td.desc {
+        width: 100%;
+        padding-left: 6px;
+	padding-right: 6px;
+	padding-top: 3px;
+	border-left: 1px solid rgba(0,0,0,0.05);
+}
+
+.directory tr.even {
+	padding-left: 6px;
+	background-color: #F7F8FB;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+.directory .levels {
+        white-space: nowrap;
+        width: 100%;
+        text-align: right;
+        font-size: 9pt;
+}
+
+.directory .levels span {
+        cursor: pointer;
+        padding-left: 2px;
+        padding-right: 2px;
+	color: #3D578C;
+}
+
+div.dynheader {
+        margin-top: 8px;
+	-webkit-touch-callout: none;
+	-webkit-user-select: none;
+	-khtml-user-select: none;
+	-moz-user-select: none;
+	-ms-user-select: none;
+	user-select: none;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+        margin-top: 4px;
+        margin-bottom: 4px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #CCCCCC;
+	color: #51626F;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+}
+table.fieldtable {
+        /*width: 100%;*/
+        margin-bottom: 10px;
+        border: 1px solid #A8B8D9;
+        border-spacing: 0px;
+        -moz-border-radius: 4px;
+        -webkit-border-radius: 4px;
+        border-radius: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+}
+
+.fieldtable td, .fieldtable th {
+        padding: 3px 7px 2px;
+}
+
+.fieldtable td.fieldtype, .fieldtable td.fieldname {
+        white-space: nowrap;
+        border-right: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        vertical-align: top;
+}
+
+.fieldtable td.fieldname {
+        padding-top: 3px;
+}
+
+.fieldtable td.fielddoc {
+        border-bottom: 1px solid #A8B8D9;
+        /*width: 100%;*/
+}
+
+.fieldtable td.fielddoc p:first-child {
+        margin-top: 0px;
+}       
+        
+.fieldtable td.fielddoc p:last-child {
+        margin-bottom: 2px;
+}
+
+.fieldtable tr:last-child td {
+        border-bottom: none;
+}
+
+.fieldtable th {
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        font-size: 90%;
+        color: #253555;
+        padding-bottom: 4px;
+        padding-top: 5px;
+        text-align:left;
+        -moz-border-radius-topleft: 4px;
+        -moz-border-radius-topright: 4px;
+        -webkit-border-top-left-radius: 4px;
+        -webkit-border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        border-top-right-radius: 4px;
+        border-bottom: 1px solid #A8B8D9;
+}
+
+
+.tabsearch {
+	top: 5px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	background-position: 0 -5px;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+	color: #283A5D;
+	font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;
+	text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+	text-decoration: none;        
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('');
+        background-repeat:repeat-x;
+	background-color: #FFFFFF;
+	margin:  0px;
+	border-bottom: 0px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */
+dl.section
+{
+	margin-left: 0px;
+	padding-left: 0px;
+}
+
+dl.note
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #505050;
+}
+
+dl.todo
+{
+        margin-left:-7px;
+        padding-left: 12px;
+        border-left:4px solid;
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #C08050;
+}
+
+dl.section dd {
+	margin-bottom: 6px;
+}
+
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+	padding: 12px;
+	
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 300% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 5px 0px;
+	text-align: right;
+	width: 100%;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 5px;
+	text-align: left;
+	width: 100%;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 11px solid #5373B4;
+}
+
+.image
+{
+        text-align: left;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
+div.zoom
+{
+	border: 1px solid #90A5CE;
+}
+
+dl.citelist {
+        margin-bottom:50px;
+}
+
+dl.citelist dt {
+        color:#334975;
+        float:left;
+        font-weight:bold;
+        margin-right:10px;
+        padding:5px;
+}
+
+dl.citelist dd {
+        margin:2px 0;
+        padding:5px 0;
+}
+
+div.toc {
+        padding: 14px 25px;
+        background-color: #F4F6FA;
+        border: 1px solid #D8DFEE;
+        border-radius: 7px 7px 7px 7px;
+        float: right;
+        height: auto;
+        margin: 0 20px 10px 10px;
+        width: 200px;
+}
+
+div.toc li {
+        background: url("bdwn.png") no-repeat scroll 0 5px transparent;
+        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;
+        margin-top: 5px;
+        padding-left: 10px;
+        padding-top: 2px;
+}
+
+div.toc h3 {
+        font: bold 12px/1.2 Arial,FreeSans,sans-serif;
+	color: #4665A2;
+        border-bottom: 0 none;
+        margin: 0;
+}
+
+div.toc ul {
+        list-style: none outside none;
+        border: medium none;
+        padding: 0px;
+}       
+
+div.toc li.level1 {
+        margin-left: 0px;
+}
+
+div.toc li.level2 {
+        margin-left: 15px;
+}
+
+div.toc li.level3 {
+        margin-left: 30px;
+}
+
+div.toc li.level4 {
+        margin-left: 45px;
+}
+
+.inherit_header {
+        font-weight: bold;
+        color: gray;
+        cursor: pointer;
+	-webkit-touch-callout: none;
+	-webkit-user-select: none;
+	-khtml-user-select: none;
+	-moz-user-select: none;
+	-ms-user-select: none;
+	user-select: none;
+}
+
+.inherit_header td {
+        padding: 6px 0px 2px 5px;
+}
+
+.inherit {
+        display: none;
+}
+
+tr.heading h2 {
+        margin-top: 12px;
+        margin-bottom: 4px;
+}
+
+/* tooltip related style info */
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+<tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bd_8c.html" target="_self">xaxidma_bd.c</a></td><td class="desc"></td></tr>
+<tr id="row_3_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bd_8h.html" target="_self">xaxidma_bd.h</a></td><td class="desc"></td></tr>
+<tr id="row_4_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bdring_8c.html" target="_self">xaxidma_bdring.c</a></td><td class="desc"></td></tr>
+<tr id="row_5_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bdring_8h.html" target="_self">xaxidma_bdring.h</a></td><td class="desc"></td></tr>
+<tr id="row_6_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__g_8c.html" target="_self">xaxidma_g.c</a></td><td class="desc"></td></tr>
+<tr id="row_7_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__hw_8h.html" target="_self">xaxidma_hw.h</a></td><td class="desc"></td></tr>
+<tr id="row_8_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__porting__guide_8h.html" target="_self">xaxidma_porting_guide.h</a></td><td class="desc"></td></tr>
+<tr id="row_9_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__selftest_8c.html" target="_self">xaxidma_selftest.c</a></td><td class="desc"></td></tr>
+<tr id="row_10_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__sinit_8c.html" target="_self">xaxidma_sinit.c</a></td><td class="desc"></td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions.html
new file mode 100644
index 000000000..0bd7ad51e
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions.html
@@ -0,0 +1,130 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="functions.html"><span>All</span></a></li>
+      <li><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div><ul>
+<li>AddrWidth
+: <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma</a>
+, <a class="el" href="struct_x_axi_dma___config.html#a6fc1c26fb40944182ff84e370e667eb0">XAxiDma_Config</a>
+</li>
+<li>AllCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing</a>
+</li>
+<li>BdaRestart
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a2519fd626856e7ab0d822adc46aab7d8">XAxiDma_BdRing</a>
+</li>
+<li>ChanBase
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdPhysAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#add2c7d765c8d95eeb9d0f94a54775528">XAxiDma_BdRing</a>
+</li>
+<li>FreeCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing</a>
+</li>
+<li>FreeHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing</a>
+</li>
+<li>HasStsCntrlStrm
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing</a>
+</li>
+<li>HwCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing</a>
+</li>
+<li>HwHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing</a>
+</li>
+<li>HwTail
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing</a>
+</li>
+<li>IsRxChannel
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing</a>
+</li>
+<li>LastBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3743d05f930d7c04abb0693f2ef0b271">XAxiDma_BdRing</a>
+</li>
+<li>Length
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af0b3fe5c9b9123209b3000e0d95193ed">XAxiDma_BdRing</a>
+</li>
+<li>PostCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing</a>
+</li>
+<li>PostHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing</a>
+</li>
+<li>PreCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing</a>
+</li>
+<li>PreHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing</a>
+</li>
+<li>RingIndex
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing</a>
+</li>
+<li>RunState
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing</a>
+</li>
+<li>Separation
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions_vars.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions_vars.html
new file mode 100644
index 000000000..ea2952237
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions_vars.html
@@ -0,0 +1,130 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: Data Fields - Variables</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>AddrWidth
+: <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma</a>
+, <a class="el" href="struct_x_axi_dma___config.html#a6fc1c26fb40944182ff84e370e667eb0">XAxiDma_Config</a>
+</li>
+<li>AllCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing</a>
+</li>
+<li>BdaRestart
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a2519fd626856e7ab0d822adc46aab7d8">XAxiDma_BdRing</a>
+</li>
+<li>ChanBase
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdPhysAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#add2c7d765c8d95eeb9d0f94a54775528">XAxiDma_BdRing</a>
+</li>
+<li>FreeCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing</a>
+</li>
+<li>FreeHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing</a>
+</li>
+<li>HasStsCntrlStrm
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing</a>
+</li>
+<li>HwCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing</a>
+</li>
+<li>HwHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing</a>
+</li>
+<li>HwTail
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing</a>
+</li>
+<li>IsRxChannel
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing</a>
+</li>
+<li>LastBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3743d05f930d7c04abb0693f2ef0b271">XAxiDma_BdRing</a>
+</li>
+<li>Length
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af0b3fe5c9b9123209b3000e0d95193ed">XAxiDma_BdRing</a>
+</li>
+<li>PostCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing</a>
+</li>
+<li>PostHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing</a>
+</li>
+<li>PreCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing</a>
+</li>
+<li>PreHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing</a>
+</li>
+<li>RingIndex
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing</a>
+</li>
+<li>RunState
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing</a>
+</li>
+<li>Separation
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals.html
new file mode 100644
index 000000000..10e1f1c51
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals.html
@@ -0,0 +1,558 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XAxiDma
+: <a class="el" href="group__axidma__v9__0.html#gac08fe7cb6508a133a7ef036bba7df5b5">xaxidma.h</a>
+</li>
+<li>XAxiDma_Bd
+: <a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">xaxidma_bd.h</a>
+</li>
+<li>XAXIDMA_BD_ADDRLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">xaxidma_hw.h</a>
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+<li>XAXIDMA_BD_BYTES_TO_CLEAR
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+<li>XAXIDMA_BD_CTRL_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_LEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_STSCNTRL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HW_NUM_BYTES
+: <a class="el" href="group__axidma__v9__0.html#gae8ddf1d33d85b0a7508b9a072d95bf14">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_ID_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MCCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MINIMUM_ALIGNMENT
+: <a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NUM_WORDS
+: <a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_START_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STRIDE_VSIZE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8018932d7e9b743c4c5c76ab3d373de1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_COMPLETE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_DEC_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae79c77f87a9887510ea53480c1e9a998">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_INT_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga09e502148e375f2d695d6d5d6e1797d2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga91b0504c621f6c06b0df4752fe65ee3a">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga29915484fd9f840a8ab727cf83bbfe81">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_SLV_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f7727fc139a6b3100a5a17cb110efa6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR1_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga7d9d62be0e0ed11b18f185b62dc72f67">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR2_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadc83ff22099fdf61a5237965ce082504">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR3_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gae1c5981447fe5ac113a6da3c1e19d6ed">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR4_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga1ccae584923d0b6d0851a8bbae4528c9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_MASK
+: <a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#ga3db5b1d09deab9660ff65c06136acbc5">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_BdClear
+: <a class="el" href="group__axidma__v9__0.html#ga6c47900232c9a5a5ba30a2c1a3343628">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetActualLength
+: <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdGetARCache
+: <a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetARUser
+: <a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetBufAddr
+: <a class="el" href="group__axidma__v9__0.html#gaf858d9659197442c9e96856c206423c6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetCtrl
+: <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetId
+: <a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetLength
+: <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetStride
+: <a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetSts
+: <a class="el" href="group__axidma__v9__0.html#gaf2448f2b2ac172da0d19adeae3cc4c48">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTId
+: <a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTUser
+: <a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetVSize
+: <a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdHwCompleted
+: <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRead
+: <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRingAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingAlloc()
+: <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingBusy
+: <a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingCheck()
+: <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingClone()
+: <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingCntCalc
+: <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingCreate()
+: <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingDumpRegs()
+: <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFree()
+: <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFromHw()
+: <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingGetCnt
+: <a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingGetCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga21aa8dbf6eabf9146097d9b3cc91c574">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetError
+: <a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetFreeCnt
+: <a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetSr
+: <a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingHwIsStarted
+: <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntDisable
+: <a class="el" href="group__axidma__v9__0.html#ga0269e07693c731cf7721c6f19f8eb69b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntEnable
+: <a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingMemCalc
+: <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingNext
+: <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingPrev
+: <a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingSetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingSnapShotCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingStart()
+: <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingToHw()
+: <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingUnAlloc()
+: <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdSetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetARCache
+: <a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetARUser
+: <a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetBufAddr()
+: <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetBufAddrMicroMode()
+: <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetCtrl()
+: <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetId
+: <a class="el" href="group__axidma__v9__0.html#ga53eeff085fd39a91b855939f13fe76f3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetLength()
+: <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetStride
+: <a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTId
+: <a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTUser
+: <a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetVSize
+: <a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdWrite
+: <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">xaxidma_bd.h</a>
+</li>
+<li>XAXIDMA_BUFFLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa7ede468ba17bf106101d4850184dc74">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_Busy()
+: <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">xaxidma.c</a>
+</li>
+<li>XAXIDMA_CDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga00ee7a235750d8795961223455407051">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_CfgInitialize()
+: <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">xaxidma.c</a>
+</li>
+<li>XAXIDMA_COALESCE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_CYCLIC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_KEYHOLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RESET_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RUNSTOP_MASK
+: <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESC_LSB_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga3a54e372851dbae81c33997ef2ba8d2f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga4e98e82ed389c23918315d833b457ea9">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_DumpBd()
+: <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">xaxidma_bd.c</a>
+</li>
+<li>XAXIDMA_ERR_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_DECODE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa19b93d226e97afd08d3869dc530b692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_INTERNAL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga87ac559811703a8ca33fc6b427913f2b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_DEC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga43ecb16ea8e8d09a33364a17610d8909">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_INT_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f9ef0d10a7456a25a4b244955659d65">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_SLV_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga0f0d25fd68716e868742115c9a28c18c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SLAVE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6d50743f6c9d6474561f6727eb956915">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_GetRxIndexRing
+: <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetRxRing
+: <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetTxRing
+: <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_HALTED_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_HasSg
+: <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IDLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_IntrAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9ff0d2e5b50846e4b6a2d683283c10d5">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrDisable
+: <a class="el" href="group__axidma__v9__0.html#ga1936b497c0fa61d326807e5ed8dd572b">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrEnable
+: <a class="el" href="group__axidma__v9__0.html#gadac28afa26e2cb55bdada1ee3c016c52">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadba63ad7c0a784d569736a8d1eb7c367">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga6a0eb17bcfcaf3331e01855d302f5f0e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IRQ_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadc4a45d09bcbf852f29b880935d607dc">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_ERROR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6ceb68e74761910e4253795a9b4992cf">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_IOC_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae420f2ad87e1e00456a6ee3a80d2480d">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_LookupConfig()
+: <a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c">xaxidma.h</a>
+</li>
+<li>XAXIDMA_MICROMODE_MIN_BUF_ALIGN
+: <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_Pause()
+: <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">xaxidma.c</a>
+</li>
+<li>XAxiDma_ReadReg
+: <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_Reset()
+: <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">xaxidma.c</a>
+</li>
+<li>XAxiDma_ResetIsDone()
+: <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">xaxidma.c</a>
+</li>
+<li>XAxiDma_Resume()
+: <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">xaxidma.c</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gad80414a88feceb1da4b9f77096d1d590">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_SelectCyclicMode()
+: <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">xaxidma.c</a>
+</li>
+<li>XAxiDma_SelectKeyHole()
+: <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">xaxidma.c</a>
+</li>
+<li>XAxiDma_Selftest()
+: <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">xaxidma.h</a>
+</li>
+<li>XAXIDMA_SGCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gab26580f9b4a94b3ab1d373ddeab7b3b6">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_SimpleTransfer()
+: <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">xaxidma.c</a>
+</li>
+<li>XAXIDMA_SR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gafaafc49751e690d818d604efe368c481">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga386fad6446792679302b362ed34022cf">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_StartBdRingHw()
+: <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">xaxidma_bdring.c</a>
+</li>
+<li>XAXIDMA_TDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_UpdateBdRingCDesc()
+: <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_WriteReg
+: <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">xaxidma_hw.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_defs.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_defs.html
new file mode 100644
index 000000000..dc4b4eaec
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_defs.html
@@ -0,0 +1,456 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
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+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XAXIDMA_BD_ADDRLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BYTES_TO_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_LEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_STSCNTRL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HW_NUM_BYTES
+: <a class="el" href="group__axidma__v9__0.html#gae8ddf1d33d85b0a7508b9a072d95bf14">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_ID_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MCCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MINIMUM_ALIGNMENT
+: <a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NUM_WORDS
+: <a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_START_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STRIDE_VSIZE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8018932d7e9b743c4c5c76ab3d373de1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_COMPLETE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_DEC_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae79c77f87a9887510ea53480c1e9a998">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_INT_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga09e502148e375f2d695d6d5d6e1797d2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga91b0504c621f6c06b0df4752fe65ee3a">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga29915484fd9f840a8ab727cf83bbfe81">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_SLV_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f7727fc139a6b3100a5a17cb110efa6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR1_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga7d9d62be0e0ed11b18f185b62dc72f67">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR2_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadc83ff22099fdf61a5237965ce082504">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR3_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gae1c5981447fe5ac113a6da3c1e19d6ed">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR4_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga1ccae584923d0b6d0851a8bbae4528c9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_MASK
+: <a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#ga3db5b1d09deab9660ff65c06136acbc5">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_BdClear
+: <a class="el" href="group__axidma__v9__0.html#ga6c47900232c9a5a5ba30a2c1a3343628">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetActualLength
+: <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetARCache
+: <a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetARUser
+: <a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetBufAddr
+: <a class="el" href="group__axidma__v9__0.html#gaf858d9659197442c9e96856c206423c6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetCtrl
+: <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetId
+: <a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetLength
+: <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetStride
+: <a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetSts
+: <a class="el" href="group__axidma__v9__0.html#gaf2448f2b2ac172da0d19adeae3cc4c48">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTId
+: <a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTUser
+: <a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetVSize
+: <a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdHwCompleted
+: <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRead
+: <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRingAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingBusy
+: <a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingCntCalc
+: <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetCnt
+: <a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga21aa8dbf6eabf9146097d9b3cc91c574">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetError
+: <a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetFreeCnt
+: <a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetSr
+: <a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingHwIsStarted
+: <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntDisable
+: <a class="el" href="group__axidma__v9__0.html#ga0269e07693c731cf7721c6f19f8eb69b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntEnable
+: <a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingMemCalc
+: <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingNext
+: <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingPrev
+: <a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingSnapShotCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdSetARCache
+: <a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetARUser
+: <a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetId
+: <a class="el" href="group__axidma__v9__0.html#ga53eeff085fd39a91b855939f13fe76f3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetStride
+: <a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTId
+: <a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTUser
+: <a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetVSize
+: <a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdWrite
+: <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">xaxidma_bd.h</a>
+</li>
+<li>XAXIDMA_BUFFLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa7ede468ba17bf106101d4850184dc74">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga00ee7a235750d8795961223455407051">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_COALESCE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_CYCLIC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_KEYHOLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RESET_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RUNSTOP_MASK
+: <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESC_LSB_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga3a54e372851dbae81c33997ef2ba8d2f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga4e98e82ed389c23918315d833b457ea9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_DECODE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa19b93d226e97afd08d3869dc530b692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_INTERNAL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga87ac559811703a8ca33fc6b427913f2b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_DEC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga43ecb16ea8e8d09a33364a17610d8909">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_INT_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f9ef0d10a7456a25a4b244955659d65">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_SLV_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga0f0d25fd68716e868742115c9a28c18c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SLAVE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6d50743f6c9d6474561f6727eb956915">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_GetRxIndexRing
+: <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetRxRing
+: <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetTxRing
+: <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_HALTED_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_HasSg
+: <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IDLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_IntrAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9ff0d2e5b50846e4b6a2d683283c10d5">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrDisable
+: <a class="el" href="group__axidma__v9__0.html#ga1936b497c0fa61d326807e5ed8dd572b">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrEnable
+: <a class="el" href="group__axidma__v9__0.html#gadac28afa26e2cb55bdada1ee3c016c52">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadba63ad7c0a784d569736a8d1eb7c367">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga6a0eb17bcfcaf3331e01855d302f5f0e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IRQ_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadc4a45d09bcbf852f29b880935d607dc">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_ERROR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6ceb68e74761910e4253795a9b4992cf">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_IOC_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae420f2ad87e1e00456a6ee3a80d2480d">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_MICROMODE_MIN_BUF_ALIGN
+: <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_ReadReg
+: <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gad80414a88feceb1da4b9f77096d1d590">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SGCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gab26580f9b4a94b3ab1d373ddeab7b3b6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gafaafc49751e690d818d604efe368c481">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga386fad6446792679302b362ed34022cf">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_WriteReg
+: <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">xaxidma_hw.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_func.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_func.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XAxiDma_BdGetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdRingAlloc()
+: <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingCheck()
+: <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingClone()
+: <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingCreate()
+: <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingDumpRegs()
+: <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFree()
+: <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFromHw()
+: <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingGetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingSetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingStart()
+: <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingToHw()
+: <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingUnAlloc()
+: <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdSetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetBufAddr()
+: <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetBufAddrMicroMode()
+: <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetCtrl()
+: <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetLength()
+: <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_Busy()
+: <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">xaxidma.c</a>
+</li>
+<li>XAxiDma_CfgInitialize()
+: <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">xaxidma.c</a>
+</li>
+<li>XAxiDma_DumpBd()
+: <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_LookupConfig()
+: <a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c">xaxidma.h</a>
+</li>
+<li>XAxiDma_Pause()
+: <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">xaxidma.c</a>
+</li>
+<li>XAxiDma_Reset()
+: <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">xaxidma.c</a>
+</li>
+<li>XAxiDma_ResetIsDone()
+: <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">xaxidma.c</a>
+</li>
+<li>XAxiDma_Resume()
+: <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">xaxidma.c</a>
+</li>
+<li>XAxiDma_SelectCyclicMode()
+: <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">xaxidma.c</a>
+</li>
+<li>XAxiDma_SelectKeyHole()
+: <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">xaxidma.c</a>
+</li>
+<li>XAxiDma_Selftest()
+: <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">xaxidma.h</a>
+</li>
+<li>XAxiDma_SimpleTransfer()
+: <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">xaxidma.c</a>
+</li>
+<li>XAxiDma_StartBdRingHw()
+: <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_UpdateBdRingCDesc()
+: <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">xaxidma_bdring.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_type.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_type.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<script type="text/javascript" src="dynsections.js"></script>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XAxiDma
+: <a class="el" href="group__axidma__v9__0.html#gac08fe7cb6508a133a7ef036bba7df5b5">xaxidma.h</a>
+</li>
+<li>XAxiDma_Bd
+: <a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">xaxidma_bd.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/group__axidma__v9__0.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/group__axidma__v9__0.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+<title>axidma_v9_0: Axidma_v9_0</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#nested-classes">Data Structures</a> &#124;
+<a href="#define-members">Macros</a> &#124;
+<a href="#typedef-members">Typedefs</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Axidma_v9_0</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+<tr class="separator:gadac28afa26e2cb55bdada1ee3c016c52"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gadba63ad7c0a784d569736a8d1eb7c367"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga1936b497c0fa61d326807e5ed8dd572b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memitem:gaf858d9659197442c9e96856c206423c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaf858d9659197442c9e96856c206423c6">XAxiDma_BdGetBufAddr</a>(BdPtr)                                      &#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>))</td></tr>
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+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe905567f3f1e4630e21d2f8192509576"></a>Register sets on TX and RX channels are identical </p>
+</td></tr>
+<tr class="memitem:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
+<tr class="separator:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register</h2></td></tr>
+<tr class="memitem:ga99f615c527035db697545614fff86bf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>(BaseAddress,  RegOffset)                      &#160;&#160;&#160;XAxiDma_In32((BaseAddress) + (RegOffset))</td></tr>
+<tr class="separator:ga99f615c527035db697545614fff86bf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga96d7b2834ae100f53627ca961393e9a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)                &#160;&#160;&#160;XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
+<tr class="separator:ga96d7b2834ae100f53627ca961393e9a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga2b64a2b3eb88233498a9dd6a01068de6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_ADDRLEN_OFFSET&#160;&#160;&#160;0x40</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Check for BD Addr. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, and <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaccd48ccba559728721eac77a4acc23d1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_BUFA_MSB_OFFSET&#160;&#160;&#160;0x0C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Buffer address. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, and <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8bb69f2401305faa1d89fb8dc31e770f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_BUFA_OFFSET&#160;&#160;&#160;0x08</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Buffer address. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>, and <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga97ec6974f990aef9ea2298c1df5d72c3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_BYTES_TO_CLEAR&#160;&#160;&#160;48</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>BD specific bytes to be cleared. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa409dba5ec46ad5a31953e22c4d3333f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_CTRL_ALL_MASK&#160;&#160;&#160;0x0C000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>All control bits. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac3372d0a1625537d5b637f40ca20f52c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_CTRL_LEN_OFFSET&#160;&#160;&#160;0x18</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Control/buffer length. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>, <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength()</a>, and <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae9f4d328b9fb0bbdcadd6dc4c09fd4fa"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_CTRL_TXEOF_MASK&#160;&#160;&#160;0x04000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Last tx packet. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, and <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac279d381208f7f123ac07736702f8ff1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_CTRL_TXSOF_MASK&#160;&#160;&#160;0x08000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>First tx packet. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad40d36cf3371ad3d176835933dc85e4b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_HAS_DRE_MASK&#160;&#160;&#160;0xF00</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Whether has DRE mask. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga932a4ab54f38046e6635b9b87a584c79"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_HAS_DRE_OFFSET&#160;&#160;&#160;0x3C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Whether has DRE. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, and <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac15dd4e956aa14d53a6f92544db468d1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_HAS_DRE_SHIFT&#160;&#160;&#160;8</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Whether has DRE shift. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga819b1b14cd4d386e588679105a8738a6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET&#160;&#160;&#160;0x38</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Whether has stscntrl strm. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">XAxiDma_BdGetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord()</a>, and <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae8ddf1d33d85b0a7508b9a072d95bf14"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_HW_NUM_BYTES&#160;&#160;&#160;52</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Number of bytes hw used. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga117e266cba3edbd1fd2f1e29305dcfc8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_ID_OFFSET&#160;&#160;&#160;0x34</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Sw ID. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6daf74c6d99207a0d8ba91a049e661c6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_MCCTL_OFFSET&#160;&#160;&#160;0x10</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Multichannel Control Fields. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga7957d90570574e9c7a7ee308b290ecab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_MINIMUM_ALIGNMENT&#160;&#160;&#160;0x40</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga730aa200407e3c7e38e6fad914ad1eb0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_NDESC_MSB_OFFSET&#160;&#160;&#160;0x04</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Next descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga64e86b7df328bc7209a28152f86fd609"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_NDESC_OFFSET&#160;&#160;&#160;0x00</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Next descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga751f6662ab9baed908685eef30d322b8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_NUM_WORDS&#160;&#160;&#160;20U</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Total number of words for one BD. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9eac2b100bcdf0aa763d1575f43c822b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_START_CLEAR&#160;&#160;&#160;8</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Offset to start clear. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga83d7d4d6e88ab44910242b61fcd7f8fe"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET&#160;&#160;&#160;0x14</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>2D Transfer Sizes </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8018932d7e9b743c4c5c76ab3d373de1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_ALL_ERR_MASK&#160;&#160;&#160;0x70000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>All errors. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac433a776854849cbeaadcbed14132cb6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_ALL_MASK&#160;&#160;&#160;0xFC000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>All status bits. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadb7c73caf5e5007dcb56ea029d7390ba"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_COMPLETE_MASK&#160;&#160;&#160;0x80000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Completed. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae79c77f87a9887510ea53480c1e9a998"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_DEC_ERR_MASK&#160;&#160;&#160;0x40000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Decode error. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga09e502148e375f2d695d6d5d6e1797d2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_INT_ERR_MASK&#160;&#160;&#160;0x10000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Internal err. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac71ad6cd79fc11e699bc10e3736fa08c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_OFFSET&#160;&#160;&#160;0x1C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Status. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga91b0504c621f6c06b0df4752fe65ee3a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_RXEOF_MASK&#160;&#160;&#160;0x04000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Last rx pkt. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga29915484fd9f840a8ab727cf83bbfe81"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_RXSOF_MASK&#160;&#160;&#160;0x08000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>First rx pkt. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga1f7727fc139a6b3100a5a17cb110efa6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_STS_SLV_ERR_MASK&#160;&#160;&#160;0x20000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Slave error. </p>
+
+</div>
+</div>
+<a class="anchor" id="gace0f0376ed9e0aad3d3e3c80254b20b4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_USR0_OFFSET&#160;&#160;&#160;0x20</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>User IP specific word0. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">XAxiDma_BdGetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord()</a>, and <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga7d9d62be0e0ed11b18f185b62dc72f67"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_USR1_OFFSET&#160;&#160;&#160;0x24</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>User IP specific word1. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gadc83ff22099fdf61a5237965ce082504"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_USR2_OFFSET&#160;&#160;&#160;0x28</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>User IP specific word2. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae1c5981447fe5ac113a6da3c1e19d6ed"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_USR3_OFFSET&#160;&#160;&#160;0x2C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>User IP specific word3. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga1ccae584923d0b6d0851a8bbae4528c9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_USR4_OFFSET&#160;&#160;&#160;0x30</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>User IP specific word4. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gafcbd1a131c650a5d6ceee6be15008a77"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_WORDLEN_MASK&#160;&#160;&#160;0xFF</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Whether has DRE mask. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga3db5b1d09deab9660ff65c06136acbc5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BD_WORDLEN_SHIFT&#160;&#160;&#160;0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Whether has DRE shift. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6c47900232c9a5a5ba30a2c1a3343628"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdClear</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">memset((<span class="keywordtype">void</span> *)(((UINTPTR)(BdPtr)) + <a class="code" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">XAXIDMA_BD_START_CLEAR</a>), 0, \</div>
+<div class="line">    <a class="code" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">XAXIDMA_BD_BYTES_TO_CLEAR</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga97ec6974f990aef9ea2298c1df5d72c3"><div class="ttname"><a href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">XAXIDMA_BD_BYTES_TO_CLEAR</a></div><div class="ttdeci">#define XAXIDMA_BD_BYTES_TO_CLEAR</div><div class="ttdoc">BD specific bytes to be cleared. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:248</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga9eac2b100bcdf0aa763d1575f43c822b"><div class="ttname"><a href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">XAXIDMA_BD_START_CLEAR</a></div><div class="ttdeci">#define XAXIDMA_BD_START_CLEAR</div><div class="ttdoc">Offset to start clear. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:247</div></div>
+</div><!-- fragment -->
+<p>Zero out BD specific fields. </p>
+<p>BD fields that are for the BD ring or for the system hardware build information are not touched.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga6c47900232c9a5a5ba30a2c1a3343628" title="Zero out BD specific fields. ">XAxiDma_BdClear(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga135667574b201437cfbdbecd8b348ee0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetActualLength</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">LengthMask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>) &amp; \</div>
+<div class="line">                LengthMask)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
+</div><!-- fragment -->
+<p>Get the actual transfer length of a BD. </p>
+<p>The BD has completed in hw.</p>
+<p>This function may not work if the BD is in cached memory.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to check on </td></tr>
+    <tr><td class="paramname">LengthMask</td><td>is the Maximum Transfer Length.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0" title="Get the actual transfer length of a BD. ">XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa5f7ba67cbbb678662e4b5d36c63d16e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetARCache</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_ARCACHE_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e" title="Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache. ">XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga72d1616af8d996f12db78473a75b54b6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetARUser</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_ARUSER_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6" title="Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser. ">XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf858d9659197442c9e96856c206423c6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetBufAddr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td>&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+
+<p>Get the BD's buffer address. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaf858d9659197442c9e96856c206423c6" title="Get the BD&#39;s buffer address. ">XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga495e780d704ecf548d3536b3bb8961a5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetCtrl</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>)    \</div>
+<div class="line">                &amp; <a class="code" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gac3372d0a1625537d5b637f40ca20f52c"><div class="ttname"><a href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_CTRL_LEN_OFFSET</div><div class="ttdoc">Control/buffer length. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:227</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa409dba5ec46ad5a31953e22c4d3333f"><div class="ttname"><a href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_BD_CTRL_ALL_MASK</div><div class="ttdoc">All control bits. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:269</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+</div><!-- fragment -->
+<p>Get the control bits for the BD. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The bit mask for the control of the BD</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5" title="Get the control bits for the BD. ">XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaf3f333d78d115724bfcac84746d8cfa6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetId</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td>&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+
+<p>Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6" title="Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId. ">XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9875ecb45b47664b70d74e8810fd5cf0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetLength</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">LengthMask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>) &amp; \</div>
+<div class="line">                LengthMask)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gac3372d0a1625537d5b637f40ca20f52c"><div class="ttname"><a href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_CTRL_LEN_OFFSET</div><div class="ttdoc">Control/buffer length. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:227</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+</div><!-- fragment -->
+<p>Retrieve the length field value from the given BD. </p>
+<p>The returned value is the same as what was written with <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07" title="Set the length field for the given BD. ">XAxiDma_BdSetLength()</a>. Note that in the this value does not reflect the real length of received data. See the comments of <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07" title="Set the length field for the given BD. ">XAxiDma_BdSetLength()</a> for more details. To obtain the actual transfer length, use <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0" title="Get the actual transfer length of a BD. ">XAxiDma_BdGetActualLength()</a>.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
+    <tr><td class="paramname">LengthMask</td><td>is the Maximum Transfer Length.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The length value set in the BD.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0" title="Retrieve the length field value from the given BD. ">XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga29a75b8f1de16a347544e37b48d8129c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetStride</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_STRIDE_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
+</div><!-- fragment -->
+<p>Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c" title="Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride. ">XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf2448f2b2ac172da0d19adeae3cc4c48"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetSts</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>) &amp; <a class="code" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">		XAXIDMA_BD_STS_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac433a776854849cbeaadcbed14132cb6"><div class="ttname"><a href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">XAXIDMA_BD_STS_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_ALL_MASK</div><div class="ttdoc">All status bits. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:282</div></div>
+</div><!-- fragment -->
+<p>Retrieve the status of a BD. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_*** values defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a> to interpret the returned value</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaf2448f2b2ac172da0d19adeae3cc4c48" title="Retrieve the status of a BD. ">XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8c1e3dd04821568424ffc77caf11a851"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetTDest</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_TDEST_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
+</div><!-- fragment -->
+<p>Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851" title="Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest. ">XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac14fa76311fd7e5fb59b81fd9e251f62"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetTId</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_TID_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
+</div><!-- fragment -->
+<p>Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62" title="Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId. ">XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7a2f9668058b7e4cdc89dffcce6086d3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetTUser</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_TUSER_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
+</div><!-- fragment -->
+<p>Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3" title="Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser. ">XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad9f48ceb5b30d66bab23337edc35d2fe"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdGetVSize</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>)) &amp;  \</div>
+<div class="line">                XAXIDMA_BD_VSIZE_FIELD_MASK)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
+</div><!-- fragment -->
+<p>Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe" title="Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize. ...">XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga20937b96fad07f286948f1af50590421"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdHwCompleted</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>) &amp; <a class="code" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">		XAXIDMA_BD_STS_COMPLETE_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gadb7c73caf5e5007dcb56ea029d7390ba"><div class="ttname"><a href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_COMPLETE_MASK</div><div class="ttdoc">Completed. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:275</div></div>
+</div><!-- fragment -->
+<p>Check whether a BD has completed in hardware. </p>
+<p>This BD has been submitted to hardware. The application can use this function to poll for the completion of the BD.</p>
+<p>This function may not work if the BD is in cached memory.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to check on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>0 if not complete</li>
+<li>XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain XAXIDMA_BD_STS_*_ERR_MASK bits.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421" title="Check whether a BD has completed in hardware. ">XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa738ffd392c7ae1e844fab340ba50fee"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRead</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Offset&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(*(u32 *)((UINTPTR)((void *)(BaseAddress)) + (u32)(Offset)))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+
+<p>Read the given Buffer Descriptor word. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the BD to read </td></tr>
+    <tr><td class="paramname">Offset</td><td>is the word offset to be read</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the field</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee" title="Read the given Buffer Descriptor word. ">XAxiDma_BdRead(u32 BaseAddress, u32 Offset)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">XAxiDma_BdGetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>, <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength()</a>, <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga9e782e3715c1d2dd03e5d03434f47319"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingAckIrq</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>,\</div>
+<div class="line">                        (Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga96d7b2834ae100f53627ca961393e9a2"><div class="ttname"><a href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)                </div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:350</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>Acknowledge asserted interrupts. </p>
+<p>It modifies XAXIDMA_SR_OFFSET register. A mask bit set for an unasserted interrupt has no effect.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
+    <tr><td class="paramname">Mask</td><td>are the interrupt signals to acknowledge</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319" title="Acknowledge asserted interrupts. ">XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf7c291190c92ce93d72f95c5b04ef1d4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingBusy</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>(RingPtr) &amp;&amp;          \</div>
+<div class="line">                ((<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div>
+<div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a>) ? FALSE : TRUE))</div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa3538e8c2a6e024641259c85368667f0"><div class="ttname"><a href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a></div><div class="ttdeci">#define XAXIDMA_IDLE_MASK</div><div class="ttdoc">DMA channel idle. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:173</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga766bed2454969636d827fb79faeeee97"><div class="ttname"><a href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a></div><div class="ttdeci">#define XAxiDma_BdRingHwIsStarted(RingPtr)</div><div class="ttdoc">Check whether a DMA channel is started, meaning the channel is not halted. </div><div class="ttdef"><b>Definition:</b> xaxidma_bdring.h:369</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>Check if the current DMA channel is busy with a DMA operation. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>1 if the DMA is busy.</li>
+<li>0 otherwise</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4" title="Check if the current DMA channel is busy with a DMA operation. ">XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga98555b607a9ec831dc6473e77515bb4b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingCntCalc</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Alignment, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(uint32_t)((Bytes)/((sizeof(<a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>)+((Alignment)-1))&amp;~((Alignment)-1)))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+
+<p>Use this macro at initialization time to determine how many BDs will fit within the given memory constraints. </p>
+<p>The results of this macro can be provided to <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Alignment</td><td>specifies what byte alignment the BDs must fall on and must be a power of 2 to get an accurate calculation (32, 64, 126,...) </td></tr>
+    <tr><td class="paramname">Bytes</td><td>is the number of bytes to be used to store BDs.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Number of BDs that can fit in the given memory area</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b" title="Use this macro at initialization time to determine how many BDs will fit within the given memory cons...">XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac62389e25e6775026cf1be6c383e665b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingGetCnt</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td>&#160;&#160;&#160;((RingPtr)-&gt;AllCnt)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+
+<p>Return the total number of BDs allocated by this channel with <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The total number of BDs allocated for this channel.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b" title="Return the total number of BDs allocated by this channel with XAxiDma_BdRingCreate(). ">XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga21aa8dbf6eabf9146097d9b3cc91c574"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingGetCurrBd</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *)<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">					XAXIDMA_CDESC_OFFSET</a>)              \</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga11a02100a6c84e394caa41761ab7485c"><div class="ttname"><a href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a></div><div class="ttdeci">UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]</div><div class="ttdoc">The XAxiDma_Bd is the type for a buffer descriptor (BD). </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:135</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga24b47801eed2ab0ba326b8b40d24f2b1"><div class="ttname"><a href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">XAXIDMA_CDESC_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CDESC_OFFSET</div><div class="ttdoc">Current descriptor pointer. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:128</div></div>
+</div><!-- fragment -->
+<p>Get the BD a BD ring is processing. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The current BD that the BD ring is working on</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: XAxiDma_Bd * <a class="el" href="group__axidma__v9__0.html#ga21aa8dbf6eabf9146097d9b3cc91c574" title="Get the BD a BD ring is processing. ">XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga24cd47cdbfac0813e0d9caf966a1a3d2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingGetError</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div>
+<div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">XAXIDMA_ERR_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga4102192c408420feb5b7db14d47c6d5c"><div class="ttname"><a href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">XAXIDMA_ERR_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_ERR_ALL_MASK</div><div class="ttdoc">All errors. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:184</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>Get error bits of a DMA channel. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Rrror bits in the status register, they should be interpreted with XAXIDMA_ERR_*_MASK defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a></dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2" title="Get error bits of a DMA channel. ">XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga415cf0c379fef0104f9f52881ead13a7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingGetFreeCnt</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td>&#160;&#160;&#160;((RingPtr)-&gt;FreeCnt)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+
+<p>Return the number of BDs allocatable with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> for pre- processing. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The number of BDs currently allocatable.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7" title="Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre- processing. ">XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7a9d2103e6d09fc3850b34a6386dc803"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingGetIrq</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div>
+<div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. </p>
+<p>This operation can be used to see which interrupts are pending.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Current contents of the IRQ_OFFSET register. Use XAXIDMA_IRQ_*** values defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a> to interpret the returned value.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803" title="Retrieve the contents of the channel&#39;s IRQ register XAXIDMA_SR_OFFSET. ">XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga740fa349c7811de2b7bae5cf83eb445e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingGetSr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td>&#160;&#160;&#160;<a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+
+<p>Retrieve the contents of the channel status register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Current contents of status register</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e" title="Retrieve the contents of the channel status register. ">XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga766bed2454969636d827fb79faeeee97"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingHwIsStarted</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div>
+<div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">XAXIDMA_HALTED_MASK</a>) ? FALSE : TRUE)</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga70671c3d8cd1e51c56723e298d268cce"><div class="ttname"><a href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">XAXIDMA_HALTED_MASK</a></div><div class="ttdeci">#define XAXIDMA_HALTED_MASK</div><div class="ttdoc">DMA channel halted. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:172</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>Check whether a DMA channel is started, meaning the channel is not halted. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>1 if channel is started</li>
+<li>0 otherwise</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97" title="Check whether a DMA channel is started, meaning the channel is not halted. ">XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga0269e07693c731cf7721c6f19f8eb69b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingIntDisable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div>
+<div class="line">                <a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) &amp; \</div>
+<div class="line">                        ~((Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)))</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga96d7b2834ae100f53627ca961393e9a2"><div class="ttname"><a href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)                </div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:350</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
+</div><!-- fragment -->
+<p>Clear interrupt enable bits for a channel. </p>
+<p>It modifies the XAXIDMA_CR_OFFSET register.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
+    <tr><td class="paramname">Mask</td><td>consists of the interrupt signals to disable.Bits not specified in the Mask are not affected.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask) This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga2518030938ab80081f6896fc5589682c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingIntEnable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div>
+<div class="line">                <a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) \</div>
+<div class="line">                        | ((Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)))</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga96d7b2834ae100f53627ca961393e9a2"><div class="ttname"><a href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)                </div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:350</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
+</div><!-- fragment -->
+<p>Set interrupt enable bits for a channel. </p>
+<p>This operation will modify the XAXIDMA_CR_OFFSET register.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
+    <tr><td class="paramname">Mask</td><td>consists of the interrupt signals to enable.Bits not specified in the mask are not affected.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c" title="Set interrupt enable bits for a channel. ">XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadbb17169213d8af8b50e6dee7f7b6d8b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingIntGetEnabled</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) \</div>
+<div class="line">                &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
+</div><!-- fragment -->
+<p>Get enabled interrupts of a channel. </p>
+<p>It is in XAXIDMA_CR_OFFSET register.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a> to interpret this returned value.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b" title="Get enabled interrupts of a channel. ">XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga6899085c400b8f453381b305ac5521d9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingMemCalc</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Alignment, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">NumBd&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(int)((sizeof(<a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>)+((Alignment)-1)) &amp; ~((Alignment)-1))*(NumBd)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+
+<p>Use this macro at initialization time to determine how many bytes of memory are required to contain a given number of BDs at a given alignment. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Alignment</td><td>specifies what byte alignment the BDs must fall on. This parameter must be a power of 2 to get an accurate calculation (32, 64,128,...) </td></tr>
+    <tr><td class="paramname">NumBd</td><td>is the number of BDs to calculate memory size requirements</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The number of bytes of memory required to create a BD list with the given memory constraints.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9" title="Use this macro at initialization time to determine how many bytes of memory are required to contain a...">XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga4b7e75d1acf86428bd79fcd0d1c13745"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingNext</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(((UINTPTR)(BdPtr) &gt;= (RingPtr)-&gt;LastBdAddr) ?  \</div>
+<div class="line">                        (UINTPTR)(RingPtr)-&gt;FirstBdAddr :       \</div>
+<div class="line">                        (UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)-&gt;Separation))</div>
+</div><!-- fragment -->
+<p>Return the next BD in the ring. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on. </td></tr>
+    <tr><td class="paramname">BdPtr</td><td>is the current BD.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The next BD in the ring relative to the BdPtr parameter.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr, XAxiDma_Bd *BdPtr) This function is used only when system is configured as SG mode </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga86c6d4b9c4f8766634d46a3078eadc8a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingPrev</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(((u32)(BdPtr) &lt;= (RingPtr)-&gt;FirstBdAddr) ?             \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>*)(RingPtr)-&gt;LastBdAddr :            \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>*)((u32)(BdPtr) - (RingPtr)-&gt;Separation))</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga11a02100a6c84e394caa41761ab7485c"><div class="ttname"><a href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a></div><div class="ttdeci">UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]</div><div class="ttdoc">The XAxiDma_Bd is the type for a buffer descriptor (BD). </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:135</div></div>
+</div><!-- fragment -->
+<p>Return the previous BD in the ring. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the DMA channel to operate on. </td></tr>
+    <tr><td class="paramname">BdPtr</td><td>is the current BD.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The previous BD in the ring relative to the BdPtr parameter.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr, XAxiDma_Bd *BdPtr) This function is used only when system is configured as SG mode </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0d79253861939c76e6d440ecde2b6edd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdRingSnapShotCurrBd</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{                                                                 \</div>
+<div class="line">                if (!RingPtr-&gt;IsRxChannel) {                              \</div>
+<div class="line">                        (RingPtr)-&gt;BdaRestart =                           \</div>
+<div class="line">                                <a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">					XAXIDMA_CDESC_OFFSET</a>);               \</div>
+<div class="line">                } <span class="keywordflow">else</span> {                                                  \</div>
+<div class="line">                        if (!RingPtr-&gt;RingIndex) {                                \</div>
+<div class="line">                                (RingPtr)-&gt;BdaRestart =                   \</div>
+<div class="line">                                <a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>(            \</div>
+<div class="line">                                        (RingPtr)-&gt;ChanBase,              <a class="code" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">					XAXIDMA_CDESC_OFFSET</a>);               \</div>
+<div class="line">                        } <span class="keywordflow">else</span> {                                          \</div>
+<div class="line">                                (RingPtr)-&gt;BdaRestart =                   \</div>
+<div class="line">                                <a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>(                  \</div>
+<div class="line">                                (RingPtr)-&gt;ChanBase,                      \</div>
+<div class="line">                                (<a class="code" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a> +               \</div>
+<div class="line">                                (RingPtr-&gt;RingIndex - 1) *                \</div>
+<div class="line">                                        <a class="code" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>));        \</div>
+<div class="line">                        }                                                 \</div>
+<div class="line">                }                                                         \</div>
+<div class="line">        }</div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6fc559cbc93b62195de6ecaf25492467"><div class="ttname"><a href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_NDESC_OFFSET</div><div class="ttdoc">Rx Next Descriptor Offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:148</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga79d2eca90f2554b8c893b2f9a70c795c"><div class="ttname"><a href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_CDESC0_OFFSET</div><div class="ttdoc">Multi-Channel DMA Descriptor Offsets. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:144</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga24b47801eed2ab0ba326b8b40d24f2b1"><div class="ttname"><a href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">XAXIDMA_CDESC_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CDESC_OFFSET</div><div class="ttdoc">Current descriptor pointer. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:128</div></div>
+</div><!-- fragment -->
+<p>Snap shot the latest BD a BD ring is processing. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd" title="Snap shot the latest BD a BD ring is processing. ">XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac7d8a383cd6d5aff6ee36c3a3db20cbf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetARCache</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">ARCache&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_ARCACHE_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(ARCache) &lt;&lt; XAXIDMA_BD_ARCACHE_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Set the ARCACHE field of the given BD. </p>
+<p>This signal provides additional information about the cacheable characteristics of the transfer.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">ARCache</td><td>is a 8 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf" title="Set the ARCACHE field of the given BD. ">XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae89253197f1aef6582d5cda3e49f8ead"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetARUser</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">ARUser&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_ARUSER_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(ARUser) &lt;&lt; XAXIDMA_BD_ARUSER_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Set the ARUSER field of the given BD. </p>
+<p>Sideband signals used for user defined information.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">ARUser</td><td>is a 8 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead" title="Set the ARUSER field of the given BD. ">XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga53eeff085fd39a91b855939f13fe76f3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetId</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Id&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>, (u32)(Id)))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+
+<p>Set the ID field of the given BD. </p>
+<p>The ID is an arbitrary piece of data the application can associate with a specific BD.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">Id</td><td>is a 32 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga53eeff085fd39a91b855939f13fe76f3" title="Set the ID field of the given BD. ">XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga58961be41e3c0bc2694444bfe37b6c27"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetStride</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stride&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_STRIDE_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(Stride) &lt;&lt; XAXIDMA_BD_STRIDE_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
+</div><!-- fragment -->
+<p>Set the STRIDE field of the given BD. </p>
+<p>It is the address distance between the first address of successive horizontal reads.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">Stride</td><td>is a 32 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27" title="Set the STRIDE field of the given BD. ">XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga5f9b3088c4e16c7f5584610a43b17462"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetTDest</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TDest&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_TDEST_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(TDest) &lt;&lt; XAXIDMA_BD_TDEST_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Set the TDEST field of the TX BD. </p>
+<p>Provides coarse routing information for the data stream.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">TDest</td><td>is a 8 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462" title="Set the TDEST field of the TX BD. ">XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa5bc321894b77ca6194c867018d9fe12"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetTId</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TId&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_TID_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(TId) &lt;&lt; XAXIDMA_BD_TID_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Set the TID field of the TX BD. </p>
+<p>Provides a stream identifier and can be used to differentiate between multiple streams of data that are being transferred across the same interface.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">TId</td><td>is a 8 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12" title="Set the TID field of the TX BD. ">XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gacf41c0ebe00870b6cdd34e46698e081b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetTUser</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TUser&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_TUSER_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(TUser) &lt;&lt; XAXIDMA_BD_TUSER_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
+</div><!-- fragment -->
+<p>Set the TUSER field of the TX BD. </p>
+<p>User defined sideband signaling.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">TUser</td><td>is a 8 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b" title="Set the TUSER field of the TX BD. ">XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga383b2c0667bf5bafa22922168895bd5e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdSetVSize</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BdPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">VSize&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 val; \</div>
+<div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>) &amp; \</div>
+<div class="line">                ~XAXIDMA_BD_VSIZE_FIELD_MASK); \</div>
+<div class="line">        val |= ((u32)(VSize) &lt;&lt; XAXIDMA_BD_VSIZE_FIELD_SHIFT); <a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">	XAxiDma_BdWrite</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>, val); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__axidma__v9__0_html_gab3b7d771208c01701b35bce165332a9f"><div class="ttname"><a href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a></div><div class="ttdeci">#define XAxiDma_BdWrite(BaseAddress, Offset, Data)</div><div class="ttdoc">Write the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:189</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:170</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
+</div><!-- fragment -->
+<p>Set the VSIZE field of the given BD. </p>
+<p>Number of horizontal lines for strided access.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">VSize</td><td>is a 32 bit quantity to set in the BD</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e" title="Set the VSIZE field of the given BD. ">XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gab3b7d771208c01701b35bce165332a9f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_BdWrite</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Offset, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Data&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+
+<p>Write the given Buffer Descriptor word. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the BD to write </td></tr>
+    <tr><td class="paramname">Offset</td><td>is the word offset to be written </td></tr>
+    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the field</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f" title="Write the given Buffer Descriptor word. ">XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>, and <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa7ede468ba17bf106101d4850184dc74"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_BUFFLEN_OFFSET&#160;&#160;&#160;0x00000028</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Tail descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga00ee7a235750d8795961223455407051"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CDESC_MSB_OFFSET&#160;&#160;&#160;0x0000000C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Current descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga24b47801eed2ab0ba326b8b40d24f2b1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CDESC_OFFSET&#160;&#160;&#160;0x00000008</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Current descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga280fd988ea7ec3fadfe7cf1293f39e36"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_COALESCE_MASK&#160;&#160;&#160;0x00FF0000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Coalesce counter. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, and <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga2d34bf268de2f2ef4d32351043835f68"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CR_CYCLIC_MASK&#160;&#160;&#160;0x00000010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Cyclic Mode. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8bdf83c8ba16d8217a2a6486a9b5b521"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CR_KEYHOLE_MASK&#160;&#160;&#160;0x00000008</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Keyhole feature. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8534b07ed878f92d2062dc1680fb0391"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CR_OFFSET&#160;&#160;&#160;0x00000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Channel control. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>, <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga33fda61f0837d37da36d3b72b90b0fba"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CR_RESET_MASK&#160;&#160;&#160;0x00000004</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Reset DMA engine. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, and <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab0ebdf6b7776e79941efe1325aac5aa9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_CR_RUNSTOP_MASK&#160;&#160;&#160;0x00000001</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Start/stop DMA channel. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae3ad7ae6b5814b99de67bba06ec77ed1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_DELAY_MASK&#160;&#160;&#160;0xFF000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Delay timeout counter. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, and <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga170ce0e12eb12686a03e006610e2acd2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_DESC_LSB_MASK&#160;&#160;&#160;(0xFFFFFFC0U)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>LSB Address mask. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga3a54e372851dbae81c33997ef2ba8d2f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_DESTADDR_MSB_OFFSET&#160;&#160;&#160;0x0000001C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Simple mode destination address pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga4e98e82ed389c23918315d833b457ea9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_DESTADDR_OFFSET&#160;&#160;&#160;0x00000018</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Simple mode destination address pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga4102192c408420feb5b7db14d47c6d5c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_ALL_MASK&#160;&#160;&#160;0x00000770</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>All errors. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa19b93d226e97afd08d3869dc530b692"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_DECODE_MASK&#160;&#160;&#160;0x00000040</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Datamover decode err. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga87ac559811703a8ca33fc6b427913f2b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_INTERNAL_MASK&#160;&#160;&#160;0x00000010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Datamover internal err. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga43ecb16ea8e8d09a33364a17610d8909"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_SG_DEC_MASK&#160;&#160;&#160;0x00000400</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>SG decode err. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga1f9ef0d10a7456a25a4b244955659d65"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_SG_INT_MASK&#160;&#160;&#160;0x00000100</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>SG internal err. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga0f0d25fd68716e868742115c9a28c18c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_SG_SLV_MASK&#160;&#160;&#160;0x00000200</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>SG slave err. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6d50743f6c9d6474561f6727eb956915"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_ERR_SLAVE_MASK&#160;&#160;&#160;0x00000020</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Datamover slave err. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf03e87b58cf2f9800e6260fda3745631"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_GetRxIndexRing</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RingIndex&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;RxBdRing[RingIndex]))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>Get Receive (Rx) Ring ptr of a Index. </p>
+<p>Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on. </td></tr>
+    <tr><td class="paramname">RingIndex</td><td>is the channel Index.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Pointer to the Rx Ring</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * XAxiDma_GetRxIndexRing(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> * InstancePtr, int RingIndex) This function is used only when system is configured as SG mode </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, and <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6373ac3baa5365607f6727f4e2ece7a5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_GetRxRing</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;RxBdRing[0]))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>Get Receive (Rx) Ring ptr. </p>
+<p>Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Pointer to the Rx Ring</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5" title="Get Receive (Rx) Ring ptr. ">XAxiDma_GetRxRing(XAxiDma * InstancePtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga9d91f29c6dc41f2106e097f1f9957a6e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_GetTxRing</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;TxBdRing))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>Get Transmit (Tx) Ring ptr. </p>
+<p>Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Pointer to the Tx Ring</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e" title="Get Transmit (Tx) Ring ptr. ">XAxiDma_GetTxRing(XAxiDma * InstancePtr)</a> This function is used only when system is configured as SG mode </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, and <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga70671c3d8cd1e51c56723e298d268cce"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_HALTED_MASK&#160;&#160;&#160;0x00000001</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>DMA channel halted. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga18dd03026dd6c0ebd13526116c09ccae"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_HasSg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;((InstancePtr)-&gt;HasSg) ? TRUE : FALSE</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>This function checks whether system is configured as Simple or Scatter Gather mode. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>TRUE if configured as SG mode</li>
+<li>FALSE if configured as simple mode</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume()</a>, and <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa3538e8c2a6e024641259c85368667f0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_IDLE_MASK&#160;&#160;&#160;0x00000002</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>DMA channel idle. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga9ff0d2e5b50846e4b6a2d683283c10d5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_IntrAckIrq</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Direction&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>, \</div>
+<div class="line">                        (Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga96d7b2834ae100f53627ca961393e9a2"><div class="ttname"><a href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)                </div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:350</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>This function acknowledges the interrupts that are specified in Mask. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
+    <tr><td class="paramname">Mask</td><td>is the mask for the interrupts to be acknowledge </td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1936b497c0fa61d326807e5ed8dd572b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_IntrDisable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Direction&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>)) \</div>
+<div class="line">                        &amp; ~(Mask &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>))</div>
+<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga96d7b2834ae100f53627ca961393e9a2"><div class="ttname"><a href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)                </div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:350</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
+</div><!-- fragment -->
+<p>This function disables interrupts specified by the Mask. </p>
+<p>Interrupts that are not in the mask are not affected.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
+    <tr><td class="paramname">Mask</td><td>is the mask for the interrupts to be disabled </td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA. </li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadac28afa26e2cb55bdada1ee3c016c52"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_IntrEnable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Direction&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>)) \</div>
+<div class="line">                        | (Mask &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>))</div>
+<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga96d7b2834ae100f53627ca961393e9a2"><div class="ttname"><a href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)                </div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:350</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
+</div><!-- fragment -->
+<p>This function enables interrupts specified by the Mask in specified direction, Interrupts that are not in the mask are not affected. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
+    <tr><td class="paramname">Mask</td><td>is the mask for the interrupts to be enabled </td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA. </li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadba63ad7c0a784d569736a8d1eb7c367"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_IntrGetEnabled</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Direction&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) &amp;<a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">							XAXIDMA_IRQ_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
+</div><!-- fragment -->
+<p>This function gets the mask for the interrupts that are currently enabled. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The bit mask for the interrupts that are currently enabled</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga6a0eb17bcfcaf3331e01855d302f5f0e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_IntrGetIrq</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Direction&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div>
+<div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) &amp;<a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">\</a></div>
+<div class="line"><a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">							XAXIDMA_IRQ_ALL_MASK</a>)</div>
+<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga99f615c527035db697545614fff86bf2"><div class="ttname"><a href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)                      </div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:331</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
+<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
+</div><!-- fragment -->
+<p>This function gets the interrupts that are asserted. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The bit mask for the interrupts asserted.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga8347e41a5c01bdabefce9c8484a7ced1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_IRQ_ALL_MASK&#160;&#160;&#160;0x00007000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>All interrupts. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadc4a45d09bcbf852f29b880935d607dc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_IRQ_DELAY_MASK&#160;&#160;&#160;0x00002000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Delay interrupt. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6ceb68e74761910e4253795a9b4992cf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_IRQ_ERROR_MASK&#160;&#160;&#160;0x00004000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Error interrupt. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae420f2ad87e1e00456a6ee3a80d2480d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_IRQ_IOC_MASK&#160;&#160;&#160;0x00001000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Completion intr. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf0f7e862f42d26800868816eea2a949b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN&#160;&#160;&#160;0xFFF</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Minimum byte alignment requirement for buffer address in Micro DMA mode. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>, and <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga99f615c527035db697545614fff86bf2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_ReadReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XAxiDma_In32((BaseAddress) + (RegOffset))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Read the given register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
+    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2" title="Read the given register. ">XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>, <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad80414a88feceb1da4b9f77096d1d590"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_RX_CDESC0_MSB_OFFSET&#160;&#160;&#160;0x00000044</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Rx Current Descriptor 0. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga79d2eca90f2554b8c893b2f9a70c795c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_RX_CDESC0_OFFSET&#160;&#160;&#160;0x00000040</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Multi-Channel DMA Descriptor Offsets. </p>
+<p>Rx Current Descriptor 0 </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6fc559cbc93b62195de6ecaf25492467"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_RX_NDESC_OFFSET&#160;&#160;&#160;0x00000020</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Rx Next Descriptor Offset. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gadfdc083e0b249c04624a66e700d7a7c4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_RX_OFFSET&#160;&#160;&#160;0x00000030</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>RX channel registers base offset. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa9b5991af857e7bac763311fd917978d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_RX_TDESC0_MSB_OFFSET&#160;&#160;&#160;0x0000004C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Rx Tail Descriptor 0. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gadfa4d02f0dd1fd005c695e9977457722"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_RX_TDESC0_OFFSET&#160;&#160;&#160;0x00000048</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Rx Tail Descriptor 0. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab26580f9b4a94b3ab1d373ddeab7b3b6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_SGCTL_OFFSET&#160;&#160;&#160;0x0000002c</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>SG Control Register. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga50d6957f8447d4eab9e444666730f692"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_SR_OFFSET&#160;&#160;&#160;0x00000004</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Status. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>, and <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gafaafc49751e690d818d604efe368c481"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_SRCADDR_MSB_OFFSET&#160;&#160;&#160;0x0000001C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Simple mode source address pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga386fad6446792679302b362ed34022cf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_SRCADDR_OFFSET&#160;&#160;&#160;0x00000018</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Simple mode source address pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6063ffb7cb46cdca589e6f31069f7758"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_TDESC_MSB_OFFSET&#160;&#160;&#160;0x00000014</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Tail descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac8626fb2bed7230a2c82a7e1db0ddd35"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_TDESC_OFFSET&#160;&#160;&#160;0x00000010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Tail descriptor pointer. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga88232281611059fd669f0339888cd44e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIDMA_TX_OFFSET&#160;&#160;&#160;0x00000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>TX channel registers base offset. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga96d7b2834ae100f53627ca961393e9a2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxiDma_WriteReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Data&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>
+
+<p>Write the given register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
+    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
+    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2" title="Write the given register. ">XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>, <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="gac08fe7cb6508a133a7ef036bba7df5b5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="struct_x_axi_dma.html">XAxiDma</a>  <a class="el" href="struct_x_axi_dma.html">XAxiDma</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>The <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> driver instance data. </p>
+<p>An instance must be allocated for each DMA engine in use. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga11a02100a6c84e394caa41761ab7485c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef UINTPTR XAxiDma_Bd[<a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">XAXIDMA_BD_NUM_WORDS</a>]</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
+
+<p>The XAxiDma_Bd is the type for a buffer descriptor (BD). </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga9d2814e4249884e68fe9e6f370920ca4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdGetAppWord </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Offset</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&#160;</td>
+          <td class="paramname"><em>Valid</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Get the APP word at the specified APP word offset for a BD. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
+    <tr><td class="paramname">Offset</td><td>is the offset inside the APP word, it is valid from 0 to 4 </td></tr>
+    <tr><td class="paramname">Valid</td><td>is to tell the caller whether parameters are valid</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The APP word. Passed in parameter Valid holds 0 for failure, and 1 for success.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">XAXIDMA_BD_USR0_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga44003cd704b7d4868d1dc00bb433a91f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingAlloc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>NumBd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> **&#160;</td>
+          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Reserve locations in the BD ring. </p>
+<p>The set of returned BDs may be modified in preparation for future DMA transactions. Once the BDs are ready to be submitted to hardware, the application must call <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> in the same order which they were allocated here. Example:</p>
+<pre>
+       NumBd = 2;
+       Status = XDsma_RingBdAlloc(MyRingPtr, NumBd, &amp;MyBdSet);</pre><pre>       if (Status != XST_SUCCESS)
+       {
+           // Not enough BDs available for the request
+       }</pre><pre>       CurBd = MyBdSet;
+       for (i=0; i&lt;NumBd; i++)
+       {
+           // Prepare CurBd.....</pre><pre>           // Onto next BD
+           CurBd = <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext(MyRingPtr, CurBd)</a>;
+       }</pre><pre>       // Give list to hardware
+       Status = XAxiDma_BdRingToHw(MyRingPtr, NumBd, MyBdSet);
+</pre><p>A more advanced use of this function may allocate multiple sets of BDs. They must be allocated and given to hardware in the correct sequence: </p><pre>
+       // Legal
+       XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &amp;MySet1);
+       XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);</pre><pre>       // Legal
+       XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &amp;MySet1);
+       XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &amp;MySet2);
+       XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+       XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);</pre><pre>       // Not legal
+       XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &amp;MySet1);
+       XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &amp;MySet2);
+       XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);
+       XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+</pre><p>Use the API defined in xaxidmabd.h to modify individual BDs. Traversal of the BD set can be done using <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext()</a> and <a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a" title="Return the previous BD in the ring. ">XAxiDma_BdRingPrev()</a>.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">NumBd</td><td>is the number of BDs to allocate </td></tr>
+    <tr><td class="paramname">BdSetPtr</td><td>is an output parameter, it points to the first BD available for modification.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the requested number of BDs were returned in the BdSetPtr parameter.</li>
+<li>XST_INVALID_PARAM if passed in NumBd is not positive</li>
+<li>XST_FAILURE if there were not enough free BDs to satisfy the request.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</dd></dl>
+<p>Do not modify more BDs than the number requested with the NumBd parameter. Doing so will lead to data corruption and system instability.</p>
+<p>This function can be used only when DMA is in SG mode </p>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing::FreeHead</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga64cf3c732bc803da742c256ab6372e0e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingCheck </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Check the internal data structures of the BD ring for the provided channel. </p>
+<p>The following checks are made:</p>
+<ul>
+<li>The BD ring is linked correctly in physical address space.</li>
+<li>The internal pointers point to BDs in the ring.</li>
+<li>The internal counters add up.</li>
+</ul>
+<p>The channel should be stopped (through <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c" title="Pause DMA transactions on both channels. ">XAxiDma_Pause()</a> or <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f" title="Reset both TX and RX channels of a DMA engine. ">XAxiDma_Reset()</a>) prior to calling this function.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if no errors were found.</li>
+<li>XST_DMA_SG_NO_LIST if the ring has not been created.</li>
+<li>XST_IS_STARTED if the channel is not stopped.</li>
+<li>XST_DMA_SG_LIST_ERROR if a problem is found with the internal data structures. If this value is returned, the channel should be reset,and the BD ring should be recreated through <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a> to avoid data corruption or system instability.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing::FirstBdAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#add2c7d765c8d95eeb9d0f94a54775528">XAxiDma_BdRing::FirstBdPhysAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing::FreeHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing::HwHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing::HwTail</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a3743d05f930d7c04abb0693f2ef0b271">XAxiDma_BdRing::LastBdAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing::PostCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing::PostHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing::PreHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing::Separation</a>, <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">XAXIDMA_BD_NDESC_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad044df5bd676a71226411ba7f78ef20b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingClone </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>SrcBdPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Clone the given BD into every BD in the ring. </p>
+<p>Only the fields offset from XAXIDMA_BD_START_CLEAR are copied, for XAXIDMA_BD_BYTES_TO_CLEAR bytes. This covers: BufferAddr, Control/Buffer length, status, APP words 0 - 4, and software ID fields.</p>
+<p>This function can be called only when all BDs are in the free group such as immediately after creation of the ring. This prevents modification of BDs while they are in use by hardware or the application.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">SrcBdPtr</td><td>is the source BD template to be cloned into the list.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the list was modified.</li>
+<li>XST_DMA_SG_NO_LIST if a list has not been created.</li>
+<li>XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.</li>
+<li>XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under hardware or application control.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing::FirstBdAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing::Separation</a>, <a class="el" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">XAXIDMA_BD_BYTES_TO_CLEAR</a>, <a class="el" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">XAXIDMA_BD_START_CLEAR</a>, <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga5c6d6f492642dd355478c3a853556d6b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdRingCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">UINTPTR&#160;</td>
+          <td class="paramname"><em>PhysAddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">UINTPTR&#160;</td>
+          <td class="paramname"><em>VirtAddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Alignment</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>BdCount</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the BD ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">PhysAddr</td><td>is the physical base address of application memory region. </td></tr>
+    <tr><td class="paramname">VirtAddr</td><td>is the virtual base address of the application memory region.If address translation is not being utilized, then VirtAddr should be equivalent to PhysAddr. </td></tr>
+    <tr><td class="paramname">Alignment</td><td>governs the byte alignment of individual BDs. This function will enforce a minimum alignment of XAXIDMA_BD_MINIMUM_ALIGNMENT bytes with no maximum as long as it is specified as a power of 2. </td></tr>
+    <tr><td class="paramname">BdCount</td><td>is the number of BDs to setup in the application memory region. It is assumed the region is large enough to contain the BDs.Refer to the "SGDMA Ring Creation" section in <a class="el" href="xaxidma_8h.html">xaxidma.h</a> for more information. The minimum valid value for this parameter is 1.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if initialization was successful<ul>
+<li>XST_NO_FEATURE if the provided instance is a non SGDMA type of DMA channel.</li>
+</ul>
+</li>
+<li>XST_INVALID_PARAM under any of the following conditions: 1) BdCount is not positive</li>
+</ul>
+</dd></dl>
+<p>2) PhysAddr and/or VirtAddr are not aligned to the given Alignment parameter;</p>
+<p>3) Alignment parameter does not meet minimum requirements or is not a power of 2 value.</p>
+<ul>
+<li>XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans over address 0x00000000 in virtual address space.</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a2519fd626856e7ab0d822adc46aab7d8">XAxiDma_BdRing::BdaRestart</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing::FirstBdAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#add2c7d765c8d95eeb9d0f94a54775528">XAxiDma_BdRing::FirstBdPhysAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing::FreeHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing::HasStsCntrlStrm</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing::HwHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing::HwTail</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a3743d05f930d7c04abb0693f2ef0b271">XAxiDma_BdRing::LastBdAddr</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#af0b3fe5c9b9123209b3000e0d95193ed">XAxiDma_BdRing::Length</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing::PostCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing::PostHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing::PreHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing::Separation</a>, <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">XAXIDMA_BD_ADDRLEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">XAXIDMA_BD_HAS_DRE_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">XAXIDMA_BD_HAS_DRE_SHIFT</a>, <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">XAXIDMA_BD_MINIMUM_ALIGNMENT</a>, <a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">XAXIDMA_BD_NDESC_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">XAXIDMA_BD_NDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>, and <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">XAXIDMA_DESC_LSB_MASK</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaffa661a9a2467c1e274842c147531cea"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxiDma_BdRingDumpRegs </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Dump the registers for a channel. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">XAXIDMA_CDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">XAXIDMA_RX_TDESC0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">XAXIDMA_TDESC_OFFSET</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad2ac76e5a39486896cd484e51d2898c7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingFree </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>NumBd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Frees a set of BDs that had been previously retrieved with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">NumBd</td><td>is the number of BDs to free. </td></tr>
+    <tr><td class="paramname">BdSetPtr</td><td>is the head of a list of BDs returned by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the set of BDs was freed.</li>
+<li>XST_INVALID_PARAM if NumBd is negative</li>
+<li>XST_DMA_SG_LIST_ERROR if this function was called out of sequence with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> function call that modifies the BD space. It is the caller's responsibility to ensure mutual exclusion.</dd></dl>
+<p>This function can be used only when DMA is in SG mode </p>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing::PostCnt</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing::PostHead</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga1e5d328b4d4a247d1530fac3efe4c59c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingFromHw </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>BdLimit</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> **&#160;</td>
+          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Returns a set of BD(s) that have been processed by hardware. </p>
+<p>The returned BDs may be examined by the application to determine the outcome of the DMA transactions. Once the BDs have been examined, the application must call <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a> in the same order which they were retrieved here.</p>
+<p>Example:</p>
+<pre>
+       NumBd = XAxiDma_BdRingFromHw(MyRingPtr, XAXIDMA_ALL_BDS, &amp;MyBdSet);</pre><pre>       if (NumBd == 0)
+       {
+          // hardware has nothing ready for us yet
+       }</pre><pre>       CurBd = MyBdSet;
+       for (i=0; i&lt;NumBd; i++)
+       {
+          // Examine CurBd for post processing.....</pre><pre>          // Onto next BD
+          CurBd = <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext(MyRingPtr, CurBd)</a>;
+       }</pre><pre>       XAxiDma_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return the list
+</pre><p>A more advanced use of this function may allocate multiple sets of BDs. They must be retrieved from hardware and freed in the correct sequence: </p><pre>
+       // Legal
+       XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &amp;MySet1);
+       XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);</pre><pre>       // Legal
+       XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &amp;MySet1);
+       XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &amp;MySet2);
+       XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
+       XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);</pre><pre>       // Not legal
+       XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &amp;MySet1);
+       XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &amp;MySet2);
+       XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);
+       XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
+</pre><p>If hardware has partially completed a packet spanning multiple BDs, then none of the BDs for that packet will be included in the results.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">BdLimit</td><td>is the maximum number of BDs to return in the set. Use XAXIDMA_ALL_BDS to return all BDs that have been processed. </td></tr>
+    <tr><td class="paramname">BdSetPtr</td><td>is an output parameter, it points to the first BD available for examination.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The number of BDs processed by hardware. A value of 0 indicates that no data is available. No more than BdLimit BDs will be returned.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Treat BDs returned by this function as read-only.</dd></dl>
+<p>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</p>
+<p>This function can be used only when DMA is in SG mode </p>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing::HwHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing::HwTail</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing::IsRxChannel</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing::PostCnt</a>, <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">XAXIDMA_BD_CTRL_TXEOF_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga91b0504c621f6c06b0df4752fe65ee3a">XAXIDMA_BD_STS_RXEOF_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">XAxiDma_BdRingNext</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga0d3794bbccf028da8e94407d061dfc68"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxiDma_BdRingGetCoalesce </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32 *&#160;</td>
+          <td class="paramname"><em>CounterPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32 *&#160;</td>
+          <td class="paramname"><em>TimerPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Retrieve current interrupt coalescing parameters from the given descriptor ring channel. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">CounterPtr</td><td>points to a memory location where the current packet counter will be written. </td></tr>
+    <tr><td class="paramname">TimerPtr</td><td>points to a memory location where the current waitbound timer will be written.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The passed in parameters, CounterPtr and TimerPtr, holds the references to the return values.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">XAXIDMA_COALESCE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">XAXIDMA_DELAY_MASK</a>, and <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaaebba5c661e04485582e887e74dbeb94"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingSetCoalesce </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Counter</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Timer</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Set interrupt coalescing parameters for the given descriptor ring channel. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">Counter</td><td>sets the packet counter on the channel. Valid range is<ul>
+<li>1..255.</li>
+<li>XAXIDMA_NO_CHANGE to leave this setting unchanged. </li>
+</ul>
+</td></tr>
+    <tr><td class="paramname">Timer</td><td>sets the waitbound timer on the channel. Valid range is<ul>
+<li>0..255.</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<ul>
+<li>XAXIDMA_NO_CHANGE to leave this setting unchanged. Each unit depend on hardware building parameter C_DLYTMR_RESOLUTION,which is in the range from 0 to 100,000 clock cycles. A value of 0 disables the delay interrupt.</li>
+</ul>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if interrupt coalescing settings updated</li>
+<li>XST_FAILURE if Counter or Timer parameters are out of range</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">XAXIDMA_COALESCE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">XAXIDMA_DELAY_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaafd18a1df185c30b4745c147e3295ac3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingStart </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed. </p>
+<p>After a DMA channel is started, it is not halted, and it is idle (no active DMA transfers).</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the Channel instance to be worked on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS upon success</li>
+<li>XST_DMA_ERROR if no valid BD available to put into current BD register</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaac81111b373e373be7dd3989fffffe7b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingToHw </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>NumBd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Enqueue a set of BDs to hardware that were previously allocated by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>. </p>
+<p>Once this function returns, the argument BD set goes under hardware control. Changes to these BDs should be held until they are finished by hardware to avoid data corruption and system instability.</p>
+<p>For transmit, the set will be rejected if the last BD of the set does not mark the end of a packet or the first BD does not mark the start of a packet.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">NumBd</td><td>is the number of BDs in the set. </td></tr>
+    <tr><td class="paramname">BdSetPtr</td><td>is the first BD of the set to commit to hardware.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the set of BDs was accepted and enqueued to hardware</li>
+<li>XST_INVALID_PARAM if passed in NumBd is negative</li>
+<li>XST_FAILURE if the set of BDs was rejected because the first BD does not have its start-of-packet bit set, or the last BD does not have its end-of-packet bit set, or any one of the BDs has 0 length.</li>
+<li>XST_DMA_SG_LIST_ERROR if this function was called out of sequence with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a></li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</dd></dl>
+<p>This function can be used only when DMA is in SG mode </p>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing::HwTail</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing::IsRxChannel</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing::PreHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">XAXIDMA_BD_CTRL_TXEOF_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">XAXIDMA_BD_CTRL_TXSOF_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">XAxiDma_BdGetCtrl</a>, <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0">XAxiDma_BdGetLength</a>, <a class="el" href="group__axidma__v9__0.html#gaf2448f2b2ac172da0d19adeae3cc4c48">XAxiDma_BdGetSts</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">XAxiDma_BdRingNext</a>, <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>, <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">XAXIDMA_DESC_LSB_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">XAXIDMA_RX_TDESC0_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">XAXIDMA_RX_TDESC0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">XAXIDMA_TDESC_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">XAXIDMA_TDESC_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac58b1ab7a89890142baf67211772d3ce"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRingUnAlloc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>NumBd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Fully or partially undo an <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> operation. </p>
+<p>Use this function if all the BDs allocated by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> could not be transferred to hardware with <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a>.</p>
+<p>This function releases the BDs after they have been allocated but before they have been given to hardware.</p>
+<p>This function is not the same as <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a>. The Free function returns BDs to the free list after they have been processed by hardware, while UnAlloc returns them before being processed by hardware.</p>
+<p>There are two scenarios where this function can be used. Full UnAlloc or Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:</p>
+<pre>
+   Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &amp;BdPtr);
+       ...
+       ...
+   if (Error)
+   {
+       Status = XAxiDma_BdRingUnAlloc(MyRingPtr, 10, &amp;BdPtr);
+   }
+</pre><p>A partial UnAlloc means some of the BDs Alloc'd will be returned:</p>
+<pre>
+   Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &amp;BdPtr);
+   BdsLeft = 10;
+   CurBdPtr = BdPtr;</pre><pre>   while (BdsLeft)
+   {
+      if (Error)
+      {
+         Status = XAxiDma_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr);
+      }</pre><pre>      CurBdPtr = <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext(MyRingPtr, CurBdPtr)</a>;
+      BdsLeft--;
+   }
+</pre><p>A partial UnAlloc must include the last BD in the list that was Alloc'd.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
+    <tr><td class="paramname">NumBd</td><td>is the number of BDs to unallocate </td></tr>
+    <tr><td class="paramname">BdSetPtr</td><td>points to the first of the BDs to be returned.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the BDs were unallocated.</li>
+<li>XST_INVALID_PARAM if passed in NumBd is negative</li>
+<li>XST_FAILURE if NumBd parameter was greater that the number of BDs in the preprocessing state.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</dd></dl>
+<p>This function can be used only when DMA is in SG mode </p>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing::FreeHead</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gafc6434a23594c20c2b601f010a979e48"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdSetAppWord </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Offset</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Word</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Set the APP word at the specified APP word offset for a BD. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
+    <tr><td class="paramname">Offset</td><td>is the offset inside the APP word, it is valid from 0 to 4 </td></tr>
+    <tr><td class="paramname">Word</td><td>is the value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS for success</li>
+<li>XST_INVALID_PARAM under following error conditions: 1) StsCntrlStrm is not built in hardware 2) Offset is not in valid range</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>If the hardware build has C_SG_USE_STSAPP_LENGTH set to 1, then the last APP word, XAXIDMA_LAST_APPWORD, must have non-zero value when AND with 0x7FFFFF. Not doing so will cause the hardware to stall. This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">XAXIDMA_BD_USR0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac1a9cb01ba6cd686ee08245f5e08cb22"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdSetBufAddr </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">UINTPTR&#160;</td>
+          <td class="paramname"><em>Addr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Set the BD's buffer address. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">Addr</td><td>is the address to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if buffer address set successfully</li>
+<li>XST_INVALID_PARAM if hardware has no DRE and address is not aligned</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">XAXIDMA_BD_ADDRLEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">XAXIDMA_BD_BUFA_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">XAXIDMA_BD_HAS_DRE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">XAXIDMA_BD_HAS_DRE_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">XAXIDMA_BD_WORDLEN_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8947514b5acfea6298d0f969f3d2b97e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdSetBufAddrMicroMode </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">UINTPTR&#160;</td>
+          <td class="paramname"><em>Addr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Set the BD's buffer address when configured for Micro Mode. </p>
+<p>The buffer address should be 4K aligned.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
+    <tr><td class="paramname">Addr</td><td>is the address to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if buffer address set successfully</li>
+<li>XST_INVALID_PARAM if hardware has no DRE and address is not aligned</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">XAXIDMA_BD_ADDRLEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">XAXIDMA_BD_BUFA_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>, and <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">XAXIDMA_MICROMODE_MIN_BUF_ALIGN</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga4eb2615ac89054e982c3f3c37f0ddb52"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxiDma_BdSetCtrl </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Data</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Set the control bits for a BD. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
+    <tr><td class="paramname">Data</td><td>is the bit value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga4056035d8e7c90a68fa954c60d021e07"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdSetLength </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>LenBytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>LengthMask</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Set the length field for the given BD. </p>
+<p>Length has to be non-zero and less than LengthMask.</p>
+<p>For TX channels, the value passed in should be the number of bytes to transmit from the TX buffer associated with the given BD.</p>
+<p>For RX channels, the value passed in should be the size of the RX buffer associated with the given BD in bytes. This is to notify the RX channel the capability of the RX buffer to avoid buffer overflow.</p>
+<p>The actual receive length can be equal or smaller than the specified length. The actual transfer length will be updated by the hardware in the XAXIDMA_BD_STS_OFFSET word in the BD.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
+    <tr><td class="paramname">LenBytes</td><td>is the requested transfer length </td></tr>
+    <tr><td class="paramname">LengthMask</td><td>is the maximum transfer length</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS for success</li>
+<li>XST_INVALID_PARAM for invalid BD length</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaff68c0ba3e9e25dfe5e39153301862f8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_Busy </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Direction</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>This function checks whether specified DMA channel is busy. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on</td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>- TRUE if channel is busy<ul>
+<li>FALSE if channel is idle</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8026e76c90d891d21c9c355ff776cb77"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_CfgInitialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a> *&#160;</td>
+          <td class="paramname"><em>Config</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>This function initializes a DMA engine. </p>
+<p>This function must be called prior to using a DMA engine. Initializing a engine includes setting up the register base address, setting up the instance data, and ensuring the hardware is in a quiescent state.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on. </td></tr>
+    <tr><td class="paramname">Config</td><td>is a pointer to an <a class="el" href="struct_x_axi_dma___config.html" title="The configuration structure for AXI DMA engine. ">XAxiDma_Config</a> structure. It contains the information about the hardware build, including base address,and whether status control stream (StsCntrlStrm), MM2S and S2MM are included in the build.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS for successful initialization</li>
+<li>XST_INVALID_PARAM if pointer to the configuration structure is NULL</li>
+<li>XST_DMA_ERROR if reset operation failed at the end of initialization</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>We assume the hardware building tool will check and error out for a hardware build that has no transfer channels. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma::AddrWidth</a>, <a class="el" href="struct_x_axi_dma___config.html#a6fc1c26fb40944182ff84e370e667eb0">XAxiDma_Config::AddrWidth</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing::HasStsCntrlStrm</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing::IsRxChannel</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">XAXIDMA_TX_OFFSET</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga53983f629aba5b4ebf27f803a7a9284e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxiDma_DumpBd </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a> *&#160;</td>
+          <td class="paramname"><em>BdPtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>
+
+<p>Dump the fields of a BD. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">XAXIDMA_BD_HAS_DRE_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">XAXIDMA_BD_NDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">XAXIDMA_BD_USR0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga7d9d62be0e0ed11b18f185b62dc72f67">XAXIDMA_BD_USR1_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gadc83ff22099fdf61a5237965ce082504">XAXIDMA_BD_USR2_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gae1c5981447fe5ac113a6da3c1e19d6ed">XAXIDMA_BD_USR3_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga1ccae584923d0b6d0851a8bbae4528c9">XAXIDMA_BD_USR4_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga0cbcf5259635ea3c336fe5413c98f75c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a> * XAxiDma_LookupConfig </td>
+          <td>(</td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>DeviceId</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>Look up the hardware configuration for a device instance. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device to lookup for</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadb572b623215a7df62b1e0468e3bd68c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_Pause </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>Pause DMA transactions on both channels. </p>
+<p>If the engine is running and doing transfers, this function does not stop the DMA transactions immediately, because then hardware will throw away our previously queued transfers. All submitted transfers will finish. Transfers submitted after this function will not start until <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a> or <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574" title="Resume DMA transactions on both channels. ">XAxiDma_Resume()</a> is called.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if successful</li>
+<li>XST_NOT_SGDMA, if the driver instance is not initialized</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">XAXIDMA_CR_RUNSTOP_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">XAxiDma_GetRxIndexRing</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga5b7d1248ef065915fd8c9e8d5e00640f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxiDma_Reset </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>Reset both TX and RX channels of a DMA engine. </p>
+<p>Reset one channel resets the whole AXI DMA engine.</p>
+<p>Any DMA transaction in progress will finish gracefully before engine starts reset. Any other transactions that have been submitted to hardware will be discarded by the hardware.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>After the reset:<ul>
+<li>All interrupts are disabled.</li>
+<li>Engine is halted </li>
+</ul>
+</dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">XAxiDma_BdRingSnapShotCurrBd</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">XAXIDMA_CR_RESET_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">XAxiDma_GetRxIndexRing</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">XAXIDMA_TX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, and <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">XAxiDma_Selftest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaf73e1329e40c8ac1ae47a7d9c104af75"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_ResetIsDone </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>Check whether reset is done. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>1 if reset is done.</li>
+</ul>
+</dd></dl>
+<ul>
+<li>0 if reset is not done</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">XAXIDMA_CR_RESET_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">XAxiDma_GetRxRing</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, and <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, and <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">XAxiDma_Selftest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga847cd9a0255fcb444bce58b945de8574"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_Resume </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>Resume DMA transactions on both channels. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS for success</li>
+<li>XST_NOT_SGDMA if the driver instance has not been initialized</li>
+<li>XST_DMA_ERROR if one of the channels fails to start</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart()</a>, <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">XAxiDma_GetRxIndexRing</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, and <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga2d93bfcf1c3e34cb9fc4a22da6148dc5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_SelectCyclicMode </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Direction</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Select</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>This function Enable or Disable Cyclic Mode Feature. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on</td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.  Select is the option to enable (TRUE) or disable (FALSE).</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>- XST_SUCCESS for success</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">XAXIDMA_CR_CYCLIC_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga5becc8b0f9945af34e372ced2b37aebb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_SelectKeyHole </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Direction</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Select</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>This function Enable or Disable KeyHole Feature. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on</td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.  Select is the option to enable (TRUE) or disable (FALSE).</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>- XST_SUCCESS for success</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">XAXIDMA_CR_KEYHOLE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad4ea3039216916336ae1c7598ff26afc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_Selftest </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
+
+<p>Runs a self-test on the driver/device. </p>
+<p>This test perform a reset of the DMA device and checks the device is coming out of reset or not</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if self-test was successful</li>
+</ul>
+</dd></dl>
+<ul>
+<li>XST_FAILURE if the device is not coming out of reset.</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, and <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga32ca6099d7926297a4c17cdb4a19511b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_SimpleTransfer </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">UINTPTR&#160;</td>
+          <td class="paramname"><em>BuffAddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Length</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Direction</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>
+
+<p>This function does one simple transfer submission. </p>
+<p>It checks in the following sequence:</p><ul>
+<li>if engine is busy, cannot submit</li>
+<li>if engine is in SG mode , cannot submit</li>
+</ul>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is the pointer to the driver instance </td></tr>
+    <tr><td class="paramname">BuffAddr</td><td>is the address of the source/destination buffer </td></tr>
+    <tr><td class="paramname">Length</td><td>is the length of the transfer </td></tr>
+    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
+<li>XAXIDMA_DMA_TO_DEVICE.</li>
+<li>XAXIDMA_DEVICE_TO_DMA.</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS for success of submission</li>
+<li>XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going</li>
+<li>XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function is used only when system is configured as Simple mode. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma::AddrWidth</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#gaa7ede468ba17bf106101d4850184dc74">XAXIDMA_BUFFLEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">XAXIDMA_CR_RUNSTOP_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga3a54e372851dbae81c33997ef2ba8d2f">XAXIDMA_DESTADDR_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga4e98e82ed389c23918315d833b457ea9">XAXIDMA_DESTADDR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">XAXIDMA_HALTED_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>, <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">XAXIDMA_MICROMODE_MIN_BUF_ALIGN</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gafaafc49751e690d818d604efe368c481">XAXIDMA_SRCADDR_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga386fad6446792679302b362ed34022cf">XAXIDMA_SRCADDR_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga7b38bc9220c391823219937580bd816f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_StartBdRingHw </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed. </p>
+<p>After a DMA channel is started, it is not halted, and it is idle (no active DMA transfers).</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the Channel instance to be worked on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS upon success</li>
+<li>XST_DMA_ERROR if no valid BD available to put into current BD register</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing::HwTail</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing::IsRxChannel</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">XAXIDMA_CR_RUNSTOP_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">XAXIDMA_DESC_LSB_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">XAXIDMA_RX_TDESC0_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">XAXIDMA_RX_TDESC0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">XAXIDMA_TDESC_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">XAXIDMA_TDESC_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga39ee7d89e4453276d615849acad27fde"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_UpdateBdRingCDesc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
+          <td class="paramname"><em>RingPtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>
+
+<p>Update Current Descriptor. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">RingPtr</td><td>is the Channel instance to be worked on</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS upon success</li>
+<li>XST_DMA_ERROR if no valid BD available to put into current BD register</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>
+
+<p>References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a2519fd626856e7ab0d822adc46aab7d8">XAxiDma_BdRing::BdaRestart</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing::IsRxChannel</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421">XAxiDma_BdHwCompleted</a>, <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>, <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">XAxiDma_BdRingNext</a>, <a class="el" href="group__axidma__v9__0.html#ga00ee7a235750d8795961223455407051">XAXIDMA_CDESC_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">XAXIDMA_CDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">XAXIDMA_DESC_LSB_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gad80414a88feceb1da4b9f77096d1d590">XAXIDMA_RX_CDESC0_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
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+</html>
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
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+<div class="title">axidma_v9_0 Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>This is the driver API for the AXI DMA engine.For a full description of DMA features, please see the hardware spec. This driver supports the following features:</p>
+<ul>
+<li>Scatter-Gather DMA (SGDMA)</li>
+<li>Simple DMA</li>
+<li>Interrupts</li>
+<li>Programmable interrupt coalescing for SGDMA</li>
+<li>APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA engine</li>
+</ul>
+<p><b>Simple DMA</b></p>
+<p>Simple DMA allows the application to define a single transaction between DMA and Device. It has two channels: one from the DMA to Device and the other from Device to DMA. Application has to set the buffer address and length fields to initiate the transfer in respective channel.</p>
+<p><b>Transactions</b></p>
+<p>The object used to describe a transaction is referred to as a Buffer Descriptor (BD). Buffer descriptors are allocated in the user application. The user application needs to set buffer address, transfer length, and control information for this transfer. The control information includes SOF and EOF. Definition of those masks are in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a></p>
+<p><b>Scatter-Gather DMA</b></p>
+<p>SGDMA allows the application to define a list of transactions in memory which the hardware will process without further application intervention. During this time, the application is free to continue adding more work to keep the Hardware busy.</p>
+<p>User can check for the completion of transactions through polling the hardware, or interrupts.</p>
+<p>SGDMA processes whole packets. A packet is defined as a series of data bytes that represent a message. SGDMA allows a packet of data to be broken up into one or more transactions. For example, take an Ethernet IP packet which consists of a 14 byte header followed by a 1 or more bytes of payload. With SGDMA, the application may point a BD to the header and another BD to the payload, then transfer them as a single message. This strategy can make a TCP/IP stack more efficient by allowing it to keep packet header and data in different memory regions instead of assembling packets into contiguous blocks of memory.</p>
+<p><b>BD Ring Management</b></p>
+<p>BD rings are shared by the software and the hardware.</p>
+<p>The hardware expects BDs to be setup as a linked list. The DMA hardware walks through the list by following the next pointer field of a completed BD. The hardware stops processing when the just completed BD is the same as the BD specified in the Tail Ptr register in the hardware.</p>
+<p>The last BD in the ring is linked to the first BD in the ring.</p>
+<p>All BD management are done inside the driver. The user application should not directly modify the BD fields. Modifications to the BD fields should always go through the specific API functions.</p>
+<p>Within the ring, the driver maintains four groups of BDs. Each group consists of 0 or more adjacent BDs:</p>
+<ul>
+<li>Free: The BDs that can be allocated by the application with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>.</li>
+<li>Pre-process: The BDs that have been allocated with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>. These BDs are under application control. The application modifies these BDs through driver API to prepare them for DMA transactions.</li>
+<li>Hardware: The BDs that have been enqueued to hardware with <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a>. These BDs are under hardware control and may be in a state of awaiting hardware processing, in process, or processed by hardware. It is considered an error for the application to change BDs while they are in this group. Doing so can cause data corruption and lead to system instability.</li>
+<li>Post-process: The BDs that have been processed by hardware and have been extracted from the Hardware group with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>. These BDs are under application control. The application can check the transfer status of these BDs. The application use <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a> to put them into the Free group.</li>
+</ul>
+<p>BDs are expected to transition in the following way for continuous DMA transfers: </p><pre></pre><pre>        <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>                   <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a>
+  Free ------------------------&gt; Pre-process ----------------------&gt; Hardware
+                                                                     |
+   /|\                                                               |
+    |   <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a>                  <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a> |
+    +--------------------------- Post-process &lt;----------------------+</pre><pre></pre><p>When a DMA transfer is to be cancelled before enqueuing to hardware, application can return the requested BDs to the Free group using <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce" title="Fully or partially undo an XAxiDma_BdRingAlloc() operation. ">XAxiDma_BdRingUnAlloc()</a>, as shown below: </p><pre></pre><pre>        <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce" title="Fully or partially undo an XAxiDma_BdRingAlloc() operation. ">XAxiDma_BdRingUnAlloc()</a>
+  Free &lt;----------------------- Pre-process</pre><pre></pre><p>The API provides functions for BD list traversal:</p><ul>
+<li><a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext()</a></li>
+<li><a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a" title="Return the previous BD in the ring. ">XAxiDma_BdRingPrev()</a></li>
+</ul>
+<p>These functions should be used with care as they do not understand where one group ends and another begins.</p>
+<p><b>SGDMA Descriptor Ring Creation</b></p>
+<p>BD ring is created using <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>. The memory for the BD ring is allocated by the application, and it has to be contiguous. Physical address is required to setup the BD ring.</p>
+<p>The applicaiton can use <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9" title="Use this macro at initialization time to determine how many bytes of memory are required to contain a...">XAxiDma_BdRingMemCalc()</a> to find out the amount of memory needed for a certain number of BDs. <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b" title="Use this macro at initialization time to determine how many BDs will fit within the given memory cons...">XAxiDma_BdRingCntCalc()</a> can be used to find out how many BDs can be allocated for certain amount of memory.</p>
+<p>A helper function, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b" title="Clone the given BD into every BD in the ring. ">XAxiDma_BdRingClone()</a>, can speed up the BD ring setup if the BDs have same types of controls, for example, SOF and EOF. After using the <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b" title="Clone the given BD into every BD in the ring. ">XAxiDma_BdRingClone()</a>, the application only needs to setup the buffer address and transfer length. Note that certain BDs in one packet, for example, the first BD and the last BD, may need to setup special control information.</p>
+<p><b>Descriptor Ring State Machine</b></p>
+<p>There are two states of the BD ring:</p>
+<ul>
+<li>HALTED (H), where hardware is not running</li>
+<li>NOT HALTED (NH), where hardware is running</li>
+</ul>
+<p>The following diagram shows the state transition for the DMA engine:</p>
+<pre>
+  _____ <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f" title="Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are read...">XAxiDma_StartBdRingHw()</a>, or <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>,   ______
+  |   |               or <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574" title="Resume DMA transactions on both channels. ">XAxiDma_Resume()</a>                    |    |
+  | H |-----------------------------------------------------&gt;| NH |
+  |   |&lt;-----------------------------------------------------|    |
+  -----   <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c" title="Pause DMA transactions on both channels. ">XAxiDma_Pause()</a> or <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f" title="Reset both TX and RX channels of a DMA engine. ">XAxiDma_Reset()</a>                 ------
+</pre><p><b>Interrupt Coalescing</b></p>
+<p>SGDMA provides control over the frequency of interrupts through interrupt coalescing. The DMA engine provides two ways to tune the interrupt coalescing:</p>
+<ul>
+<li>The packet threshold counter. Interrupt will fire once the programmable number of packets have been processed by the engine.</li>
+<li>The packet delay timer counter. Interrupt will fire once the programmable amount of time has passed after processing the last packet, and no new packets to process. Note that the interrupt will only fire if at least one packet has been processed.</li>
+</ul>
+<p><b> Interrupt </b></p>
+<p>Interrupts are handled by the user application. Each DMA channel has its own interrupt ID. The driver provides APIs to enable/disable interrupt, and tune the interrupt frequency regarding to packet processing frequency.</p>
+<p><b> Software Initialization </b></p>
+<p>To use the Simple mode DMA engine for transfers, the following setup is required:</p>
+<ul>
+<li>DMA Initialization using <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77" title="This function initializes a DMA engine. ">XAxiDma_CfgInitialize()</a> function. This step initializes a driver instance for the given DMA engine and resets the engine.</li>
+<li>Enable interrupts if chosen to use interrupt mode. The application is responsible for setting up the interrupt system, which includes providing and connecting interrupt handlers and call back functions, before enabling the interrupts.</li>
+<li>Set the buffer address and length field in respective channels to start the DMA transfer</li>
+</ul>
+<p>To use the SG mode DMA engine for transfers, the following setup are required:</p>
+<ul>
+<li>DMA Initialization using <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77" title="This function initializes a DMA engine. ">XAxiDma_CfgInitialize()</a> function. This step initializes a driver instance for the given DMA engine and resets the engine.</li>
+<li>BD Ring creation. A BD ring is needed per DMA channel and can be built by calling <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>.</li>
+<li>Enable interrupts if chose to use interrupt mode. The application is responsible for setting up the interrupt system, which includes providing and connecting interrupt handlers and call back functions, before enabling the interrupts.</li>
+<li>Start a DMA transfer: Call <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a> to start a transfer for the first time or after a reset, and <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> if the channel is already started. Calling <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> when a DMA channel is not running will not put the BDs to the hardware, and the BDs will be processed later when the DMA channel is started through <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>.</li>
+</ul>
+<p><b> How to start DMA transactions </b></p>
+<p>The user application uses <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> to submit BDs to the hardware to start DMA transfers.</p>
+<p>For both channels, if the DMA engine is currently stopped (using <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c" title="Pause DMA transactions on both channels. ">XAxiDma_Pause()</a>), the newly added BDs will be accepted but not processed until the DMA engine is started, using <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>, or resumed, using <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574" title="Resume DMA transactions on both channels. ">XAxiDma_Resume()</a>.</p>
+<p><b> Software Post-Processing on completed DMA transactions </b></p>
+<p>If the interrupt system has been set up and the interrupts are enabled, a DMA channels notifies the software about the completion of a transfer through interrupts. Otherwise, the user application can poll for completions of the BDs, using <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a> or <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421" title="Check whether a BD has completed in hardware. ">XAxiDma_BdHwCompleted()</a>.</p>
+<ul>
+<li>Once BDs are finished by a channel, the application first needs to fetch them from the channel using <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.</li>
+<li>On the TX side, the application now could free the data buffers attached to those BDs as the data in the buffers has been transmitted.</li>
+<li>On the RX side, the application now could use the received data in the buffers attached to those BDs.</li>
+<li>For both channels, completed BDs need to be put back to the Free group using <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a>, so they can be used for future transactions.</li>
+<li>On the RX side, it is the application's responsibility to have BDs ready to receive data at any time. Otherwise, the RX channel refuses to accept any data if it has no RX BDs.</li>
+</ul>
+<p><b> Examples </b></p>
+<p>We provide five examples to show how to use the driver API:</p><ul>
+<li>One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer</li>
+<li>One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.</li>
+<li>One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer</li>
+<li>One for simple polling mode (xaxidma_example_simple_poll.c)</li>
+<li>One for simple Interrupt mode (xaxidma_example_simple_intr.c)</li>
+</ul>
+<p><b> Address Translation </b></p>
+<p>All buffer addresses and BD addresses for the hardware are physical addresses. The user application is responsible to provide physical buffer address for the BD upon BD ring creation. The user application accesses BD through its virtual addess. The driver maintains the address translation between the physical and virtual address for BDs.</p>
+<p><b> Cache Coherency </b></p>
+<p>This driver expects all application buffers attached to BDs to be in cache coherent memory. If cache is used in the system, buffers for transmit MUST be flushed from the cache before passing the associated BD to this driver. Buffers for receive MUST be invalidated before accessing the data.</p>
+<p><b> Alignment </b></p>
+<p>For BDs:</p>
+<p>Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT. This is the smallest alignment allowed by both hardware and software for them to properly work.</p>
+<p>If the descriptor ring is to be placed in cached memory, alignment also MUST be at least the processor's cache-line size. Otherwise, system instability occurs. For alignment larger than the cache line size, multiple cache line size alignment is required.</p>
+<p>Aside from the initial creation of the descriptor ring (see <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>), there are no other run-time checks for proper alignment of BDs.</p>
+<p>For application data buffers:</p>
+<p>Application data buffers may reside on any alignment if DRE is built into the hardware. Otherwise, application data buffer must be word-aligned. The word is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.</p>
+<p>For scatter gather transfers that have more than one BDs in the chain of BDs, Each BD transfer length must be multiple of word too. Otherwise, internal error happens in the hardware.</p>
+<p><b> Error Handling </b></p>
+<p>The DMA engine will halt on all error conditions. It requires the software to do a reset before it can start process new transfer requests.</p>
+<p><b> Restart After Stopping </b></p>
+<p>After the DMA engine has been stopped (through reset or reset after an error) the software keeps track of the current BD pointer when reset happens, and processing of BDs can be resumed through <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>.</p>
+<p><b> Limitations </b></p>
+<p>This driver does not have any mechanisms for mutual exclusion. It is up to the application to provide this protection.</p>
+<p><b> Hardware Defaults &amp; Exclusive Use </b></p>
+<p>After the initialization or reset, the DMA engine is in the following default mode:</p><ul>
+<li>All interrupts are disabled.</li>
+<li>Interrupt coalescing counter is 1.</li>
+<li>The DMA engine is not running (halted). Each DMA channel is started separately, using <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f" title="Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are read...">XAxiDma_StartBdRingHw()</a> if no BDs are setup for transfer yet, or <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a> otherwise.</li>
+</ul>
+<p>The driver has exclusive use of the registers and BDs. All accesses to the registers and BDs should go through the driver interface.</p>
+<p><b> Debug Print </b></p>
+<p>To see the debug print for the driver, please put "-DDEBUG" as the extra compiler flags in software platform settings. Also comment out the line in xdebug.h: "#undef DEBUG".</p>
+<p><b>Changes From v1.00a</b></p>
+<p>. We have changes return type for <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22" title="Set the BD&#39;s buffer address. ">XAxiDma_BdSetBufAddr()</a> from void to int . We added <a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c" title="Look up the hardware configuration for a device instance. ">XAxiDma_LookupConfig()</a> so that user does not need to look for the hardware settings anymore.</p>
+<pre>
+MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
+----- ---- -------- -------------------------------------------------------
+1.00a jz   05/18/10 First release
+2.00a jz   08/10/10 Second release, added in <a class="el" href="xaxidma__g_8c.html">xaxidma_g.c</a>, <a class="el" href="xaxidma__sinit_8c.html">xaxidma_sinit.c</a>,
+                    updated tcl file, added <a class="el" href="xaxidma__porting__guide_8h.html">xaxidma_porting_guide.h</a>
+3.00a jz   11/22/10 Support IP core parameters change
+4.00a rkv  02/22/11 Added support for simple DMA mode
+      	      New API added for simple DMA mode are</p><ul>
+<li>XAxiDma_Busy</li>
+<li>XAxiDma_SimpleTransfer
+      	      New Macros added for simple DMA mode are<ul>
+<li>XAxiDma_HasSg</li>
+<li>XAxiDma_IntrEnable</li>
+<li>XAxiDma_IntrGetEnabled</li>
+<li>XAxiDma_IntrDisable</li>
+<li>XAxiDma_IntrGetIrq</li>
+<li>XAxiDma_IntrAckIrq
+5.00a srt  08/25/11  Added support for memory barrier and modified
+      		Cache Macros to have a common API for Microblaze
+      		and Zynq.
+6.00a srt  01/24/12 Added support for Multi-Channel DMA mode.</li>
+</ul>
+</li>
+</ul>
+</pre><pre>Changed APIs:
+      		* <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5" title="Get Receive (Rx) Ring ptr. ">XAxiDma_GetRxRing(InstancePtr, RingIndex)</a>
+      		* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_SimpleTransfer(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> *InstancePtr,
+       					u32 BuffAddr, u32 Length,
+      					int Direction, int RingIndex)
+      		* XAxiDma_StartBdRingHw(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      				int RingIndex)
+      		* XAxiDma_BdRingStart(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					 int RingIndex)
+      		* XAxiDma_BdRingToHw(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+       			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+      		* XAxiDma_BdRingDumpRegs(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					 int RingIndex)
+      		* XAxiDma_BdRingSnapShotCurrBd(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					 int RingIndex)
+      		* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+      				u32 LenBytes, u32 LengthMask)
+      		* <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0" title="Get the actual transfer length of a BD. ">XAxiDma_BdGetActualLength(BdPtr, LengthMask)</a>
+      		* <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0" title="Retrieve the length field value from the given BD. ">XAxiDma_BdGetLength(BdPtr, LengthMask)</a></p><ul>
+<li>New APIs
+      		* XAxiDma_SelectKeyHole(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> *InstancePtr,
+      					int Direction, int Select)
+      		* XAxiDma_UpdateBdRingCDesc(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					int RingIndex)
+7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+      	       backward compatibility.<ul>
+<li>New API:
+      		  <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631" title="Get Receive (Rx) Ring ptr of a Index. ">XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)</a>
+7.01a srt  10/26/12  - Fixed issue with driver as it fails with IP version
+      	         &lt; 6.00a as the parameter C_NUM_*_CHANNELS is not
+      		 applicable.</li>
+</ul>
+</li>
+<li>Changed the logic of MCDMA BD fields Set APIs, to
+      		 clear the field first and then set it.
+7.02a srt  01/23/13  Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
+      	       (CR 691867)
+      	       Updated DDR base address for IPI designs (CR 703656).
+8.0   adk  19/12/13  Updated as per the New Tcl API's
+      srt  01/29/14  Added support for Micro DMA Mode and cyclic mode of
+      	       operations.</li>
+</ul>
+</pre><pre>New APIs:
+      		* XAxiDma_SelectCyclicMode(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> *InstancePtr,
+      					int Direction, int Select)
+			* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
+8.1   adk  20/01/15  Added support for peripheral test. Created the self
+      	       test example to include it on peripheral test's(CR#823144).
+8.1   adk  29/01/15  Added the sefltest api (XAxiDma_Selftest) to the driver source files
+		      (<a class="el" href="xaxidma__selftest_8c.html">xaxidma_selftest.c</a>) and called this from the selftest example
+9.0 	adk  27/07/15  Added support for 64-bit Addressing.
+9.0   adk  19/08/15  Fixed CR#873125 DMA SG Mode example tests are failing on
+      	       HW in 2015.3.</pre><pre></pre> </div></div><!-- contents -->
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+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/jquery.js b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/jquery.js
new file mode 100644
index 000000000..1f4d0b47c
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/jquery.js
@@ -0,0 +1,68 @@
+/*!
+ * jQuery JavaScript Library v1.7.1
+ * http://jquery.com/
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+ * Date: Mon Nov 21 21:11:03 2011 -0500
+ */
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+/*!
+ * Sizzle CSS Selector Engine
+ *  Copyright 2011, The Dojo Foundation
+ *  Released under the MIT, BSD, and GPL Licenses.
+ *  More information: http://sizzlejs.com/
+ */
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+ * jQuery UI 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI
+ */
+(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:"1.8.18",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e==="number"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css("overflow")==="hidden"){return false}var e=(f&&f==="left")?"scrollLeft":"scrollTop",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!
+ * jQuery UI Widget 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Widget
+ */
+(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!
+ * jQuery UI Mouse 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Mouse
+ *
+ * Depends:
+ *	jquery.ui.widget.js
+ */
+(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e=="sw"){h.left=j.left+(f.width-h.width);h.top=null}if(e=="nw"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css("borderTopWidth"),h.css("borderRightWidth"),h.css("borderBottomWidth"),h.css("borderLeftWidth")],j=[h.css("paddingTop"),h.css("paddingRight"),h.css("paddingBottom"),h.css("paddingLeft")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(":hidden")||c(g).parents(":hidden").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var 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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">APIs</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__axidma__v9__0.html" target="_self">Axidma_v9_0</a></td><td class="desc">This file implements DMA engine-wise initialization and control functions </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma.html
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+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: XAxiDma Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XAxiDma Struct Reference<div class="ingroups"><a class="el" href="group__axidma__v9__0.html">Axidma_v9_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>An instance must be allocated for each DMA engine in use. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a663f5757eabe6b1b8813ed5fdb0d0edb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma::AddrWidth</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Address Width. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, and <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma___bd_ring.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma___bd_ring.html
new file mode 100644
index 000000000..f3afc940d
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma___bd_ring.html
@@ -0,0 +1,398 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: XAxiDma_BdRing Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XAxiDma_BdRing Struct Reference<div class="ingroups"><a class="el" href="group__axidma__v9__0.html">Axidma_v9_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>If address translation is enabled, then all addresses and pointers excluding FirstBdPhysAddr are expressed in terms of the virtual address. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3c928d2f36e8daf845a70afdae2573a4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::AllCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Total Number of BDs for channel. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a2519fd626856e7ab0d822adc46aab7d8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::BdaRestart</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>BD to load when channel is started. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a138fd282802e5f6ed3cb1d2505ede08a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdRing::ChanBase</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>physical base address </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a6d41078607d5a8165e67d6483e40e9ab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::FirstBdAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Virtual address of 1st BD in list. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="add2c7d765c8d95eeb9d0f94a54775528"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::FirstBdPhysAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Physical address of 1st BD in list. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a51ec0929002582a900d404502e9a1622"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::FreeCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of allocatable BDs in free group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree()</a>, and <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3e067ffdf2820a816f2d6dda6e3f9114"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::FreeHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the free group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a7d35cb00bb50fff2e24c15f7d7d8dae0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::HasStsCntrlStrm</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Whether has stscntrl stream. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ab49406dd2d9ec65e3f38d1cc3c880391"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::HwCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of BDs in work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af097be199cf9d1d62cf32f775309a4f3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::HwHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a7abe8351de43377407c579cd158f2448"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::HwTail</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Last BD in the work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a912bf38e61c8b03995ece842426b3ccf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::IsRxChannel</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Is this a receive channel. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3743d05f930d7c04abb0693f2ef0b271"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::LastBdAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Virtual address of last BD in the list. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af0b3fe5c9b9123209b3000e0d95193ed"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdRing::Length</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Total size of ring in bytes. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="afd4e1620895f91a829354e131432d2b3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::PostCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of BDs in post-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree()</a>, and <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a92668e60e10a940428e68f816c64eab6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::PostHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the post-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a68e8042d227f7a40821a478deb063215"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::PreCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of BDs in pre-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8a2958fb6be370d3cc29972f57203952"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::PreHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the pre-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac14f09fcd00f1869c8194d790f73d791"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::RingIndex</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Ring Index. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a443e5c48e677e9a1a4e85a383eefc2be"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile int XAxiDma_BdRing::RunState</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Whether channel is running. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aafd8e01bf65c7950235d8f21cf225e12"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::Separation</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of bytes between the starting address of adjacent BDs. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma___config.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/struct_x_axi_dma___config.html
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+</table>
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+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
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+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XAxiDma_Config Struct Reference<div class="ingroups"><a class="el" href="group__axidma__v9__0.html">Axidma_v9_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>This structure passes the hardware building information to the driver </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a6fc1c26fb40944182ff84e370e667eb0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_Config::AddrWidth</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Address Width. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+<tr class="separator:gad4ea3039216916336ae1c7598ff26afc"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bd_8c.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bd_8c.html
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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: xaxidma_bd.c File Reference</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
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+<div id="titlearea">
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+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+ </tbody>
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+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
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+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_457bf2146d2f72d07796ff92ec9d3b09.html">axidma_v9_0</a></li><li class="navelem"><a class="el" href="dir_239ebfe70a102f9d662a37767b146b91.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxidma_bd.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bd_8h.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bd_8h.html
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: xaxidma_bd.h File Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_457bf2146d2f72d07796ff92ec9d3b09.html">axidma_v9_0</a></li><li class="navelem"><a class="el" href="dir_239ebfe70a102f9d662a37767b146b91.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxidma_bd.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bdring_8c.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bdring_8c.html
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+<title>axidma_v9_0: xaxidma_bdring.c File Reference</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_457bf2146d2f72d07796ff92ec9d3b09.html">axidma_v9_0</a></li><li class="navelem"><a class="el" href="dir_239ebfe70a102f9d662a37767b146b91.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxidma_bdring.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bdring_8h.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__bdring_8h.html
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+   <div id="projectname">axidma_v9_0
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+      <li><a href="globals.html"><span>APIs</span></a></li>
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_457bf2146d2f72d07796ff92ec9d3b09.html">axidma_v9_0</a></li><li class="navelem"><a class="el" href="dir_239ebfe70a102f9d662a37767b146b91.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
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+  <div class="summary">
+<a href="#nested-classes">Data Structures</a> &#124;
+<a href="#define-members">Macros</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxidma_bdring.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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+</table>
+</div><!-- contents -->
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+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__hw_8h.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__hw_8h.html
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_457bf2146d2f72d07796ff92ec9d3b09.html">axidma_v9_0</a></li><li class="navelem"><a class="el" href="dir_239ebfe70a102f9d662a37767b146b91.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">xaxidma_hw.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">DMA Transfer Direction</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor Alignment</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Micro DMA Buffer Address Alignment</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Maximum transfer length</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>This is determined by hardware </p>
+</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Register sets on TX and RX channels are identical </p>
+</div></td></tr>
+<tr class="memitem:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
+<tr class="separator:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_CR_OFFSET register</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_SR_OFFSET register</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts (note that interrupt masks are shared with XAXIDMA_CR_OFFSET register, and are defined in the _IRQ_ section.</p>
+<p>The interrupt coalescing threshold value and delay counter value are also shared with XAXIDMA_CR_OFFSET register, and are defined in a later section. </p>
+</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmask for interrupts</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register </p>
+</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmask and shift for delay and coalesce</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register </p>
+</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor offsets</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>USR* fields are defined by higher level IP.</p>
+<p>setup for EMAC type devices. The first 13 words are used by hardware. All words after the 13rd word are for software use only. </p>
+</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_BD_CTRL_OFFSET register</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmasks of XAXIDMA_BD_STS_OFFSET register</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register</div></td></tr>
+<tr class="memitem:ga99f615c527035db697545614fff86bf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">XAxiDma_ReadReg</a>(BaseAddress,  RegOffset)                      &#160;&#160;&#160;XAxiDma_In32((BaseAddress) + (RegOffset))</td></tr>
+<tr class="separator:ga99f615c527035db697545614fff86bf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga96d7b2834ae100f53627ca961393e9a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">XAxiDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)                &#160;&#160;&#160;XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
+<tr class="separator:ga96d7b2834ae100f53627ca961393e9a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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diff --git a/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__porting__guide_8h.html b/thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/xaxidma__porting__guide_8h.html
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+<a href="#func-members">Functions</a>  </div>
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+<div class="title">xaxidma_selftest.c File Reference</div>  </div>
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+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:gad4ea3039216916336ae1c7598ff26afc"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">XAxiDma_Selftest</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr)</td></tr>
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+</div>
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+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
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+<div class="title">xaxidma_sinit.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
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diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/index.html b/thirdparty/xilinx/orig/axidma_v9_0/examples/index.html
new file mode 100644
index 000000000..a0cd01662
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/index.html
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver axidma_v8_0 </h1>
+<HR>
+<ul>
+  <li>xaxidma_example_sg_intr.c <a href="xaxidma_example_sg_intr.c">(source)</a> </li>
+  <li>xaxidma_example_sg_poll.c <a href="xaxidma_example_sg_poll.c">(source)</a> </li>
+  <li>xaxidma_example_simple_intr.c <a href="xaxidma_example_simple_intr.c">(source)</a> </li>
+  <li>xaxidma_example_simple_poll.c <a href="xaxidma_example_simple_poll.c">(source)</a> </li>
+  <li>xaxidma_poll_multi_pkts.c <a href="xaxidma_poll_multi_pkts.c">(source)</a> </li>
+  <li>xaxidma_multichan_sg_intr.c <a href="xaxidma_multichan_sg_intr.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright � 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_selftest.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_selftest.c
new file mode 100644
index 000000000..023582dd5
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_selftest.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xdebug.h"
+
+/******************** Constant Definitions **********************************/
+
+/*
+ * Device hardware build related constants.
+ */
+
+ #ifndef TESTAPP_GEN
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+#endif
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int AxiDMASelfTestExample(u16 DeviceId);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XAxiDma AxiDma;
+
+
+/*****************************************************************************/
+/*
+* The entry point for this example. It invokes the example function,
+* and reports the execution status.
+*
+* @param	None.
+*
+* @return
+*		- XST_SUCCESS if example finishes successfully
+*		- XST_FAILURE if example fails.
+*
+* @note		None.
+*
+******************************************************************************/
+#ifndef TESTAPP_GEN
+int main()
+{
+	int Status;
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+
+	/* Run the poll example for simple transfer */
+	Status = AxiDMASelfTestExample(DMA_DEV_ID);
+
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("AxiDMASelfTestExample: Failed\r\n");
+		return XST_FAILURE;
+	}
+
+	xil_printf("AxiDMASelfTestExample: Passed\r\n");
+
+	xil_printf("--- Exiting main() --- \r\n");
+
+	return XST_SUCCESS;
+
+}
+#endif
+
+/*****************************************************************************/
+/*
+* This function performance a reset of the DMA device and checks the device is
+* coming out of reset or not.
+*
+* @param	DeviceId is the DMA device id.
+*
+* @return	- XST_SUCCESS if channel reset is successful
+*		- XST_FAILURE if channel reset fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int AxiDMASelfTestExample(u16 DeviceId)
+{
+	XAxiDma_Config *CfgPtr;
+	int Status = XST_SUCCESS;
+
+	CfgPtr = XAxiDma_LookupConfig(DeviceId);
+	if (!CfgPtr) {
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_Selftest(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return Status;
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_sg_intr.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_sg_intr.c
new file mode 100644
index 000000000..e1dc2117a
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_sg_intr.c
@@ -0,0 +1,1214 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_example_sg_intr.c
+ *
+ * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
+ * DMA core (AXIDMA) to transfer packets in interrupt mode when the AXIDMA
+ * core is configured in Scatter Gather Mode
+ *
+ * We show how to do multiple packets transfers, as well as how to do multiple
+ * BDs per packet transfers.
+ *
+ * This code assumes a loopback hardware widget is connected to the AXI DMA
+ * core for data packet loopback.
+ *
+ * To see the debug print, you need a Uart16550 or uartlite in your system,
+ * and please set "-DDEBUG" in your compiler options. You need to rebuild your
+ * software executable.
+ *
+ * Make sure that MEMORY_BASE is defined properly as per the HW system. The
+ * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
+ * throughput mode, it is 512MB.  These limits are need to ensured for
+ * proper operation of this code.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *		       		   updated tcl file, added xaxidma_porting_guide.h, removed
+ *		         	   workaround for endianness
+ * 4.00a rkv  02/22/11 Name of the file has been changed for naming consistency
+ *		       		   Added interrupt support for Zynq.
+ * 5.00a srt  03/05/12 Added Flushing and Invalidation of Caches to fix CRs
+ *		       		   648103, 648701.
+ *		       		   Added V7 DDR Base Address to fix CR 649405.
+ * 6.00a srt  01/24/12 Changed API calls to support MCDMA driver.
+ * 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+ * 7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
+ *		       DDR memory limit of the h/w system built with Area mode
+ * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+/***************************** Include Files *********************************/
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xdebug.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#ifndef DEBUG
+extern void xil_printf(const char *format, ...);
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #include "xintc.h"
+#else
+ #include "xscugic.h"
+#endif
+
+/******************** Constant Definitions **********************************/
+/*
+ * Device hardware build related constants.
+ */
+
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+			DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR		0x01000000
+#else
+#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define RX_INTR_ID		XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID
+#define TX_INTR_ID		XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID
+#else
+#define RX_INTR_ID		XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID
+#define TX_INTR_ID		XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID
+#endif
+
+#define RX_BD_SPACE_BASE	(MEM_BASE_ADDR)
+#define RX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x0000FFFF)
+#define TX_BD_SPACE_BASE	(MEM_BASE_ADDR + 0x00010000)
+#define TX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x0001FFFF)
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
+#else
+#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
+#endif
+
+/* Timeout loop counter for reset
+ */
+#define RESET_TIMEOUT_COUNTER	10000
+
+/*
+ * Buffer and Buffer Descriptor related constant definition
+ */
+#define MAX_PKT_LEN		0x100
+#define MARK_UNCACHEABLE        0x701
+
+/*
+ * Number of BDs in the transfer example
+ * We show how to submit multiple BDs for one transmit.
+ * The receive side gets one completion per transfer.
+ */
+#define NUMBER_OF_BDS_PER_PKT		12
+#define NUMBER_OF_PKTS_TO_TRANSFER 	11
+#define NUMBER_OF_BDS_TO_TRANSFER	(NUMBER_OF_PKTS_TO_TRANSFER * \
+						NUMBER_OF_BDS_PER_PKT)
+
+/* The interrupt coalescing threshold and delay timer threshold
+ * Valid range is 1 to 255
+ *
+ * We set the coalescing threshold to be the total number of packets.
+ * The receive side will only get one completion interrupt for this example.
+ */
+#define COALESCING_COUNT		NUMBER_OF_PKTS_TO_TRANSFER
+#define DELAY_TIMER_COUNT		100
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #define INTC		XIntc
+ #define INTC_HANDLER	XIntc_InterruptHandler
+#else
+ #define INTC		XScuGic
+ #define INTC_HANDLER	XScuGic_InterruptHandler
+#endif
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+static int CheckData(int Length, u8 StartValue);
+static void TxCallBack(XAxiDma_BdRing * TxRingPtr);
+static void TxIntrHandler(void *Callback);
+static void RxCallBack(XAxiDma_BdRing * RxRingPtr);
+static void RxIntrHandler(void *Callback);
+
+
+
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId);
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+					u16 TxIntrId, u16 RxIntrId);
+
+static int RxSetup(XAxiDma * AxiDmaInstPtr);
+static int TxSetup(XAxiDma * AxiDmaInstPtr);
+static int SendPacket(XAxiDma * AxiDmaInstPtr);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XAxiDma AxiDma;
+
+
+static INTC Intc;	/* Instance of the Interrupt Controller */
+
+/*
+ * Flags interrupt handlers use to notify the application context the events.
+ */
+volatile int TxDone;
+volatile int RxDone;
+volatile int Error;
+
+/*
+ * Buffer for transmit packet. Must be 32-bit aligned to be used by DMA.
+ */
+u32 *Packet = (u32 *) TX_BUFFER_BASE;
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the interrupt test. It does the following:
+*	- Set up the output terminal if UART16550 is in the hardware build
+*	- Initialize the DMA engine
+*	- Set up Tx and Rx channels
+*	- Set up the interrupt system for the Tx and Rx interrupts
+*	- Submit a transfer
+*	- Wait for the transfer to finish
+*	- Check transfer status
+*	- Disable Tx and Rx interrupts
+*	- Print test status and exit
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if tests pass
+*		- XST_FAILURE if fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+	XAxiDma_Config *Config;
+
+	/* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+#ifdef __aarch64__
+	Xil_SetTlbAttributes(TX_BD_SPACE_BASE, MARK_UNCACHEABLE);
+	Xil_SetTlbAttributes(RX_BD_SPACE_BASE, MARK_UNCACHEABLE);
+#endif
+
+	Config = XAxiDma_LookupConfig(DMA_DEV_ID);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DMA_DEV_ID);
+
+		return XST_FAILURE;
+	}
+
+	/* Initialize DMA engine */
+	XAxiDma_CfgInitialize(&AxiDma, Config);
+
+	if(!XAxiDma_HasSg(&AxiDma)) {
+		xil_printf("Device configured as Simple mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Set up TX/RX channels to be ready to transmit and receive packets */
+	Status = TxSetup(&AxiDma);
+
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed TX setup\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = RxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed RX setup\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Set up Interrupt system  */
+	Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed intr setup\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Initialize flags before start transfer test  */
+	TxDone = 0;
+	RxDone = 0;
+	Error = 0;
+
+	/* Send a packet */
+	Status = SendPacket(&AxiDma);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed send packet\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Wait TX done and RX done
+	 */
+	while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
+			(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
+		/* NOP */
+	}
+
+	if (Error) {
+		xil_printf("Failed test transmit%s done, "
+			"receive%s done\r\n", TxDone? "":" not",
+					RxDone? "":" not");
+
+		goto Done;
+
+	}else {
+
+		/*
+		 * Test finished, check data
+		 */
+		Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
+									0xC);
+		if (Status != XST_SUCCESS) {
+
+			xil_printf("Data check failed\r\n");
+
+			goto Done;
+		}
+
+		xil_printf("AXI DMA SG interrupt Test passed\r\n");
+	}
+
+	/* Disable TX and RX Ring interrupts and return success */
+
+	DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
+
+Done:
+
+	xil_printf("--- Exiting main() --- \r\n");
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This function checks data buffer after the DMA transfer is finished.
+*
+* We use the static tx/rx buffers.
+*
+* @param	Length is the length to check
+* @param	StartValue is the starting value of the first byte
+*
+* @return	- XST_SUCCESS if validation is successful
+*		- XST_FAILURE if validation fails.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckData(int Length, u8 StartValue)
+{
+	u8 *RxPacket;
+	int Index = 0;
+	u8 Value;
+
+	RxPacket = (u8 *) RX_BUFFER_BASE;
+	Value = StartValue;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+#ifndef __aarch64__
+	Xil_DCacheInvalidateRange((u32)RxPacket, Length);
+#endif
+
+	for(Index = 0; Index < Length; Index++) {
+		if (RxPacket[Index] != Value) {
+			xil_printf("Data error %d: %x/%x\r\n",
+			    Index, RxPacket[Index], Value);
+
+			return XST_FAILURE;
+		}
+		Value = (Value + 1) & 0xFF;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA TX callback function to be called by TX interrupt handler.
+* This function handles BDs finished by hardware.
+*
+* @param	TxRingPtr is a pointer to TX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void TxCallBack(XAxiDma_BdRing * TxRingPtr)
+{
+	int BdCount;
+	u32 BdSts;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	int Status;
+	int Index;
+
+	/* Get all processed BDs from hardware */
+	BdCount = XAxiDma_BdRingFromHw(TxRingPtr, XAXIDMA_ALL_BDS, &BdPtr);
+
+	/* Handle the BDs */
+	BdCurPtr = BdPtr;
+	for (Index = 0; Index < BdCount; Index++) {
+
+		/*
+		 * Check the status in each BD
+		 * If error happens, the DMA engine will be halted after this
+		 * BD processing stops.
+		 */
+		BdSts = XAxiDma_BdGetSts(BdCurPtr);
+		if ((BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
+		    (!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK))) {
+
+			Error = 1;
+			break;
+		}
+
+		/*
+		 * Here we don't need to do anything. But if a RTOS is being
+		 * used, we may need to free the packet buffer attached to
+		 * the processed BD
+		 */
+
+		/* Find the next processed BD */
+		BdCurPtr = XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
+	}
+
+	/* Free all processed BDs for future transmission */
+	Status = XAxiDma_BdRingFree(TxRingPtr, BdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		Error = 1;
+	}
+
+	if(!Error) {
+
+		TxDone += BdCount;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA TX Interrupt handler function.
+*
+* It gets the interrupt status from the hardware, acknowledges it, and if any
+* error happens, it resets the hardware. Otherwise, if a completion interrupt
+* presents, then it calls the callback function.
+*
+* @param	Callback is a pointer to TX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void TxIntrHandler(void *Callback)
+{
+	XAxiDma_BdRing *TxRingPtr = (XAxiDma_BdRing *) Callback;
+	u32 IrqStatus;
+	int TimeOut;
+
+	/* Read pending interrupts */
+	IrqStatus = XAxiDma_BdRingGetIrq(TxRingPtr);
+
+	/* Acknowledge pending interrupts */
+	XAxiDma_BdRingAckIrq(TxRingPtr, IrqStatus);
+
+	/* If no interrupt is asserted, we do not do anything
+	 */
+	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
+
+		return;
+	}
+
+	/*
+	 * If error interrupt is asserted, raise error flag, reset the
+	 * hardware to recover from the error, and return with no further
+	 * processing.
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
+
+		XAxiDma_BdRingDumpRegs(TxRingPtr);
+
+		Error = 1;
+
+		/*
+		 * Reset should never fail for transmit channel
+		 */
+		XAxiDma_Reset(&AxiDma);
+
+		TimeOut = RESET_TIMEOUT_COUNTER;
+
+		while (TimeOut) {
+			if (XAxiDma_ResetIsDone(&AxiDma)) {
+				break;
+			}
+
+			TimeOut -= 1;
+		}
+
+		return;
+	}
+
+	/*
+	 * If Transmit done interrupt is asserted, call TX call back function
+	 * to handle the processed BDs and raise the according flag
+	 */
+	if ((IrqStatus & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
+		TxCallBack(TxRingPtr);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA RX callback function called by the RX interrupt handler.
+* This function handles finished BDs by hardware, attaches new buffers to those
+* BDs, and give them back to hardware to receive more incoming packets
+*
+* @param	RxRingPtr is a pointer to RX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void RxCallBack(XAxiDma_BdRing * RxRingPtr)
+{
+	int BdCount;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	u32 BdSts;
+	int Index;
+
+	/* Get finished BDs from hardware */
+	BdCount = XAxiDma_BdRingFromHw(RxRingPtr, XAXIDMA_ALL_BDS, &BdPtr);
+
+	BdCurPtr = BdPtr;
+	for (Index = 0; Index < BdCount; Index++) {
+
+		/*
+		 * Check the flags set by the hardware for status
+		 * If error happens, processing stops, because the DMA engine
+		 * is halted after this BD.
+		 */
+		BdSts = XAxiDma_BdGetSts(BdCurPtr);
+		if ((BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
+		    (!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK))) {
+			Error = 1;
+			break;
+		}
+
+		/* Find the next processed BD */
+		BdCurPtr = XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+		RxDone += 1;
+	}
+
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA RX interrupt handler function
+*
+* It gets the interrupt status from the hardware, acknowledges it, and if any
+* error happens, it resets the hardware. Otherwise, if a completion interrupt
+* presents, then it calls the callback function.
+*
+* @param	Callback is a pointer to RX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void RxIntrHandler(void *Callback)
+{
+	XAxiDma_BdRing *RxRingPtr = (XAxiDma_BdRing *) Callback;
+	u32 IrqStatus;
+	int TimeOut;
+
+	/* Read pending interrupts */
+	IrqStatus = XAxiDma_BdRingGetIrq(RxRingPtr);
+
+	/* Acknowledge pending interrupts */
+	XAxiDma_BdRingAckIrq(RxRingPtr, IrqStatus);
+
+	/*
+	 * If no interrupt is asserted, we do not do anything
+	 */
+	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
+		return;
+	}
+
+	/*
+	 * If error interrupt is asserted, raise error flag, reset the
+	 * hardware to recover from the error, and return with no further
+	 * processing.
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
+
+		XAxiDma_BdRingDumpRegs(RxRingPtr);
+
+		Error = 1;
+
+		/* Reset could fail and hang
+		 * NEED a way to handle this or do not call it??
+		 */
+		XAxiDma_Reset(&AxiDma);
+
+		TimeOut = RESET_TIMEOUT_COUNTER;
+
+		while (TimeOut) {
+			if(XAxiDma_ResetIsDone(&AxiDma)) {
+				break;
+			}
+
+			TimeOut -= 1;
+		}
+
+		return;
+	}
+
+	/*
+	 * If completion interrupt is asserted, call RX call back function
+	 * to handle the processed BDs and then raise the according flag.
+	 */
+	if ((IrqStatus & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
+		RxCallBack(RxRingPtr);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function setups the interrupt system so interrupts can occur for the
+* DMA, it assumes INTC component exists in the hardware system.
+*
+* @param	IntcInstancePtr is a pointer to the instance of the INTC.
+* @param	AxiDmaPtr is a pointer to the instance of the DMA engine
+* @param	TxIntrId is the TX channel Interrupt ID.
+* @param	RxIntrId is the RX channel Interrupt ID.
+*
+* @return
+*		- XST_SUCCESS if successful,
+*		- XST_FAILURE.if not succesful
+*
+* @note		None.
+*
+******************************************************************************/
+
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId)
+{
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(AxiDmaPtr);
+	XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxRing(AxiDmaPtr);
+	int Status;
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+
+	/* Initialize the interrupt controller and connect the ISRs */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed init intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
+			       (XInterruptHandler) TxIntrHandler, TxRingPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed tx connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
+			       (XInterruptHandler) RxIntrHandler, RxRingPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed rx connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Start the interrupt controller */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed to start intc\r\n");
+		return XST_FAILURE;
+	}
+
+	XIntc_Enable(IntcInstancePtr, TxIntrId);
+	XIntc_Enable(IntcInstancePtr, RxIntrId);
+
+#else
+
+	XScuGic_Config *IntcConfig;
+
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+					IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
+				(Xil_InterruptHandler)TxIntrHandler,
+				TxRingPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
+				(Xil_InterruptHandler)RxIntrHandler,
+				RxRingPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XScuGic_Enable(IntcInstancePtr, TxIntrId);
+	XScuGic_Enable(IntcInstancePtr, RxIntrId);
+#endif
+
+	/* Enable interrupts from the hardware */
+
+	Xil_ExceptionInit();
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+			(Xil_ExceptionHandler)INTC_HANDLER,
+			(void *)IntcInstancePtr);
+
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts for DMA engine.
+*
+* @param	IntcInstancePtr is the pointer to the INTC component instance
+* @param	TxIntrId is interrupt ID associated w/ DMA TX channel
+* @param	RxIntrId is interrupt ID associated w/ DMA RX channel
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+					u16 TxIntrId, u16 RxIntrId)
+{
+#ifdef XPAR_INTC_0_DEVICE_ID
+	/* Disconnect the interrupts for the DMA TX and RX channels */
+	XIntc_Disconnect(IntcInstancePtr, TxIntrId);
+	XIntc_Disconnect(IntcInstancePtr, RxIntrId);
+#else
+	XScuGic_Disconnect(IntcInstancePtr, TxIntrId);
+	XScuGic_Disconnect(IntcInstancePtr, RxIntrId);
+#endif
+}
+
+/*****************************************************************************/
+/*
+*
+* This function sets up RX channel of the DMA engine to be ready for packet
+* reception
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful.
+*		- XST_FAILURE if fails.
+*
+* @note		None.
+*
+******************************************************************************/
+static int RxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *RxRingPtr;
+	int Status;
+	XAxiDma_Bd BdTemplate;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	int BdCount;
+	int FreeBdCount;
+	u32 RxBufferPtr;
+	int Index;
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+
+	/* Disable all RX interrupts before RxBD space setup */
+	XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Setup Rx BD space */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+				RX_BD_SPACE_HIGH - RX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(RxRingPtr, RX_BD_SPACE_BASE,
+					RX_BD_SPACE_BASE,
+					XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Rx bd create failed with %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup a BD template for the Rx channel. Then copy it to every RX BD.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+	Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Rx bd clone failed with %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/* Attach buffers to RxBD ring so we are ready to receive packets */
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Rx bd alloc failed with %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	BdCurPtr = BdPtr;
+	RxBufferPtr = RX_BUFFER_BASE;
+
+	for (Index = 0; Index < FreeBdCount; Index++) {
+
+		Status = XAxiDma_BdSetBufAddr(BdCurPtr, RxBufferPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set buffer addr %x on BD %x failed %d\r\n",
+			(unsigned int)RxBufferPtr,
+			(unsigned int)BdCurPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdSetLength(BdCurPtr, MAX_PKT_LEN,
+					RxRingPtr->MaxTransferLen);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set length %d on BD %x failed %d\r\n",
+			    MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		/* Receive BDs do not need to set anything for the control
+		 * The hardware will set the SOF/EOF bits per stream status
+		 */
+		XAxiDma_BdSetCtrl(BdCurPtr, 0);
+
+		XAxiDma_BdSetId(BdCurPtr, RxBufferPtr);
+
+		RxBufferPtr += MAX_PKT_LEN;
+		BdCurPtr = XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+	}
+
+	/*
+	 * Set the coalescing threshold, so only one receive interrupt
+	 * occurs for this example
+	 *
+	 * If you would like to have multiple interrupts to happen, change
+	 * the COALESCING_COUNT to be a smaller value
+	 */
+	Status = XAxiDma_BdRingSetCoalesce(RxRingPtr, COALESCING_COUNT,
+			DELAY_TIMER_COUNT);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Rx set coalesce failed with %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Rx ToHw failed with %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/* Enable all RX interrupts */
+	XAxiDma_BdRingIntEnable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Start RX DMA channel */
+	Status = XAxiDma_BdRingStart(RxRingPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Rx start BD ring failed with %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function sets up the TX channel of a DMA engine to be ready for packet
+* transmission.
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful.
+*		- XST_FAILURE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+static int TxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+	XAxiDma_Bd BdTemplate;
+	int Status;
+	u32 BdCount;
+
+	/* Disable all TX interrupts before TxBD space setup */
+	XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Setup TxBD space  */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+			(u32)TX_BD_SPACE_HIGH - (u32)TX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(TxRingPtr, TX_BD_SPACE_BASE,
+				     TX_BD_SPACE_BASE,
+				     XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed create BD ring\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Like the RxBD space, we create a template and set all BDs to be the
+	 * same as the template. The sender has to set up the BDs as needed.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed clone BDs\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the coalescing threshold, so only one transmit interrupt
+	 * occurs for this example
+	 *
+	 * If you would like to have multiple interrupts to happen, change
+	 * the COALESCING_COUNT to be a smaller value
+	 */
+	Status = XAxiDma_BdRingSetCoalesce(TxRingPtr, COALESCING_COUNT,
+			DELAY_TIMER_COUNT);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed set coalescing"
+		" %d/%d\r\n",COALESCING_COUNT, DELAY_TIMER_COUNT);
+		return XST_FAILURE;
+	}
+
+	/* Enable all TX interrupts */
+	XAxiDma_BdRingIntEnable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Start the TX channel */
+	Status = XAxiDma_BdRingStart(TxRingPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed bd start\r\n");
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function non-blockingly transmits all packets through the DMA engine.
+*
+* @param	AxiDmaInstPtr points to the DMA engine instance
+*
+* @return
+* 		- XST_SUCCESS if the DMA accepts all the packets successfully,
+* 		- XST_FAILURE if error occurs
+*
+* @note		None.
+*
+******************************************************************************/
+static int SendPacket(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
+	u8 *TxPacket;
+	u8 Value;
+	XAxiDma_Bd *BdPtr, *BdCurPtr;
+	int Status;
+	int Index, Pkts;
+	u32 BufferAddr;
+
+	/*
+	 * Each packet is limited to TxRingPtr->MaxTransferLen
+	 *
+	 * This will not be the case if hardware has store and forward built in
+	 */
+	if (MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT >
+			TxRingPtr->MaxTransferLen) {
+
+		xil_printf("Invalid total per packet transfer length for the "
+		    "packet %d/%d\r\n",
+		    MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT,
+		    TxRingPtr->MaxTransferLen);
+
+		return XST_INVALID_PARAM;
+	}
+
+	TxPacket = (u8 *) Packet;
+
+	Value = 0xC;
+
+	for(Index = 0; Index < MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER;
+								Index ++) {
+		TxPacket[Index] = Value;
+
+		Value = (Value + 1) & 0xFF;
+	}
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN *
+							NUMBER_OF_BDS_TO_TRANSFER);
+#ifdef __aarch64__
+	Xil_DCacheFlushRange((UINTPTR)RX_BUFFER_BASE, MAX_PKT_LEN *
+							NUMBER_OF_BDS_TO_TRANSFER);
+#endif
+
+	Status = XAxiDma_BdRingAlloc(TxRingPtr, NUMBER_OF_BDS_TO_TRANSFER,
+								&BdPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed bd alloc\r\n");
+		return XST_FAILURE;
+	}
+
+	BufferAddr = (u32) Packet;
+	BdCurPtr = BdPtr;
+
+	/*
+	 * Set up the BD using the information of the packet to transmit
+	 * Each transfer has NUMBER_OF_BDS_PER_PKT BDs
+	 */
+	for(Index = 0; Index < NUMBER_OF_PKTS_TO_TRANSFER; Index++) {
+
+		for(Pkts = 0; Pkts < NUMBER_OF_BDS_PER_PKT; Pkts++) {
+			u32 CrBits = 0;
+
+			Status = XAxiDma_BdSetBufAddr(BdCurPtr, BufferAddr);
+			if (Status != XST_SUCCESS) {
+				xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
+				(unsigned int)BufferAddr,
+				(unsigned int)BdCurPtr, Status);
+
+				return XST_FAILURE;
+			}
+
+			Status = XAxiDma_BdSetLength(BdCurPtr, MAX_PKT_LEN,
+						TxRingPtr->MaxTransferLen);
+			if (Status != XST_SUCCESS) {
+				xil_printf("Tx set length %d on BD %x failed %d\r\n",
+				MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
+
+				return XST_FAILURE;
+			}
+
+			if (Pkts == 0) {
+				/* The first BD has SOF set
+				 */
+				CrBits |= XAXIDMA_BD_CTRL_TXSOF_MASK;
+
+#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
+				/* The first BD has total transfer length set
+				 * in the last APP word, this is for the
+				 * loopback widget
+				 */
+				Status = XAxiDma_BdSetAppWord(BdCurPtr,
+				    XAXIDMA_LAST_APPWORD,
+				    MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT);
+
+				if (Status != XST_SUCCESS) {
+					xil_printf("Set app word failed with %d\r\n",
+					Status);
+				}
+#endif
+			}
+
+			if(Pkts == (NUMBER_OF_BDS_PER_PKT - 1)) {
+				/* The last BD should have EOF and IOC set
+				 */
+				CrBits |= XAXIDMA_BD_CTRL_TXEOF_MASK;
+			}
+
+			XAxiDma_BdSetCtrl(BdCurPtr, CrBits);
+			XAxiDma_BdSetId(BdCurPtr, BufferAddr);
+
+			BufferAddr += MAX_PKT_LEN;
+			BdCurPtr = XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
+		}
+	}
+
+	/* Give the BD to hardware */
+	Status = XAxiDma_BdRingToHw(TxRingPtr, NUMBER_OF_BDS_TO_TRANSFER,
+						BdPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed to hw, length %d\r\n",
+			(int)XAxiDma_BdGetLength(BdPtr,
+					TxRingPtr->MaxTransferLen));
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_sg_poll.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_sg_poll.c
new file mode 100644
index 000000000..c198b3c8e
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_sg_poll.c
@@ -0,0 +1,701 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_example_sg_poll.c
+ *
+ * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
+ * DMA core (AXIDMA) to transfer packets in polling mode when the AXIDMA
+ * core is configured in Scatter Gather Mode.
+ *
+ * This code assumes a loopback hardware widget is connected to the AXI DMA
+ * core for data packet loopback.
+ *
+ * To see the debug print, you need a Uart16550 or uartlite in your system,
+ * and please set "-DDEBUG" in your compiler options. You need to rebuild your
+ * software executable.
+ *
+ * Make sure that MEMORY_BASE is defined properly as per the HW system. The
+ * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
+ * throughput mode, it is 512MB.  These limits are need to ensured for
+ * proper operation of this code.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/17/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h, removed
+ *                     workaround for endianness
+ * 4.00a rkv  02/22/11 Name of the file has been changed for naming consistency
+ *       	       	   Added interrupt support for ARM.
+ * 5.00a srt  03/05/12 Added Flushing and Invalidation of Caches to fix CRs
+ *		       		   648103, 648701.
+ *		       		   Added V7 DDR Base Address to fix CR 649405.
+ * 6.00a srt  03/27/12 Changed API calls to support MCDMA driver.
+ * 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+ * 7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
+ *		       DDR memory limit of the h/w system built with Area mode
+ * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+/***************************** Include Files *********************************/
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xdebug.h"
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#if (!defined(DEBUG))
+extern void xil_printf(const char *format, ...);
+#endif
+
+/******************** Constant Definitions **********************************/
+
+/*
+ * Device hardware build related constants.
+ */
+
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
+#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#define MEMORY_BASE	XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+			DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR		0x01000000
+#else
+#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#define TX_BD_SPACE_BASE	(MEM_BASE_ADDR)
+#define TX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x00000FFF)
+#define RX_BD_SPACE_BASE	(MEM_BASE_ADDR + 0x00001000)
+#define RX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x00001FFF)
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
+
+
+#define MAX_PKT_LEN		0x20
+#define MARK_UNCACHEABLE        0x701
+
+#define TEST_START_VALUE	0xC
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+static void Uart550_Setup(void);
+#endif
+
+static int RxSetup(XAxiDma * AxiDmaInstPtr);
+static int TxSetup(XAxiDma * AxiDmaInstPtr);
+static int SendPacket(XAxiDma * AxiDmaInstPtr);
+static int CheckData(void);
+static int CheckDmaResult(XAxiDma * AxiDmaInstPtr);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XAxiDma AxiDma;
+
+/*
+ * Buffer for transmit packet. Must be 32-bit aligned to be used by DMA.
+ */
+u32 *Packet = (u32 *) TX_BUFFER_BASE;
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the tests on DMA core. It sets up
+* DMA engine to be ready to receive and send packets, then a packet is
+* transmitted and will be verified after it is received via the DMA loopback
+* widget.
+*
+* @param	None
+*
+* @return
+*		- XST_SUCCESS if test passes
+*		- XST_FAILURE if test fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+	XAxiDma_Config *Config;
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+
+	Uart550_Setup();
+
+#endif
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+
+#ifdef __aarch64__
+	Xil_SetTlbAttributes(TX_BD_SPACE_BASE, MARK_UNCACHEABLE);
+	Xil_SetTlbAttributes(RX_BD_SPACE_BASE, MARK_UNCACHEABLE);
+#endif
+
+	Config = XAxiDma_LookupConfig(DMA_DEV_ID);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DMA_DEV_ID);
+
+		return XST_FAILURE;
+	}
+
+	/* Initialize DMA engine */
+	Status = XAxiDma_CfgInitialize(&AxiDma, Config);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	if(!XAxiDma_HasSg(&AxiDma)) {
+		xil_printf("Device configured as Simple mode \r\n");
+
+		return XST_FAILURE;
+	}
+
+	Status = TxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Status = RxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Send a packet */
+	Status = SendPacket(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Check DMA transfer result */
+	Status = CheckDmaResult(&AxiDma);
+
+	xil_printf("AXI DMA SG Polling Test %s\r\n",
+		(Status == XST_SUCCESS)? "passed":"failed");
+
+	xil_printf("--- Exiting main() --- \r\n");
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600, and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	/* Set the baudrate to be predictable
+	 */
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets up RX channel of the DMA engine to be ready for packet
+* reception
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	XST_SUCCESS if the setup is successful, XST_FAILURE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+static int RxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *RxRingPtr;
+	int Delay = 0;
+	int Coalesce = 1;
+	int Status;
+	XAxiDma_Bd BdTemplate;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	u32 BdCount;
+	u32 FreeBdCount;
+	UINTPTR RxBufferPtr;
+	int Index;
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+
+	/* Disable all RX interrupts before RxBD space setup */
+
+	XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set delay and coalescing */
+	XAxiDma_BdRingSetCoalesce(RxRingPtr, Coalesce, Delay);
+
+	/* Setup Rx BD space */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+				RX_BD_SPACE_HIGH - RX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(RxRingPtr, RX_BD_SPACE_BASE,
+				RX_BD_SPACE_BASE,
+				XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+
+	if (Status != XST_SUCCESS) {
+		xil_printf("RX create BD ring failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup an all-zero BD as the template for the Rx channel.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+
+	Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		xil_printf("RX clone BD failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	/* Attach buffers to RxBD ring so we are ready to receive packets */
+
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("RX alloc BD failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	BdCurPtr = BdPtr;
+	RxBufferPtr = RX_BUFFER_BASE;
+	for (Index = 0; Index < FreeBdCount; Index++) {
+		Status = XAxiDma_BdSetBufAddr(BdCurPtr, RxBufferPtr);
+
+		if (Status != XST_SUCCESS) {
+			xil_printf("Set buffer addr %x on BD %x failed %d\r\n",
+			    (unsigned int)RxBufferPtr,
+			    (unsigned int)BdCurPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdSetLength(BdCurPtr, MAX_PKT_LEN,
+				RxRingPtr->MaxTransferLen);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set length %d on BD %x failed %d\r\n",
+			    MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		/* Receive BDs do not need to set anything for the control
+		 * The hardware will set the SOF/EOF bits per stream status
+		 */
+		XAxiDma_BdSetCtrl(BdCurPtr, 0);
+		XAxiDma_BdSetId(BdCurPtr, RxBufferPtr);
+
+		RxBufferPtr += MAX_PKT_LEN;
+		BdCurPtr = XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+	}
+
+	/* Clear the receive buffer, so we can verify data
+	 */
+	memset((void *)RX_BUFFER_BASE, 0, MAX_PKT_LEN);
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount,
+						BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("RX submit hw failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	/* Start RX DMA channel */
+	Status = XAxiDma_BdRingStart(RxRingPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("RX start hw failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the TX channel of a DMA engine to be ready for packet
+* transmission
+*
+* @param	AxiDmaInstPtr is the instance pointer to the DMA engine.
+*
+* @return	XST_SUCCESS if the setup is successful, XST_FAILURE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+static int TxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_Bd BdTemplate;
+	int Delay = 0;
+	int Coalesce = 1;
+	int Status;
+	u32 BdCount;
+
+	TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+
+	/* Disable all TX interrupts before TxBD space setup */
+
+	XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set TX delay and coalesce */
+	XAxiDma_BdRingSetCoalesce(TxRingPtr, Coalesce, Delay);
+
+	/* Setup TxBD space  */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+				TX_BD_SPACE_HIGH - TX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(TxRingPtr, TX_BD_SPACE_BASE,
+				TX_BD_SPACE_BASE,
+				XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed create BD ring in txsetup\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/*
+	 * We create an all-zero BD as the template.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+
+	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed bdring clone in txsetup %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	/* Start the TX channel */
+	Status = XAxiDma_BdRingStart(TxRingPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed start bdring txsetup %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function transmits one packet non-blockingly through the DMA engine.
+*
+* @param	AxiDmaInstPtr points to the DMA engine instance
+*
+* @return	- XST_SUCCESS if the DMA accepts the packet successfully,
+*		- XST_FAILURE otherwise.
+*
+* @note     None.
+*
+******************************************************************************/
+static int SendPacket(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	u8 *TxPacket;
+	u8 Value;
+	XAxiDma_Bd *BdPtr;
+	int Status;
+	int Index;
+
+	TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
+
+	/* Create pattern in the packet to transmit */
+	TxPacket = (u8 *) Packet;
+
+	Value = TEST_START_VALUE;
+
+	for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
+		TxPacket[Index] = Value;
+
+		Value = (Value + 1) & 0xFF;
+	}
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((UINTPTR)TxPacket, MAX_PKT_LEN);
+#ifdef __aarch64__
+	Xil_DCacheFlushRange((UINTPTR)RX_BUFFER_BASE, MAX_PKT_LEN);
+#endif
+
+
+	/* Allocate a BD */
+	Status = XAxiDma_BdRingAlloc(TxRingPtr, 1, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Set up the BD using the information of the packet to transmit */
+	Status = XAxiDma_BdSetBufAddr(BdPtr, (UINTPTR) Packet);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
+		    (unsigned int)Packet, (unsigned int)BdPtr, Status);
+
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_BdSetLength(BdPtr, MAX_PKT_LEN,
+				TxRingPtr->MaxTransferLen);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Tx set length %d on BD %x failed %d\r\n",
+		    MAX_PKT_LEN, (unsigned int)BdPtr, Status);
+
+		return XST_FAILURE;
+	}
+
+#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
+	Status = XAxiDma_BdSetAppWord(BdPtr,
+	    XAXIDMA_LAST_APPWORD, MAX_PKT_LEN);
+
+	/* If Set app length failed, it is not fatal
+	 */
+	if (Status != XST_SUCCESS) {
+		xil_printf("Set app word failed with %d\r\n", Status);
+	}
+#endif
+
+	/* For single packet, both SOF and EOF are to be set
+	 */
+	XAxiDma_BdSetCtrl(BdPtr, XAXIDMA_BD_CTRL_TXEOF_MASK |
+						XAXIDMA_BD_CTRL_TXSOF_MASK);
+
+	XAxiDma_BdSetId(BdPtr, (u32) Packet);
+
+	/* Give the BD to DMA to kick off the transmission. */
+	Status = XAxiDma_BdRingToHw(TxRingPtr, 1, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("to hw failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function checks data buffer after the DMA transfer is finished.
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if validation is successful
+*		- XST_FAILURE if validation is failure.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckData(void)
+{
+	u8 *RxPacket;
+	int Index = 0;
+	u8 Value;
+
+
+	RxPacket = (u8 *) RX_BUFFER_BASE;
+	Value = TEST_START_VALUE;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+#ifndef __aarch64__
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN);
+#endif
+
+	for(Index = 0; Index < MAX_PKT_LEN; Index++) {
+		if (RxPacket[Index] != Value) {
+			xil_printf("Data error %d: %x/%x\r\n",
+			    Index, (unsigned int)RxPacket[Index],
+			    (unsigned int)Value);
+
+			return XST_FAILURE;
+		}
+		Value = (Value + 1) & 0xFF;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function waits until the DMA transaction is finished, checks data,
+* and cleans up.
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if DMA transfer is successful and data is correct,
+*		- XST_FAILURE if fails.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckDmaResult(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+	XAxiDma_Bd *BdPtr;
+	int ProcessedBdCount;
+	int FreeBdCount;
+	int Status;
+
+	TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
+	RxRingPtr = XAxiDma_GetRxRing(AxiDmaInstPtr);
+
+	/* Wait until the one BD TX transaction is done */
+	while ((ProcessedBdCount = XAxiDma_BdRingFromHw(TxRingPtr,
+						       XAXIDMA_ALL_BDS,
+						       &BdPtr)) == 0) {
+	}
+
+	/* Free all processed TX BDs for future transmission */
+	Status = XAxiDma_BdRingFree(TxRingPtr, ProcessedBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed to free %d tx BDs %d\r\n",
+		    ProcessedBdCount, Status);
+		return XST_FAILURE;
+	}
+
+	/* Wait until the data has been received by the Rx channel */
+	while ((ProcessedBdCount = XAxiDma_BdRingFromHw(RxRingPtr,
+						       XAXIDMA_ALL_BDS,
+						       &BdPtr)) == 0) {
+	}
+
+	/* Check received data */
+	if (CheckData() != XST_SUCCESS) {
+
+		return XST_FAILURE;
+	}
+
+	/* Free all processed RX BDs for future transmission */
+	Status = XAxiDma_BdRingFree(RxRingPtr, ProcessedBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed to free %d rx BDs %d\r\n",
+		    ProcessedBdCount, Status);
+		return XST_FAILURE;
+	}
+
+	/* Return processed BDs to RX channel so we are ready to receive new
+	 * packets:
+	 *    - Allocate all free RX BDs
+	 *    - Pass the BDs to RX channel
+	 */
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("bd alloc failed\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Submit %d rx BDs failed %d\r\n", FreeBdCount, Status);
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_simple_intr.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_simple_intr.c
new file mode 100644
index 000000000..0f8983956
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_simple_intr.c
@@ -0,0 +1,753 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_example_simple_intr.c
+ *
+ * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
+ * DMA core (AXIDMA) to transfer packets.in interrupt mode when the AXIDMA core
+ * is configured in simple mode
+ *
+ * This code assumes a loopback hardware widget is connected to the AXI DMA
+ * core for data packet loopback.
+ *
+ * To see the debug print, you need a Uart16550 or uartlite in your system,
+ * and please set "-DDEBUG" in your compiler options. You need to rebuild your
+ * software executable.
+ *
+ * Make sure that MEMORY_BASE is defined properly as per the HW system. The
+ * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
+ * throughput mode, it is 512MB.  These limits are need to ensured for
+ * proper operation of this code.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 4.00a rkv  02/22/11 New example created for simple DMA, this example is for
+ *       	       simple DMA,Added interrupt support for Zynq.
+ * 4.00a srt  08/04/11 Changed a typo in the RxIntrHandler, changed
+ *		       XAXIDMA_DMA_TO_DEVICE to XAXIDMA_DEVICE_TO_DMA
+ * 5.00a srt  03/06/12 Added Flushing and Invalidation of Caches to fix CRs
+ *		       648103, 648701.
+ *		       Added V7 DDR Base Address to fix CR 649405.
+ * 6.00a srt  03/27/12 Changed API calls to support MCDMA driver.
+ * 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+ * 7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
+ *		       DDR memory limit of the h/w system built with Area mode
+ * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xdebug.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #include "xintc.h"
+#else
+ #include "xscugic.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Device hardware build related constants.
+ */
+
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+		DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR		0x01000000
+#else
+#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define RX_INTR_ID		XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID
+#define TX_INTR_ID		XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID
+#else
+#define RX_INTR_ID		XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID
+#define TX_INTR_ID		XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID
+#endif
+
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
+#else
+#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #define INTC		XIntc
+ #define INTC_HANDLER	XIntc_InterruptHandler
+#else
+ #define INTC		XScuGic
+ #define INTC_HANDLER	XScuGic_InterruptHandler
+#endif
+
+
+/* Timeout loop counter for reset
+ */
+#define RESET_TIMEOUT_COUNTER	10000
+
+#define TEST_START_VALUE	0xC
+/*
+ * Buffer and Buffer Descriptor related constant definition
+ */
+#define MAX_PKT_LEN		0x100
+
+#define NUMBER_OF_TRANSFERS	10
+
+/* The interrupt coalescing threshold and delay timer threshold
+ * Valid range is 1 to 255
+ *
+ * We set the coalescing threshold to be the total number of packets.
+ * The receive side will only get one completion interrupt for this example.
+ */
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#ifndef DEBUG
+extern void xil_printf(const char *format, ...);
+#endif
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+static int CheckData(int Length, u8 StartValue);
+static void TxIntrHandler(void *Callback);
+static void RxIntrHandler(void *Callback);
+
+
+
+
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId);
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+					u16 TxIntrId, u16 RxIntrId);
+
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+
+
+static XAxiDma AxiDma;		/* Instance of the XAxiDma */
+
+static INTC Intc;	/* Instance of the Interrupt Controller */
+
+/*
+ * Flags interrupt handlers use to notify the application context the events.
+ */
+volatile int TxDone;
+volatile int RxDone;
+volatile int Error;
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the interrupt test. It does the following:
+*	Set up the output terminal if UART16550 is in the hardware build
+*	Initialize the DMA engine
+*	Set up Tx and Rx channels
+*	Set up the interrupt system for the Tx and Rx interrupts
+*	Submit a transfer
+*	Wait for the transfer to finish
+*	Check transfer status
+*	Disable Tx and Rx interrupts
+*	Print test status and exit
+*
+* @param	None
+*
+* @return
+*		- XST_SUCCESS if example finishes successfully
+*		- XST_FAILURE if example fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+	XAxiDma_Config *Config;
+	int Tries = NUMBER_OF_TRANSFERS;
+	int Index;
+	u8 *TxBufferPtr;
+	u8 *RxBufferPtr;
+	u8 Value;
+
+	TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
+	RxBufferPtr = (u8 *)RX_BUFFER_BASE;
+	/* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+
+	Config = XAxiDma_LookupConfig(DMA_DEV_ID);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DMA_DEV_ID);
+
+		return XST_FAILURE;
+	}
+
+	/* Initialize DMA engine */
+	Status = XAxiDma_CfgInitialize(&AxiDma, Config);
+
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	if(XAxiDma_HasSg(&AxiDma)){
+		xil_printf("Device configured as SG mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Set up Interrupt system  */
+	Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed intr setup\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable all interrupts before setup */
+
+	XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DMA_TO_DEVICE);
+
+	XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
+				XAXIDMA_DEVICE_TO_DMA);
+
+	/* Enable all interrupts */
+	XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
+							XAXIDMA_DMA_TO_DEVICE);
+
+
+	XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
+							XAXIDMA_DEVICE_TO_DMA);
+
+	/* Initialize flags before start transfer test  */
+	TxDone = 0;
+	RxDone = 0;
+	Error = 0;
+
+	Value = TEST_START_VALUE;
+
+	for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
+			TxBufferPtr[Index] = Value;
+
+			Value = (Value + 1) & 0xFF;
+	}
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
+#ifdef __aarch64__
+	Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN);
+#endif
+
+	/* Send a packet */
+	for(Index = 0; Index < Tries; Index ++) {
+
+		Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
+					MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
+
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
+					MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
+
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+
+		/*
+		 * Wait TX done and RX done
+		 */
+		while (!TxDone && !RxDone && !Error) {
+				/* NOP */
+		}
+
+		if (Error) {
+			xil_printf("Failed test transmit%s done, "
+			"receive%s done\r\n", TxDone? "":" not",
+							RxDone? "":" not");
+
+			goto Done;
+
+		}
+
+		/*
+		 * Test finished, check data
+		 */
+		Status = CheckData(MAX_PKT_LEN, 0xC);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Data check failed\r\n");
+			goto Done;
+		}
+	}
+
+
+	xil_printf("AXI DMA interrupt example test passed\r\n");
+
+
+	/* Disable TX and RX Ring interrupts and return success */
+
+	DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
+
+Done:
+	xil_printf("--- Exiting main() --- \r\n");
+
+	return XST_SUCCESS;
+}
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This function checks data buffer after the DMA transfer is finished.
+*
+* We use the static tx/rx buffers.
+*
+* @param	Length is the length to check
+* @param	StartValue is the starting value of the first byte
+*
+* @return
+*		- XST_SUCCESS if validation is successful
+*		- XST_FAILURE if validation is failure.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckData(int Length, u8 StartValue)
+{
+	u8 *RxPacket;
+	int Index = 0;
+	u8 Value;
+
+	RxPacket = (u8 *) RX_BUFFER_BASE;
+	Value = StartValue;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+#ifndef __aarch64__
+	Xil_DCacheInvalidateRange((u32)RxPacket, Length);
+#endif
+
+	for(Index = 0; Index < Length; Index++) {
+		if (RxPacket[Index] != Value) {
+			xil_printf("Data error %d: %x/%x\r\n",
+			    Index, RxPacket[Index], Value);
+
+			return XST_FAILURE;
+		}
+		Value = (Value + 1) & 0xFF;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA TX Interrupt handler function.
+*
+* It gets the interrupt status from the hardware, acknowledges it, and if any
+* error happens, it resets the hardware. Otherwise, if a completion interrupt
+* is present, then sets the TxDone.flag
+*
+* @param	Callback is a pointer to TX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void TxIntrHandler(void *Callback)
+{
+
+	u32 IrqStatus;
+	int TimeOut;
+	XAxiDma *AxiDmaInst = (XAxiDma *)Callback;
+
+	/* Read pending interrupts */
+	IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DMA_TO_DEVICE);
+
+	/* Acknowledge pending interrupts */
+
+
+	XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DMA_TO_DEVICE);
+
+	/*
+	 * If no interrupt is asserted, we do not do anything
+	 */
+	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
+
+		return;
+	}
+
+	/*
+	 * If error interrupt is asserted, raise error flag, reset the
+	 * hardware to recover from the error, and return with no further
+	 * processing.
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
+
+		Error = 1;
+
+		/*
+		 * Reset should never fail for transmit channel
+		 */
+		XAxiDma_Reset(AxiDmaInst);
+
+		TimeOut = RESET_TIMEOUT_COUNTER;
+
+		while (TimeOut) {
+			if (XAxiDma_ResetIsDone(AxiDmaInst)) {
+				break;
+			}
+
+			TimeOut -= 1;
+		}
+
+		return;
+	}
+
+	/*
+	 * If Completion interrupt is asserted, then set the TxDone flag
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
+
+		TxDone = 1;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA RX interrupt handler function
+*
+* It gets the interrupt status from the hardware, acknowledges it, and if any
+* error happens, it resets the hardware. Otherwise, if a completion interrupt
+* is present, then it sets the RxDone flag.
+*
+* @param	Callback is a pointer to RX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void RxIntrHandler(void *Callback)
+{
+	u32 IrqStatus;
+	int TimeOut;
+	XAxiDma *AxiDmaInst = (XAxiDma *)Callback;
+
+	/* Read pending interrupts */
+	IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DEVICE_TO_DMA);
+
+	/* Acknowledge pending interrupts */
+	XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DEVICE_TO_DMA);
+
+	/*
+	 * If no interrupt is asserted, we do not do anything
+	 */
+	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
+		return;
+	}
+
+	/*
+	 * If error interrupt is asserted, raise error flag, reset the
+	 * hardware to recover from the error, and return with no further
+	 * processing.
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
+
+		Error = 1;
+
+		/* Reset could fail and hang
+		 * NEED a way to handle this or do not call it??
+		 */
+		XAxiDma_Reset(AxiDmaInst);
+
+		TimeOut = RESET_TIMEOUT_COUNTER;
+
+		while (TimeOut) {
+			if(XAxiDma_ResetIsDone(AxiDmaInst)) {
+				break;
+			}
+
+			TimeOut -= 1;
+		}
+
+		return;
+	}
+
+	/*
+	 * If completion interrupt is asserted, then set RxDone flag
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
+
+		RxDone = 1;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function setups the interrupt system so interrupts can occur for the
+* DMA, it assumes INTC component exists in the hardware system.
+*
+* @param	IntcInstancePtr is a pointer to the instance of the INTC.
+* @param	AxiDmaPtr is a pointer to the instance of the DMA engine
+* @param	TxIntrId is the TX channel Interrupt ID.
+* @param	RxIntrId is the RX channel Interrupt ID.
+*
+* @return
+*		- XST_SUCCESS if successful,
+*		- XST_FAILURE.if not succesful
+*
+* @note		None.
+*
+******************************************************************************/
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId)
+{
+	int Status;
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+
+	/* Initialize the interrupt controller and connect the ISRs */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed init intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
+			       (XInterruptHandler) TxIntrHandler, AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed tx connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
+			       (XInterruptHandler) RxIntrHandler, AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed rx connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Start the interrupt controller */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed to start intc\r\n");
+		return XST_FAILURE;
+	}
+
+	XIntc_Enable(IntcInstancePtr, TxIntrId);
+	XIntc_Enable(IntcInstancePtr, RxIntrId);
+
+#else
+
+	XScuGic_Config *IntcConfig;
+
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+					IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
+				(Xil_InterruptHandler)TxIntrHandler,
+				AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
+				(Xil_InterruptHandler)RxIntrHandler,
+				AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XScuGic_Enable(IntcInstancePtr, TxIntrId);
+	XScuGic_Enable(IntcInstancePtr, RxIntrId);
+
+
+#endif
+
+	/* Enable interrupts from the hardware */
+
+	Xil_ExceptionInit();
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+			(Xil_ExceptionHandler)INTC_HANDLER,
+			(void *)IntcInstancePtr);
+
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts for DMA engine.
+*
+* @param	IntcInstancePtr is the pointer to the INTC component instance
+* @param	TxIntrId is interrupt ID associated w/ DMA TX channel
+* @param	RxIntrId is interrupt ID associated w/ DMA RX channel
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+					u16 TxIntrId, u16 RxIntrId)
+{
+#ifdef XPAR_INTC_0_DEVICE_ID
+	/* Disconnect the interrupts for the DMA TX and RX channels */
+	XIntc_Disconnect(IntcInstancePtr, TxIntrId);
+	XIntc_Disconnect(IntcInstancePtr, RxIntrId);
+#else
+	XScuGic_Disconnect(IntcInstancePtr, TxIntrId);
+	XScuGic_Disconnect(IntcInstancePtr, RxIntrId);
+#endif
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_simple_poll.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_simple_poll.c
new file mode 100644
index 000000000..3f15807bc
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_example_simple_poll.c
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_example_simple_poll.c
+ *
+ * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
+ * DMA core (AXIDMA) to transfer packets in polling mode when the AXI DMA core
+ * is configured in simple mode.
+ *
+ * This code assumes a loopback hardware widget is connected to the AXI DMA
+ * core for data packet loopback.
+ *
+ * To see the debug print, you need a Uart16550 or uartlite in your system,
+ * and please set "-DDEBUG" in your compiler options. You need to rebuild your
+ * software executable.
+ *
+ * Make sure that MEMORY_BASE is defined properly as per the HW system. The
+ * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
+ * throughput mode, it is 512MB.  These limits are need to ensured for
+ * proper operation of this code.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 4.00a rkv  02/22/11 New example created for simple DMA, this example is for
+ *       	       simple DMA
+ * 5.00a srt  03/06/12 Added Flushing and Invalidation of Caches to fix CRs
+ *		       648103, 648701.
+ *		       Added V7 DDR Base Address to fix CR 649405.
+ * 6.00a srt  03/27/12 Changed API calls to support MCDMA driver.
+ * 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+ * 7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
+ *		       DDR memory limit of the h/w system built with Area mode
+ * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+
+ */
+/***************************** Include Files *********************************/
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xdebug.h"
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+/******************** Constant Definitions **********************************/
+
+/*
+ * Device hardware build related constants.
+ */
+
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+		 DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR		0x01000000
+#else
+#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
+
+#define MAX_PKT_LEN		0x20
+
+#define TEST_START_VALUE	0xC
+
+#define NUMBER_OF_TRANSFERS	10
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#if (!defined(DEBUG))
+extern void xil_printf(const char *format, ...);
+#endif
+
+int XAxiDma_SimplePollExample(u16 DeviceId);
+static int CheckData(void);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XAxiDma AxiDma;
+
+
+/*****************************************************************************/
+/*
+* The entry point for this example. It invokes the example function,
+* and reports the execution status.
+*
+* @param	None.
+*
+* @return
+*		- XST_SUCCESS if example finishes successfully
+*		- XST_FAILURE if example fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+
+	/* Run the poll example for simple transfer */
+	Status = XAxiDma_SimplePollExample(DMA_DEV_ID);
+
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("XAxiDma_SimplePollExample: Failed\r\n");
+		return XST_FAILURE;
+	}
+
+	xil_printf("XAxiDma_SimplePollExample: Passed\r\n");
+
+	xil_printf("--- Exiting main() --- \r\n");
+
+	return XST_SUCCESS;
+
+}
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600, and data bits to 8
+*
+* @param	None.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	/* Set the baudrate to be predictable
+	 */
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+* The example to do the simple transfer through polling. The constant
+* NUMBER_OF_TRANSFERS defines how many times a simple transfer is repeated.
+*
+* @param	DeviceId is the Device Id of the XAxiDma instance
+*
+* @return
+*		- XST_SUCCESS if example finishes successfully
+*		- XST_FAILURE if error occurs
+*
+* @note		None
+*
+*
+******************************************************************************/
+int XAxiDma_SimplePollExample(u16 DeviceId)
+{
+	XAxiDma_Config *CfgPtr;
+	int Status;
+	int Tries = NUMBER_OF_TRANSFERS;
+	int Index;
+	u8 *TxBufferPtr;
+	u8 *RxBufferPtr;
+	u8 Value;
+
+	TxBufferPtr = (u8 *)TX_BUFFER_BASE ;
+	RxBufferPtr = (u8 *)RX_BUFFER_BASE;
+
+	/* Initialize the XAxiDma device.
+	 */
+	CfgPtr = XAxiDma_LookupConfig(DeviceId);
+	if (!CfgPtr) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	if(XAxiDma_HasSg(&AxiDma)){
+		xil_printf("Device configured as SG mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable interrupts, we use polling mode
+	 */
+	XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DEVICE_TO_DMA);
+	XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DMA_TO_DEVICE);
+
+	Value = TEST_START_VALUE;
+
+	for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
+			TxBufferPtr[Index] = Value;
+
+			Value = (Value + 1) & 0xFF;
+	}
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);
+#ifdef __aarch64__
+	Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN);
+#endif
+
+	for(Index = 0; Index < Tries; Index ++) {
+
+
+		Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr,
+					MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
+
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr,
+					MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);
+
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+		while ((XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) ||
+			(XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE))) {
+				/* Wait */
+		}
+
+		Status = CheckData();
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+	}
+
+	/* Test finishes successfully
+	 */
+	return XST_SUCCESS;
+}
+
+
+
+/*****************************************************************************/
+/*
+*
+* This function checks data buffer after the DMA transfer is finished.
+*
+* @param	None
+*
+* @return
+*		- XST_SUCCESS if validation is successful.
+*		- XST_FAILURE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckData(void)
+{
+	u8 *RxPacket;
+	int Index = 0;
+	u8 Value;
+
+	RxPacket = (u8 *) RX_BUFFER_BASE;
+	Value = TEST_START_VALUE;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+#ifndef __aarch64__
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN);
+#endif
+
+	for(Index = 0; Index < MAX_PKT_LEN; Index++) {
+		if (RxPacket[Index] != Value) {
+			xil_printf("Data error %d: %x/%x\r\n",
+			Index, (unsigned int)RxPacket[Index],
+				(unsigned int)Value);
+
+			return XST_FAILURE;
+		}
+		Value = (Value + 1) & 0xFF;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_multichan_sg_intr.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_multichan_sg_intr.c
new file mode 100644
index 000000000..8d4067551
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_multichan_sg_intr.c
@@ -0,0 +1,1317 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaximcdma_example_sg_intr.c
+ *
+ * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
+ * DMA core v6_00_a (AXIDMA) to transfer packets in interrupt mode for
+ * Multiple Channel capability.
+ * Thi example is designed to work only when AXIDMA core is configured
+ * in Scatter Gather Mode and Multiple Channel mode.
+ *
+ * We show how to do multiple packets transfers, as well as how to do multiple
+ * BDs per packet transfers.
+ *
+ * This code is tested only with two channels on both Tx and Rx.
+ * This code assumes a loopback hardware widget is connected to the AXI DMA
+ * core for data packet loopback. The loopback widget is configured in a way
+ * that, when a packet is transmitted on "Tx Channel 0" it will be received
+ * on the "Rx channel 1" and if "Tx Channel 1" it is on Rx Channel 0.
+ * Both the cases are included in this example.
+ *
+ * To see the debug print, you need a Uart16550 or uartlite in your system,
+ * and please set "-DDEBUG" in your compiler options. You need to rebuild your
+ * software executable.
+ *
+ * Make sure that MEMORY_BASE is defined properly as per the HW system. The
+ * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
+ * throughput mode, it is 512MB.  These limits are need to ensured for
+ * proper operation of this code.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a srt  03/27/12 First release
+ * 2.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+ * 2.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
+ *		       DDR memory limit of the h/w system built with Area mode
+ * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+/***************************** Include Files *********************************/
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xdebug.h"
+#include "xaxidma_bd.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#ifndef DEBUG
+extern void xil_printf(const char *format, ...);
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #include "xintc.h"
+#else
+ #include "xscugic.h"
+#endif
+
+/******************** Constant Definitions **********************************/
+/*
+ * Device hardware build related constants.
+ */
+
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+			DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR		0x01000000
+#else
+#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
+#else
+#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define RX_INTR_ID		XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID
+#define TX_INTR_ID		XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID
+#else
+#define RX_INTR_ID		XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID
+#define TX_INTR_ID		XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID
+#endif
+
+#define RX_BD_SPACE_BASE	(MEM_BASE_ADDR)
+#define RX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x0000FFFF)
+#define TX_BD_SPACE_BASE	(MEM_BASE_ADDR + 0x00040000)
+#define TX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x0004FFFF)
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
+#else
+#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
+#endif
+
+/* Timeout loop counter for reset
+ */
+#define RESET_TIMEOUT_COUNTER	10000
+
+/*
+ * Number of BDs in the transfer example
+ * We show how to submit multiple BDs for one transmit.
+ * The receive side gets one completion per transfer.
+ */
+#define NUMBER_OF_BDS_PER_PKT		2
+#define NUMBER_OF_PKTS_TO_TRANSFER 	1
+#define NUMBER_OF_BDS_TO_TRANSFER	(NUMBER_OF_PKTS_TO_TRANSFER * \
+						NUMBER_OF_BDS_PER_PKT)
+#define MAX_BD_COUNT		1024
+
+/* The interrupt coalescing threshold and delay timer threshold
+ * Valid range is 1
+ *
+ * Note: Coalescing threshold configured for more than one is not
+ * 	 supported by the AXIDMA IP v6_00_a.
+ */
+#define COALESCING_COUNT		1
+#define DELAY_TIMER_COUNT		100
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #define INTC		XIntc
+ #define INTC_HANDLER	XIntc_InterruptHandler
+#else
+ #define INTC		XScuGic
+ #define INTC_HANDLER	XScuGic_InterruptHandler
+#endif
+
+/*
+ * Packet Data Values
+ */
+#define PACKET0_DATA	0x1
+#define PACKET1_DATA	0xC
+
+/*
+ * MCDMA Values
+ */
+#define TID0	0x0		/* Stream identifier 0 */
+#define TDEST0 	0x0		/* Coarse Routing info for stream 0 */
+#define TID1 	0x1		/* Stream identifier 1 */
+#define TDEST1 	0x1		/* Coarse Routing info for stream 1 */
+#define TUSER	0x0		/* User defined sideband signaling */
+#define ARCACHE 0x3		/* Cache type */
+#define ARUSER 	0x0		/* Sideband signals */
+#define VSIZE	0x4		/* Vsize */
+#define STRIDE	0x20		/* Stride control */
+#define HSIZE   0x100  		/* Hsize */
+
+/*
+ * Buffer and Buffer Descriptor related constant definition
+ */
+#define MAX_PKT_LEN		VSIZE * STRIDE
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+static int CheckData(int Length, u8 *RxPacket, u8 StartValue);
+static void TxCallBack(XAxiDma * AxiDmaInstPtr);
+static void TxIntrHandler(void *Callback);
+static void RxCallBack(XAxiDma * AxiDmaInstPtr);
+static void RxIntrHandler(void *Callback);
+extern void XaxiDma_DumpBd(XAxiDma_Bd *BdPtr);
+
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			   XAxiDma * AxiDmaPtr, u16 TxIntrId,
+			   u16 RxIntrId, int RingIndex);
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+					u16 TxIntrId, u16 RxIntrId);
+
+static int RxSetup(XAxiDma * AxiDmaInstPtr);
+static int TxSetup(XAxiDma * AxiDmaInstPtr);
+static int SendPacket(XAxiDma * AxiDmaInstPtr,
+		u8 TDest, u8 TId, u8 Value);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XAxiDma AxiDma;
+
+
+static INTC Intc;	/* Instance of the Interrupt Controller */
+
+/*
+ * Flags interrupt handlers use to notify the application context the events.
+ */
+volatile int TxDone;
+volatile int RxDone;
+volatile int Error;
+
+/*
+ * Buffer for transmit packet. Must be 32-bit aligned to be used by DMA.
+ */
+u32 *Packet = (u32 *) TX_BUFFER_BASE;
+
+/*
+ * Buffer for Receive packet. Must be 32-bit aligned to be used by DMA.
+ */
+u8 *RxPacket0 = (u8 *) RX_BUFFER_BASE;
+u8 *RxPacket1 = (u8 *) (RX_BUFFER_BASE + MAX_BD_COUNT
+				* MAX_PKT_LEN);
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the interrupt test. It does the following:
+*	- Set up the output terminal if UART16550 is in the hardware build
+*	- Initialize the DMA engine
+*	- Set up Tx and Rx channels
+*	- Set up the interrupt system for the Tx and Rx interrupts
+*	- Submit a transfer
+*	- Wait for the transfer to finish
+*	- Check transfer status
+*	- Disable Tx and Rx interrupts
+*	- Print test status and exit
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if tests pass
+*		- XST_FAILURE if fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+	XAxiDma_Config *Config;
+
+	/* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+
+	Config = XAxiDma_LookupConfig(DMA_DEV_ID);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DMA_DEV_ID);
+
+		return XST_FAILURE;
+	}
+
+	/* Initialize DMA engine */
+	XAxiDma_CfgInitialize(&AxiDma, Config);
+
+	if(!XAxiDma_HasSg(&AxiDma)) {
+		xil_printf("Device configured as Simple mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Set up TX/RX channels to be ready to transmit and receive packets */
+	Status = TxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed TX setup\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = RxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed RX setup\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Set up Interrupt system  */
+	Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID,
+					RX_INTR_ID, 1);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed intr setup\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Initialize flags before start transfer test  */
+	TxDone = 0;
+	RxDone = 0;
+	Error = 0;
+
+	/* Send a packet */
+	Status = SendPacket(&AxiDma, TDEST0, TID0, PACKET0_DATA);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed send packet\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Wait TX done and RX done
+	 */
+	while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
+			(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
+		/* NOP */
+	}
+
+	if (Error) {
+		xil_printf("Failed test transmit%s done, "
+			"receive%s done\r\n", TxDone? "":" not",
+				RxDone? "":" not");
+		goto Done;
+	}else {
+		/*
+		 * Test finished, check data
+		 */
+		Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
+							RxPacket1, PACKET0_DATA);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Data check failed\r\n");
+			goto Done;
+		}
+	}
+
+	xil_printf("Sent Packet with Tdest 0 Successfully\n\r");
+
+	/* Initialize flags before start transfer test  */
+	TxDone = 0;
+	RxDone = 0;
+	Error = 0;
+
+	/* Send a packet */
+	Status = SendPacket(&AxiDma, TDEST1, TID1, PACKET1_DATA);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed send packet\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Wait TX done and RX done
+	 */
+	while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) ||
+		(RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) {
+		/* NOP */
+	}
+
+
+	if (Error) {
+		xil_printf("Failed test transmit%s done, "
+				"receive%s done\r\n", TxDone? "":" not",
+				RxDone? "":" not");
+		goto Done;
+	}else {
+		/*
+		 * Test finished, check data
+		 */
+		Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER,
+					RxPacket0, PACKET1_DATA);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Data check failed\r\n");
+			goto Done;
+		}
+	}
+
+	/* Disable TX and RX Ring interrupts and return success */
+	DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
+
+	xil_printf("Sent Packet with Tdest 1 Successfully\n\r");
+
+	xil_printf("AXI DMA SG interrupt Test passed\r\n");
+
+Done:
+
+	xil_printf("--- Exiting main() --- \r\n");
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This function checks data buffer after the DMA transfer is finished.
+*
+* We use the static tx/rx buffers.
+*
+* @param	Length is the length to check
+* @param	StartValue is the starting value of the first byte
+*
+* @return	- XST_SUCCESS if validation is successful
+*		- XST_FAILURE if validation fails.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckData(int Length, u8 *RxPacket, u8 StartValue)
+{
+	int Index = 0;
+	u8 Value;
+
+	Value = StartValue;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+	Xil_DCacheInvalidateRange((u32)RxPacket, Length);
+
+	for(Index = 0; Index < Length; Index++) {
+		if (RxPacket[Index] != Value) {
+			xil_printf("Data error %d: %x/%x\r\n",
+			    Index, RxPacket[Index], Value);
+
+			return XST_FAILURE;
+		}
+		Value = (Value + 1) & 0xFF;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA TX callback function to be called by TX interrupt handler.
+* This function handles BDs finished by hardware.
+*
+* @param	TxRingPtr is a pointer to TX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void TxCallBack(XAxiDma *AxiDmaPtr)
+{
+	int BdCount;
+	u32 BdSts;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	int Status;
+	int Index;
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(AxiDmaPtr);
+
+	/* Get all processed BDs from hardware */
+	BdCount = XAxiDma_BdRingFromHw(TxRingPtr, XAXIDMA_ALL_BDS, &BdPtr);
+
+	/* Handle the BDs */
+	BdCurPtr = BdPtr;
+	for (Index = 0; Index < BdCount; Index++) {
+
+		/*
+		 * Check the status in each BD
+		 * If error happens, the DMA engine will be halted after this
+		 * BD processing stops.
+		 */
+		BdSts = XAxiDma_BdGetSts(BdCurPtr);
+		if ((BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
+		    (!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK))) {
+
+			Error = 1;
+			break;
+		}
+
+		/*
+		 * Here we don't need to do anything. But if a RTOS is being
+		 * used, we may need to free the packet buffer attached to
+		 * the processed BD
+		 */
+
+		/* Find the next processed BD */
+		BdCurPtr = XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
+	}
+
+	/* Free all processed BDs for future transmission */
+	Status = XAxiDma_BdRingFree(TxRingPtr, BdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		Error = 1;
+	}
+
+	if(!Error) {
+		TxDone += BdCount;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA TX Interrupt handler function.
+*
+* It gets the interrupt status from the hardware, acknowledges it, and if any
+* error happens, it resets the hardware. Otherwise, if a completion interrupt
+* presents, then it calls the callback function.
+*
+* @param	Callback is a pointer to TX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void TxIntrHandler(void *Callback)
+{
+	XAxiDma *AxiDmaPtr = (XAxiDma *) Callback;
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(AxiDmaPtr);
+	u32 IrqStatus;
+	int TimeOut;
+
+	/* Read pending interrupts */
+	IrqStatus = XAxiDma_BdRingGetIrq(TxRingPtr);
+
+	/* Acknowledge pending interrupts */
+	XAxiDma_BdRingAckIrq(TxRingPtr, IrqStatus);
+
+	/* If no interrupt is asserted, we do not do anything
+	 */
+	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
+
+		return;
+	}
+
+	/*
+	 * If error interrupt is asserted, raise error flag, reset the
+	 * hardware to recover from the error, and return with no further
+	 * processing.
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
+
+		Error = 1;
+
+		/*
+		 * Reset should never fail for transmit channel
+		 */
+		XAxiDma_Reset(&AxiDma);
+
+		TimeOut = RESET_TIMEOUT_COUNTER;
+
+		while (TimeOut) {
+			if (XAxiDma_ResetIsDone(&AxiDma)) {
+				break;
+			}
+
+			TimeOut -= 1;
+		}
+
+		return;
+	}
+
+	/*
+	 * If Transmit done interrupt is asserted, call TX call back function
+	 * to handle the processed BDs and raise the according flag
+	 */
+	if ((IrqStatus & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
+		TxCallBack(AxiDmaPtr);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA RX callback function called by the RX interrupt handler.
+* This function handles finished BDs by hardware, attaches new buffers to those
+* BDs, and give them back to hardware to receive more incoming packets
+*
+* @param	RxRingPtr is a pointer to RX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void RxCallBack(XAxiDma *AxiDmaPtr)
+{
+	int BdCount;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	u32 BdSts;
+	int Index;
+	int RingIndex;
+	XAxiDma_BdRing *RxRingPtr;
+
+	for (RingIndex = 0;
+			RingIndex < AxiDmaPtr->RxNumChannels; RingIndex++) {
+
+		RxRingPtr = XAxiDma_GetRxIndexRing(AxiDmaPtr, RingIndex);
+		BdCount = XAxiDma_BdRingFromHw(RxRingPtr, XAXIDMA_ALL_BDS, &BdPtr);
+
+		BdCurPtr = BdPtr;
+		for (Index = 0; Index < BdCount; Index++) {
+
+			/*
+			 * Check the flags set by the hardware for status
+			 * If error happens, processing stops, because the DMA engine
+			 * is halted after this BD.
+			 */
+			BdSts = XAxiDma_BdGetSts(BdCurPtr);
+			if ((BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
+			    (!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK))) {
+				Error = 1;
+				break;
+			}
+
+			/* Find the next processed BD */
+			BdCurPtr = XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+			RxDone += 1;
+		}
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the DMA RX interrupt handler function
+*
+* It gets the interrupt status from the hardware, acknowledges it, and if any
+* error happens, it resets the hardware. Otherwise, if a completion interrupt
+* presents, then it calls the callback function.
+*
+* @param	Callback is a pointer to RX channel of the DMA engine.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void RxIntrHandler(void *Callback)
+{
+	XAxiDma *AxiDmaPtr = (XAxiDma *) Callback;
+
+	XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxIndexRing(AxiDmaPtr, 0);
+
+	u32 IrqStatus;
+	int TimeOut;
+
+
+	/* Read pending interrupts */
+	IrqStatus = XAxiDma_BdRingGetIrq(RxRingPtr);
+
+	/* Acknowledge pending interrupts */
+	XAxiDma_BdRingAckIrq(RxRingPtr, IrqStatus);
+
+	/*
+	 * If no interrupt is asserted, we do not do anything
+	 */
+	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
+		return;
+	}
+
+	/*
+	 * If error interrupt is asserted, raise error flag, reset the
+	 * hardware to recover from the error, and return with no further
+	 * processing.
+	 */
+	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
+
+		Error = 1;
+
+		/* Reset could fail and hang
+		 * NEED a way to handle this or do not call it??
+		 */
+		XAxiDma_Reset(&AxiDma);
+
+		TimeOut = RESET_TIMEOUT_COUNTER;
+
+		while (TimeOut) {
+			if(XAxiDma_ResetIsDone(&AxiDma)) {
+				break;
+			}
+
+			TimeOut -= 1;
+		}
+
+		return;
+	}
+
+	/*
+	 * If completion interrupt is asserted, call RX call back function
+	 * to handle the processed BDs and then raise the according flag.
+	 */
+	if ((IrqStatus & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
+		RxCallBack(AxiDmaPtr);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function setups the interrupt system so interrupts can occur for the
+* DMA, it assumes INTC component exists in the hardware system.
+*
+* @param	IntcInstancePtr is a pointer to the instance of the INTC.
+* @param	AxiDmaPtr is a pointer to the instance of the DMA engine
+* @param	TxIntrId is the TX channel Interrupt ID.
+* @param	RxIntrId is the RX channel Interrupt ID.
+*
+* @return
+*		- XST_SUCCESS if successful,
+*		- XST_FAILURE.if not succesful
+*
+* @note		None.
+*
+******************************************************************************/
+
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			   XAxiDma * AxiDmaPtr, u16 TxIntrId,
+			   u16 RxIntrId, int RingIndex)
+{
+	int Status;
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+
+	/* Initialize the interrupt controller and connect the ISRs */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed init intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
+			       (XInterruptHandler) TxIntrHandler, AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed tx connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
+			       (XInterruptHandler) RxIntrHandler, AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed rx connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Start the interrupt controller */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed to start intc\r\n");
+		return XST_FAILURE;
+	}
+
+	XIntc_Enable(IntcInstancePtr, TxIntrId);
+	XIntc_Enable(IntcInstancePtr, RxIntrId);
+
+#else
+
+	XScuGic_Config *IntcConfig;
+
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+					IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
+				(Xil_InterruptHandler)TxIntrHandler,
+				AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
+				(Xil_InterruptHandler)RxIntrHandler,
+				AxiDmaPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XScuGic_Enable(IntcInstancePtr, TxIntrId);
+	XScuGic_Enable(IntcInstancePtr, RxIntrId);
+#endif
+
+	/* Enable interrupts from the hardware */
+
+	Xil_ExceptionInit();
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+			(Xil_ExceptionHandler)INTC_HANDLER,
+			(void *)IntcInstancePtr);
+
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts for DMA engine.
+*
+* @param	IntcInstancePtr is the pointer to the INTC component instance
+* @param	TxIntrId is interrupt ID associated w/ DMA TX channel
+* @param	RxIntrId is interrupt ID associated w/ DMA RX channel
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+					u16 TxIntrId, u16 RxIntrId)
+{
+#ifdef XPAR_INTC_0_DEVICE_ID
+	/* Disconnect the interrupts for the DMA TX and RX channels */
+	XIntc_Disconnect(IntcInstancePtr, TxIntrId);
+	XIntc_Disconnect(IntcInstancePtr, RxIntrId);
+#else
+	XScuGic_Disconnect(IntcInstancePtr, TxIntrId);
+	XScuGic_Disconnect(IntcInstancePtr, RxIntrId);
+#endif
+}
+
+/*****************************************************************************/
+/*
+*
+* This function sets up RX channel of the DMA engine to be ready for packet
+* reception
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful.
+*		- XST_FAILURE if fails.
+*
+* @note		None.
+*
+******************************************************************************/
+static int RxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *RxRingPtr;
+	int Status;
+	XAxiDma_Bd BdTemplate;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	int BdCount;
+	int FreeBdCount;
+	u32 RxBufferPtr;
+	u32 RxBdSpacePtr;
+	int Index;
+	int RingIndex;
+
+	RxBufferPtr = RX_BUFFER_BASE;
+	RxBdSpacePtr = RX_BD_SPACE_BASE;
+
+	for (RingIndex = 0;
+			RingIndex < AxiDmaInstPtr->RxNumChannels; RingIndex++) {
+
+		RxRingPtr = XAxiDma_GetRxIndexRing(&AxiDma, RingIndex);
+
+		/* Disable all RX interrupts before RxBD space setup */
+		XAxiDma_BdRingIntDisable(RxRingPtr,
+						XAXIDMA_IRQ_ALL_MASK);
+
+		/* Setup Rx BD space */
+		BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+				RX_BD_SPACE_HIGH - RX_BD_SPACE_BASE + 1);
+
+		Status = XAxiDma_BdRingCreate(RxRingPtr,
+					RxBdSpacePtr,
+					RxBdSpacePtr,
+					XAXIDMA_BD_MINIMUM_ALIGNMENT,
+					BdCount);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx bd create failed with %d\r\n",
+				Status);
+			return XST_FAILURE;
+		}
+
+		/*
+		 * Setup a BD template for the Rx channel. Then copy it
+		 * to every RX BD.
+		 */
+		XAxiDma_BdClear(&BdTemplate);
+		Status = XAxiDma_BdRingClone(RxRingPtr,
+						 &BdTemplate);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx bd clone failed with %d\r\n",
+				Status);
+			return XST_FAILURE;
+		}
+
+		/* Attach buffers to RxBD ring so we are ready to receive packets */
+		FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+
+		Status = XAxiDma_BdRingAlloc(RxRingPtr,
+					FreeBdCount, &BdPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx bd alloc failed with %d\r\n",
+				Status);
+			return XST_FAILURE;
+		}
+
+		BdCurPtr = BdPtr;
+
+		for (Index = 0; Index < FreeBdCount; Index++) {
+
+			Status = XAxiDma_BdSetBufAddr(BdCurPtr, RxBufferPtr);
+			if (Status != XST_SUCCESS) {
+				xil_printf("Rx set buffer addr %x on BD %x failed %d\r\n",
+				(unsigned int)RxBufferPtr,
+				(unsigned int)BdCurPtr, Status);
+
+				return XST_FAILURE;
+			}
+
+			Status = XAxiDma_BdSetLength(BdCurPtr, HSIZE,
+						RxRingPtr->MaxTransferLen);
+			if (Status != XST_SUCCESS) {
+				xil_printf("Rx set length %d on BD %x failed %d\r\n",
+				MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
+
+				return XST_FAILURE;
+			}
+
+			/* Receive BDs do not need to set anything for the control
+			 * The hardware will set the SOF/EOF bits per stream status
+			 */
+			XAxiDma_BdSetCtrl(BdCurPtr, 0);
+			XAxiDma_BdSetId(BdCurPtr, RxBufferPtr);
+			XAxiDma_BdSetARCache(BdCurPtr, ARCACHE);
+			XAxiDma_BdSetARUser(BdCurPtr, ARUSER);
+			XAxiDma_BdSetVSize(BdCurPtr, VSIZE);
+			XAxiDma_BdSetStride(BdCurPtr, STRIDE);
+
+			RxBufferPtr += MAX_PKT_LEN;
+			BdCurPtr = XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+		}
+
+		/*
+		 * Set the coalescing threshold, so only one receive interrupt
+		 * occurs for this example
+		 *
+		 * If you would like to have multiple interrupts to happen, change
+		 * the COALESCING_COUNT to be a smaller value
+		 */
+		Status = XAxiDma_BdRingSetCoalesce(RxRingPtr, COALESCING_COUNT,
+				DELAY_TIMER_COUNT);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set coalesce failed with %d\r\n", Status);
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx ToHw failed with %d\r\n", Status);
+			return XST_FAILURE;
+		}
+
+		/* Enable all RX interrupts */
+		XAxiDma_BdRingIntEnable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+		/* Start RX DMA channel */
+		Status = XAxiDma_UpdateBdRingCDesc(RxRingPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Failed bd start %x\r\n", Status);
+			return XST_FAILURE;
+		}
+
+		RxBdSpacePtr += BdCount * sizeof(XAxiDma_Bd);
+
+	}
+
+	for (RingIndex = 0;
+			RingIndex < AxiDmaInstPtr->RxNumChannels; RingIndex++) {
+		RxRingPtr = XAxiDma_GetRxIndexRing(&AxiDma, RingIndex);
+		Status = XAxiDma_StartBdRingHw(RxRingPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx start BD ring failed with %d\r\n", Status);
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function sets up the TX channel of a DMA engine to be ready for packet
+* transmission.
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful.
+*		- XST_FAILURE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+static int TxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+	XAxiDma_Bd BdTemplate;
+	int Status;
+	u32 BdCount;
+
+	u32 TxBdSpacePtr = TX_BD_SPACE_BASE;
+
+	/* Disable all TX interrupts before TxBD space setup */
+	XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Setup TxBD space  */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+			(u32)TX_BD_SPACE_HIGH - (u32)TX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(TxRingPtr, TxBdSpacePtr,
+				TxBdSpacePtr,
+			     XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed create BD ring\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Like the RxBD space, we create a template and set all BDs to be the
+	 * same as the template. The sender has to set up the BDs as needed.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed clone BDs\r\n");
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the coalescing threshold, so only one transmit interrupt
+	 * occurs for this example
+	 *
+	 * If you would like to have multiple interrupts to happen, change
+	 * the COALESCING_COUNT to be a smaller value
+	 */
+	Status = XAxiDma_BdRingSetCoalesce(TxRingPtr, COALESCING_COUNT,
+			DELAY_TIMER_COUNT);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed set coalescing"
+		" %d/%d\r\n",COALESCING_COUNT, DELAY_TIMER_COUNT);
+		return XST_FAILURE;
+	}
+
+	/* Enable all TX interrupts */
+	XAxiDma_BdRingIntEnable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Start the TX channel */
+	Status = XAxiDma_UpdateBdRingCDesc(TxRingPtr);
+		if (Status != XST_SUCCESS) {
+
+			xil_printf("Failed bd start %x\r\n", Status);
+			return XST_FAILURE;
+	}
+
+	Status = XAxiDma_StartBdRingHw(TxRingPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed bd start %x\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function non-blockingly transmits all packets through the DMA engine.
+*
+* @param	AxiDmaInstPtr points to the DMA engine instance
+*
+* @return
+* 		- XST_SUCCESS if the DMA accepts all the packets successfully,
+* 		- XST_FAILURE if error occurs
+*
+* @note		None.
+*
+******************************************************************************/
+static int SendPacket(XAxiDma * AxiDmaInstPtr, u8 TDest, u8 TId, u8 Value)
+{
+	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
+	u8 *TxPacket;
+	XAxiDma_Bd *BdPtr, *BdCurPtr;
+	int Status;
+	int Index, Pkts;
+	u32 BufferAddr;
+
+	/*
+	 * Each packet is limited to TxRingPtr->MaxTransferLen
+	 *
+	 * This will not be the case if hardware has store and forward built in
+	 */
+	if (MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT > TxRingPtr->MaxTransferLen) {
+
+		xil_printf("Invalid total per packet transfer length for the "
+		    "packet %d/%d\r\n",
+		    MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT,
+		    TxRingPtr->MaxTransferLen);
+
+		return XST_INVALID_PARAM;
+	}
+
+	TxPacket = (u8 *) Packet;
+
+	for(Index = 0; Index < MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER;
+					Index ++) {
+		TxPacket[Index] = Value;
+
+		Value = (Value + 1) & 0xFF;
+	}
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN *
+				NUMBER_OF_BDS_TO_TRANSFER);
+
+	Status = XAxiDma_BdRingAlloc(TxRingPtr,
+				NUMBER_OF_BDS_TO_TRANSFER,
+				&BdPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed bd alloc\r\n");
+		return XST_FAILURE;
+	}
+
+	BufferAddr = (u32) TxPacket;
+	BdCurPtr = BdPtr;
+
+	/*
+	 * Set up the BD using the information of the packet to transmit
+	 * Each transfer has NUMBER_OF_BDS_PER_PKT BDs
+	 */
+	for(Index = 0; Index < NUMBER_OF_PKTS_TO_TRANSFER; Index++) {
+
+		for(Pkts = 0; Pkts < NUMBER_OF_BDS_PER_PKT; Pkts++) {
+			u32 CrBits = 0;
+
+			Status = XAxiDma_BdSetBufAddr(BdCurPtr, BufferAddr);
+			if (Status != XST_SUCCESS) {
+				xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
+				(unsigned int)BufferAddr,
+				(unsigned int)BdCurPtr, Status);
+
+				return XST_FAILURE;
+			}
+
+			Status = XAxiDma_BdSetLength(BdCurPtr, HSIZE,
+						TxRingPtr->MaxTransferLen);
+			if (Status != XST_SUCCESS) {
+				xil_printf("Tx set length %d on BD %x failed %d\r\n",
+				MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
+
+				return XST_FAILURE;
+			}
+
+			if (Pkts == 0) {
+				/* The first BD has SOF set
+				 */
+				CrBits |= XAXIDMA_BD_CTRL_TXSOF_MASK;
+
+#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
+				/* The first BD has total transfer length set
+				 * in the last APP word, this is for the
+				 * loopback widget
+				 */
+				Status = XAxiDma_BdSetAppWord(BdCurPtr,
+				    XAXIDMA_LAST_APPWORD,
+				    MAX_PKT_LEN * NUMBER_OF_BDS_PER_PKT);
+
+				if (Status != XST_SUCCESS) {
+					xil_printf("Set app word failed with %d\r\n",
+					Status);
+				}
+#endif
+			}
+
+			if(Pkts == (NUMBER_OF_BDS_PER_PKT - 1)) {
+				/* The last BD should have EOF and IOC set
+				 */
+				CrBits |= XAXIDMA_BD_CTRL_TXEOF_MASK;
+			}
+
+			XAxiDma_BdSetCtrl(BdCurPtr, CrBits);
+			XAxiDma_BdSetId(BdCurPtr, BufferAddr);
+			XAxiDma_BdSetTId(BdCurPtr, TId);
+			XAxiDma_BdSetTDest(BdCurPtr, TDest);
+			XAxiDma_BdSetTUser(BdCurPtr, TUSER);
+			XAxiDma_BdSetARCache(BdCurPtr, ARCACHE);
+			XAxiDma_BdSetARUser(BdCurPtr, ARUSER);
+			XAxiDma_BdSetVSize(BdCurPtr, VSIZE);
+			XAxiDma_BdSetStride(BdCurPtr, STRIDE);
+
+			BufferAddr += MAX_PKT_LEN;
+			BdCurPtr = XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
+		}
+	}
+
+	/* Give the BD to hardware */
+	Status = XAxiDma_BdRingToHw(TxRingPtr, NUMBER_OF_BDS_TO_TRANSFER,
+					BdPtr);
+	if (Status != XST_SUCCESS) {
+
+		xil_printf("Failed to hw, length %d\r\n",
+			(int)XAxiDma_BdGetLength(BdPtr,
+					TxRingPtr->MaxTransferLen));
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_poll_multi_pkts.c b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_poll_multi_pkts.c
new file mode 100644
index 000000000..077e59b6f
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/examples/xaxidma_poll_multi_pkts.c
@@ -0,0 +1,696 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2015 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_poll_multi_pkts.c
+ *
+ * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
+ * DMA core (AXIDMA) to transfer multiple packets in polling mode when the
+ * AXI DMA core is configured in Scatter Gather Mode.
+ *
+ * This code assumes a loopback hardware widget is connected to the AXI DMA
+ * core for data packet loopback.
+ *
+ * To see the debug print, you need a Uart16550 or uartlite in your system,
+ * and please set "-DDEBUG" in your compiler options. You need to rebuild your
+ * software executable.
+ *
+ * Make sure that MEMORY_BASE is defined properly as per the HW system. The
+ * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
+ * throughput mode, it is 512MB.  These limits are need to ensured for
+ * proper operation of this code.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/17/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *		       updated tcl file, added xaxidma_porting_guide.h, removed
+ *		       workaround for endianness
+ * 4.00a rkv  02/22/11 Name of the file has been changed for naming consistency
+ * 5.00a srt  03/06/12 Added Flushing and Invalidation of Caches to fix CRs
+ *		       648103, 648701.
+ *		       Added V7 DDR Base Address to fix CR 649405.
+ * 6.00a srt  03/27/12 Changed API calls to support MCDMA driver.
+ * 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+ * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+/***************************** Include Files *********************************/
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xdebug.h"
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#ifndef DEBUG
+extern void xil_printf(const char *format, ...);
+#endif
+
+/******************** Constant Definitions **********************************/
+
+/*********************** TEMPORARY ******************************************/
+/*
+ * Device hardware build related constants.
+ */
+#define DMA_BASE_ADDR		XPAR_AXIDMA_0_BASEADDR
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+		DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR		0x01000000
+#else
+#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#define TX_BD_SPACE_BASE	(MEM_BASE_ADDR)
+#define TX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x00000FFF)
+#define RX_BD_SPACE_BASE	(MEM_BASE_ADDR + 0x00001000)
+#define RX_BD_SPACE_HIGH	(MEM_BASE_ADDR + 0x00001FFF)
+#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00020000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00030000)
+#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x0003FFFF)
+
+#define MAX_PKT_LEN		0x200
+#define NUMBER_OF_PACKETS 	0x10
+#define TEST_START_VALUE	0xC
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+static void Uart550_Setup(void);
+#endif
+
+static int RxSetup(XAxiDma * AxiDmaInstPtr);
+static int TxSetup(XAxiDma * AxiDmaInstPtr);
+static int SendPackets(XAxiDma * AxiDmaInstPtr);
+static int CheckData(void);
+static int CheckDmaResult(XAxiDma * AxiDmaInstPtr);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XAxiDma AxiDma;
+
+/*
+ * Buffer for transmit packet.
+ */
+u32 *Packet = (u32 *) TX_BUFFER_BASE;
+
+static XAxiDma_Bd *LastRxBdPtr = NULL;
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the tests on DMA core. It sets up
+* DMA engine to be ready to receive and send packets, then a packet is
+* transmitted and will be verified after it is received via the DMA loopback
+* widget.
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if test pass,
+* 		- XST_FAILURE if test fails
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+	XAxiDma_Config *Config;
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+
+	Uart550_Setup();
+
+#endif
+
+	xil_printf("\r\n--- Entering main() --- \r\n");
+
+	Config = XAxiDma_LookupConfig(DMA_DEV_ID);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DMA_DEV_ID);
+
+		return XST_FAILURE;
+	}
+
+	/* Initialize DMA engine */
+	Status = XAxiDma_CfgInitialize(&AxiDma, Config);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	if(!XAxiDma_HasSg(&AxiDma)) {
+		xil_printf("Device configured as simple mode \r\n");
+
+		return XST_FAILURE;
+	}
+
+	Status = TxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Status = RxSetup(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Send packets */
+	Status = SendPackets(&AxiDma);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Check DMA transfer result */
+
+	Status = CheckDmaResult(&AxiDma);
+
+	xil_printf("Test %s\r\n",
+		(Status == XST_SUCCESS)? "passed":"failed");
+
+	xil_printf("--- Exiting main() --- \r\n");
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+#if defined(XPAR_UARTNS550_0_BASEADDR)
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None.
+*
+
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+	/* Set the baudrate to be predictable
+	 */
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets up RX channel of the DMA engine to be ready for packet
+* reception
+*
+* @param	AxiDmaInstPtr is the pointer to the instance of the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful
+*		- XST_FAILURE if setup is failure
+*
+* @note		None.
+*
+******************************************************************************/
+static int RxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *RxRingPtr;
+	int Delay = 0;
+	int Coalesce = 1;
+	int Status;
+	XAxiDma_Bd BdTemplate;
+	XAxiDma_Bd *BdPtr;
+	XAxiDma_Bd *BdCurPtr;
+	u32 BdCount;
+	u32 FreeBdCount;
+	u32 RxBufferPtr;
+	int i;
+
+	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
+
+	/* Disable all RX interrupts before RxBD space setup */
+
+	XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set delay and coalescing */
+	XAxiDma_BdRingSetCoalesce(RxRingPtr, Coalesce, Delay);
+
+	/* Setup Rx BD space */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+				RX_BD_SPACE_HIGH - RX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(RxRingPtr, RX_BD_SPACE_BASE,
+				RX_BD_SPACE_BASE,
+				XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup an all-zero BD as the template for the Rx channel.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+
+	Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Attach buffers to RxBD ring so we are ready to receive packets
+	 */
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	BdCurPtr = BdPtr;
+	RxBufferPtr = RX_BUFFER_BASE;
+
+	for (i = 0; i < FreeBdCount; i++) {
+
+		Status = XAxiDma_BdSetBufAddr(BdCurPtr, RxBufferPtr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set buffer addr %x on BD %x failed %d\r\n",
+			(unsigned int)RxBufferPtr, (unsigned int)BdCurPtr,
+								Status);
+
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdSetLength(BdCurPtr, MAX_PKT_LEN,
+				RxRingPtr->MaxTransferLen);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Rx set length %d on BD %x failed %d\r\n",
+			    MAX_PKT_LEN, (unsigned int)BdCurPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		/* Receive BDs do not need to set anything for the control
+		 * The hardware will set the SOF/EOF bits per stream status
+		 */
+		XAxiDma_BdSetCtrl(BdPtr, 0);
+		XAxiDma_BdSetId(BdCurPtr, RxBufferPtr);
+		RxBufferPtr += MAX_PKT_LEN;
+
+		if (i == (FreeBdCount - 1)) {
+			LastRxBdPtr = BdCurPtr;
+		}
+
+		BdCurPtr = XAxiDma_BdRingNext(RxRingPtr, BdCurPtr);
+	}
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Start RX DMA channel */
+	Status = XAxiDma_BdRingStart(RxRingPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the TX channel of a DMA engine to be ready for packet
+* transmission
+*
+* @param	AxiDmaInstPtr is the instance pointer to the DMA engine.
+*
+* @return	- XST_SUCCESS if the setup is successful
+*		- XST_FAILURE if setup is failure
+*
+* @note     None.
+*
+******************************************************************************/
+static int TxSetup(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_Bd BdTemplate;
+	int Delay = 0;
+	int Coalesce = 1;
+	int Status;
+	u32 BdCount;
+
+	TxRingPtr = XAxiDma_GetTxRing(&AxiDma);
+
+	/* Disable all TX interrupts before Tx BD space setup */
+
+	XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set TX delay and coalesce */
+	XAxiDma_BdRingSetCoalesce(TxRingPtr, Coalesce, Delay);
+
+	/* Setup Tx BD space  */
+	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
+				TX_BD_SPACE_HIGH - TX_BD_SPACE_BASE + 1);
+
+	Status = XAxiDma_BdRingCreate(TxRingPtr, TX_BD_SPACE_BASE,
+				TX_BD_SPACE_BASE,
+				XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed create BD ring in txsetup\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/*
+	 * We create an all-zero BD as the template.
+	 */
+	XAxiDma_BdClear(&BdTemplate);
+
+	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed bdring clone in txsetup %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	/* Start the TX channel */
+	Status = XAxiDma_BdRingStart(TxRingPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("failed start bdring txsetup %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function transmits packets non-blockingly through the DMA engine.
+*
+* @param	AxiDmaInstPtr points to the DMA engine instance
+*
+* @return	- XST_SUCCESS if the DMA accepts the packet successfully,
+*		- XST_FAILURE if failure.
+*
+* @note		None.
+*
+******************************************************************************/
+static int SendPackets(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	u8 *TxPacket;
+	u8 Value;
+	XAxiDma_Bd *BdPtr;
+	int Status;
+	int i;
+	u32 BufAddr;
+	XAxiDma_Bd *CurBdPtr;
+
+	/* Create pattern in the packet to transmit
+	 */
+	TxPacket = (u8 *) Packet;
+
+	Value = TEST_START_VALUE;
+
+	for(i = 0; i < MAX_PKT_LEN * NUMBER_OF_PACKETS; i ++) {
+		TxPacket[i] = Value;
+
+		Value = (Value + 1) & 0xFF;
+	}
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
+	 * is enabled
+	 */
+	Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN *
+							NUMBER_OF_PACKETS);
+
+	TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
+
+	/* Allocate BDs */
+	Status = XAxiDma_BdRingAlloc(TxRingPtr, NUMBER_OF_PACKETS, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Set up the BDs using the information of the packet to transmit */
+	BufAddr = (u32)Packet;
+	CurBdPtr = BdPtr;
+
+	for (i = 0; i < NUMBER_OF_PACKETS; i++) {
+		u32 CrBits = 0;
+
+		Status = XAxiDma_BdSetBufAddr(CurBdPtr, BufAddr);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n",
+			(unsigned int)BufAddr, (unsigned int)CurBdPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		Status = XAxiDma_BdSetLength(CurBdPtr, MAX_PKT_LEN,
+				TxRingPtr->MaxTransferLen);
+		if (Status != XST_SUCCESS) {
+			xil_printf("Tx set length %d on BD %x failed %d\r\n",
+			    MAX_PKT_LEN, (unsigned int)CurBdPtr, Status);
+
+			return XST_FAILURE;
+		}
+
+		if (i == 0) {
+			CrBits |= XAXIDMA_BD_CTRL_TXSOF_MASK;
+
+#if (XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM == 1)
+			/* The first BD has total transfer length set in
+			 * the last APP word, this is for the loopback widget
+			 */
+			Status = XAxiDma_BdSetAppWord(CurBdPtr,
+			    XAXIDMA_LAST_APPWORD,
+			    MAX_PKT_LEN * NUMBER_OF_PACKETS);
+
+			if (Status != XST_SUCCESS) {
+				xil_printf("Set app word failed with %d\r\n",
+								Status);
+			}
+#endif
+		}
+		if (i == (NUMBER_OF_PACKETS - 1)) {
+			CrBits |= XAXIDMA_BD_CTRL_TXEOF_MASK;
+			XAxiDma_BdSetCtrl(CurBdPtr,
+					XAXIDMA_BD_CTRL_TXEOF_MASK);
+		}
+		XAxiDma_BdSetCtrl(CurBdPtr, CrBits);
+
+		XAxiDma_BdSetId(CurBdPtr, BufAddr);
+
+		BufAddr += MAX_PKT_LEN;
+		CurBdPtr = XAxiDma_BdRingNext(TxRingPtr, CurBdPtr);
+	}
+
+	/* Give the BD to DMA to kick off the transmission. */
+	Status = XAxiDma_BdRingToHw(TxRingPtr, NUMBER_OF_PACKETS, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("to hw failed %d\r\n", Status);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks data buffer after the DMA transfer is finished.
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if validation is successful
+*		- XST_FAILURE if validation is failure.
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckData(void)
+{
+	u8 *RxPacket;
+	int i = 0;
+	u8 Value;
+
+	RxPacket = (u8 *) RX_BUFFER_BASE;
+	Value = TEST_START_VALUE;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+	Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN *
+								NUMBER_OF_PACKETS);
+
+	for(i = 0; i < MAX_PKT_LEN * NUMBER_OF_PACKETS; i++) {
+		if (RxPacket[i] != Value) {
+			xil_printf("Data error %d: %x/%x\r\n",
+			    i, (unsigned int)RxPacket[i], (unsigned int)Value);
+
+			return XST_FAILURE;
+		}
+		Value = (Value + 1) & 0xFF;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function delays until the DMA transaction is finished, checks data,
+* and cleans up.
+*
+* @param	AxiDmaInstPtr points to the DMA engine instance
+*
+* @return	- XST_SUCCESS if DMA transfer is successful and data is correct
+*		- XST_FAILURE if failure
+*
+* @note		None.
+*
+******************************************************************************/
+static int CheckDmaResult(XAxiDma * AxiDmaInstPtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+	XAxiDma_Bd *BdPtr;
+	u32 ProcessedBdCount = 0;
+	u32 FreeBdCount;
+	int Status;
+
+	TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr);
+	RxRingPtr = XAxiDma_GetRxRing(AxiDmaInstPtr);
+
+	/* Wait until the TX transactions are done */
+	while (ProcessedBdCount < NUMBER_OF_PACKETS) {
+		ProcessedBdCount += XAxiDma_BdRingFromHw(TxRingPtr,
+					       XAXIDMA_ALL_BDS, &BdPtr);
+	}
+
+	/* Free all processed TX BDs for future transmission */
+	Status = XAxiDma_BdRingFree(TxRingPtr, ProcessedBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Wait until the data has been received by the Rx channel */
+	ProcessedBdCount = 0;
+
+	while (ProcessedBdCount < NUMBER_OF_PACKETS) {
+
+		ProcessedBdCount += XAxiDma_BdRingFromHw(RxRingPtr,
+					       XAXIDMA_ALL_BDS, &BdPtr);
+	}
+
+
+	/* Check received data */
+	if (CheckData() != XST_SUCCESS) {
+
+		return XST_FAILURE;
+	}
+
+	/* Free all processed RX BDs for future transmission */
+	Status = XAxiDma_BdRingFree(RxRingPtr, ProcessedBdCount, BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("free bd failed\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Return processed BDs to RX channel so we are ready to receive new
+	 * packets:
+	 *    - Allocate all free RX BDs
+	 *    - Pass the BDs to RX channel
+	 */
+	FreeBdCount = XAxiDma_BdRingGetFreeCnt(RxRingPtr);
+	Status = XAxiDma_BdRingAlloc(RxRingPtr, FreeBdCount, &BdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("bd alloc failed\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_BdRingToHw(RxRingPtr, FreeBdCount, BdPtr);
+
+	return Status;
+}
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/Makefile b/thirdparty/xilinx/orig/axidma_v9_0/src/Makefile
new file mode 100644
index 000000000..f4e121b7b
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/Makefile
@@ -0,0 +1,27 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+	echo "Compiling axidma"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf $(OUTS)
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma.c b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma.c
new file mode 100644
index 000000000..54ece7f0f
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma.c
@@ -0,0 +1,974 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma.c
+* @addtogroup axidma_v9_0
+* @{
+*
+* This file implements DMA engine-wise initialization and control functions.
+* For more information on the implementation of this driver, see xaxidma.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+*		      New API added for simple DMA mode are
+*			- XAxiDma_Busy
+*			- XAxiDma_SimpleTransfer
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode.
+*		      - Changed APIs:
+*			* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*        					u32 BuffAddr, u32 Length,
+*						int Direction, int RingIndex)
+*		      - New API:
+*			* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+* 7.01a srt  10/26/12  Fixed issue with driver as it fails with IP version
+*		       < 6.00a as the parameter C_NUM_*_CHANNELS is not
+*		       applicable.
+* 8.0   srt  01/29/14  Added support for Micro DMA Mode and Cyclic mode of
+*		       operations.
+*		      - New API:
+*			* XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xaxidma.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Loop counter to check reset done
+ */
+#define XAXIDMA_RESET_TIMEOUT	500
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+static int XAxiDma_Start(XAxiDma * InstancePtr);
+static int XAxiDma_Started(XAxiDma * InstancePtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * This function initializes a DMA engine.  This function must be called
+ * prior to using a DMA engine. Initializing a engine includes setting
+ * up the register base address, setting up the instance data, and ensuring the
+ * hardware is in a quiescent state.
+ *
+ * @param	InstancePtr is a pointer to the DMA engine instance to be
+ *		worked on.
+ * @param	Config is a pointer to an XAxiDma_Config structure. It contains
+ *		the information about the hardware build, including base
+ *		address,and whether status control stream (StsCntrlStrm), MM2S
+ *		and S2MM are included in the build.
+ *
+ * @return
+ * 		- XST_SUCCESS for successful initialization
+ * 		- XST_INVALID_PARAM if pointer to the configuration structure
+ *		is NULL
+ * 		- XST_DMA_ERROR if reset operation failed at the end of
+ *		initialization
+ *
+ * @note	We assume the hardware building tool will check and error out
+ *		for a hardware build that has no transfer channels.
+ *****************************************************************************/
+int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config)
+{
+	u32 BaseAddr;
+	int TimeOut;
+	int Index;
+	u32 MaxTransferLen;
+
+	InstancePtr->Initialized = 0;
+
+	if(!Config) {
+		return XST_INVALID_PARAM;
+	}
+
+	BaseAddr = Config->BaseAddr;
+
+	/* Setup the instance */
+	memset(InstancePtr, 0, sizeof(XAxiDma));
+	InstancePtr->RegBase = BaseAddr;
+
+	/* Get hardware setting information from the configuration structure
+	 */
+	InstancePtr->HasMm2S = Config->HasMm2S;
+	InstancePtr->HasS2Mm = Config->HasS2Mm;
+
+	InstancePtr->HasSg = Config->HasSg;
+
+	InstancePtr->MicroDmaMode = Config->MicroDmaMode;
+	InstancePtr->AddrWidth = Config->AddrWidth;
+
+	/* Get the number of channels */
+	InstancePtr->TxNumChannels = Config->Mm2sNumChannels;
+	InstancePtr->RxNumChannels = Config->S2MmNumChannels;
+
+	/* This condition is for IP version < 6.00a */
+	if (!InstancePtr->TxNumChannels)
+		InstancePtr->TxNumChannels = 1;
+	if (!InstancePtr->RxNumChannels)
+		InstancePtr->RxNumChannels = 1;
+
+	if ((InstancePtr->RxNumChannels > 1) ||
+		(InstancePtr->TxNumChannels > 1)) {
+		MaxTransferLen =
+			XAXIDMA_MCHAN_MAX_TRANSFER_LEN;
+	}
+	else {
+		MaxTransferLen =
+			XAXIDMA_MAX_TRANSFER_LEN;
+	}
+
+	/* Initialize the ring structures */
+	InstancePtr->TxBdRing.RunState = AXIDMA_CHANNEL_HALTED;
+	InstancePtr->TxBdRing.IsRxChannel = 0;
+	if (!InstancePtr->MicroDmaMode) {
+		InstancePtr->TxBdRing.MaxTransferLen = MaxTransferLen;
+	}
+	else {
+		/* In MicroDMA mode, Maximum length that can be transferred
+		 * is '(Memory Data Width / 4) * Burst Size'
+		 */
+		InstancePtr->TxBdRing.MaxTransferLen =
+				((Config->Mm2SDataWidth / 4) *
+				 Config->Mm2SBurstSize);
+	}
+	InstancePtr->TxBdRing.RingIndex = 0;
+
+	for (Index = 0; Index < InstancePtr->RxNumChannels; Index++) {
+		InstancePtr->RxBdRing[Index].RunState
+						 = AXIDMA_CHANNEL_HALTED;
+		InstancePtr->RxBdRing[Index].IsRxChannel = 1;
+		InstancePtr->RxBdRing[Index].RingIndex = Index;
+	}
+
+	if (InstancePtr->HasMm2S) {
+		InstancePtr->TxBdRing.ChanBase =
+				BaseAddr + XAXIDMA_TX_OFFSET;
+		InstancePtr->TxBdRing.HasStsCntrlStrm =
+					Config->HasStsCntrlStrm;
+		if (InstancePtr->AddrWidth > 32)
+			InstancePtr->TxBdRing.Addr_ext = 1;
+		else
+			InstancePtr->TxBdRing.Addr_ext = 0;
+
+		InstancePtr->TxBdRing.HasDRE = Config->HasMm2SDRE;
+		InstancePtr->TxBdRing.DataWidth =
+			((unsigned int)Config->Mm2SDataWidth >> 3);
+	}
+
+	if (InstancePtr->HasS2Mm) {
+		for (Index = 0;
+			Index < InstancePtr->RxNumChannels; Index++) {
+			InstancePtr->RxBdRing[Index].ChanBase =
+					BaseAddr + XAXIDMA_RX_OFFSET;
+			InstancePtr->RxBdRing[Index].HasStsCntrlStrm =
+					Config->HasStsCntrlStrm;
+			InstancePtr->RxBdRing[Index].HasDRE =
+					Config->HasS2MmDRE;
+			InstancePtr->RxBdRing[Index].DataWidth =
+			((unsigned int)Config->S2MmDataWidth >> 3);
+
+			if (!InstancePtr->MicroDmaMode) {
+				InstancePtr->RxBdRing[Index].MaxTransferLen =
+							MaxTransferLen;
+			}
+			else {
+			/* In MicroDMA mode, Maximum length that can be transferred
+			 * is '(Memory Data Width / 4) * Burst Size'
+			 */
+				InstancePtr->RxBdRing[Index].MaxTransferLen =
+						((Config->S2MmDataWidth / 4) *
+						Config->S2MmBurstSize);
+			}
+			if (InstancePtr->AddrWidth > 32)
+				InstancePtr->RxBdRing[Index].Addr_ext = 1;
+			else
+				InstancePtr->RxBdRing[Index].Addr_ext = 0;
+		}
+	}
+
+	/* Reset the engine so the hardware starts from a known state
+	 */
+	XAxiDma_Reset(InstancePtr);
+
+	/* At the initialization time, hardware should finish reset quickly
+	 */
+	TimeOut = XAXIDMA_RESET_TIMEOUT;
+
+	while (TimeOut) {
+
+		if(XAxiDma_ResetIsDone(InstancePtr)) {
+			break;
+		}
+
+		TimeOut -= 1;
+
+	}
+
+	if (!TimeOut) {
+		xdbg_printf(XDBG_DEBUG_ERROR, "Failed reset in"
+							"initialize\r\n");
+
+		/* Need system hard reset to recover
+		 */
+		InstancePtr->Initialized = 0;
+		return XST_DMA_ERROR;
+	}
+
+	/* Initialization is successful
+	 */
+	InstancePtr->Initialized = 1;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Reset both TX and RX channels of a DMA engine.
+*
+* Reset one channel resets the whole AXI DMA engine.
+*
+* Any DMA transaction in progress will finish gracefully before engine starts
+* reset. Any other transactions that have been submitted to hardware will be
+* discarded by the hardware.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	None
+*
+* @note		After the reset:
+*		- All interrupts are disabled.
+*		- Engine is halted
+*
+******************************************************************************/
+void XAxiDma_Reset(XAxiDma * InstancePtr)
+{
+	u32 RegBase;
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+	int RingIndex;
+
+	TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
+
+	/* Save the locations of current BDs both rings are working on
+	 * before the reset so later we can resume the rings smoothly.
+	 */
+	if(XAxiDma_HasSg(InstancePtr)){
+		XAxiDma_BdRingSnapShotCurrBd(TxRingPtr);
+
+		for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
+						RingIndex++) {
+			RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr,
+						RingIndex);
+			XAxiDma_BdRingSnapShotCurrBd(RxRingPtr);
+		}
+	}
+
+	/* Reset
+	 */
+	if (InstancePtr->HasMm2S) {
+		RegBase = InstancePtr->RegBase + XAXIDMA_TX_OFFSET;
+	}
+	else {
+		RegBase = InstancePtr->RegBase + XAXIDMA_RX_OFFSET;
+	}
+
+	XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
+
+	/* Set TX/RX Channel state */
+	if (InstancePtr->HasMm2S) {
+		TxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
+	}
+
+	for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
+					RingIndex++) {
+		RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex);
+		if (InstancePtr->HasS2Mm) {
+			RxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Check whether reset is done
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+* 		- 1 if reset is done.
+*		- 0 if reset is not done
+*
+* @note		None
+*
+******************************************************************************/
+int XAxiDma_ResetIsDone(XAxiDma * InstancePtr)
+{
+	u32 RegisterValue;
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+
+	TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
+	RxRingPtr = XAxiDma_GetRxRing(InstancePtr);
+
+	/* Check transmit channel
+	 */
+	if (InstancePtr->HasMm2S) {
+		RegisterValue = XAxiDma_ReadReg(TxRingPtr->ChanBase,
+			XAXIDMA_CR_OFFSET);
+
+		/* Reset is done when the reset bit is low
+		 */
+		if(RegisterValue & XAXIDMA_CR_RESET_MASK) {
+
+			return 0;
+		}
+	}
+
+	/* Check receive channel
+	 */
+	if (InstancePtr->HasS2Mm) {
+		RegisterValue = XAxiDma_ReadReg(RxRingPtr->ChanBase,
+				XAXIDMA_CR_OFFSET);
+
+		/* Reset is done when the reset bit is low
+		 */
+		if(RegisterValue & XAXIDMA_CR_RESET_MASK) {
+
+			return 0;
+		}
+	}
+
+	return 1;
+}
+/*****************************************************************************/
+/*
+* Start the DMA engine.
+*
+* Start a halted engine. Processing of BDs is not started.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+* 		- XST_SUCCESS for success
+* 		- XST_NOT_SGDMA if the driver instance has not been initialized
+* 		- XST_DMA_ERROR if starting the hardware channel fails
+*
+* @note		None
+*
+*****************************************************************************/
+static int XAxiDma_Start(XAxiDma * InstancePtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+	int Status;
+	int RingIndex = 0;
+
+	if (!InstancePtr->Initialized) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Start: Driver not initialized "
+				"%d\r\n", InstancePtr->Initialized);
+
+		return XST_NOT_SGDMA;
+	}
+
+	if (InstancePtr->HasMm2S) {
+		TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
+
+		if (TxRingPtr->RunState == AXIDMA_CHANNEL_HALTED) {
+
+			/* Start the channel
+			 */
+			if(XAxiDma_HasSg(InstancePtr)) {
+				Status = XAxiDma_BdRingStart(TxRingPtr);
+				if (Status != XST_SUCCESS) {
+					xdbg_printf(XDBG_DEBUG_ERROR,
+					"Start hw tx channel failed %d\r\n",
+								Status);
+
+					return XST_DMA_ERROR;
+				}
+			}
+			else {
+				XAxiDma_WriteReg(TxRingPtr->ChanBase,
+					XAXIDMA_CR_OFFSET,
+					XAxiDma_ReadReg(TxRingPtr->ChanBase,
+					XAXIDMA_CR_OFFSET)
+					| XAXIDMA_CR_RUNSTOP_MASK);
+			}
+			TxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
+		}
+	}
+
+	if (InstancePtr->HasS2Mm) {
+
+		for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
+						RingIndex++) {
+			RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr,
+							 RingIndex);
+
+			if (RxRingPtr->RunState != AXIDMA_CHANNEL_HALTED) {
+				return XST_SUCCESS;
+			}
+
+			/* Start the channel
+			 */
+			if(XAxiDma_HasSg(InstancePtr)) {
+				Status = XAxiDma_BdRingStart(RxRingPtr);
+				if (Status != XST_SUCCESS) {
+					xdbg_printf(XDBG_DEBUG_ERROR,
+					"Start hw tx channel failed %d\r\n",
+								Status);
+
+					return XST_DMA_ERROR;
+				}
+			}
+			else {
+				XAxiDma_WriteReg(RxRingPtr->ChanBase,
+					XAXIDMA_CR_OFFSET,
+					XAxiDma_ReadReg(RxRingPtr->ChanBase,
+					XAXIDMA_CR_OFFSET) |
+					XAXIDMA_CR_RUNSTOP_MASK);
+			}
+
+			RxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
+		}
+	}
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+* Pause DMA transactions on both channels.
+*
+* If the engine is running and doing transfers, this function does not stop
+* the DMA transactions immediately, because then hardware will throw away
+* our previously queued transfers. All submitted transfers will finish.
+* Transfers submitted after this function will not start until
+* XAxiDma_BdRingStart() or XAxiDma_Resume() is called.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+* 		- XST_SUCCESS if successful
+* 		- XST_NOT_SGDMA, if the driver instance is not initialized
+*
+* @note		None
+*
+*****************************************************************************/
+int XAxiDma_Pause(XAxiDma * InstancePtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+	int RingIndex = 0;
+
+	if (!InstancePtr->Initialized) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Pause: Driver not initialized"
+					" %d\r\n",InstancePtr->Initialized);
+
+		return XST_NOT_SGDMA;
+	}
+
+	if (InstancePtr->HasMm2S) {
+		TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
+
+		/* If channel is halted, then we do not need to do anything
+		 */
+		if(!XAxiDma_HasSg(InstancePtr)) {
+			XAxiDma_WriteReg(TxRingPtr->ChanBase,
+				XAXIDMA_CR_OFFSET,
+				XAxiDma_ReadReg(TxRingPtr->ChanBase,
+				XAXIDMA_CR_OFFSET)
+				& ~XAXIDMA_CR_RUNSTOP_MASK);
+		}
+
+		TxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
+	}
+
+	if (InstancePtr->HasS2Mm) {
+		for (RingIndex = 0; RingIndex < InstancePtr->RxNumChannels;
+				RingIndex++) {
+			RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex);
+
+			/* If channel is halted, then we do not need to do anything
+			 */
+
+			if(!XAxiDma_HasSg(InstancePtr) && !RingIndex) {
+				XAxiDma_WriteReg(RxRingPtr->ChanBase,
+					XAXIDMA_CR_OFFSET,
+					XAxiDma_ReadReg(RxRingPtr->ChanBase,
+					XAXIDMA_CR_OFFSET)
+					& ~XAXIDMA_CR_RUNSTOP_MASK);
+			}
+
+			RxRingPtr->RunState = AXIDMA_CHANNEL_HALTED;
+		}
+	}
+
+	return XST_SUCCESS;
+
+}
+
+/*****************************************************************************/
+/**
+* Resume DMA transactions on both channels.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+*		- XST_SUCCESS for success
+*		- XST_NOT_SGDMA if the driver instance has not been initialized
+*		- XST_DMA_ERROR if one of the channels fails to start
+*
+* @note		None
+*
+*****************************************************************************/
+int XAxiDma_Resume(XAxiDma * InstancePtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+	int Status;
+	int RingIndex = 0;
+
+	if (!InstancePtr->Initialized) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Resume: Driver not initialized"
+		" %d\r\n",InstancePtr->Initialized);
+
+		return XST_NOT_SGDMA;
+	}
+
+	/* If the DMA engine is not running, start it. Start may fail.
+	 */
+	if (!XAxiDma_Started(InstancePtr)) {
+		Status = XAxiDma_Start(InstancePtr);
+
+		if (Status != XST_SUCCESS) {
+			xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed to start"
+				" engine %d\r\n", Status);
+
+			return Status;
+		}
+	}
+
+	/* Mark the state to be not halted
+	 */
+	if (InstancePtr->HasMm2S) {
+		TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
+
+		if(XAxiDma_HasSg(InstancePtr)) {
+			Status = XAxiDma_BdRingStart(TxRingPtr);
+			if (Status != XST_SUCCESS) {
+				xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed"
+				" to start tx ring %d\r\n", Status);
+
+				return XST_DMA_ERROR;
+			}
+		}
+
+		TxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
+	}
+
+	if (InstancePtr->HasS2Mm) {
+		for (RingIndex = 0 ; RingIndex < InstancePtr->RxNumChannels;
+					RingIndex++) {
+			RxRingPtr = XAxiDma_GetRxIndexRing(InstancePtr, RingIndex);
+
+			if(XAxiDma_HasSg(InstancePtr)) {
+				Status = XAxiDma_BdRingStart(RxRingPtr);
+				if (Status != XST_SUCCESS) {
+					xdbg_printf(XDBG_DEBUG_ERROR, "Resume: failed"
+					"to start rx ring %d\r\n", Status);
+
+					return XST_DMA_ERROR;
+				}
+			}
+
+			RxRingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* Check whether the DMA engine is started.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+*		- 1 if engine is started
+*		- 0 otherwise.
+*
+* @note		None
+*
+*****************************************************************************/
+static int XAxiDma_Started(XAxiDma * InstancePtr)
+{
+	XAxiDma_BdRing *TxRingPtr;
+	XAxiDma_BdRing *RxRingPtr;
+
+	if (!InstancePtr->Initialized) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Started: Driver not initialized"
+		" %d\r\n",InstancePtr->Initialized);
+
+		return 0;
+	}
+
+	if (InstancePtr->HasMm2S) {
+		TxRingPtr = XAxiDma_GetTxRing(InstancePtr);
+
+		if (!XAxiDma_BdRingHwIsStarted(TxRingPtr)) {
+			xdbg_printf(XDBG_DEBUG_ERROR,
+				"Started: tx ring not started\r\n");
+
+			return 0;
+		}
+	}
+
+	if (InstancePtr->HasS2Mm) {
+		RxRingPtr = XAxiDma_GetRxRing(InstancePtr);
+
+		if (!XAxiDma_BdRingHwIsStarted(RxRingPtr)) {
+			xdbg_printf(XDBG_DEBUG_ERROR,
+				"Started: rx ring not started\r\n");
+
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+/*****************************************************************************/
+/**
+ * This function checks whether specified DMA channel is busy
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ *
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	- TRUE if channel is busy
+ *		- FALSE if channel is idle
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+u32 XAxiDma_Busy(XAxiDma *InstancePtr, int Direction)
+{
+
+	return ((XAxiDma_ReadReg(InstancePtr->RegBase +
+				(XAXIDMA_RX_OFFSET * Direction),
+				XAXIDMA_SR_OFFSET) &
+				XAXIDMA_IDLE_MASK) ? FALSE : TRUE);
+}
+
+
+/*****************************************************************************/
+/**
+ * This function Enable or Disable KeyHole Feature
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ *
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @Select	Select is the option to enable (TRUE) or disable (FALSE).
+ *
+ * @return	- XST_SUCCESS for success
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select)
+{
+	u32 Value;
+
+	Value = XAxiDma_ReadReg(InstancePtr->RegBase +
+				(XAXIDMA_RX_OFFSET * Direction),
+				XAXIDMA_CR_OFFSET);
+
+	if (Select)
+		Value |= XAXIDMA_CR_KEYHOLE_MASK;
+	else
+		Value &= ~XAXIDMA_CR_KEYHOLE_MASK;
+
+	XAxiDma_WriteReg(InstancePtr->RegBase +
+			(XAXIDMA_RX_OFFSET * Direction),
+			XAXIDMA_CR_OFFSET, Value);
+
+	return XST_SUCCESS;
+
+}
+
+/*****************************************************************************/
+/**
+ * This function Enable or Disable Cyclic Mode Feature
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ *
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @Select	Select is the option to enable (TRUE) or disable (FALSE).
+ *
+ * @return	- XST_SUCCESS for success
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select)
+{
+	u32 Value;
+
+	Value = XAxiDma_ReadReg(InstancePtr->RegBase +
+				(XAXIDMA_RX_OFFSET * Direction),
+				XAXIDMA_CR_OFFSET);
+
+	if (Select)
+		Value |= XAXIDMA_CR_CYCLIC_MASK;
+	else
+		Value &= ~XAXIDMA_CR_CYCLIC_MASK;
+
+	XAxiDma_WriteReg(InstancePtr->RegBase +
+			(XAXIDMA_RX_OFFSET * Direction),
+			XAXIDMA_CR_OFFSET, Value);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This function does one simple transfer submission
+ *
+ * It checks in the following sequence:
+ *	- if engine is busy, cannot submit
+ *	- if engine is in SG mode , cannot submit
+ *
+ * @param	InstancePtr is the pointer to the driver instance
+ * @param	BuffAddr is the address of the source/destination buffer
+ * @param	Length is the length of the transfer
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+
+ * @return
+ *		- XST_SUCCESS for success of submission
+ *		- XST_FAILURE for submission failure, maybe caused by:
+ *		Another simple transfer is still going
+ *		- XST_INVALID_PARAM if:Length out of valid range [1:8M]
+ *		Or, address not aligned when DRE is not built in
+ *
+ * @note	This function is used only when system is configured as
+ *		Simple mode.
+ *
+ *****************************************************************************/
+u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
+	int Direction)
+{
+	u32 WordBits;
+	int RingIndex = 0;
+
+	/* If Scatter Gather is included then, cannot submit
+	 */
+	if (XAxiDma_HasSg(InstancePtr)) {
+		xdbg_printf(XDBG_DEBUG_ERROR, "Simple DMA mode is not"
+							" supported\r\n");
+
+		return XST_FAILURE;
+	}
+
+	if(Direction == XAXIDMA_DMA_TO_DEVICE){
+		if ((Length < 1) ||
+			(Length > InstancePtr->TxBdRing.MaxTransferLen)) {
+			return XST_INVALID_PARAM;
+		}
+
+		if (!InstancePtr->HasMm2S) {
+			xdbg_printf(XDBG_DEBUG_ERROR, "MM2S channel is not"
+							"supported\r\n");
+
+			return XST_FAILURE;
+		}
+
+		/* If the engine is doing transfer, cannot submit
+		 */
+
+		if(!(XAxiDma_ReadReg(InstancePtr->TxBdRing.ChanBase,
+				XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) {
+			if (XAxiDma_Busy(InstancePtr,Direction)) {
+				xdbg_printf(XDBG_DEBUG_ERROR,
+							"Engine is busy\r\n");
+				return XST_FAILURE;
+			}
+		}
+
+		if (!InstancePtr->MicroDmaMode) {
+			WordBits = (u32)((InstancePtr->TxBdRing.DataWidth) - 1);
+		}
+		else {
+			WordBits = XAXIDMA_MICROMODE_MIN_BUF_ALIGN;
+		}
+
+		if ((BuffAddr & WordBits)) {
+
+			if (!InstancePtr->TxBdRing.HasDRE) {
+				xdbg_printf(XDBG_DEBUG_ERROR,
+					"Unaligned transfer without"
+					" DRE %x\r\n",(unsigned int)BuffAddr);
+
+				return XST_INVALID_PARAM;
+			}
+		}
+
+
+		XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
+				 XAXIDMA_SRCADDR_OFFSET, LOWER_32_BITS(BuffAddr));
+		if (InstancePtr->AddrWidth > 32)
+			XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
+					 XAXIDMA_SRCADDR_MSB_OFFSET,
+					 UPPER_32_BITS(BuffAddr));
+
+		XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
+				XAXIDMA_CR_OFFSET,
+				XAxiDma_ReadReg(
+				InstancePtr->TxBdRing.ChanBase,
+				XAXIDMA_CR_OFFSET)| XAXIDMA_CR_RUNSTOP_MASK);
+
+		/* Writing to the BTT register starts the transfer
+		 */
+		XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase,
+					XAXIDMA_BUFFLEN_OFFSET, Length);
+	}
+	else if(Direction == XAXIDMA_DEVICE_TO_DMA){
+		if ((Length < 1) ||
+			(Length >
+			InstancePtr->RxBdRing[RingIndex].MaxTransferLen)) {
+			return XST_INVALID_PARAM;
+		}
+
+
+		if (!InstancePtr->HasS2Mm) {
+			xdbg_printf(XDBG_DEBUG_ERROR, "S2MM channel is not"
+							" supported\r\n");
+
+			return XST_FAILURE;
+		}
+
+		if(!(XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
+				XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK)) {
+			if (XAxiDma_Busy(InstancePtr,Direction)) {
+				xdbg_printf(XDBG_DEBUG_ERROR,
+							"Engine is busy\r\n");
+				return XST_FAILURE;
+			}
+		}
+
+		if (!InstancePtr->MicroDmaMode) {
+			WordBits =
+			 (u32)((InstancePtr->RxBdRing[RingIndex].DataWidth) - 1);
+		}
+		else {
+			WordBits = XAXIDMA_MICROMODE_MIN_BUF_ALIGN;
+		}
+
+		if ((BuffAddr & WordBits)) {
+
+			if (!InstancePtr->RxBdRing[RingIndex].HasDRE) {
+				xdbg_printf(XDBG_DEBUG_ERROR,
+					"Unaligned transfer without"
+				" DRE %x\r\n", (unsigned int)BuffAddr);
+
+				return XST_INVALID_PARAM;
+			}
+		}
+
+
+		XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
+				 XAXIDMA_DESTADDR_OFFSET, LOWER_32_BITS(BuffAddr));
+		if (InstancePtr->AddrWidth > 32)
+			XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
+					 XAXIDMA_DESTADDR_MSB_OFFSET,
+					 UPPER_32_BITS(BuffAddr));
+
+		XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
+				XAXIDMA_CR_OFFSET,
+			XAxiDma_ReadReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
+			XAXIDMA_CR_OFFSET)| XAXIDMA_CR_RUNSTOP_MASK);
+		/* Writing to the BTT register starts the transfer
+		 */
+		XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase,
+					XAXIDMA_BUFFLEN_OFFSET, Length);
+
+	}
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma.h b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma.h
new file mode 100644
index 000000000..86f62dd65
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma.h
@@ -0,0 +1,741 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma.h
+* @addtogroup axidma_v9_0
+* @{
+* @details
+*
+* This is the driver API for the AXI DMA engine.
+*
+* For a full description of DMA features, please see the hardware spec. This
+* driver supports the following features:
+*
+*   - Scatter-Gather DMA (SGDMA)
+*   - Simple DMA
+*   - Interrupts
+*   - Programmable interrupt coalescing for SGDMA
+*   - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA
+*     engine
+*
+* <b>Simple DMA</b>
+*
+* Simple DMA allows the application to define a single transaction between DMA
+* and Device. It has two channels: one from the DMA to Device and the other
+* from Device to DMA. Application has to set the buffer address and
+* length fields to initiate the transfer in respective channel.
+*
+* <b>Transactions</b>
+*
+* The object used to describe a transaction is referred to as a Buffer
+* Descriptor (BD). Buffer descriptors are allocated in the user application.
+* The user application needs to set buffer address, transfer length, and
+* control information for this transfer. The control information includes
+* SOF and EOF. Definition of those masks are in xaxidma_hw.h
+*
+* <b>Scatter-Gather DMA</b>
+*
+* SGDMA allows the application to define a list of transactions in memory which
+* the hardware will process without further application intervention. During
+* this time, the application is free to continue adding more work to keep the
+* Hardware busy.
+*
+* User can check for the completion of transactions through polling the
+* hardware, or interrupts.
+*
+* SGDMA processes whole packets. A packet is defined as a series of
+* data bytes that represent a message. SGDMA allows a packet of data to be
+* broken up into one or more transactions. For example, take an Ethernet IP
+* packet which consists of a 14 byte header followed by a 1 or more bytes of
+* payload. With SGDMA, the application may point a BD to the header and another
+* BD to the payload, then transfer them as a single message. This strategy can
+* make a TCP/IP stack more efficient by allowing it to keep packet header and
+* data in different memory regions instead of assembling packets into
+* contiguous blocks of memory.
+*
+* <b>BD Ring Management</b>
+*
+* BD rings are shared by the software and the hardware.
+*
+* The hardware expects BDs to be setup as a linked list. The DMA hardware walks
+* through the list by following the next pointer field of a completed BD.
+* The hardware stops processing when the just completed BD is the same as the
+* BD specified in the Tail Ptr register in the hardware.
+*
+* The last BD in the ring is linked to the first BD in the ring.
+*
+* All BD management are done inside the driver. The user application should not
+* directly modify the BD fields. Modifications to the BD fields should always
+* go through the specific API functions.
+*
+* Within the ring, the driver maintains four groups of BDs. Each group consists
+* of 0 or more adjacent BDs:
+*
+*   - Free: The BDs that can be allocated by the application with
+*     XAxiDma_BdRingAlloc().
+*
+*   - Pre-process: The BDs that have been allocated with
+*     XAxiDma_BdRingAlloc(). These BDs are under application control. The
+*     application modifies these BDs through driver API to prepare them
+*     for DMA transactions.
+*
+*   - Hardware: The BDs that have been enqueued to hardware with
+*     XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a
+*     state of awaiting hardware processing, in process, or processed by
+*     hardware. It is considered an error for the application to change BDs
+*     while they are in this group. Doing so can cause data corruption and lead
+*     to system instability.
+*
+*   - Post-process: The BDs that have been processed by hardware and have
+*     been extracted from the Hardware group with XAxiDma_BdRingFromHw().
+*     These BDs are under application control. The application can check the
+*     transfer status of these BDs. The application use XAxiDma_BdRingFree()
+*     to put them into the Free group.
+*
+* BDs are expected to transition in the following way for continuous
+* DMA transfers:
+* <pre>
+*
+*         XAxiDma_BdRingAlloc()                   XAxiDma_BdRingToHw()
+*   Free ------------------------> Pre-process ----------------------> Hardware
+*                                                                      |
+*    /|\                                                               |
+*     |   XAxiDma_BdRingFree()                  XAxiDma_BdRingFromHw() |
+*     +--------------------------- Post-process <----------------------+
+*
+* </pre>
+*
+* When a DMA transfer is to be cancelled before enqueuing to hardware,
+* application can return the requested BDs to the Free group using
+* XAxiDma_BdRingUnAlloc(), as shown below:
+* <pre>
+*
+*         XAxiDma_BdRingUnAlloc()
+*   Free <----------------------- Pre-process
+*
+* </pre>
+*
+* The API provides functions for BD list traversal:
+* - XAxiDma_BdRingNext()
+* - XAxiDma_BdRingPrev()
+*
+* These functions should be used with care as they do not understand where
+* one group ends and another begins.
+*
+* <b>SGDMA Descriptor Ring Creation</b>
+*
+* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring
+* is allocated by the application, and it has to be contiguous. Physical
+* address is required to setup the BD ring.
+*
+* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of
+* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be
+* used to find out how many BDs can be allocated for certain amount of memory.
+*
+* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if
+* the BDs have same types of controls, for example, SOF and EOF. After
+* using the XAxiDma_BdRingClone(), the application only needs to setup the
+* buffer address and transfer length. Note that certain BDs in one packet,
+* for example, the first BD and the last BD, may need to setup special
+* control information.
+*
+* <b>Descriptor Ring State Machine</b>
+*
+* There are two states of the BD ring:
+*
+*   - HALTED (H), where hardware is not running
+*
+*   - NOT HALTED (NH), where hardware is running
+*
+* The following diagram shows the state transition for the DMA engine:
+*
+* <pre>
+*   _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(),   ______
+*   |   |               or XAxiDma_Resume()                    |    |
+*   | H |----------------------------------------------------->| NH |
+*   |   |<-----------------------------------------------------|    |
+*   -----   XAxiDma_Pause() or XAxiDma_Reset()                 ------
+* </pre>
+*
+* <b>Interrupt Coalescing</b>
+*
+* SGDMA provides control over the frequency of interrupts through interrupt
+* coalescing. The DMA engine provides two ways to tune the interrupt
+* coalescing:
+*
+* - The packet threshold counter. Interrupt will fire once the
+*   programmable number of packets have been processed by the engine.
+*
+* - The packet delay timer counter. Interrupt will fire once the
+*   programmable amount of time has passed after processing the last packet,
+*   and no new packets to process. Note that the interrupt will only fire if
+*   at least one packet has been processed.
+*
+* <b> Interrupt </b>
+*
+* Interrupts are handled by the user application. Each DMA channel has its own
+* interrupt ID. The driver provides APIs to enable/disable interrupt,
+* and tune the interrupt frequency regarding to packet processing frequency.
+*
+* <b> Software Initialization </b>
+*
+*
+* To use the Simple mode DMA engine for transfers, the following setup is
+* required:
+*
+* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
+*   initializes a driver instance for the given DMA engine and resets the
+*   engine.
+*
+* - Enable interrupts if chosen to use interrupt mode. The application is
+*   responsible for setting up the interrupt system, which includes providing
+*   and connecting interrupt handlers and call back functions, before
+*   enabling the interrupts.
+*
+* - Set the buffer address and length field in respective channels to start
+*   the DMA transfer
+*
+* To use the SG mode DMA engine for transfers, the following setup are
+* required:
+*
+* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
+*   initializes a driver instance for the given DMA engine and resets the
+*   engine.
+*
+* - BD Ring creation. A BD ring is needed per DMA channel and can be built by
+*   calling XAxiDma_BdRingCreate().
+*
+* - Enable interrupts if chose to use interrupt mode. The application is
+*   responsible for setting up the interrupt system, which includes providing
+*   and connecting interrupt handlers and call back functions, before
+*   enabling the interrupts.
+*
+* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for
+*   the first time or after a reset, and XAxiDma_BdRingToHw() if the channel
+*   is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not
+*   running will not put the BDs to the hardware, and the BDs will be processed
+*   later when the DMA channel is started through XAxiDma_BdRingStart().
+*
+* <b> How to start DMA transactions </b>
+*
+* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware
+* to start DMA transfers.
+*
+* For both channels, if the DMA engine is currently stopped (using
+* XAxiDma_Pause()), the newly added BDs will be accepted but not processed
+* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed,
+* using XAxiDma_Resume().
+*
+* <b> Software Post-Processing on completed DMA transactions </b>
+*
+* If the interrupt system has been set up and the interrupts are enabled,
+* a DMA channels notifies the software about the completion of a transfer
+* through interrupts. Otherwise, the user application can poll for
+* completions of the BDs, using XAxiDma_BdRingFromHw() or
+* XAxiDma_BdHwCompleted().
+*
+* - Once BDs are finished by a channel, the application first needs to fetch
+*   them from the channel using XAxiDma_BdRingFromHw().
+*
+* - On the TX side, the application now could free the data buffers attached to
+*   those BDs as the data in the buffers has been transmitted.
+*
+* - On the RX side, the application now could use the received data in the
+*	buffers attached to those BDs.
+*
+* - For both channels, completed BDs need to be put back to the Free group
+*   using XAxiDma_BdRingFree(), so they can be used for future transactions.
+*
+* - On the RX side, it is the application's responsibility to have BDs ready
+*   to receive data at any time. Otherwise, the RX channel refuses to
+*   accept any data if it has no RX BDs.
+*
+* <b> Examples </b>
+*
+* We provide five examples to show how to use the driver API:
+* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer
+* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.
+* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer
+* - One for simple polling mode (xaxidma_example_simple_poll.c)
+* - One for simple Interrupt mode (xaxidma_example_simple_intr.c)
+*
+* <b> Address Translation </b>
+*
+* All buffer addresses and BD addresses for the hardware are physical
+* addresses. The user application is responsible to provide physical buffer
+* address for the BD upon BD ring creation. The user application accesses BD
+* through its virtual addess. The driver maintains the address translation
+* between the physical and virtual address for BDs.
+*
+* <b> Cache Coherency </b>
+*
+* This driver expects all application buffers attached to BDs to be in cache
+* coherent memory. If cache is used in the system, buffers for transmit MUST
+* be flushed from the cache before passing the associated BD to this driver.
+* Buffers for receive MUST be invalidated before accessing the data.
+*
+* <b> Alignment </b>
+*
+* For BDs:
+*
+* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT.
+* This is the smallest alignment allowed by both hardware and software for them
+* to properly work.
+*
+* If the descriptor ring is to be placed in cached memory, alignment also MUST
+* be at least the processor's cache-line size. Otherwise, system instability
+* occurs. For alignment larger than the cache line size, multiple cache line
+* size alignment is required.
+*
+* Aside from the initial creation of the descriptor ring (see
+* XAxiDma_BdRingCreate()), there are no other run-time checks for proper
+* alignment of BDs.
+*
+* For application data buffers:
+*
+* Application data buffers may reside on any alignment if DRE is built into the
+* hardware. Otherwise, application data buffer must be word-aligned. The word
+* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and
+* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.
+*
+* For scatter gather transfers that have more than one BDs in the chain of BDs,
+* Each BD transfer length must be multiple of word too. Otherwise, internal
+* error happens in the hardware.
+*
+* <b> Error Handling </b>
+*
+* The DMA engine will halt on all error conditions. It requires the software
+* to do a reset before it can start process new transfer requests.
+*
+* <b> Restart After Stopping </b>
+*
+* After the DMA engine has been stopped (through reset or reset after an error)
+* the software keeps track of the current BD pointer when reset happens, and
+* processing of BDs can be resumed through XAxiDma_BdRingStart().
+*
+* <b> Limitations </b>
+*
+* This driver does not have any mechanisms for mutual exclusion. It is up to
+* the application to provide this protection.
+*
+* <b> Hardware Defaults & Exclusive Use </b>
+*
+* After the initialization or reset, the DMA engine is in the following
+* default mode:
+* - All interrupts are disabled.
+*
+* - Interrupt coalescing counter is 1.
+*
+* - The DMA engine is not running (halted). Each DMA channel is started
+*   separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer
+*   yet, or XAxiDma_BdRingStart() otherwise.
+*
+* The driver has exclusive use of the registers and BDs. All accesses to the
+* registers and BDs should go through the driver interface.
+*
+* <b> Debug Print </b>
+*
+* To see the debug print for the driver, please put "-DDEBUG" as the extra
+* compiler flags in software platform settings. Also comment out the line in
+* xdebug.h: "#undef DEBUG".
+*
+* <b>Changes From v1.00a</b>
+*
+* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int
+* . We added XAxiDma_LookupConfig() so that user does not need to look for the
+* hardware settings anymore.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+*		      New API added for simple DMA mode are
+*			- XAxiDma_Busy
+*			- XAxiDma_SimpleTransfer
+*		      New Macros added for simple DMA mode are
+* 			- XAxiDma_HasSg
+* 			- XAxiDma_IntrEnable
+* 			- XAxiDma_IntrGetEnabled
+* 			- XAxiDma_IntrDisable
+* 			- XAxiDma_IntrGetIrq
+* 			- XAxiDma_IntrAckIrq
+* 5.00a srt  08/25/11  Added support for memory barrier and modified
+*			Cache Macros to have a common API for Microblaze
+*			and Zynq.
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode.
+*		      - Changed APIs:
+*			* XAxiDma_GetRxRing(InstancePtr, RingIndex)
+*			* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*        					u32 BuffAddr, u32 Length,
+*						int Direction, int RingIndex)
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+*					u32 LenBytes, u32 LengthMask)
+*       		* XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+*			* XAxiDma_BdGetLength(BdPtr, LengthMask)
+*		       - New APIs
+*			* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*			- New API:
+*			  XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
+* 7.01a srt  10/26/12  - Fixed issue with driver as it fails with IP version
+*		         < 6.00a as the parameter C_NUM_*_CHANNELS is not
+*			 applicable.
+*		       - Changed the logic of MCDMA BD fields Set APIs, to
+*			 clear the field first and then set it.
+* 7.02a srt  01/23/13  Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
+*		       (CR 691867)
+*		       Updated DDR base address for IPI designs (CR 703656).
+* 8.0   adk  19/12/13  Updated as per the New Tcl API's
+*	srt  01/29/14  Added support for Micro DMA Mode and cyclic mode of
+*		       operations.
+*		      - New APIs:
+*			* XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+ *			* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
+* 8.1   adk  20/01/15  Added support for peripheral test. Created the self
+*		       test example to include it on peripheral test's(CR#823144).
+* 8.1   adk  29/01/15  Added the sefltest api (XAxiDma_Selftest) to the driver source files
+* 		      (xaxidma_selftest.c) and called this from the selftest example
+* 9.0 	adk  27/07/15  Added support for 64-bit Addressing.
+* 9.0   adk  19/08/15  Fixed CR#873125 DMA SG Mode example tests are failing on
+*		       HW in 2015.3.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XAXIDMA_H_   /* prevent circular inclusions */
+#define XAXIDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xaxidma_bdring.h"
+#ifdef __MICROBLAZE__
+#include "xenv.h"
+#else
+#include <string.h>
+#include "xil_cache.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The XAxiDma driver instance data. An instance must be allocated for each DMA
+ * engine in use.
+ */
+typedef struct XAxiDma {
+	u32 RegBase;		/* Virtual base address of DMA engine */
+
+	int HasMm2S;		/* Has transmit channel */
+	int HasS2Mm;		/* Has receive channel */
+	int Initialized;	/* Driver has been initialized */
+	int HasSg;
+
+	XAxiDma_BdRing TxBdRing;     /* BD container management for TX channel */
+	XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
+	int TxNumChannels;
+	int RxNumChannels;
+	int MicroDmaMode;
+	int AddrWidth;		  /**< Address Width */
+} XAxiDma;
+
+/**
+ * The configuration structure for AXI DMA engine
+ *
+ * This structure passes the hardware building information to the driver
+ */
+typedef struct {
+	u32 DeviceId;
+	u32 BaseAddr;
+
+	int HasStsCntrlStrm;
+	int HasMm2S;
+	int HasMm2SDRE;
+	int Mm2SDataWidth;
+	int HasS2Mm;
+	int HasS2MmDRE;
+	int S2MmDataWidth;
+	int HasSg;
+	int Mm2sNumChannels;
+	int S2MmNumChannels;
+	int Mm2SBurstSize;
+	int S2MmBurstSize;
+	int MicroDmaMode;
+	int AddrWidth;		  /**< Address Width */
+} XAxiDma_Config;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/*****************************************************************************/
+/**
+* Get Transmit (Tx) Ring ptr
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	Pointer to the Tx Ring
+*
+* @note		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr)
+* 		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetTxRing(InstancePtr) \
+			(&((InstancePtr)->TxBdRing))
+
+/*****************************************************************************/
+/**
+* Get Receive (Rx) Ring ptr
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	Pointer to the Rx Ring
+*
+* @note
+* 		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetRxRing(InstancePtr) \
+			(&((InstancePtr)->RxBdRing[0]))
+
+/*****************************************************************************/
+/**
+* Get Receive (Rx) Ring ptr of a Index
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+* @param	RingIndex is the channel Index.
+*
+* @return	Pointer to the Rx Ring
+*
+* @note
+* 		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr,
+						int RingIndex)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \
+			(&((InstancePtr)->RxBdRing[RingIndex]))
+
+/*****************************************************************************/
+/**
+* This function checks whether system is configured as Simple or
+* Scatter Gather mode
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+*		- TRUE if configured as SG mode
+*		- FALSE if configured as simple mode
+*
+* @note		None
+*
+*****************************************************************************/
+#define XAxiDma_HasSg(InstancePtr)	((InstancePtr)->HasSg) ? TRUE : FALSE
+
+/*****************************************************************************/
+/**
+ * This function enables interrupts specified by the Mask in specified
+ * direction, Interrupts that are not in the mask are not affected.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be enabled
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @return	None
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrEnable(InstancePtr, Mask, Direction) 	\
+	XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
+			| (Mask & XAXIDMA_IRQ_ALL_MASK))
+
+
+/*****************************************************************************/
+/**
+ * This function gets the mask for the interrupts that are currently enabled
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	The bit mask for the interrupts that are currently enabled
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define   XAxiDma_IntrGetEnabled(InstancePtr, Direction)	\
+			XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
+							XAXIDMA_IRQ_ALL_MASK)
+
+
+
+/*****************************************************************************/
+/**
+ * This function disables interrupts specified by the Mask. Interrupts that
+ * are not in the mask are not affected.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be disabled
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @return	None
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+ #define XAxiDma_IntrDisable(InstancePtr, Mask, Direction)	\
+		XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
+			& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
+
+
+/*****************************************************************************/
+/**
+ * This function gets the interrupts that are asserted.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	The bit mask for the interrupts asserted.
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrGetIrq(InstancePtr, Direction)	\
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
+							XAXIDMA_IRQ_ALL_MASK)
+
+/*****************************************************************************/
+/**
+ * This function acknowledges the interrupts that are specified in Mask
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be acknowledge
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	None
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction)	\
+			XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
+			(Mask) & XAXIDMA_IRQ_ALL_MASK)
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization and control functions in xaxidma.c
+ */
+XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
+int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
+void XAxiDma_Reset(XAxiDma * InstancePtr);
+int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
+int XAxiDma_Pause(XAxiDma * InstancePtr);
+int XAxiDma_Resume(XAxiDma * InstancePtr);
+u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
+u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
+	int Direction);
+int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select);
+int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select);
+int XAxiDma_Selftest(XAxiDma * InstancePtr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bd.c b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bd.c
new file mode 100644
index 000000000..260946d82
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bd.c
@@ -0,0 +1,354 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_bd.c
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Buffer descriptor (BD) management API implementation.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 6.00a srt  01/24/12 Added support for Multi-Channel DMA.
+ *		       - Changed APIs
+ *			* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+ *					u32 LenBytes, u32 LengthMask)
+ *       		* XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+ *			* XAxiDma_BdGetLength(BdPtr, LengthMask)
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode:
+ *		       - New API
+ *			 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+
+#include "xaxidma_bd.h"
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+ * Set the length field for the given BD.
+ *
+ * Length has to be non-zero and less than LengthMask.
+ *
+ * For TX channels, the value passed in should be the number of bytes to
+ * transmit from the TX buffer associated with the given BD.
+ *
+ * For RX channels, the value passed in should be the size of the RX buffer
+ * associated with the given BD in bytes. This is to notify the RX channel
+ * the capability of the RX buffer to avoid buffer overflow.
+ *
+ * The actual receive length can be equal or smaller than the specified length.
+ * The actual transfer length will be updated by the hardware in the
+ * XAXIDMA_BD_STS_OFFSET word in the BD.
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	LenBytes is the requested transfer length
+ * @param	LengthMask is the maximum transfer length
+ *
+ * @returns
+ *		- XST_SUCCESS for success
+ *		- XST_INVALID_PARAM for invalid BD length
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, u32 LenBytes, u32 LengthMask)
+{
+	if (LenBytes <= 0 || (LenBytes > LengthMask)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "invalid length %d\n",
+		    (int)LenBytes);
+
+		return XST_INVALID_PARAM;
+	}
+
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET,
+		((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
+		~LengthMask)) | LenBytes);
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Set the BD's buffer address.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Addr is the address to set
+ *
+ * @return
+ *		- XST_SUCCESS if buffer address set successfully
+ *		- XST_INVALID_PARAM if hardware has no DRE and address is not
+ *		aligned
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr)
+{
+	u32 HasDRE;
+	u8 WordLen;
+	u32 Addrlen;
+
+	HasDRE = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET);
+	WordLen = HasDRE & XAXIDMA_BD_WORDLEN_MASK;
+	Addrlen = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ADDRLEN_OFFSET);
+
+
+	if (Addr & (WordLen - 1)) {
+		if ((HasDRE & XAXIDMA_BD_HAS_DRE_MASK) == 0) {
+			xil_printf("Error set buf addr %x with %x and %x,"
+			" %x\r\n",Addr, HasDRE, (WordLen - 1),
+			Addr & (WordLen - 1));
+
+			return XST_INVALID_PARAM;
+		}
+	}
+
+	XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, LOWER_32_BITS(Addr));
+	if (Addrlen)
+		XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_MSB_OFFSET,
+				UPPER_32_BITS(Addr));
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Set the BD's buffer address when configured for Micro Mode.  The buffer
+ * address should be 4K aligned.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Addr is the address to set
+ *
+ * @return
+ *		- XST_SUCCESS if buffer address set successfully
+ *		- XST_INVALID_PARAM if hardware has no DRE and address is not
+ *		aligned
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr)
+{
+	u32 Addrlen;
+	Addrlen = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ADDRLEN_OFFSET);
+
+	if (Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN) {
+			xil_printf("Error set buf addr %x and %x,"
+			" %x\r\n", Addr, XAXIDMA_MICROMODE_MIN_BUF_ALIGN,
+			Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN);
+
+			return XST_INVALID_PARAM;
+	}
+
+	XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET,
+			LOWER_32_BITS(Addr));
+	if (Addrlen)
+		XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_MSB_OFFSET,
+				UPPER_32_BITS(Addr));
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Set the APP word at the specified APP word offset for a BD.
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	Offset is the offset inside the APP word, it is valid from
+ *		0 to 4
+ * @param	Word is the value to set
+ *
+ * @returns
+ *		- XST_SUCCESS for success
+ *		- XST_INVALID_PARAM under following error conditions:
+ *		1) StsCntrlStrm is not built in hardware
+ *		2) Offset is not in valid range
+ *
+ * @note
+ *		If the hardware build has C_SG_USE_STSAPP_LENGTH set to 1,
+ *		then the last APP word, XAXIDMA_LAST_APPWORD, must have
+ *		non-zero value when AND with 0x7FFFFF. Not doing so will cause
+ *		the hardware to stall.
+ *		This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdSetAppWord(XAxiDma_Bd* BdPtr, int Offset, u32 Word)
+{
+	if (XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET) == 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetAppWord: no sts cntrl"
+			"stream in hardware build, cannot set app word\r\n");
+
+		return XST_INVALID_PARAM;
+	}
+
+	if ((Offset < 0) || (Offset > XAXIDMA_LAST_APPWORD)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetAppWord: invalid"
+			"offset %d",Offset);
+
+		return XST_INVALID_PARAM;
+	}
+
+	XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_USR0_OFFSET + Offset * 4, Word);
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Get the APP word at the specified APP word offset for a BD.
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	Offset is the offset inside the APP word, it is valid from
+ *		0 to 4
+ * @param	Valid is to tell the caller whether parameters are valid
+ *
+ * @returns
+ *		The APP word. Passed in parameter Valid holds 0 for failure,
+ *		and 1 for success.
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+u32 XAxiDma_BdGetAppWord(XAxiDma_Bd* BdPtr, int Offset, int *Valid)
+{
+	*Valid = 0;
+
+	if (XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET) == 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingGetAppWord: no sts cntrl "
+			"stream in hardware build, no app word available\r\n");
+
+		return (u32)0;
+	}
+
+	if((Offset < 0) || (Offset > XAXIDMA_LAST_APPWORD)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingGetAppWord: invalid"
+			" offset %d", Offset);
+
+		return (u32)0;
+	}
+
+	*Valid = 1;
+
+	return XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR0_OFFSET + Offset * 4);
+}
+
+/*****************************************************************************/
+/**
+ * Set the control bits for a BD.
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	Data is the bit value to set
+ *
+ * @return	None
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+void XAxiDma_BdSetCtrl(XAxiDma_Bd* BdPtr, u32 Data)
+{
+	u32 RegValue = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET);
+
+	RegValue &= ~XAXIDMA_BD_CTRL_ALL_MASK;
+
+	RegValue |= (Data & XAXIDMA_BD_CTRL_ALL_MASK);
+
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET, RegValue);
+
+	return;
+}
+/*****************************************************************************/
+/**
+ * Dump the fields of a BD.
+ *
+ * @param	BdPtr is the BD to operate on.
+ *
+ * @return	None
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr)
+{
+
+	xil_printf("Dump BD %x:\r\n", (UINTPTR)BdPtr);
+	xil_printf("\tNext Bd Ptr: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_NDESC_OFFSET));
+	xil_printf("\tBuff addr: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_BUFA_OFFSET));
+	xil_printf("\tMCDMA Fields: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_MCCTL_OFFSET));
+	xil_printf("\tVSIZE_STRIDE: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr,
+					XAXIDMA_BD_STRIDE_VSIZE_OFFSET));
+	xil_printf("\tContrl len: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET));
+	xil_printf("\tStatus: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_STS_OFFSET));
+
+	xil_printf("\tAPP 0: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR0_OFFSET));
+	xil_printf("\tAPP 1: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR1_OFFSET));
+	xil_printf("\tAPP 2: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR2_OFFSET));
+	xil_printf("\tAPP 3: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR3_OFFSET));
+	xil_printf("\tAPP 4: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_USR4_OFFSET));
+
+	xil_printf("\tSW ID: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ID_OFFSET));
+	xil_printf("\tStsCtrl: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr,
+	           XAXIDMA_BD_HAS_STSCNTRL_OFFSET));
+	xil_printf("\tDRE: %x\r\n",
+	    (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET));
+
+	xil_printf("\r\n");
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bd.h b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bd.h
new file mode 100644
index 000000000..0b8879ce1
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bd.h
@@ -0,0 +1,679 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_bd.h
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Buffer descriptor (BD) management API.
+ *
+ * <b> Buffer Descriptors </b>
+ *
+ * A BD defines a DMA transaction (see "Transaction" section in xaxidma.h).
+ * All accesses to a BD go through this set of API.
+ *
+ * The XAxiDma_Bd structure defines a BD. The first XAXIDMA_BD_HW_NUM_BYTES
+ * are shared between hardware and software.
+ *
+ * <b> Actual Transfer Length </b>
+ *
+ * The actual transfer length for receive could be smaller than the requested
+ * transfer length. The hardware sets the actual transfer length in the
+ * completed BD. The API to retrieve the actual transfer length is
+ * XAxiDma_GetActualLength().
+ *
+ * <b> User IP words </b>
+ *
+ * There are 5 user IP words in each BD.
+ *
+ * If hardware does not have the StsCntrl stream built in, then these words
+ * are not usable. Retrieving these words get a NULL pointer and setting
+ * these words results an error.
+ *
+ * <b> Performance </b>
+ *
+ * BDs are typically in a non-cached memory space. Reducing the number of
+ * I/O operations to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 5.00a srt  08/25/11 Changed Cache Macros to have a common API for Zynq
+ *		           and Microblaze.
+ * 6.00a srt  01/24/12 Added APIs to support Multi-Channel DMA:
+ *			XAxiDma_BdSetTId()
+ *			XAxiDma_BdGetTId()
+ *			XAxiDma_BdSetTDest()
+ *			XAxiDma_BdGetTDest()
+ *			XAxiDma_BdSetTUser()
+ *			XAxiDma_BdGetTUser()
+ *			XAxiDma_BdSetARCache()
+ *			XAxiDma_BdGetARCache()
+ *			XAxiDma_BdSetARUser()
+ *			XAxiDma_BdGetARUser()
+ *			XAxiDma_BdSetStride()
+ *			XAxiDma_BdGetStride()
+ *			XAxiDma_BdSetVSize()
+ *			XAxiDma_BdGetVSize()
+ *			- Changed APIs
+ *			XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+ *			XAxiDma_BdGetLength(BdPtr, LengthMask)
+ *			XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr,
+ *					u32 LenBytes, u32 LengthMask)
+ * 7.01a srt  10/26/12  Changed the logic of MCDMA BD fields Set APIs, to
+ *			clear the field first and set it.
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode.
+ *
+ * </pre>
+ *****************************************************************************/
+
+#ifndef XAXIDMA_BD_H_    /* To prevent circular inclusions */
+#define XAXIDMA_BD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xaxidma_hw.h"
+#include "xstatus.h"
+#include "xdebug.h"
+#include "xil_cache.h"
+
+#ifdef __MICROBLAZE__
+#include "xenv.h"
+#else
+#include <string.h>
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The XAxiDma_Bd is the type for a buffer descriptor (BD).
+ */
+
+typedef UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ * Define methods to flush and invalidate cache for BDs should they be
+ * located in cached memory.
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XAXIDMA_CACHE_FLUSH(BdPtr)
+#define XAXIDMA_CACHE_INVALIDATE(BdPtr)
+#else
+#define XAXIDMA_CACHE_FLUSH(BdPtr) \
+	Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
+
+#define XAXIDMA_CACHE_INVALIDATE(BdPtr) \
+	Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param	BaseAddress is the base address of the BD to read
+* @param	Offset is the word offset to be read
+*
+* @return	The 32-bit value of the field
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset)
+*
+******************************************************************************/
+#define XAxiDma_BdRead(BaseAddress, Offset)				\
+	(*(u32 *)((UINTPTR)((void *)(BaseAddress)) + (u32)(Offset)))
+
+/*****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param	BaseAddress is the base address of the BD to write
+* @param	Offset is the word offset to be written
+* @param	Data is the 32-bit value to write to the field
+*
+* @return	None.
+*
+* @note
+* 		C-style signature:
+*		void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XAxiDma_BdWrite(BaseAddress, Offset, Data)			\
+	(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)
+
+/*****************************************************************************/
+/**
+ * Zero out BD specific fields. BD fields that are for the BD ring or for the
+ * system hardware build information are not touched.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdClear(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdClear(BdPtr)                    \
+  memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \
+    XAXIDMA_BD_BYTES_TO_CLEAR)
+
+/*****************************************************************************/
+/**
+ * Get the control bits for the BD
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	The bit mask for the control of the BD
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetCtrl(BdPtr)				\
+		(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET)	\
+		& XAXIDMA_BD_CTRL_ALL_MASK)
+/*****************************************************************************/
+/**
+ * Retrieve the status of a BD
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_***
+ *		values defined in xaxidma_hw.h to interpret the returned value
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetSts(BdPtr)              \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		XAXIDMA_BD_STS_ALL_MASK)
+/*****************************************************************************/
+/**
+ * Retrieve the length field value from the given BD.  The returned value is
+ * the same as what was written with XAxiDma_BdSetLength(). Note that in the
+ * this value does not reflect the real length of received data.
+ * See the comments of XAxiDma_BdSetLength() for more details. To obtain the
+ * actual transfer length, use XAxiDma_BdGetActualLength().
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	LengthMask is the Maximum Transfer Length.
+ *
+ * @return	The length value set in the BD.
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetLength(BdPtr, LengthMask)                \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
+		LengthMask)
+
+
+/*****************************************************************************/
+/**
+ * Set the ID field of the given BD. The ID is an arbitrary piece of data the
+ * application can associate with a specific BD.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Id is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetId(BdPtr, Id)                                      \
+	(XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (u32)(Id)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))
+
+/*****************************************************************************/
+/**
+ * Get the BD's buffer address
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetBufAddr(BdPtr)                     \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))
+
+/*****************************************************************************/
+/**
+ * Check whether a BD has completed in hardware. This BD has been submitted
+ * to hardware. The application can use this function to poll for the
+ * completion of the BD.
+ *
+ * This function may not work if the BD is in cached memory.
+ *
+ * @param	BdPtr is the BD to check on
+ *
+ * @return
+ *		- 0 if not complete
+ *		- XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain
+ * 		XAXIDMA_BD_STS_*_ERR_MASK bits.
+ *
+ * @note
+ * 		C-style signature:
+ *		int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdHwCompleted(BdPtr)                     \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		XAXIDMA_BD_STS_COMPLETE_MASK)
+
+/*****************************************************************************/
+/**
+ * Get the actual transfer length of a BD. The BD has completed in hw.
+ *
+ * This function may not work if the BD is in cached memory.
+ *
+ * @param	BdPtr is the BD to check on
+ * @param	LengthMask is the Maximum Transfer Length.
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetActualLength(BdPtr, LengthMask)      \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		LengthMask)
+
+/*****************************************************************************/
+/**
+ * Set the TID field of the TX BD.
+ * Provides a stream identifier and can be used to differentiate between
+ * multiple streams of data that are being transferred across the same
+ * interface.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TId is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTId(BdPtr, TId) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TID_FIELD_MASK); \
+	val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTId(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TID_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the TDEST field of the TX BD.
+ * Provides coarse routing information for the data stream.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TDest is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTDest(BdPtr, TDest) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TDEST_FIELD_MASK); \
+	val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TDest field of the RX BD previously set with i
+ * XAxiDma_BdSetTDest.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTDest(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TDEST_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the TUSER field of the TX BD.
+ * User defined sideband signaling.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TUser is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTUser(BdPtr, TUser)	\
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TUSER_FIELD_MASK); \
+	val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TUSER field of the RX BD previously set with
+ * XAxiDma_BdSetTUser.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTUser(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TUSER_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the ARCACHE field of the given BD.
+ * This signal provides additional information about the cacheable
+ * characteristics of the transfer.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	ARCache is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetARCache(BdPtr, ARCache) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_ARCACHE_FIELD_MASK); \
+	val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the ARCACHE field of the given BD previously set with
+ * XAxiDma_BdSetARCache.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetARCache(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) &  \
+		XAXIDMA_BD_ARCACHE_FIELD_MASK)
+
+
+/*****************************************************************************/
+/**
+ * Set the ARUSER field of the given BD.
+ * Sideband signals used for user defined information.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	ARUser is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetARUser(BdPtr, ARUser) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_ARUSER_FIELD_MASK); \
+	val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the ARUSER field of the given BD previously set with
+ * XAxiDma_BdSetARUser.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetARUser(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) &  \
+		XAXIDMA_BD_ARUSER_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the STRIDE field of the given BD.
+ * It is the address distance between the first address of successive
+ * horizontal reads.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Stride is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetStride(BdPtr, Stride) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
+		~XAXIDMA_BD_STRIDE_FIELD_MASK); \
+	val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the STRIDE field of the given BD previously set with
+ * XAxiDma_BdSetStride.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetStride(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) &  \
+		XAXIDMA_BD_STRIDE_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the VSIZE field of the given BD.
+ * Number of horizontal lines for strided access.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	VSize is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetVSize(BdPtr, VSize) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
+		~XAXIDMA_BD_VSIZE_FIELD_MASK); \
+	val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the STRIDE field of the given BD previously set with
+ * XAxiDma_BdSetVSize.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetVSize(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) &  \
+		XAXIDMA_BD_VSIZE_FIELD_MASK)
+
+/*****************************************************************************/
+
+/************************** Function Prototypes ******************************/
+
+int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask);
+u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr);
+u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr);
+int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
+u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
+void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+
+/* Debug utility
+ */
+void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bdring.c b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bdring.c
new file mode 100644
index 000000000..5036f4fc8
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bdring.c
@@ -0,0 +1,1587 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_bdring.c
+* @addtogroup axidma_v9_0
+* @{
+*
+* This file implements buffer descriptor ring related functions. For more
+* information on how to manage the BD ring, please see xaxidma.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 5.00a srt  08/25/11 Added support for memory barrier.
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA.
+*		      - New API
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+*		      - Changed APIs
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xaxidma_bdring.h"
+
+/************************** Constant Definitions *****************************/
+/* Use 100 milliseconds for 100 MHz
+ * This interval is sufficient for hardware to finish 40MB transfer with
+ * 32-bit bus.
+ */
+#define XAXIDMA_STOP_TIMEOUT	500000   /* about 100 milliseconds on 100MHz */
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/* The following macros are helper functions inside this file.
+ */
+
+/******************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param	BdPtr is the virtual address of the BD
+ *
+ * @returns	Physical address of BdPtr
+ *
+ * @note	Assume virtual and physical mapping is flat.
+ *		RingPtr is an implicit parameter
+ *
+ *****************************************************************************/
+#define XAXIDMA_VIRT_TO_PHYS(BdPtr) \
+	((UINTPTR)(BdPtr) + (RingPtr->FirstBdPhysAddr - RingPtr->FirstBdAddr))
+
+/******************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wraparound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses the 0xFFFFFFFF
+ * to 0 boundary.
+ *
+ * @param	RingPtr is the ring BdPtr appears in
+ * @param	BdPtr on input is the starting BD position and on output is the
+ *		final BD position
+ * @param	NumBd is the number of BD spaces to increment
+ *
+ * @returns	None
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+#define XAXIDMA_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd)                \
+    {                                                                \
+        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                                     \
+                                                                     \
+        Addr += ((RingPtr)->Separation * (NumBd));                   \
+        if ((Addr > (RingPtr)->LastBdAddr) || ((UINTPTR)(BdPtr) > Addr)) \
+        {                                                            \
+            Addr -= (RingPtr)->Length;                               \
+        }                                                            \
+                                                                     \
+        (BdPtr) = (XAxiDma_Bd*)(void *)Addr;                                 \
+    }
+/******************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wraparound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses the 0xFFFFFFFF
+ * to 0 boundary.
+ *
+ * @param	RingPtr is the ring BdPtr appears in
+ * @param	BdPtr on input is the starting BD position and on output is the
+ *		final BD position
+ * @param	NumBd is the number of BD spaces to increment
+ *
+ * @returns	None
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+#define XAXIDMA_RING_SEEKBACK(RingPtr, BdPtr, NumBd)                  \
+    {                                                                 \
+        UINTPTR Addr = (UINTPTR)(BdPtr);                                      \
+                                                                      \
+        Addr -= ((RingPtr)->Separation * (NumBd));                    \
+        if ((Addr < (RingPtr)->FirstBdAddr) || ((UINTPTR)(BdPtr) < Addr)) \
+        {                                                             \
+            Addr += (RingPtr)->Length;                                \
+        }                                                             \
+                                                                      \
+        (BdPtr) = (XAxiDma_Bd*)Addr;                                  \
+    }
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Update Current Descriptor
+ *
+ * @param	RingPtr is the Channel instance to be worked on
+ *
+ * @return
+ *		- XST_SUCCESS upon success
+ *		- XST_DMA_ERROR if no valid BD available to put into current
+ *		BD register
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr)
+{
+	u32 RegBase;
+	UINTPTR BdPtr;
+	int RingIndex = RingPtr->RingIndex;
+
+	/* BD list has yet to be created for this channel */
+	if (RingPtr->AllCnt == 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingStart: no bds\r\n");
+
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* Do nothing if already started */
+	if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) {
+		/* Need to update tail pointer if needed (Engine is not
+		 * transferring)
+		 */
+		return XST_SUCCESS;
+	}
+
+	if (!XAxiDma_BdRingHwIsStarted(RingPtr)) {
+		/* If hardware is not running, then we need to put a valid current
+		 * BD pointer to the current BD register before start the hardware
+		 */
+		RegBase = RingPtr->ChanBase;
+
+		/* Put a valid BD pointer in the current BD pointer register
+		 * So, the hardware is ready to go when tail BD pointer is updated
+		 */
+		BdPtr = (UINTPTR)(void *)(RingPtr->BdaRestart);
+
+		if (!XAxiDma_BdHwCompleted(BdPtr)) {
+			if (RingPtr->IsRxChannel) {
+				if (!RingIndex) {
+					XAxiDma_WriteReg(RegBase,
+							 XAXIDMA_CDESC_OFFSET,
+							 (XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
+					if (RingPtr->Addr_ext)
+						XAxiDma_WriteReg(RegBase,
+								 XAXIDMA_CDESC_MSB_OFFSET,
+								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
+				}
+				else {
+					XAxiDma_WriteReg(RegBase,
+					(XAXIDMA_RX_CDESC0_OFFSET +
+					(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+					(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
+					if (RingPtr->Addr_ext)
+						XAxiDma_WriteReg(RegBase,
+								 (XAXIDMA_RX_CDESC0_MSB_OFFSET +
+								 (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
+				}
+			}
+			else {
+				XAxiDma_WriteReg(RegBase,
+						 XAXIDMA_CDESC_OFFSET,
+						 (XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
+				if (RingPtr->Addr_ext)
+					XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET,
+							 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
+			}
+		}
+		else {
+			/* Look for an uncompleted BD
+			*/
+			while (XAxiDma_BdHwCompleted(BdPtr)) {
+				BdPtr = XAxiDma_BdRingNext(RingPtr, BdPtr);
+
+				if ((UINTPTR)BdPtr == (UINTPTR) RingPtr->BdaRestart) {
+					xdbg_printf(XDBG_DEBUG_ERROR,
+					"StartBdRingHw: Cannot find valid cdesc\r\n");
+
+					return XST_DMA_ERROR;
+				}
+
+				if (!XAxiDma_BdHwCompleted(BdPtr)) {
+					if (RingPtr->IsRxChannel) {
+						if (!RingIndex) {
+							XAxiDma_WriteReg(RegBase,
+								XAXIDMA_CDESC_OFFSET,(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
+							if (RingPtr->Addr_ext)
+								XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET,
+									UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
+						}
+						else {
+							XAxiDma_WriteReg(RegBase,
+								(XAXIDMA_RX_CDESC0_OFFSET +
+								(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+								(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
+							if (RingPtr->Addr_ext)
+								XAxiDma_WriteReg(RegBase,
+									(XAXIDMA_RX_CDESC0_MSB_OFFSET +
+									(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+									UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
+						}
+					}
+					else {
+						XAxiDma_WriteReg(RegBase,
+								XAXIDMA_CDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
+						if (RingPtr->Addr_ext)
+							XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET,
+									 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
+					}
+					break;
+				}
+			}
+		}
+
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, This fundtion creates and
+ * setup the BD ring.
+ *
+ * @param	RingPtr is the BD ring instance to be worked on.
+ * @param	PhysAddr is the physical base address of application memory
+ *		region.
+ * @param	VirtAddr is the virtual base address of the application memory
+ *		region.If address translation is not being utilized, then
+ *		VirtAddr should be equivalent to PhysAddr.
+ * @param	Alignment governs the byte alignment of individual BDs. This
+ *		function will enforce a minimum alignment of
+ *		XAXIDMA_BD_MINIMUM_ALIGNMENT bytes with no maximum as long as
+ *		it is specified as a power of 2.
+ * @param	BdCount is the number of BDs to setup in the application memory
+ *		region. It is assumed the region is large enough to contain the
+ *		BDs.Refer to the "SGDMA Ring Creation" section  in xaxidma.h
+ *		for more information. The minimum valid value for this
+ *		parameter is 1.
+ *
+ * @return
+ *		- XST_SUCCESS if initialization was successful
+ * 		- XST_NO_FEATURE if the provided instance is a non SGDMA type
+ *		of DMA channel.
+ *		- XST_INVALID_PARAM under any of the following conditions:
+ *		1) BdCount is not positive
+ *
+ *		2) PhysAddr and/or VirtAddr are not aligned to the given
+ *		Alignment parameter;
+ *
+ *		3) Alignment parameter does not meet minimum requirements or
+ *		is not a power of 2 value.
+ *
+ *		- XST_DMA_SG_LIST_ERROR if the memory segment containing the
+ *		list spans over address 0x00000000 in virtual address space.
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+u32 XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, UINTPTR PhysAddr,
+			UINTPTR VirtAddr, u32 Alignment, int BdCount)
+{
+	int i;
+	UINTPTR BdVirtAddr;
+	UINTPTR BdPhysAddr;
+
+	if (BdCount <= 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: non-positive BD"
+				" number %d\r\n", BdCount);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* In case there is a failure prior to creating list, make sure the
+	 * following attributes are 0 to prevent calls to other SG functions
+	 * from doing anything
+	 */
+	RingPtr->AllCnt = 0;
+	RingPtr->FreeCnt = 0;
+	RingPtr->HwCnt = 0;
+	RingPtr->PreCnt = 0;
+	RingPtr->PostCnt = 0;
+
+	/* Make sure Alignment parameter meets minimum requirements */
+	if (Alignment < XAXIDMA_BD_MINIMUM_ALIGNMENT) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: alignment too "
+		"small %d, need to be at least %d\r\n", (int)Alignment,
+			XAXIDMA_BD_MINIMUM_ALIGNMENT);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* Make sure Alignment is a power of 2 */
+	if ((Alignment - 1) & Alignment) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: alignment not"
+				" valid %d\r\n", (int)Alignment);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* Make sure PhysAddr and VirtAddr are on same Alignment */
+	if ((PhysAddr % Alignment) || (VirtAddr % Alignment)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: Physical address"
+		" %x and virtual address %x have different alignment\r\n",
+			(unsigned int)PhysAddr, (unsigned int)VirtAddr);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* Compute how many bytes will be between the start of adjacent BDs */
+	RingPtr->Separation =
+		(sizeof(XAxiDma_Bd) + (Alignment - 1)) & ~(Alignment - 1);
+
+	/* Must make sure the ring doesn't span address 0x00000000. If it does,
+	 * then the next/prev BD traversal macros will fail.
+	 */
+	if (VirtAddr > (VirtAddr + (RingPtr->Separation * BdCount) - 1)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCreate: BD space cross "
+			"0x0\r\n");
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* Initial ring setup:
+	 *  - Clear the entire space
+	 *  - Setup each BD's next pointer with the physical address of the
+	 *    next BD
+	 *  - Put hardware information in each BD
+	 */
+	memset((void *) VirtAddr, 0, (RingPtr->Separation * BdCount));
+
+	BdVirtAddr = VirtAddr;
+	BdPhysAddr = PhysAddr + RingPtr->Separation;
+	for (i = 1; i < BdCount; i++) {
+		XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_ADDRLEN_OFFSET,
+				RingPtr->Addr_ext);
+		XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET,
+				(BdPhysAddr & XAXIDMA_DESC_LSB_MASK));
+		XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_MSB_OFFSET,
+				UPPER_32_BITS(BdPhysAddr));
+
+		/* Put hardware information in the BDs
+		 */
+		XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET,
+				(u32)RingPtr->HasStsCntrlStrm);
+
+		XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_DRE_OFFSET,
+		    (((u32)(RingPtr->HasDRE)) << XAXIDMA_BD_HAS_DRE_SHIFT) |
+		    RingPtr->DataWidth);
+
+		XAXIDMA_CACHE_FLUSH(BdVirtAddr);
+		BdVirtAddr += RingPtr->Separation;
+		BdPhysAddr += RingPtr->Separation;
+	}
+
+	/* At the end of the ring, link the last BD back to the top */
+	XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_ADDRLEN_OFFSET,
+			RingPtr->Addr_ext);
+	XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET,
+			(PhysAddr & XAXIDMA_DESC_LSB_MASK));
+	XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_MSB_OFFSET,
+			UPPER_32_BITS(PhysAddr));
+
+
+	/* Setup the last BD's hardware information */
+	XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET,
+		(u32)RingPtr->HasStsCntrlStrm);
+
+	XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_DRE_OFFSET,
+	    (((u32)(RingPtr->HasDRE)) << XAXIDMA_BD_HAS_DRE_SHIFT) |
+	    RingPtr->DataWidth);
+
+	/* Setup and initialize pointers and counters */
+	RingPtr->RunState = AXIDMA_CHANNEL_HALTED;
+	RingPtr->FirstBdAddr = VirtAddr;
+	RingPtr->FirstBdPhysAddr = PhysAddr;
+	RingPtr->LastBdAddr = BdVirtAddr;
+	RingPtr->Length = RingPtr->LastBdAddr - RingPtr->FirstBdAddr +
+		RingPtr->Separation;
+	RingPtr->AllCnt = BdCount;
+	RingPtr->FreeCnt = BdCount;
+	RingPtr->FreeHead = (XAxiDma_Bd *) VirtAddr;
+	RingPtr->PreHead = (XAxiDma_Bd *) VirtAddr;
+	RingPtr->HwHead = (XAxiDma_Bd *) VirtAddr;
+	RingPtr->HwTail = (XAxiDma_Bd *) VirtAddr;
+	RingPtr->PostHead = (XAxiDma_Bd *) VirtAddr;
+	RingPtr->BdaRestart = (XAxiDma_Bd *) VirtAddr;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the ring. Only the fields offset from
+ * XAXIDMA_BD_START_CLEAR are copied, for XAXIDMA_BD_BYTES_TO_CLEAR bytes.
+ * This covers: BufferAddr, Control/Buffer length, status, APP words 0 - 4,
+ * and software ID fields.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * immediately after creation of the ring. This prevents modification
+ * of BDs while they are in use by hardware or the application.
+ *
+ * @param	RingPtr is the BD ring instance to be worked on.
+ * @param	SrcBdPtr is the source BD template to be cloned into the list.
+ *
+ * @return
+ *		- XST_SUCCESS if the list was modified.
+ *		- XST_DMA_SG_NO_LIST if a list has not been created.
+ *		- XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *		- XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are
+ *		under hardware or application control.
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr)
+{
+	int i;
+	UINTPTR CurBd;
+	u32 Save;
+	XAxiDma_Bd TmpBd;
+
+	/* Can't do this function if there isn't a ring */
+	if (RingPtr->AllCnt == 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingClone: no bds\r\n");
+
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* Can't do this function with the channel running */
+	if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingClone: bd ring started "
+			"already, cannot do\r\n");
+
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/* Can't do this function with some of the BDs in use */
+	if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingClone: some bds already "
+			"in use %d/%d\r\n",RingPtr->FreeCnt, RingPtr->AllCnt);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* Make a copy of the template then modify it by clearing
+	 * the complete bit in status/control field
+	 */
+	memcpy(&TmpBd, SrcBdPtr, sizeof(XAxiDma_Bd));
+
+	Save = XAxiDma_BdRead(&TmpBd, XAXIDMA_BD_STS_OFFSET);
+	Save &= ~XAXIDMA_BD_STS_COMPLETE_MASK;
+	XAxiDma_BdWrite(&TmpBd, XAXIDMA_BD_STS_OFFSET, Save);
+
+	for (i = 0, CurBd = RingPtr->FirstBdAddr;
+	     i < RingPtr->AllCnt; i++, CurBd += RingPtr->Separation) {
+
+		memcpy((void *)((UINTPTR)CurBd + XAXIDMA_BD_START_CLEAR),
+		    (void *)((UINTPTR)(&TmpBd) + XAXIDMA_BD_START_CLEAR),
+		    XAXIDMA_BD_BYTES_TO_CLEAR);
+
+		XAXIDMA_CACHE_FLUSH(CurBd);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Start a DMA channel and
+ * Allow DMA transactions to commence on a given channel if descriptors are
+ * ready to be processed.
+ *
+ * After a DMA channel is started, it is not halted, and it is idle (no active
+ * DMA transfers).
+ *
+ * @param	RingPtr is the Channel instance to be worked on
+ *
+ * @return
+ *		- XST_SUCCESS upon success
+ *		- XST_DMA_ERROR if no valid BD available to put into current
+ *		BD register
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr)
+{
+	u32 RegBase;
+	int RingIndex = RingPtr->RingIndex;
+
+	if (!XAxiDma_BdRingHwIsStarted(RingPtr)) {
+		/* Start the hardware
+		*/
+		RegBase = RingPtr->ChanBase;
+		XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET,
+			XAxiDma_ReadReg(RegBase, XAXIDMA_CR_OFFSET)
+			| XAXIDMA_CR_RUNSTOP_MASK);
+	}
+
+	if (XAxiDma_BdRingHwIsStarted(RingPtr)) {
+		/* Note as started */
+		RingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
+
+		/* If there are unprocessed BDs then we want the channel to begin
+		 * processing right away
+		 */
+		if (RingPtr->HwCnt > 0) {
+
+			XAXIDMA_CACHE_INVALIDATE(RingPtr->HwTail);
+
+			if ((XAxiDma_BdRead(RingPtr->HwTail,
+				    XAXIDMA_BD_STS_OFFSET) &
+				XAXIDMA_BD_STS_COMPLETE_MASK) == 0) {
+				if (RingPtr->IsRxChannel) {
+					if (!RingIndex) {
+						XAxiDma_WriteReg(RingPtr->ChanBase,
+							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
+						if (RingPtr->Addr_ext)
+							XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
+								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
+					}
+					else {
+						XAxiDma_WriteReg(RingPtr->ChanBase,
+							(XAXIDMA_RX_TDESC0_OFFSET +
+							(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+							(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK ));
+						if (RingPtr->Addr_ext)
+							XAxiDma_WriteReg(RingPtr->ChanBase,
+								(XAXIDMA_RX_TDESC0_MSB_OFFSET +
+								(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+								UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
+					}
+				}
+				else {
+					XAxiDma_WriteReg(RingPtr->ChanBase,
+							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
+					if (RingPtr->Addr_ext)
+						XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
+								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
+				}
+			}
+		}
+
+		return XST_SUCCESS;
+	}
+
+	return XST_DMA_ERROR;
+}
+
+/*****************************************************************************/
+/**
+ * Start a DMA channel, updates current descriptors and
+ * Allow DMA transactions to commence on a given channel if descriptors are
+ * ready to be processed.
+ *
+ * After a DMA channel is started, it is not halted, and it is idle (no active
+ * DMA transfers).
+ *
+ * @param	RingPtr is the Channel instance to be worked on
+ *
+ * @return
+ *		- XST_SUCCESS upon success
+ *		- XST_DMA_ERROR if no valid BD available to put into current
+ *		BD register
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr)
+{
+	int Status;
+
+	Status = XAxiDma_UpdateBdRingCDesc(RingPtr);
+	if (Status != XST_SUCCESS) {
+		 xdbg_printf(XDBG_DEBUG_ERROR, "BdRingStart: "
+			"Updating Current Descriptor Failed\n\r");
+		return Status;
+	}
+
+	Status = XAxiDma_StartBdRingHw(RingPtr);
+	if (Status != XST_SUCCESS) {
+		 xdbg_printf(XDBG_DEBUG_ERROR, "BdRingStart: "
+			"Starting Hardware Failed\n\r");
+		return Status;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Set interrupt coalescing parameters for the given descriptor ring channel.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	Counter sets the packet counter on the channel. Valid range is
+ *		- 1..255.
+ *		- XAXIDMA_NO_CHANGE to leave this setting unchanged.
+ * @param	Timer sets the waitbound timer on the channel. Valid range is
+ * 		- 0..255.
+ *		- XAXIDMA_NO_CHANGE to leave this setting unchanged.
+ *		Each unit depend on hardware building parameter
+ *		C_DLYTMR_RESOLUTION,which is in the range from 0 to 100,000
+ *		clock cycles. A value of 0 disables the delay interrupt.
+ *
+ * @return
+ *		- XST_SUCCESS if interrupt coalescing settings updated
+ *		- XST_FAILURE if Counter or Timer parameters are out of range
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing *RingPtr, u32 Counter, u32 Timer)
+{
+	u32 Cr;
+
+	Cr = XAxiDma_ReadReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET);
+
+	if (Counter != XAXIDMA_NO_CHANGE) {
+		if ((Counter == 0) || (Counter > 0xFF)) {
+
+			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: "
+			"invalid  coalescing threshold %d", (int)Counter);
+			return XST_FAILURE;
+		}
+
+		Cr = (Cr & ~XAXIDMA_COALESCE_MASK) |
+			(Counter << XAXIDMA_COALESCE_SHIFT);
+	}
+
+	if (Timer != XAXIDMA_NO_CHANGE) {
+		if (Timer > 0xFF) {
+
+			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: "
+			"invalid  delay counter %d", (int)Timer);
+
+			return XST_FAILURE;
+		}
+
+		Cr = (Cr & ~XAXIDMA_DELAY_MASK) |
+			(Timer << XAXIDMA_DELAY_SHIFT);
+	}
+
+	XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET, Cr);
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Retrieve current interrupt coalescing parameters from the given descriptor
+ * ring channel.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	CounterPtr points to a memory location where the current packet
+ *		counter will be written.
+ * @param	TimerPtr points to a memory location where the current
+ *		waitbound timer will be written.
+ *
+ * @return	The passed in parameters, CounterPtr and TimerPtr, holds the
+ *		references to the return values.
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr,
+			      u32 *CounterPtr, u32 *TimerPtr)
+{
+	u32 Cr;
+
+	Cr = XAxiDma_ReadReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET);
+
+	*CounterPtr = ((Cr & XAXIDMA_COALESCE_MASK) >> XAXIDMA_COALESCE_SHIFT);
+	*TimerPtr = ((Cr & XAXIDMA_DELAY_MASK) >> XAXIDMA_DELAY_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD ring. The set of returned BDs may be modified in
+ * preparation for future DMA transactions. Once the BDs are ready to be
+ * submitted to hardware, the application must call XAxiDma_BdRingToHw() in the
+ * same order which they were allocated here. Example:
+ *
+ * <pre>
+ *        NumBd = 2;
+ *        Status = XDsma_RingBdAlloc(MyRingPtr, NumBd, &MyBdSet);
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            // Not enough BDs available for the request
+ *        }
+ *
+ *        CurBd = MyBdSet;
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *            // Prepare CurBd.....
+ *
+ *            // Onto next BD
+ *            CurBd = XAxiDma_BdRingNext(MyRingPtr, CurBd);
+ *        }
+ *
+ *        // Give list to hardware
+ *        Status = XAxiDma_BdRingToHw(MyRingPtr, NumBd, MyBdSet);
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * <pre>
+ *        // Legal
+ *        XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
+ *        XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+ *
+ *        // Legal
+ *        XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
+ *        XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
+ *        XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+ *        XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);
+ *
+ *        // Not legal
+ *        XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
+ *        XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
+ *        XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);
+ *        XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+ * </pre>
+ *
+ * Use the API defined in xaxidmabd.h to modify individual BDs. Traversal of
+ * the BD set can be done using XAxiDma_BdRingNext() and XAxiDma_BdRingPrev().
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	NumBd is the number of BDs to allocate
+ * @param	BdSetPtr is an output parameter, it points to the first BD
+ *		available for modification.
+ *
+ * @return
+ *		- XST_SUCCESS if the requested number of BDs were returned in
+ *		the BdSetPtr parameter.
+ *		- XST_INVALID_PARAM if passed in NumBd is not positive
+ *		- XST_FAILURE if there were not enough free BDs to satisfy
+ *		the request.
+ *
+ * @note	This function should not be preempted by another XAxiDma_BdRing
+ *		function call that modifies the BD space. It is the caller's
+ *		responsibility to provide a mutual exclusion mechanism.
+ *
+ *		Do not modify more BDs than the number requested with the NumBd
+ *		parameter. Doing so will lead to data corruption and system
+ *		instability.
+ *
+ *		This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+	XAxiDma_Bd ** BdSetPtr)
+{
+	if (NumBd <= 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingAlloc: negative BD "
+				"number %d\r\n", NumBd);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		xdbg_printf(XDBG_DEBUG_ERROR,
+		"Not enough BDs to alloc %d/%d\r\n", NumBd, RingPtr->FreeCnt);
+
+		return XST_FAILURE;
+	}
+
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XAxiDma_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XAxiDma_BdRingAlloc() could not be
+ * transferred to hardware with XAxiDma_BdRingToHw().
+ *
+ * This function releases the BDs after they have been allocated but before
+ * they have been given to hardware.
+ *
+ * This function is not the same as XAxiDma_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ *    Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &BdPtr);
+ *        ...
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XAxiDma_BdRingUnAlloc(MyRingPtr, 10, &BdPtr);
+ *    }
+ * </pre>
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ *    Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &BdPtr);
+ *    BdsLeft = 10;
+ *    CurBdPtr = BdPtr;
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XAxiDma_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr);
+ *       }
+ *
+ *       CurBdPtr = XAxiDma_BdRingNext(MyRingPtr, CurBdPtr);
+ *       BdsLeft--;
+ *    }
+ * </pre>
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	NumBd is the number of BDs to unallocate
+ * @param	BdSetPtr points to the first of the BDs to be returned.
+ *
+ * @return
+ *		- XST_SUCCESS if the BDs were unallocated.
+ *		- XST_INVALID_PARAM if passed in NumBd is negative
+ *		- XST_FAILURE if NumBd parameter was greater that the number of
+ *		BDs in the preprocessing state.
+ *
+ * @note	This function should not be preempted by another XAxiDma ring
+ *		function call that modifies the BD space. It is the caller's
+ *		responsibility to provide a mutual exclusion mechanism.
+ *
+ *		This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+	XAxiDma_Bd * BdSetPtr)
+{
+	XAxiDma_Bd *TmpBd;
+
+	if (NumBd <= 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingUnAlloc: negative BD"
+		" number %d\r\n", NumBd);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* Enough BDs in the preprocessing state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		xdbg_printf(XDBG_DEBUG_ERROR,
+		"Pre-allocated BDs less than requested %d/%d\r\n",
+		RingPtr->PreCnt, NumBd);
+
+		return XST_FAILURE;
+	}
+
+	/* The last BD in the BD set must has the FreeHead as its next BD.
+	 * Otherwise, this is not a valid operation.
+	 */
+	TmpBd = BdSetPtr;
+	XAXIDMA_RING_SEEKAHEAD(RingPtr, TmpBd, NumBd);
+
+	if (TmpBd != RingPtr->FreeHead) {
+		xdbg_printf(XDBG_DEBUG_ERROR,
+		    "Unalloc does not go back to free head\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/* Set the return argument and move FreeHead backward */
+	XAXIDMA_RING_SEEKBACK(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XAxiDma_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Changes to these BDs should be held until they are
+ * finished by hardware to avoid data corruption and system instability.
+ *
+ * For transmit, the set will be rejected if the last BD of the set does not
+ * mark the end of a packet or the first BD does not mark the start of a packet.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	NumBd is the number of BDs in the set.
+ * @param	BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *		- XST_SUCCESS if the set of BDs was accepted and enqueued to
+ *		hardware
+ *		- XST_INVALID_PARAM if passed in NumBd is negative
+ *		- XST_FAILURE if the set of BDs was rejected because the first
+ *		BD does not have its start-of-packet bit set, or the last BD
+ *		does not have its end-of-packet bit set, or any one of the BDs
+ *		has 0 length.
+ *		- XST_DMA_SG_LIST_ERROR if this function was called out of
+ *		sequence with XAxiDma_BdRingAlloc()
+ *
+ * @note	This function should not be preempted by another XAxiDma ring
+ *		function call that modifies the BD space. It is the caller's
+ *		responsibility to provide a mutual exclusion mechanism.
+ *
+ *		This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd,
+	XAxiDma_Bd * BdSetPtr)
+{
+	XAxiDma_Bd *CurBdPtr;
+	int i;
+	u32 BdCr;
+	u32 BdSts;
+	int RingIndex = RingPtr->RingIndex;
+
+	if (NumBd < 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingToHw: negative BD number "
+			"%d\r\n", NumBd);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* If the commit set is empty, do nothing */
+	if (NumBd == 0) {
+		return XST_SUCCESS;
+	}
+
+	/* Make sure we are in sync with XAxiDma_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Bd ring has problems\r\n");
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	CurBdPtr = BdSetPtr;
+	BdCr = XAxiDma_BdGetCtrl(CurBdPtr);
+	BdSts = XAxiDma_BdGetSts(CurBdPtr);
+
+	/* In case of Tx channel, the first BD should have been marked
+	 * as start-of-frame
+	 */
+	if (!(RingPtr->IsRxChannel) && !(BdCr & XAXIDMA_BD_CTRL_TXSOF_MASK)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Tx first BD does not have "
+								"SOF\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/* Clear the completed status bit
+	 */
+	for (i = 0; i < NumBd - 1; i++) {
+
+		/* Make sure the length value in the BD is non-zero. */
+		if (XAxiDma_BdGetLength(CurBdPtr,
+				RingPtr->MaxTransferLen) == 0) {
+
+			xdbg_printf(XDBG_DEBUG_ERROR, "0 length bd\r\n");
+
+			return XST_FAILURE;
+		}
+
+		BdSts &=  ~XAXIDMA_BD_STS_COMPLETE_MASK;
+		XAxiDma_BdWrite(CurBdPtr, XAXIDMA_BD_STS_OFFSET, BdSts);
+
+		/* Flush the current BD so DMA core could see the updates */
+		XAXIDMA_CACHE_FLUSH(CurBdPtr);
+
+		CurBdPtr = (XAxiDma_Bd *)((void *)XAxiDma_BdRingNext(RingPtr, CurBdPtr));
+		BdCr = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET);
+		BdSts = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_STS_OFFSET);
+	}
+
+	/* In case of Tx channel, the last BD should have EOF bit set */
+	if (!(RingPtr->IsRxChannel) && !(BdCr & XAXIDMA_BD_CTRL_TXEOF_MASK)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "Tx last BD does not have "
+								"EOF\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/* Make sure the length value in the last BD is non-zero. */
+	if (XAxiDma_BdGetLength(CurBdPtr,
+			RingPtr->MaxTransferLen) == 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "0 length bd\r\n");
+
+		return XST_FAILURE;
+	}
+
+	/* The last BD should also have the completed status bit cleared
+	 */
+	BdSts &= ~XAXIDMA_BD_STS_COMPLETE_MASK;
+	XAxiDma_BdWrite(CurBdPtr, XAXIDMA_BD_STS_OFFSET, BdSts);
+
+	/* Flush the last BD so DMA core could see the updates */
+	XAXIDMA_CACHE_FLUSH(CurBdPtr);
+	DATA_SYNC;
+
+	/* This set has completed pre-processing, adjust ring pointers and
+	 * counters
+	 */
+	XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+	/* If it is running, signal the engine to begin processing */
+	if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) {
+			if (RingPtr->IsRxChannel) {
+				if (!RingIndex) {
+					XAxiDma_WriteReg(RingPtr->ChanBase,
+							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
+					if (RingPtr->Addr_ext)
+						XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
+								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
+				}
+				else {
+					XAxiDma_WriteReg(RingPtr->ChanBase,
+						(XAXIDMA_RX_TDESC0_OFFSET +
+						(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+						(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK ));
+					if (RingPtr->Addr_ext)
+						XAxiDma_WriteReg(RingPtr->ChanBase,
+							(XAXIDMA_RX_TDESC0_MSB_OFFSET +
+							(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
+							UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
+				}
+			}
+			else {
+				XAxiDma_WriteReg(RingPtr->ChanBase,
+							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
+				if (RingPtr->Addr_ext)
+					XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
+								UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
+			}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined by the application to determine the outcome of the DMA
+ * transactions. Once the BDs have been examined, the application must call
+ * XAxiDma_BdRingFree() in the same order which they were retrieved here.
+ *
+ * Example:
+ *
+ * <pre>
+ *        NumBd = XAxiDma_BdRingFromHw(MyRingPtr, XAXIDMA_ALL_BDS, &MyBdSet);
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           // hardware has nothing ready for us yet
+ *        }
+ *
+ *        CurBd = MyBdSet;
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *           // Examine CurBd for post processing.....
+ *
+ *           // Onto next BD
+ *           CurBd = XAxiDma_BdRingNext(MyRingPtr, CurBd);
+ *        }
+ *
+ *        XAxiDma_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return the list
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ *        // Legal
+ *        XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1);
+ *        XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ *
+ *        // Legal
+ *        XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1);
+ *        XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &MySet2);
+ *        XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ *        XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);
+ *
+ *        // Not legal
+ *        XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1);
+ *        XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &MySet2);
+ *        XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);
+ *        XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ * </pre>
+ *
+ * If hardware has partially completed a packet spanning multiple BDs, then
+ * none of the BDs for that packet will be included in the results.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	BdLimit is the maximum number of BDs to return in the set. Use
+ *		XAXIDMA_ALL_BDS to return all BDs that have been processed.
+ * @param	BdSetPtr is an output parameter, it points to the first BD
+ *		available for examination.
+ *
+ * @return	The number of BDs processed by hardware. A value of 0 indicates
+ *		that no data is available. No more than BdLimit BDs will be
+ *		returned.
+ *
+ * @note	Treat BDs returned by this function as read-only.
+ *
+ * 		This function should not be preempted by another XAxiDma ring
+ *		function call that modifies the BD space. It is the caller's
+ *		responsibility to provide a mutual exclusion mechanism.
+ *
+ *		This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit,
+			     XAxiDma_Bd ** BdSetPtr)
+{
+	XAxiDma_Bd *CurBdPtr;
+	int BdCount;
+	int BdPartialCount;
+	u32 BdSts;
+	u32 BdCr;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0;
+	BdPartialCount = 0;
+	BdSts = 0;
+	BdCr = 0;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0) {
+		*BdSetPtr = (XAxiDma_Bd *)NULL;
+
+		return 0;
+	}
+
+	if (BdLimit > RingPtr->HwCnt) {
+		BdLimit = RingPtr->HwCnt;
+	}
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its completed bit clear in the status
+	 *    word which means hardware has not completed processing of that
+	 *    BD.
+	 *  - RingPtr->HwTail is reached
+	 *  - The number of requested BDs has been processed
+	 */
+
+	while (BdCount < BdLimit) {
+		/* Read the status */
+		XAXIDMA_CACHE_INVALIDATE(CurBdPtr);
+		BdSts = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_STS_OFFSET);
+		BdCr = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET);
+
+		/* If the hardware still hasn't processed this BD then we are
+		 * done
+		 */
+		if (!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK)) {
+			break;
+		}
+
+		BdCount++;
+
+		/* Hardware has processed this BD so check the "last" bit. If
+		 * it is clear, then there are more BDs for the current packet.
+		 * Keep a count of these partial packet BDs.
+		 *
+		 * For tx BDs, EOF bit is in the control word
+		 * For rx BDs, EOF bit is in the status word
+		 */
+		if (((!(RingPtr->IsRxChannel) &&
+		(BdCr & XAXIDMA_BD_CTRL_TXEOF_MASK)) ||
+		((RingPtr->IsRxChannel) && (BdSts &
+			XAXIDMA_BD_STS_RXEOF_MASK)))) {
+
+			BdPartialCount = 0;
+		}
+		else {
+			BdPartialCount++;
+		}
+
+		/* Reached the end of the work group */
+		if (CurBdPtr == RingPtr->HwTail) {
+			break;
+		}
+
+		/* Move on to the next BD in work group */
+		CurBdPtr = (XAxiDma_Bd *)((void *)XAxiDma_BdRingNext(RingPtr, CurBdPtr));
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+	if (BdCount) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+
+		return BdCount;
+	}
+	else {
+		*BdSetPtr = (XAxiDma_Bd *)NULL;
+
+		return 0;
+	}
+}
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XAxiDma_BdRingFromHw().
+ *
+ * @param	RingPtr is a pointer to the descriptor ring instance to be
+ *		worked on.
+ * @param	NumBd is the number of BDs to free.
+ * @param	BdSetPtr is the head of a list of BDs returned by
+ *		XAxiDma_BdRingFromHw().
+ *
+ * @return
+ *		- XST_SUCCESS if the set of BDs was freed.
+ *		- XST_INVALID_PARAM if NumBd is negative
+ *		- XST_DMA_SG_LIST_ERROR if this function was called out of
+ *		sequence with XAxiDma_BdRingFromHw().
+ *
+ * @note	This function should not be preempted by another XAxiDma
+ *		function call that modifies the BD space. It is the caller's
+ *		responsibility to ensure mutual exclusion.
+ *
+ *		This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd,
+		      XAxiDma_Bd * BdSetPtr)
+{
+	if (NumBd < 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR,
+		    "BdRingFree: negative BDs %d\r\n", NumBd);
+
+		return XST_INVALID_PARAM;
+	}
+
+	/* If the BD Set to free is empty, do nothing
+	 */
+	if (NumBd == 0) {
+		return XST_SUCCESS;
+	}
+
+	/* Make sure we are in sync with XAxiDma_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingFree: Error free BDs: "
+		"post count %d to free %d, PostHead %x to free ptr %x\r\n",
+			RingPtr->PostCnt, NumBd,
+			(UINTPTR)RingPtr->PostHead,
+			(UINTPTR)BdSetPtr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XAXIDMA_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *	- The BD ring is linked correctly in physical address space.
+ *	- The internal pointers point to BDs in the ring.
+ *	- The internal counters add up.
+ *
+ * The channel should be stopped (through XAxiDma_Pause() or XAxiDma_Reset())
+ * prior to calling this function.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring to be worked on.
+ *
+ * @return
+ *		- XST_SUCCESS if no errors were found.
+ *		- XST_DMA_SG_NO_LIST if the ring has not been created.
+ *		- XST_IS_STARTED if the channel is not stopped.
+ *		- XST_DMA_SG_LIST_ERROR if a problem is found with the internal
+ *		data structures. If this value is returned, the channel should
+ *		be reset,and the BD ring should be recreated through
+ *		XAxiDma_BdRingCreate() to avoid data corruption or system
+ *		instability.
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr)
+{
+	u32 AddrV;
+	u32 AddrP;
+	int i;
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: no BDs\r\n");
+
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == AXIDMA_CHANNEL_NOT_HALTED) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: Bd ring is "
+		"running, cannot check it\r\n");
+
+		return XST_IS_STARTED;
+	}
+
+	/* RunState doesn't make sense */
+	else if (RingPtr->RunState != AXIDMA_CHANNEL_HALTED) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: unknown BD ring "
+			"state %d ", RingPtr->RunState);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: FreeHead wrong "
+		"%x, should be in range of %x/%x\r\n",
+		    (unsigned int)AddrV,
+		    (unsigned int)RingPtr->FirstBdAddr,
+			(unsigned int)RingPtr->LastBdAddr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: PreHead wrong %x, "
+			"should be in range of %x/%x\r\n",
+		    (unsigned int)AddrV,
+		    (unsigned int)RingPtr->FirstBdAddr,
+			(unsigned int)RingPtr->LastBdAddr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: HwHead wrong %x, "
+			"should be in range of %x/%x\r\n",
+		    (unsigned int)AddrV,
+		    (unsigned int)RingPtr->FirstBdAddr,
+			(unsigned int)RingPtr->LastBdAddr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: HwTail wrong %x, "
+			"should be in range of %x/%x\r\n",
+		    (unsigned int)AddrV,
+		    (unsigned int)RingPtr->FirstBdAddr,
+			(unsigned int)RingPtr->LastBdAddr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: PostHead wrong "
+		"%x, should be in range of %x/%x\r\n",
+		    (unsigned int)AddrV,
+		    (unsigned int)RingPtr->FirstBdAddr,
+			(unsigned int)RingPtr->LastBdAddr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: internal counter "
+			"error\r\n");
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->FirstBdAddr;
+	AddrP = RingPtr->FirstBdPhysAddr + RingPtr->Separation;
+	for (i = 1; i < RingPtr->AllCnt; i++) {
+		XAXIDMA_CACHE_INVALIDATE(AddrV);
+		/* Check next pointer for this BD. It should equal to the
+		 * physical address of next BD
+		 */
+		if (XAxiDma_BdRead(AddrV, XAXIDMA_BD_NDESC_OFFSET) != AddrP) {
+
+			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: Next Bd "
+			"ptr %x wrong, expect %x\r\n",
+				(unsigned int)XAxiDma_BdRead(AddrV,
+			        XAXIDMA_BD_NDESC_OFFSET),
+				(unsigned int)AddrP);
+
+			return XST_DMA_SG_LIST_ERROR;
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	XAXIDMA_CACHE_INVALIDATE(AddrV);
+	/* Last BD should point back to the beginning of ring */
+	if (XAxiDma_BdRead(AddrV, XAXIDMA_BD_NDESC_OFFSET) !=
+	    RingPtr->FirstBdPhysAddr) {
+
+		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: last Bd Next BD "
+		"ptr %x wrong, expect %x\r\n",
+			(unsigned int)XAxiDma_BdRead(AddrV,
+		          XAXIDMA_BD_NDESC_OFFSET),
+			(unsigned int)RingPtr->FirstBdPhysAddr);
+
+		return XST_DMA_SG_LIST_ERROR;
+	}
+
+	/* No problems found */
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+ * Dump the registers for a channel.
+ *
+ * @param	RingPtr is a pointer to the descriptor ring to be worked on.
+ *
+ * @return	None
+ *
+ * @note	This function can be used only when DMA is in SG mode
+ *
+ *****************************************************************************/
+void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr) {
+	u32 RegBase = RingPtr->ChanBase;
+	int RingIndex = RingPtr->RingIndex;
+
+	xil_printf("Dump registers %x:\r\n", (unsigned int)RegBase);
+	xil_printf("Control REG: %08x\r\n",
+		(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_CR_OFFSET));
+	xil_printf("Status REG: %08x\r\n",
+		(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_SR_OFFSET));
+
+	if (RingIndex) {
+	xil_printf("Cur BD REG: %08x\r\n",
+		(unsigned int)XAxiDma_ReadReg(RegBase,
+		XAXIDMA_RX_CDESC0_OFFSET + ((RingIndex - 1) *
+		XAXIDMA_RX_NDESC_OFFSET)));
+	xil_printf("Tail BD REG: %08x\r\n",
+		(unsigned int)XAxiDma_ReadReg(RegBase,
+		XAXIDMA_RX_TDESC0_OFFSET + ((RingIndex - 1) *
+		XAXIDMA_RX_NDESC_OFFSET)));
+	}
+	else {
+	xil_printf("Cur BD REG: %08x\r\n",
+		(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_CDESC_OFFSET));
+	xil_printf("Tail BD REG: %08x\r\n",
+		(unsigned int)XAxiDma_ReadReg(RegBase, XAXIDMA_TDESC_OFFSET));
+	}
+
+	xil_printf("\r\n");
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bdring.h b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bdring.h
new file mode 100644
index 000000000..351f65827
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_bdring.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_bdring.h
+* @addtogroup axidma_v9_0
+* @{
+*
+* This file contains DMA channel related structure and constant definition
+* as well as function prototypes. Each DMA channel is managed by a Buffer
+* Descriptor ring, and XAxiDma_BdRing is chosen as the symbol prefix used in
+* this file. See xaxidma.h for more information on how a BD ring is managed.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA.
+*		      - New API
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+*		      - Changed APIs
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XAXIDMA_BDRING_H_	/* prevent circular inclusions */
+#define XAXIDMA_BDRING_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xaxidma_bd.h"
+
+
+
+/************************** Constant Definitions *****************************/
+/* State of a DMA channel
+ */
+#define AXIDMA_CHANNEL_NOT_HALTED	1
+#define AXIDMA_CHANNEL_HALTED		2
+
+/* Argument constant to simplify argument setting
+ */
+#define XAXIDMA_NO_CHANGE		0xFFFFFFFF
+#define XAXIDMA_ALL_BDS			0x0FFFFFFF /* 268 Million */
+
+/**************************** Type Definitions *******************************/
+
+/** Container structure for descriptor storage control. If address translation
+ * is enabled, then all addresses and pointers excluding FirstBdPhysAddr are
+ * expressed in terms of the virtual address.
+ */
+typedef struct {
+	u32 ChanBase;		/**< physical base address*/
+
+	int IsRxChannel;	/**< Is this a receive channel */
+	volatile int RunState;	/**< Whether channel is running */
+	int HasStsCntrlStrm; 	/**< Whether has stscntrl stream */
+	int HasDRE;
+	int DataWidth;
+	int Addr_ext;
+	u32 MaxTransferLen;
+
+	UINTPTR FirstBdPhysAddr;	/**< Physical address of 1st BD in list */
+	UINTPTR FirstBdAddr;	/**< Virtual address of 1st BD in list */
+	UINTPTR LastBdAddr;		/**< Virtual address of last BD in the list */
+	u32 Length;		/**< Total size of ring in bytes */
+	UINTPTR Separation;		/**< Number of bytes between the starting
+				     address of adjacent BDs */
+	XAxiDma_Bd *FreeHead;	/**< First BD in the free group */
+	XAxiDma_Bd *PreHead;	/**< First BD in the pre-work group */
+	XAxiDma_Bd *HwHead;	/**< First BD in the work group */
+	XAxiDma_Bd *HwTail;	/**< Last BD in the work group */
+	XAxiDma_Bd *PostHead;	/**< First BD in the post-work group */
+	XAxiDma_Bd *BdaRestart;	/**< BD to load when channel is started */
+	int FreeCnt;		/**< Number of allocatable BDs in free group */
+	int PreCnt;		/**< Number of BDs in pre-work group */
+	int HwCnt;		/**< Number of BDs in work group */
+	int PostCnt;		/**< Number of BDs in post-work group */
+	int AllCnt;		/**< Total Number of BDs for channel */
+	int RingIndex;		/**< Ring Index */
+} XAxiDma_BdRing;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* within the given memory constraints.
+*
+* The results of this macro can be provided to XAxiDma_BdRingCreate().
+*
+* @param	Alignment specifies what byte alignment the BDs must fall
+*		on and must be a power of 2 to get an accurate calculation
+*		(32, 64, 126,...)
+* @param	Bytes is the number of bytes to be used to store BDs.
+*
+* @return	Number of BDs that can fit in the given memory area
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*		This function is used only when system is configured as SG mode
+*
+******************************************************************************/
+#define XAxiDma_BdRingCntCalc(Alignment, Bytes)                           \
+	(uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* are required to contain a given number of BDs at a given alignment.
+*
+* @param	Alignment specifies what byte alignment the BDs must fall on.
+*		This parameter must be a power of 2 to get an accurate
+*		calculation (32, 64,128,...)
+* @param	NumBd is the number of BDs to calculate memory size
+*		requirements
+*
+* @return	The number of bytes of memory required to create a BD list
+*		with the given memory constraints.
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*		This function is used only when system is configured as SG mode
+*
+******************************************************************************/
+#define XAxiDma_BdRingMemCalc(Alignment, NumBd)			\
+	(int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XAxiDma_BdRingCreate().
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The total number of BDs allocated for this channel.
+*
+* @note
+* 		C-style signature:
+*		int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre-
+* processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The number of BDs currently allocatable.
+*
+* @note
+* 		C-style signature:
+*		int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetFreeCnt(RingPtr)  ((RingPtr)->FreeCnt)
+
+
+/****************************************************************************/
+/**
+* Snap shot the latest BD a BD ring is processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	None
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingSnapShotCurrBd(RingPtr)				  \
+	{								  \
+		if (!RingPtr->IsRxChannel) {				  \
+			(RingPtr)->BdaRestart = (XAxiDma_Bd *)		  \
+				XAxiDma_ReadReg((RingPtr)->ChanBase,	  \
+					XAXIDMA_CDESC_OFFSET);		  \
+		} else {						  \
+			if (!RingPtr->RingIndex) {			  \
+				(RingPtr)->BdaRestart =	(XAxiDma_Bd *)	  \
+				XAxiDma_ReadReg(			  \
+					(RingPtr)->ChanBase,		  \
+					XAXIDMA_CDESC_OFFSET);		  \
+			} else {					  \
+				(RingPtr)->BdaRestart =	(XAxiDma_Bd *)	  \
+				XAxiDma_ReadReg(			  \
+				(RingPtr)->ChanBase,			  \
+				(XAXIDMA_RX_CDESC0_OFFSET +		  \
+				(RingPtr->RingIndex - 1) * 		  \
+					XAXIDMA_RX_NDESC_OFFSET));	  \
+			}						  \
+		}							  \
+	}
+
+/****************************************************************************/
+/**
+* Get the BD a BD ring is processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The current BD that the BD ring is working on
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetCurrBd(RingPtr)               \
+	(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \
+					XAXIDMA_CDESC_OFFSET)              \
+
+/****************************************************************************/
+/**
+* Return the next BD in the ring.
+*
+* @param	RingPtr is the BD ring to operate on.
+* @param	BdPtr is the current BD.
+*
+* @return	The next BD in the ring relative to the BdPtr parameter.
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr,
+*							XAxiDma_Bd *BdPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingNext(RingPtr, BdPtr)			\
+		(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ?	\
+			(UINTPTR)(RingPtr)->FirstBdAddr :	\
+			(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD in the ring.
+*
+* @param	RingPtr is the DMA channel to operate on.
+* @param	BdPtr is the current BD.
+*
+* @return	The previous BD in the ring relative to the BdPtr parameter.
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr,
+*		XAxiDma_Bd *BdPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingPrev(RingPtr, BdPtr)				\
+		(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ?		\
+			(XAxiDma_Bd*)(RingPtr)->LastBdAddr :		\
+			(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Retrieve the contents of the channel status register
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Current contents of status register
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetSr(RingPtr)				\
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get error bits of a DMA channel
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Rrror bits in the status register, they should be interpreted
+*		with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetError(RingPtr)				\
+		(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_ERR_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Check whether a DMA channel is started, meaning the channel is not halted.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return
+*		- 1 if channel is started
+*		- 0 otherwise
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XAxiDma_BdRingHwIsStarted(RingPtr)				\
+		((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_HALTED_MASK) ? FALSE : TRUE)
+
+/****************************************************************************/
+/**
+* Check if the current DMA channel is busy with a DMA operation.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return
+*		- 1 if the DMA is busy.
+*		- 0 otherwise
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingBusy(RingPtr)					 \
+		(XAxiDma_BdRingHwIsStarted(RingPtr) &&		\
+		((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_IDLE_MASK) ? FALSE : TRUE))
+
+/****************************************************************************/
+/**
+* Set interrupt enable bits for a channel. This operation will modify the
+* XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @param	Mask consists of the interrupt signals to enable.Bits not
+*		specified in the mask are not affected.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntEnable(RingPtr, Mask)			\
+		(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
+			| ((Mask) & XAXIDMA_IRQ_ALL_MASK)))
+
+/****************************************************************************/
+/**
+* Get enabled interrupts of a channel. It is in XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @return	Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in
+*		xaxidma_hw.h to interpret this returned value.
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntGetEnabled(RingPtr)				\
+	(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
+		& XAXIDMA_IRQ_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Clear interrupt enable bits for a channel. It modifies the
+* XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @param	Mask consists of the interrupt signals to disable.Bits not
+*		specified in the Mask are not affected.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr,
+*								u32 Mask)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntDisable(RingPtr, Mask)				\
+		(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \
+			~((Mask) & XAXIDMA_IRQ_ALL_MASK)))
+
+/****************************************************************************/
+/**
+* Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. This
+* operation can be used to see which interrupts are pending.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Current contents of the IRQ_OFFSET register. Use
+*		XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret
+*		the returned value.
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetIrq(RingPtr)				\
+		(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_IRQ_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Acknowledge asserted interrupts. It modifies XAXIDMA_SR_OFFSET register.
+* A mask bit set for an unasserted interrupt has no effect.
+*
+* @param 	RingPtr is the channel instance to operate on.
+* @param	Mask are the interrupt signals to acknowledge
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingAckIrq(RingPtr, Mask)				\
+		XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\
+			(Mask) & XAXIDMA_IRQ_ALL_MASK)
+
+/************************* Function Prototypes ******************************/
+
+/*
+ * Descriptor ring functions xaxidma_bdring.c
+ */
+int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
+int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr);
+u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr,
+		UINTPTR VirtAddr, u32 Alignment, int BdCount);
+int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr);
+int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd ** BdSetPtr);
+int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit,
+		XAxiDma_Bd ** BdSetPtr);
+int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr);
+int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, u32 Timer);
+void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr,
+		u32 *CounterPtr, u32 *TimerPtr);
+
+/* The following functions are for debug only
+ */
+int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr);
+void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_g.c b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_g.c
new file mode 100644
index 000000000..73da03fb2
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_g.c
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_g.c
+* @addtogroup axidma_v9_0
+* @{
+*
+* Provide a template for user to define their own hardware settings.
+*
+* If using XPS, then XPS will automatically generate this file.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   08/16/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode
+* 7.02a srt  01/23/13 Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
+*		      (CR 691867)
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xaxidma.h"
+
+/************************** Constant Definitions *****************************/
+#define XPAR_AXIDMA_0_INCLUDE_SG	0
+
+XAxiDma_Config XAxiDma_ConfigTable[] =
+{
+#if defined(XPAR_XAXIDMA_NUM_INSTANCES) && (XPAR_XAXIDMA_NUM_INSTANCES > 0)
+	{
+		XPAR_AXIDMA_0_DEVICE_ID,
+		XPAR_AXIDMA_0_BASEADDR,
+		XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM,
+		XPAR_AXIDMA_0_INCLUDE_MM2S,
+		XPAR_AXIDMA_0_INCLUDE_MM2S_DRE,
+		XPAR_AXIDMA_0_M_AXI_MM2S_DATA_WIDTH,
+		XPAR_AXIDMA_0_INCLUDE_S2MM,
+		XPAR_AXIDMA_0_INCLUDE_S2MM_DRE,
+		XPAR_AXIDMA_0_M_AXI_S2MM_DATA_WIDTH,
+		XPAR_AXIDMA_0_INCLUDE_SG,
+		XPAR_AXIDMA_0_NUM_MM2S_CHANNELS,
+		XPAR_AXIDMA_0_NUM_S2MM_CHANNELS
+	}
+#endif
+};
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_hw.h b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_hw.h
new file mode 100644
index 000000000..cc467a83b
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_hw.h
@@ -0,0 +1,344 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *  @file xaxidma_hw.h
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Hardware definition file. It defines the register interface and Buffer
+ * Descriptor (BD) definitions.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 4.00a rkv  02/22/11 Added support for simple DMA mode
+ * 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode and Cyclic mode of
+ *		       operations.
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+
+#ifndef XAXIDMA_HW_H_    /* prevent circular inclusions */
+#define XAXIDMA_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name DMA Transfer Direction
+ *  @{
+ */
+#define XAXIDMA_DMA_TO_DEVICE		0x00
+#define XAXIDMA_DEVICE_TO_DMA		0x01
+
+
+/** @name Buffer Descriptor Alignment
+ *  @{
+ */
+#define XAXIDMA_BD_MINIMUM_ALIGNMENT	0x40	/**< Minimum byte alignment
+						requirement for descriptors to
+						satisfy both hardware/software
+						needs */
+/*@}*/
+
+/** @name Micro DMA Buffer Address Alignment
+ *  @{
+ */
+#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN	0xFFF	/**< Minimum byte alignment
+						requirement for buffer address
+						in Micro DMA mode */
+/*@}*/
+
+/** @name Maximum transfer length
+ *	This is determined by hardware
+ * @{
+ */
+#define XAXIDMA_MAX_TRANSFER_LEN	0x7FFFFF  /* Max length hw supports */
+#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN	0x00FFFF  /* Max length MCDMA
+						     hw supports */
+/*@}*/
+
+/* Register offset definitions. Register accesses are 32-bit.
+ */
+/** @name Device registers
+ *  Register sets on TX and RX channels are identical
+ *  @{
+ */
+#define XAXIDMA_TX_OFFSET	0x00000000 /**< TX channel registers base
+					     *  offset */
+#define XAXIDMA_RX_OFFSET	0x00000030 /**< RX channel registers base
+					     * offset */
+
+/* This set of registers are applicable for both channels. Add
+ * XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX
+ * channel
+ */
+#define XAXIDMA_CR_OFFSET	 0x00000000   /**< Channel control */
+#define XAXIDMA_SR_OFFSET	 0x00000004   /**< Status */
+#define XAXIDMA_CDESC_OFFSET	 0x00000008   /**< Current descriptor pointer */
+#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C   /**< Current descriptor pointer */
+#define XAXIDMA_TDESC_OFFSET	 0x00000010   /**< Tail descriptor pointer */
+#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014   /**< Tail descriptor pointer */
+#define XAXIDMA_SRCADDR_OFFSET	 0x00000018   /**< Simple mode source address
+						pointer */
+#define XAXIDMA_SRCADDR_MSB_OFFSET	0x0000001C  /**< Simple mode source address
+						pointer */
+#define XAXIDMA_DESTADDR_OFFSET		0x00000018   /**< Simple mode destination address pointer */
+#define XAXIDMA_DESTADDR_MSB_OFFSET	0x0000001C   /**< Simple mode destination address pointer */
+#define XAXIDMA_BUFFLEN_OFFSET		0x00000028   /**< Tail descriptor pointer */
+#define XAXIDMA_SGCTL_OFFSET		0x0000002c   /**< SG Control Register */
+
+/** Multi-Channel DMA Descriptor Offsets **/
+#define XAXIDMA_RX_CDESC0_OFFSET	0x00000040   /**< Rx Current Descriptor 0 */
+#define XAXIDMA_RX_CDESC0_MSB_OFFSET	0x00000044   /**< Rx Current Descriptor 0 */
+#define XAXIDMA_RX_TDESC0_OFFSET	0x00000048   /**< Rx Tail Descriptor 0 */
+#define XAXIDMA_RX_TDESC0_MSB_OFFSET	0x0000004C   /**< Rx Tail Descriptor 0 */
+#define XAXIDMA_RX_NDESC_OFFSET		0x00000020   /**< Rx Next Descriptor Offset */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_CR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /**< Start/stop DMA channel */
+#define XAXIDMA_CR_RESET_MASK	0x00000004 /**< Reset DMA engine */
+#define XAXIDMA_CR_KEYHOLE_MASK	0x00000008 /**< Keyhole feature */
+#define XAXIDMA_CR_CYCLIC_MASK	0x00000010 /**< Cyclic Mode */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_SR_OFFSET register
+ *
+ * This register reports status of a DMA channel, including
+ * run/stop/idle state, errors, and interrupts (note that interrupt
+ * masks are shared with XAXIDMA_CR_OFFSET register, and are defined
+ * in the _IRQ_ section.
+ *
+ * The interrupt coalescing threshold value and delay counter value are
+ * also shared with XAXIDMA_CR_OFFSET register, and are defined in a
+ * later section.
+ * @{
+ */
+#define XAXIDMA_HALTED_MASK		0x00000001  /**< DMA channel halted */
+#define XAXIDMA_IDLE_MASK		0x00000002  /**< DMA channel idle */
+#define XAXIDMA_ERR_INTERNAL_MASK	0x00000010  /**< Datamover internal
+						      *  err */
+#define XAXIDMA_ERR_SLAVE_MASK		0x00000020  /**< Datamover slave err */
+#define XAXIDMA_ERR_DECODE_MASK		0x00000040  /**< Datamover decode
+						      *  err */
+#define XAXIDMA_ERR_SG_INT_MASK		0x00000100  /**< SG internal err */
+#define XAXIDMA_ERR_SG_SLV_MASK		0x00000200  /**< SG slave err */
+#define XAXIDMA_ERR_SG_DEC_MASK		0x00000400  /**< SG decode err */
+#define XAXIDMA_ERR_ALL_MASK		0x00000770  /**< All errors */
+
+/** @name Bitmask for interrupts
+ * These masks are shared by XAXIDMA_CR_OFFSET register and
+ * XAXIDMA_SR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_IRQ_IOC_MASK		0x00001000 /**< Completion intr */
+#define XAXIDMA_IRQ_DELAY_MASK		0x00002000 /**< Delay interrupt */
+#define XAXIDMA_IRQ_ERROR_MASK		0x00004000 /**< Error interrupt */
+#define XAXIDMA_IRQ_ALL_MASK		0x00007000 /**< All interrupts */
+/*@}*/
+
+/** @name Bitmask and shift for delay and coalesce
+ * These masks are shared by XAXIDMA_CR_OFFSET register and
+ * XAXIDMA_SR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_DELAY_MASK		0xFF000000 /**< Delay timeout
+						     *  counter */
+#define XAXIDMA_COALESCE_MASK		0x00FF0000 /**< Coalesce counter */
+
+#define XAXIDMA_DELAY_SHIFT		24
+#define XAXIDMA_COALESCE_SHIFT		16
+/*@}*/
+
+
+/* Buffer Descriptor (BD) definitions
+ */
+
+/** @name Buffer Descriptor offsets
+ *  USR* fields are defined by higher level IP.
+ *  setup for EMAC type devices. The first 13 words are used by hardware.
+ *  All words after the 13rd word are for software use only.
+ *  @{
+ */
+#define XAXIDMA_BD_NDESC_OFFSET		0x00  /**< Next descriptor pointer */
+#define XAXIDMA_BD_NDESC_MSB_OFFSET	0x04  /**< Next descriptor pointer */
+#define XAXIDMA_BD_BUFA_OFFSET		0x08  /**< Buffer address */
+#define XAXIDMA_BD_BUFA_MSB_OFFSET	0x0C  /**< Buffer address */
+#define XAXIDMA_BD_MCCTL_OFFSET		0x10  /**< Multichannel Control Fields */
+#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET	0x14  /**< 2D Transfer Sizes */
+#define XAXIDMA_BD_CTRL_LEN_OFFSET	0x18  /**< Control/buffer length */
+#define XAXIDMA_BD_STS_OFFSET		0x1C  /**< Status */
+
+#define XAXIDMA_BD_USR0_OFFSET		0x20  /**< User IP specific word0 */
+#define XAXIDMA_BD_USR1_OFFSET		0x24  /**< User IP specific word1 */
+#define XAXIDMA_BD_USR2_OFFSET		0x28  /**< User IP specific word2 */
+#define XAXIDMA_BD_USR3_OFFSET		0x2C  /**< User IP specific word3 */
+#define XAXIDMA_BD_USR4_OFFSET		0x30  /**< User IP specific word4 */
+
+#define XAXIDMA_BD_ID_OFFSET		0x34  /**< Sw ID */
+#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET	0x38  /**< Whether has stscntrl strm */
+#define XAXIDMA_BD_HAS_DRE_OFFSET	0x3C  /**< Whether has DRE */
+#define XAXIDMA_BD_ADDRLEN_OFFSET	0x40  /**< Check for BD Addr */
+
+#define XAXIDMA_BD_HAS_DRE_MASK		0xF00 /**< Whether has DRE mask */
+#define XAXIDMA_BD_WORDLEN_MASK		0xFF  /**< Whether has DRE mask */
+
+#define XAXIDMA_BD_HAS_DRE_SHIFT	8     /**< Whether has DRE shift */
+#define XAXIDMA_BD_WORDLEN_SHIFT	0     /**< Whether has DRE shift */
+
+#define XAXIDMA_BD_START_CLEAR		8   /**< Offset to start clear */
+#define XAXIDMA_BD_BYTES_TO_CLEAR	48  /**< BD specific bytes to be
+					      *  cleared */
+
+#define XAXIDMA_BD_NUM_WORDS		20U  /**< Total number of words for
+					       * one BD*/
+#define XAXIDMA_BD_HW_NUM_BYTES		52  /**< Number of bytes hw used */
+
+/* The offset of the last app word.
+ */
+#define XAXIDMA_LAST_APPWORD		4
+
+/*@}*/
+#define XAXIDMA_DESC_LSB_MASK	(0xFFFFFFC0U)	/**< LSB Address mask */
+
+/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /**< First tx packet */
+#define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /**< Last tx packet */
+#define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /**< All control bits */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_STS_COMPLETE_MASK	0x80000000 /**< Completed */
+#define XAXIDMA_BD_STS_DEC_ERR_MASK	0x40000000 /**< Decode error */
+#define XAXIDMA_BD_STS_SLV_ERR_MASK	0x20000000 /**< Slave error */
+#define XAXIDMA_BD_STS_INT_ERR_MASK	0x10000000 /**< Internal err */
+#define XAXIDMA_BD_STS_ALL_ERR_MASK	0x70000000 /**< All errors */
+#define XAXIDMA_BD_STS_RXSOF_MASK	0x08000000 /**< First rx pkt */
+#define XAXIDMA_BD_STS_RXEOF_MASK	0x04000000 /**< Last rx pkt */
+#define XAXIDMA_BD_STS_ALL_MASK		0xFC000000 /**< All status bits */
+/*@}*/
+
+/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_TDEST_FIELD_MASK	0x0000000F
+#define XAXIDMA_BD_TID_FIELD_MASK	0x00000F00
+#define XAXIDMA_BD_TUSER_FIELD_MASK	0x000F0000
+#define XAXIDMA_BD_ARCACHE_FIELD_MASK	0x0F000000
+#define XAXIDMA_BD_ARUSER_FIELD_MASK	0xF0000000
+
+#define XAXIDMA_BD_TDEST_FIELD_SHIFT	0
+#define XAXIDMA_BD_TID_FIELD_SHIFT    	8
+#define XAXIDMA_BD_TUSER_FIELD_SHIFT	16
+#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT	24
+#define XAXIDMA_BD_ARUSER_FIELD_SHIFT	28
+
+/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_STRIDE_FIELD_MASK	0x0000FFFF
+#define XAXIDMA_BD_VSIZE_FIELD_MASK	0xFFF80000
+
+#define XAXIDMA_BD_STRIDE_FIELD_SHIFT	0
+#define XAXIDMA_BD_VSIZE_FIELD_SHIFT   	19
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XAxiDma_In32	Xil_In32
+#define XAxiDma_Out32	Xil_Out32
+
+/*****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XAxiDma_ReadReg(BaseAddress, RegOffset)             \
+    XAxiDma_In32((BaseAddress) + (RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)          \
+    XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_porting_guide.h b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_porting_guide.h
new file mode 100644
index 000000000..ff10ddc7c
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_porting_guide.h
@@ -0,0 +1,254 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_porting_guide.h
+* @addtogroup axidma_v9_0
+* @{
+*
+* This is a guide on how to move from using the xlldma driver to use xaxidma
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+* 6.00a srt  03/27/12 Added support for MCDMA mode
+* 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+*
+* </pre>
+*
+* <b>Overview</b>
+*
+* The API for xaxidma driver is similar to xlldma driver. The prefix for the
+* API functions and structures is XAxiDma_ for the xaxidma driver.
+*
+* Due to hardware feature changes, signatures of some API functions are a
+* little bit different from the xlldma API functions.
+*
+* We present API functions:
+* - That only have prefix changes
+* - That have different return type
+* - That are new API functions
+* - That have been removed
+*
+* Note that data structures have different prefix of XAxiDma_. Those API
+* functions, that have data structures with prefix change, are considered as
+* prefix change.
+*
+* <b>API Functions That Only Have Prefix Changes</b>
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver (upto v5_00_a)
+* -----------------------------------------------------------------------
+*    XLlDma_Reset(...)               |  XAxiDma_Reset(...)
+*    XLlDma_BdRingSnapShotCurrBd(...)|  XAxiDma_BdRingSnapShotCurrBd(...)
+*    XLlDma_BdRingNext(...)          |  XAxiDma_BdRingNext(...)
+*    XLlDma_BdRingPrev(...)          |  XAxiDma_BdRingPrev(...)
+*    XLlDma_BdRingGetSr(...)         |  XAxiDma_BdRingGetSr(...)
+*    XLlDma_BdRingBusy(...)          |  XAxiDma_BdRingBusy(...)
+*    XLlDma_BdRingIntEnable(...)     |  XAxiDma_BdRingIntEnable(...)
+*    XLlDma_BdRingIntDisable(...)    |  XAxiDma_BdRingIntDisable(...)
+*    XLlDma_BdRingIntGetEnabled(...) |  XAxiDma_BdRingIntGetEnabled(...)
+*    XLlDma_BdRingGetIrq(...)        |  XAxiDma_BdRingGetIrq(...)
+*    XLlDma_BdRingAckIrq(...)        |  XAxiDma_BdRingAckIrq(...)
+*    XLlDma_BdRingCreate(...)        |  XAxiDma_BdRingCreate(...)
+*    XLlDma_BdRingClone(...)         |  XAxiDma_BdRingClone(...)
+*    XLlDma_BdRingAlloc(...)         |  XAxiDma_BdRingAlloc(...)
+*    XLlDma_BdRingUnAlloc(...)       |  XAxiDma_BdRingUnAlloc(...)
+*    XLlDma_BdRingToHw(...)          |  XAxiDma_BdRingToHw(...)
+*    XLlDma_BdRingFromHw(...)        |  XAxiDma_BdRingFromHw(...)
+*    XLlDma_BdRingFree(...)          |  XAxiDma_BdRingFree(...)
+*    XLlDma_BdRingStart(...)         |  XAxiDma_BdRingStart(...)
+*    XLlDma_BdRingCheck(...)         |  XAxiDma_BdRingCheck(...)
+*    XLlDma_BdRingSetCoalesce(...)   |  XAxiDma_BdRingSetCoalesce(...)
+*    XLlDma_BdRingGetCoalesce(...)   |  XAxiDma_BdRingGetCoalesce(...)
+*    XLlDma_BdRead(...)              |  XAxiDma_BdRead(...)
+*    XLlDma_BdWrite(...)             |  XAxiDma_BdWrite(...)
+*    XLlDma_BdClear(...)             |  XAxiDma_BdClear(...)
+*    XLlDma_BdSetId(...)             |  XAxiDma_BdSetId(...)
+*    XLlDma_BdGetId(...)             |  XAxiDma_BdGetId(...)
+*    XLlDma_BdGetLength(...)         |  XAxiDma_BdGetLength(...)
+*    XLlDma_BdGetBufAddr(...)        |  XAxiDma_BdGetBufAddr(...)
+*
+*</pre>
+*
+* <b>API Functions That Have Different Return Type</b>
+*
+* Due to possible hardware failures, The caller should check the return value
+* of the following functions.
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver
+* -----------------------------------------------------------------------
+* void XLlDma_Pause(...)             | int XAxiDma_Pause(...)
+* void XLlDma_Resume(...)            | int XAxiDma_Resume(...)
+* </pre>
+*
+* The following functions have return type changed:
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver
+* -----------------------------------------------------------------------
+* XLlDma_BdRing XLlDma_GetRxRing(...)| XAxiDma_BdRing * XAxiDma_GetRxRing(...)
+* XLlDma_BdRing XLlDma_GetTxRing(...)| XAxiDma_BdRing * XAxiDma_GetTxRing(...)
+* u32 XLlDma_BdRingMemCalc(...)      | int XAxiDma_BdRingMemCalc(...)
+* u32 XLlDma_BdRingCntCalc(...)      | int XAxiDma_BdRingCntCalc(...)
+* u32 XLlDma_BdRingGetCnt(...)       | int XAxiDma_BdRingGetCnt(...)
+* u32 XLlDma_BdRingGetFreeCnt(...)   | int XAxiDma_BdRingGetFreeCnt(...)
+* void XLlDma_BdSetLength(...)       | int XAxiDma_BdSetLength(...)
+* void XLlDma_BdSetBufAddr(...)      | int XAxiDma_BdSetBufAddr(...)
+*</pre>
+*
+* <b>API Functions That Are New API Functions</b>
+*
+* Now that the AXI DMA core is a standalone core, some new API are intrduced.
+* Some other functions are added due to hardware interface change, so to
+* replace old API functions.
+*
+* - XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
+* - int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
+* - int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
+* - XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr);
+* - int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr);
+* - void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
+* - int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
+* - void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+* - u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr);
+* - u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
+* - u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
+*
+* <b>API Functions That Have Been Removed</b>
+*
+* Please see individual function comments for how to replace the removed API
+* function with new API functions.
+*
+* - void XLlDma_Initialize(XLlDma * InstancePtr, u32 BaseAddress).
+*   This function is replaced by XAxiDma_LookupConfig()/XAxiDma_CfgInitialize()
+*
+* - u32 XLlDma_BdRingGetCr(XLlDma_BdRing* RingPtr).
+*   This is replaced by XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
+*
+* - u32 XLlDma_BdRingSetCr(XLlDma_BdRing* RingPtr, u32 Data).
+*   This function is covered by other API functions:
+*      - void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*      - void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*      - int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter,
+*            u32 Timer)
+*
+* - u32 XLlDma_BdSetStsCtrl(XLlDma_Bd* BdPtr, u32 Data).
+*   Replaced by XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+*
+* - u32 XLlDma_BdGetStsCtrl(XLlDma_Bd* BdPtr).
+*   Replaced by XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) and
+*   XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr).
+*
+* <b>API Functions That Have Been Added to support simple DMA mode</b>
+*
+* - u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
+* - int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, int Length,
+*	int Direction);
+* - XAxiDma_HasSg(InstancePtr);
+* - XAxiDma_IntrEnable(InstancePtr,Mask,Direction);
+* - XAxiDma_IntrGetEnabled(InstancePtr, Direction);
+* - XAxiDma_IntrDisable(InstancePtr, Mask, Direction);
+* - XAxiDma_IntrGetIrq(InstancePtr, Direction);
+* - XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction);
+*
+* <b> For xaxidma driver v6_00_a Multiple Channel Support
+*     ---------------------------------------------------
+* This driver supports Multi-channel mode and accordingly some APIs are
+* changed to index multiple channels. Few new APIs are added.
+*  - Changed APIs
+*	* XAxiDma_GetRxRing(InstancePtr, RingIndex)
+* 	* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*			u32 BuffAddr, u32 Length,
+*			int Direction, int RingIndex)
+*	* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*			int RingIndex)
+*	* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*      			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*	* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+*			u32 LenBytes, u32 LengthMask)
+*       * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+*	* XAxiDma_BdGetLength(BdPtr, LengthMask)
+*
+*  - New APIs
+*	* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*			int Direction, int Select)
+*	* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*			int RingIndex)
+*	* XAxiDma_BdSetTId()
+*	* XAxiDma_BdGetTId()
+*	* XAxiDma_BdSetTDest()
+*	* XAxiDma_BdGetTDest()
+*	* XAxiDma_BdSetTUser()
+*	* XAxiDma_BdGetTUser()
+*	* XAxiDma_BdSetARCache()
+*	* XAxiDma_BdGetARCache()
+*	* XAxiDma_BdSetARUser()
+*	* XAxiDma_BdGetARUser()
+*	* XAxiDma_BdSetStride()
+*	* XAxiDma_BdGetStride()
+*	* XAxiDma_BdSetVSize()
+*	* XAxiDma_BdGetVSize()
+* <b> For xaxidma driver v7_00_a
+*     ---------------------------------------------------
+*  - New API
+*	* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
+*
+*  - Changed APIs
+*	All the APIs changed in v6_00_a are reverted back for backward
+*	compatibility.
+*</pre>
+*
+******************************************************************************/
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_selftest.c b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_selftest.c
new file mode 100644
index 000000000..e80a66297
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_selftest.c
+* @addtogroup axidma_v9_0
+* @{
+*
+* Contains diagnostic/self-test functions for the XAxiDma component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 8.1 	adk  29/01/15 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+#include "xaxidma.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+#define XAXIDMA_RESET_TIMEOUT   500
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. This test perform a
+* reset of the DMA device and checks the device is coming out of reset or not
+*
+* @param	InstancePtr is a pointer to the XAxiDma instance.
+*
+* @return
+* 		- XST_SUCCESS if self-test was successful
+*		- XST_FAILURE if the device is not coming out of reset.
+*
+* @note
+*     None.
+*
+******************************************************************************/
+int XAxiDma_Selftest(XAxiDma * InstancePtr)
+{
+	int TimeOut;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	XAxiDma_Reset(InstancePtr);
+
+	/* At the initialization time, hardware should finish reset quickly
+	 */
+	TimeOut = XAXIDMA_RESET_TIMEOUT;
+
+	while (TimeOut) {
+
+		if(XAxiDma_ResetIsDone(InstancePtr)) {
+			break;
+		}
+
+		TimeOut -= 1;
+
+	}
+
+	if (!TimeOut)
+		return XST_FAILURE;
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_sinit.c b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_sinit.c
new file mode 100644
index 000000000..c0fe7e3e2
--- /dev/null
+++ b/thirdparty/xilinx/orig/axidma_v9_0/src/xaxidma_sinit.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_sinit.c
+* @addtogroup axidma_v9_0
+* @{
+*
+* Look up the hardware settings using device ID. The hardware setting is inside
+* the configuration table in xaxidma_g.c, generated automatically by XPS or
+* manually by the user.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   08/16/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 5.00a srt  08/29/11 Removed a compiler warning
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xaxidma.h"
+
+
+/*****************************************************************************/
+/**
+ * Look up the hardware configuration for a device instance
+ *
+ * @param	DeviceId is the unique device ID of the device to lookup for
+ *
+ * @return
+ *		The configuration structure for the device. If the device ID is
+ *		not found,a NULL pointer is returned.
+ *
+ * @note	None
+ *
+ ******************************************************************************/
+XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId)
+{
+	extern XAxiDma_Config XAxiDma_ConfigTable[];
+	XAxiDma_Config *CfgPtr;
+	u32 Index;
+
+	CfgPtr = NULL;
+
+	for (Index = 0; Index < XPAR_XAXIDMA_NUM_INSTANCES; Index++) {
+		if (XAxiDma_ConfigTable[Index].DeviceId == DeviceId) {
+
+			CfgPtr = &XAxiDma_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/data/axis_switch.mdd b/thirdparty/xilinx/orig/axis_switch_v1_0/data/axis_switch.mdd
new file mode 100644
index 000000000..d5ff27dc8
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/data/axis_switch.mdd
@@ -0,0 +1,40 @@
+##############################################################################
+#
+# Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"),to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+###############################################################################
+
+OPTION psf_version = 2.1;
+
+BEGIN driver axis_switch
+    OPTION supported_peripherals = (axis_switch);
+    OPTION driver_state = ACTIVE;
+    OPTION copyfiles = all;
+    OPTION VERSION = 1.0;
+    OPTION NAME = axis_switch;
+END driver
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/data/axis_switch.tcl b/thirdparty/xilinx/orig/axis_switch_v1_0/data/axis_switch.tcl
new file mode 100644
index 000000000..73ea5ae07
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/data/axis_switch.tcl
@@ -0,0 +1,36 @@
+##############################################################################
+#
+# Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"),to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+###############################################################################
+
+proc generate {drv_handle} {
+    ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxis_Switch" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "NUM_SI" "NUM_MI"
+    ::hsi::utils::define_config_file $drv_handle "xaxis_switch_g.c" "XAxis_Switch" "DEVICE_ID" "C_BASEADDR" "NUM_SI" "NUM_MI"
+    ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "Axis_Switch" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "NUM_SI" "NUM_MI"
+}
\ No newline at end of file
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/HTML_custom.css b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/HTML_custom.css
new file mode 100644
index 000000000..26defe1a8
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/HTML_custom.css
@@ -0,0 +1,1430 @@
+/* The standard CSS for doxygen 1.8.5 */
+
+body{
+	background: none repeat scroll 0 0 #FFFFFF;
+	color: #51626F;
+	font-family: arial,sans-serif !important;
+    	font-size: 75% !important;
+    	font-weight: normal !important;
+    	margin-left: 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+.contents, .textblock {
+font: 400 12px/15px arial,sans-serif;
+}
+.textblock ul, .contents ul{ 
+	margin: 5px 0;
+	padding: 0;
+}
+.textblockol {
+	margin:5px 15px; 
+	padding:0;
+	list-style-image: none; 
+}
+.textblock li, .contents li {
+	margin: 0 0 2px 15px;
+    	padding: 0 0 2px 2px;
+}
+
+/* For hiding RHS TOC 
+.toc{
+display:none;
+}*/
+/* For hiding RHS TOC*/ 
+
+For hiding Nav Bar
+.navpath, #nav-path{
+display:none;
+}
+/* For hiding Nav Bar*/
+/* For hiding extra navrows */
+#navrow2, #navrow3, #navrow4, #navrow5 {
+display:none;
+}
+/* @group Heading Levels */
+
+.title {
+	font: 400 14px/28px arial,sans-serif;
+	font-size: 150%;
+	font-weight: bold;
+	margin: 9px 2px;
+	text-align: left;
+}
+
+h2, h3 {
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+    text-indent: 0 !important;
+}
+h4, h5{
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+}
+h5{
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+h6{
+    color: #E66A08 !important;
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+p {
+    padding-bottom: 0px !important;
+	font: 400 12px/15px arial,sans-serif;
+}
+li p {
+    padding-bottom: 0px !important;
+	margin: 0px;
+}
+
+h1, h2.groupheader {
+    clear: both !important;
+    color: #627178 !important;
+    font-size: 1.4em !important;
+    font-weight: bold !important;
+    line-height: 28px !important;
+    margin-top: 0.6em !important;
+}
+
+h1, h2, h3, h4, h5, h6 {
+	-webkit-transition: text-shadow 0.5s linear;
+	-moz-transition: text-shadow 0.5s linear;
+	-ms-transition: text-shadow 0.5s linear;
+	-o-transition: text-shadow 0.5s linear;
+	transition: text-shadow 0.5s linear;
+	margin-right: 15px;
+}
+
+h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {
+	text-shadow: 0 0 15px cyan;
+}
+
+dt {
+	font-weight: bold;
+}
+
+
+/*Hiding Tabs - Tushar
+div.tabs 
+{ 
+    visibility: hidden; 
+} */
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #017bba;
+	font-weight: normal;
+	text-decoration: none;
+	/*font: 400 12px/15px;*/
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code, a.code:visited, a.line, a.line:visited {
+	color: #4665A2;
+}
+
+a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {
+	color: #4665A2; 
+	/*font: 400 12px/15px;*/
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+pre.fragment {
+        border: 0px solid #C4CFE5;
+        background-color: #FFFFFF;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        font-size:  9pt;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 105%;
+}
+
+div.fragment {
+        padding: 0px;
+        margin: 0px;
+	background-color: #FFFFFF;
+	border: 0px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 13px;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+div.line.glow {
+	background-color: cyan;
+	box-shadow: 0 0 10px cyan;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #51626F
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: cyan;
+	box-shadow: 0 0 15px cyan;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
+        border-bottom: 1px solid #DEE4F0;
+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+	font-size: 80%;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+        -webkit-transition: box-shadow 0.5s linear;
+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
+        display: table !important;
+        width: 100%;
+}
+
+.memitem.glow {
+         box-shadow: 0 0 15px cyan;
+}
+
+.memname {
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memname td {
+	vertical-align: bottom;
+}
+
+.memproto, dl.reflist dt {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #E66A08 !important;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+.memdoc, dl.reflist dd {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 6px 10px 2px 10px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        background-image:url('nav_g.png');
+        background-repeat:repeat-x;
+        background-color: #FFFFFF;
+        /* opera specific markup */
+        border-bottom-left-radius: 4px;
+        border-bottom-right-radius: 4px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 4px;
+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 4px;
+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
+        margin: 0px 0px 10px 0px;
+        padding: 5px;
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+.paramname code {
+        line-height: 14px;
+}
+
+.params, .retval, .exception, .tparams {
+        margin-left: 0px;
+        padding-left: 0px;
+		font: 400 12px/15px arial,sans-serif;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+table.mlabels {
+	border-spacing: 0px;
+}
+
+td.mlabels-left {
+	width: 100%;
+	padding: 0px;
+}
+
+td.mlabels-right {
+	vertical-align: bottom;
+	padding: 0px;
+	white-space: nowrap;
+}
+
+span.mlabels {
+        margin-left: 8px;
+}
+
+span.mlabel {
+        background-color: #728DC1;
+        border-top:1px solid #5373B4;
+        border-left:1px solid #5373B4;
+        border-right:1px solid #C4CFE5;
+        border-bottom:1px solid #C4CFE5;
+	text-shadow: none;
+	color: white;
+	margin-right: 4px;
+	padding: 2px 3px;
+	border-radius: 3px;
+	font-size: 7pt;
+	white-space: nowrap;
+	vertical-align: middle;
+}
+
+
+
+/* @end */
+
+/* these are for tree view when not used as main index */
+
+div.directory {
+        margin: 10px 0px;
+        border-top: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        width: 100%;
+}
+
+.directory table {
+        border-collapse:collapse;
+}
+
+.directory td {
+        margin: 0px;
+        padding: 0px;
+	vertical-align: top;
+}
+
+.directory td.entry {
+        white-space: nowrap;
+        padding-right: 6px;
+	padding-top: 3px;
+}
+
+.directory td.entry a {
+        outline:none;
+}
+
+.directory td.entry a img {
+        border: none;
+}
+
+.directory td.desc {
+        width: 100%;
+        padding-left: 6px;
+	padding-right: 6px;
+	padding-top: 3px;
+	border-left: 1px solid rgba(0,0,0,0.05);
+}
+
+.directory tr.even {
+	padding-left: 6px;
+	background-color: #F7F8FB;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+.directory .levels {
+        white-space: nowrap;
+        width: 100%;
+        text-align: right;
+        font-size: 9pt;
+}
+
+.directory .levels span {
+        cursor: pointer;
+        padding-left: 2px;
+        padding-right: 2px;
+	color: #3D578C;
+}
+
+div.dynheader {
+        margin-top: 8px;
+	-webkit-touch-callout: none;
+	-webkit-user-select: none;
+	-khtml-user-select: none;
+	-moz-user-select: none;
+	-ms-user-select: none;
+	user-select: none;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+        margin-top: 4px;
+        margin-bottom: 4px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #CCCCCC;
+	color: #51626F;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+}
+table.fieldtable {
+        /*width: 100%;*/
+        margin-bottom: 10px;
+        border: 1px solid #A8B8D9;
+        border-spacing: 0px;
+        -moz-border-radius: 4px;
+        -webkit-border-radius: 4px;
+        border-radius: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+}
+
+.fieldtable td, .fieldtable th {
+        padding: 3px 7px 2px;
+}
+
+.fieldtable td.fieldtype, .fieldtable td.fieldname {
+        white-space: nowrap;
+        border-right: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        vertical-align: top;
+}
+
+.fieldtable td.fieldname {
+        padding-top: 3px;
+}
+
+.fieldtable td.fielddoc {
+        border-bottom: 1px solid #A8B8D9;
+        /*width: 100%;*/
+}
+
+.fieldtable td.fielddoc p:first-child {
+        margin-top: 0px;
+}       
+        
+.fieldtable td.fielddoc p:last-child {
+        margin-bottom: 2px;
+}
+
+.fieldtable tr:last-child td {
+        border-bottom: none;
+}
+
+.fieldtable th {
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        font-size: 90%;
+        color: #253555;
+        padding-bottom: 4px;
+        padding-top: 5px;
+        text-align:left;
+        -moz-border-radius-topleft: 4px;
+        -moz-border-radius-topright: 4px;
+        -webkit-border-top-left-radius: 4px;
+        -webkit-border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        border-top-right-radius: 4px;
+        border-bottom: 1px solid #A8B8D9;
+}
+
+
+.tabsearch {
+	top: 5px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	background-position: 0 -5px;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+	color: #283A5D;
+	font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;
+	text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+	text-decoration: none;        
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('');
+        background-repeat:repeat-x;
+	background-color: #FFFFFF;
+	margin:  0px;
+	border-bottom: 0px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */
+dl.section
+{
+	margin-left: 0px;
+	padding-left: 0px;
+}
+
+dl.note
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #505050;
+}
+
+dl.todo
+{
+        margin-left:-7px;
+        padding-left: 12px;
+        border-left:4px solid;
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #C08050;
+}
+
+dl.section dd {
+	margin-bottom: 6px;
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+<title>axis_switch_v1_0: File List</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+ </tr>
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+</div>
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
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+  <div class="headertitle">
+<div class="title">File List</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxis__switch_8c.html" target="_self">xaxis_switch.c</a></td><td class="desc"></td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxis__switch_8h.html" target="_self">xaxis_switch.h</a></td><td class="desc"></td></tr>
+<tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxis__switch__g_8c.html" target="_self">xaxis_switch_g.c</a></td><td class="desc"></td></tr>
+<tr id="row_3_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxis__switch__hw_8h.html" target="_self">xaxis_switch_hw.h</a></td><td class="desc"></td></tr>
+<tr id="row_4_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxis__switch__selftest_8c.html" target="_self">xaxis_switch_selftest.c</a></td><td class="desc"></td></tr>
+<tr id="row_5_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxis__switch__sinit_8c.html" target="_self">xaxis_switch_sinit.c</a></td><td class="desc"></td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/functions.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/functions.html
new file mode 100644
index 000000000..eb380da41
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/functions.html
@@ -0,0 +1,81 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axis_switch_v1_0: Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+</head>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+    </ul>
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+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
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+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div><ul>
+<li>BaseAddress
+: <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config</a>
+</li>
+<li>Config
+: <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch</a>
+</li>
+<li>DeviceId
+: <a class="el" href="struct_x_axis___switch___config.html#acde4aaf90a32e9f80bdd687dfb5f46f4">XAxis_Switch_Config</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_axis___switch.html#aa6fb801f6e169f44fb21f53317b36f1f">XAxis_Switch</a>
+</li>
+<li>MaxNumMI
+: <a class="el" href="struct_x_axis___switch___config.html#a053a1f2027b8c3c2f81f6eaee1e5f824">XAxis_Switch_Config</a>
+</li>
+<li>MaxNumSI
+: <a class="el" href="struct_x_axis___switch___config.html#a20390bb97a7d14720520293d27f97404">XAxis_Switch_Config</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/functions_vars.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/functions_vars.html
new file mode 100644
index 000000000..c8e109b8b
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/functions_vars.html
@@ -0,0 +1,81 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axis_switch_v1_0: Data Fields - Variables</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>BaseAddress
+: <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config</a>
+</li>
+<li>Config
+: <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch</a>
+</li>
+<li>DeviceId
+: <a class="el" href="struct_x_axis___switch___config.html#acde4aaf90a32e9f80bdd687dfb5f46f4">XAxis_Switch_Config</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_axis___switch.html#aa6fb801f6e169f44fb21f53317b36f1f">XAxis_Switch</a>
+</li>
+<li>MaxNumMI
+: <a class="el" href="struct_x_axis___switch___config.html#a053a1f2027b8c3c2f81f6eaee1e5f824">XAxis_Switch_Config</a>
+</li>
+<li>MaxNumSI
+: <a class="el" href="struct_x_axis___switch___config.html#a20390bb97a7d14720520293d27f97404">XAxis_Switch_Config</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals.html
new file mode 100644
index 000000000..f0cba2c33
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals.html
@@ -0,0 +1,127 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axis_switch_v1_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div><ul>
+<li>XAXIS_SCR_CTRL_OFFSET
+: <a class="el" href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_CTRL_REG_UPDATE_MASK
+: <a class="el" href="group__axis__switch__v1__0.html#ga61bbd9728daef6347dc32ae4234f19de">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_MUX_END_OFFSET
+: <a class="el" href="group__axis__switch__v1__0.html#ga227adbe778b570746da42ea0437261a1">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_MUX_START_OFFSET
+: <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_X_DISABLE_MASK
+: <a class="el" href="group__axis__switch__v1__0.html#ga34b4d7358d3edcf4103e2aa5e18d1e1f">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_X_DISABLE_SHIFT
+: <a class="el" href="group__axis__switch__v1__0.html#ga06b31a381d36b949c68bbfaf92610bc3">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_X_MUX_MASK
+: <a class="el" href="group__axis__switch__v1__0.html#ga32f8940e49e11e5b238d5613ae4f667a">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SWITCH_H_
+: <a class="el" href="group__axis__switch__v1__0.html#ga19b5f68d74238e0c11856dbe5e566237">xaxis_switch.h</a>
+</li>
+<li>XAXIS_SWITCH_HW_H_
+: <a class="el" href="group__axis__switch__v1__0.html#ga5a9a509c0aec471d47a841f955c087c5">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_CfgInitialize()
+: <a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_In32
+: <a class="el" href="group__axis__switch__v1__0.html#ga81d5f42ceeea6429358b40a24b990421">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_IsMiPortDisabled()
+: <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_IsMiPortEnabled()
+: <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_LookupConfig()
+: <a class="el" href="group__axis__switch__v1__0.html#gaa631f268bd77eca8acc9534775649df1">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_MiPortDisable()
+: <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_MiPortDisableAll()
+: <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_MiPortEnable()
+: <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_Out32
+: <a class="el" href="group__axis__switch__v1__0.html#gaca96433d3b19296beb0a781e5428a5f6">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_ReadReg
+: <a class="el" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_RegUpdateDisable
+: <a class="el" href="group__axis__switch__v1__0.html#gafc168e986cd2b401045578c06bc90869">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_RegUpdateEnable
+: <a class="el" href="group__axis__switch__v1__0.html#gaa82658cbc43e600c53a429fce04d3a4c">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_SelfTest()
+: <a class="el" href="group__axis__switch__v1__0.html#gad9c646b6e8d7f5d6c431c2985592fb4b">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_WriteReg
+: <a class="el" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">xaxis_switch_hw.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals_defs.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals_defs.html
new file mode 100644
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+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals_defs.html
@@ -0,0 +1,103 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axis_switch_v1_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XAXIS_SCR_CTRL_OFFSET
+: <a class="el" href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_CTRL_REG_UPDATE_MASK
+: <a class="el" href="group__axis__switch__v1__0.html#ga61bbd9728daef6347dc32ae4234f19de">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_MUX_END_OFFSET
+: <a class="el" href="group__axis__switch__v1__0.html#ga227adbe778b570746da42ea0437261a1">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_MUX_START_OFFSET
+: <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_X_DISABLE_MASK
+: <a class="el" href="group__axis__switch__v1__0.html#ga34b4d7358d3edcf4103e2aa5e18d1e1f">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_X_DISABLE_SHIFT
+: <a class="el" href="group__axis__switch__v1__0.html#ga06b31a381d36b949c68bbfaf92610bc3">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SCR_MI_X_MUX_MASK
+: <a class="el" href="group__axis__switch__v1__0.html#ga32f8940e49e11e5b238d5613ae4f667a">xaxis_switch_hw.h</a>
+</li>
+<li>XAXIS_SWITCH_H_
+: <a class="el" href="group__axis__switch__v1__0.html#ga19b5f68d74238e0c11856dbe5e566237">xaxis_switch.h</a>
+</li>
+<li>XAXIS_SWITCH_HW_H_
+: <a class="el" href="group__axis__switch__v1__0.html#ga5a9a509c0aec471d47a841f955c087c5">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_In32
+: <a class="el" href="group__axis__switch__v1__0.html#ga81d5f42ceeea6429358b40a24b990421">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_Out32
+: <a class="el" href="group__axis__switch__v1__0.html#gaca96433d3b19296beb0a781e5428a5f6">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_ReadReg
+: <a class="el" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">xaxis_switch_hw.h</a>
+</li>
+<li>XAxisScr_RegUpdateDisable
+: <a class="el" href="group__axis__switch__v1__0.html#gafc168e986cd2b401045578c06bc90869">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_RegUpdateEnable
+: <a class="el" href="group__axis__switch__v1__0.html#gaa82658cbc43e600c53a429fce04d3a4c">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_WriteReg
+: <a class="el" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">xaxis_switch_hw.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals_func.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/globals_func.html
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+<script type="text/javascript" src="dynsections.js"></script>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XAxisScr_CfgInitialize()
+: <a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_IsMiPortDisabled()
+: <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_IsMiPortEnabled()
+: <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_LookupConfig()
+: <a class="el" href="group__axis__switch__v1__0.html#gaa631f268bd77eca8acc9534775649df1">xaxis_switch.h</a>
+</li>
+<li>XAxisScr_MiPortDisable()
+: <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_MiPortDisableAll()
+: <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_MiPortEnable()
+: <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">xaxis_switch.c</a>
+</li>
+<li>XAxisScr_SelfTest()
+: <a class="el" href="group__axis__switch__v1__0.html#gad9c646b6e8d7f5d6c431c2985592fb4b">xaxis_switch.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/group__axis__switch__v1__0.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/group__axis__switch__v1__0.html
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axis_switch_v1_0: Axis_switch_v1_0</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
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+</head>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#nested-classes">Data Structures</a> &#124;
+<a href="#define-members">Macros</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Axis_switch_v1_0</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axis___switch___config.html">XAxis_Switch_Config</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gaa82658cbc43e600c53a429fce04d3a4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#gaa82658cbc43e600c53a429fce04d3a4c">XAxisScr_RegUpdateEnable</a>(InstancePtr)</td></tr>
+<tr class="separator:gaa82658cbc43e600c53a429fce04d3a4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gafc168e986cd2b401045578c06bc90869"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#gafc168e986cd2b401045578c06bc90869">XAxisScr_RegUpdateDisable</a>(InstancePtr)</td></tr>
+<tr class="separator:gafc168e986cd2b401045578c06bc90869"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:gaf89ec8c5b66d39cb09316a163c97c357"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">XAxisScr_CfgInitialize</a> (<a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *InstancePtr, <a class="el" href="struct_x_axis___switch___config.html">XAxis_Switch_Config</a> *CfgPtr, u32 EffectiveAddr)</td></tr>
+<tr class="separator:gaf89ec8c5b66d39cb09316a163c97c357"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga943a402b210b5f2901b6d6e7ae323d50"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">XAxisScr_MiPortEnable</a> (<a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *InstancePtr, u8 MiIndex, u8 SiIndex)</td></tr>
+<tr class="separator:ga943a402b210b5f2901b6d6e7ae323d50"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga1fcba7107d4ecb9955aa302c1b798729"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga35ef34ba6c57b57506741b4a04f87e75"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga993cbd838dd30de44a943c7f4a046101"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga84a532ac4e377199c15802d84b43256e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaa631f268bd77eca8acc9534775649df1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gad9c646b6e8d7f5d6c431c2985592fb4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Register access macro definition</h2></td></tr>
+<tr class="memitem:ga68fcd4f0df5a838b218c7ebde0e6b152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__axis__switch__v1__0.html#ga81d5f42ceeea6429358b40a24b990421">XAxisScr_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
+<tr class="separator:ga68fcd4f0df5a838b218c7ebde0e6b152"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga993bec85cbffd929a7f8418e65f293de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__axis__switch__v1__0.html#gaca96433d3b19296beb0a781e5428a5f6">XAxisScr_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
+<tr class="separator:ga993bec85cbffd929a7f8418e65f293de"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga05c58dacf3ab036292d57faac0bc1cca"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_CTRL_OFFSET&#160;&#160;&#160;0x000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>Control Register offset. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga61bbd9728daef6347dc32ae4234f19de"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_CTRL_REG_UPDATE_MASK&#160;&#160;&#160;0x02</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>Register Update mask. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga227adbe778b570746da42ea0437261a1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_MI_MUX_END_OFFSET&#160;&#160;&#160;0x07C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>End of MI MUX Register offset. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga009bec9091359e44e8bf434e3528c2eb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_MI_MUX_START_OFFSET&#160;&#160;&#160;0x040</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>Start of MI MUX Register offset. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">XAxisScr_IsMiPortDisabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">XAxisScr_MiPortDisable()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">XAxisScr_MiPortEnable()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga34b4d7358d3edcf4103e2aa5e18d1e1f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_MI_X_DISABLE_MASK&#160;&#160;&#160;0x80000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>MI Disable mask. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">XAxisScr_MiPortDisable()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga06b31a381d36b949c68bbfaf92610bc3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_MI_X_DISABLE_SHIFT&#160;&#160;&#160;31</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>MI Disable shift. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">XAxisScr_IsMiPortDisabled()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga32f8940e49e11e5b238d5613ae4f667a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SCR_MI_X_MUX_MASK&#160;&#160;&#160;0x0F</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>MI MUX mask. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga19b5f68d74238e0c11856dbe5e566237"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SWITCH_H_</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8h.html">xaxis_switch.h</a>&gt;</code></p>
+
+<p>Prevent circular inclusions by using protection macros. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5a9a509c0aec471d47a841f955c087c5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAXIS_SWITCH_HW_H_</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>Prevent circular inclusions by using protection macros. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga81d5f42ceeea6429358b40a24b990421"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxisScr_In32&#160;&#160;&#160;Xil_In32</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>Input Operations. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaca96433d3b19296beb0a781e5428a5f6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxisScr_Out32&#160;&#160;&#160;Xil_Out32</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>Output Operations. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga68fcd4f0df5a838b218c7ebde0e6b152"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxisScr_ReadReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__axis__switch__v1__0.html#ga81d5f42ceeea6429358b40a24b990421">XAxisScr_In32</a>((BaseAddress) + ((u32)RegOffset))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>This macro reads a value from a AXI4-Stream Switch register. </p>
+<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152" title="This macro reads a value from a AXI4-Stream Switch register. ">XAxisScr_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">XAxisScr_IsMiPortDisabled()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gafc168e986cd2b401045578c06bc90869"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxisScr_RegUpdateDisable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8h.html">xaxis_switch.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
+<div class="line">                <a class="code" href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">XAXIS_SCR_CTRL_OFFSET</a>, \</div>
+<div class="line">                <a class="code" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
+<div class="line">                        <a class="code" href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">XAXIS_SCR_CTRL_OFFSET</a>) &amp; \</div>
+<div class="line">                                (~<a class="code" href="group__axis__switch__v1__0.html#ga61bbd9728daef6347dc32ae4234f19de">XAXIS_SCR_CTRL_REG_UPDATE_MASK</a>))</div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga68fcd4f0df5a838b218c7ebde0e6b152"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a></div><div class="ttdeci">#define XAxisScr_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a AXI4-Stream Switch register. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:133</div></div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga05c58dacf3ab036292d57faac0bc1cca"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">XAXIS_SCR_CTRL_OFFSET</a></div><div class="ttdeci">#define XAXIS_SCR_CTRL_OFFSET</div><div class="ttdoc">Control Register offset. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:75</div></div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga993bec85cbffd929a7f8418e65f293de"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a></div><div class="ttdeci">#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a AXI4-Stream Switch register. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:156</div></div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga61bbd9728daef6347dc32ae4234f19de"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga61bbd9728daef6347dc32ae4234f19de">XAXIS_SCR_CTRL_REG_UPDATE_MASK</a></div><div class="ttdeci">#define XAXIS_SCR_CTRL_REG_UPDATE_MASK</div><div class="ttdoc">Register Update mask. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:88</div></div>
+</div><!-- fragment -->
+<p>This macro disables register updates. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axis__switch__v1__0.html#gafc168e986cd2b401045578c06bc90869" title="This macro disables register updates. ">XAxisScr_RegUpdateDisable(XAxis_Switch *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa82658cbc43e600c53a429fce04d3a4c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxisScr_RegUpdateEnable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8h.html">xaxis_switch.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
+<div class="line">                <a class="code" href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">XAXIS_SCR_CTRL_OFFSET</a>, \</div>
+<div class="line">                <a class="code" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
+<div class="line">                        <a class="code" href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">XAXIS_SCR_CTRL_OFFSET</a>) | \</div>
+<div class="line">                                <a class="code" href="group__axis__switch__v1__0.html#ga61bbd9728daef6347dc32ae4234f19de">XAXIS_SCR_CTRL_REG_UPDATE_MASK</a>)</div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga68fcd4f0df5a838b218c7ebde0e6b152"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a></div><div class="ttdeci">#define XAxisScr_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a AXI4-Stream Switch register. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:133</div></div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga05c58dacf3ab036292d57faac0bc1cca"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga05c58dacf3ab036292d57faac0bc1cca">XAXIS_SCR_CTRL_OFFSET</a></div><div class="ttdeci">#define XAXIS_SCR_CTRL_OFFSET</div><div class="ttdoc">Control Register offset. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:75</div></div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga993bec85cbffd929a7f8418e65f293de"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a></div><div class="ttdeci">#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a AXI4-Stream Switch register. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:156</div></div>
+<div class="ttc" id="group__axis__switch__v1__0_html_ga61bbd9728daef6347dc32ae4234f19de"><div class="ttname"><a href="group__axis__switch__v1__0.html#ga61bbd9728daef6347dc32ae4234f19de">XAXIS_SCR_CTRL_REG_UPDATE_MASK</a></div><div class="ttdeci">#define XAXIS_SCR_CTRL_REG_UPDATE_MASK</div><div class="ttdoc">Register Update mask. </div><div class="ttdef"><b>Definition:</b> xaxis_switch_hw.h:88</div></div>
+</div><!-- fragment -->
+<p>This macro enables register updates. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axis__switch__v1__0.html#gaa82658cbc43e600c53a429fce04d3a4c" title="This macro enables register updates. ">XAxisScr_RegUpdateEnable(XAxis_Switch *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga993bec85cbffd929a7f8418e65f293de"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XAxisScr_WriteReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Data&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__axis__switch__v1__0.html#gaca96433d3b19296beb0a781e5428a5f6">XAxisScr_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch__hw_8h.html">xaxis_switch_hw.h</a>&gt;</code></p>
+
+<p>This macro writes a value to a AXI4-Stream Switch register. </p>
+<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
+    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void XAxisScr_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">XAxisScr_MiPortDisable()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">XAxisScr_MiPortEnable()</a>.</p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="gaf89ec8c5b66d39cb09316a163c97c357"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">s32 XAxisScr_CfgInitialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch___config.html">XAxis_Switch_Config</a> *&#160;</td>
+          <td class="paramname"><em>CfgPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8c.html">xaxis_switch.c</a>&gt;</code></p>
+
+<p>This function initializes the AXI4-Stream Switch core. </p>
+<p>This function must be called prior to using the core. Initialization of the core includes setting up the instance data and ensuring the hardware is in a quiescent state.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">CfgPtr</td><td>points to the configuration structure associated with the AXI4-Stream Switch core. </td></tr>
+    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if XAxisScr_CfgInitialize was successful.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Axis_Switch core connects up to 16 masters to 16 slaves. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config::BaseAddress</a>, <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch::Config</a>, <a class="el" href="struct_x_axis___switch.html#aa6fb801f6e169f44fb21f53317b36f1f">XAxis_Switch::IsReady</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga993cbd838dd30de44a943c7f4a046101"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">s32 XAxisScr_IsMiPortDisabled </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>MiIndex</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8c.html">xaxis_switch.c</a>&gt;</code></p>
+
+<p>This function returns the status of whether MUX is disabled. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">MiIndex</td><td>specifies an index that will be used for addressing the MUX which is within the range [0 to 15].</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>TRUE, if MUX is disabled.</li>
+<li>FALSE, if MUX is enabled.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Axis_Switch core connects up to 16 masters to 16 slaves. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config::BaseAddress</a>, <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch::Config</a>, <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">XAXIS_SCR_MI_MUX_START_OFFSET</a>, <a class="el" href="group__axis__switch__v1__0.html#ga06b31a381d36b949c68bbfaf92610bc3">XAXIS_SCR_MI_X_DISABLE_SHIFT</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga35ef34ba6c57b57506741b4a04f87e75"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">s32 XAxisScr_IsMiPortEnabled </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>MiIndex</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>SiIndex</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8c.html">xaxis_switch.c</a>&gt;</code></p>
+
+<p>This function returns the status of whether MUX is sourced from desired SI. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">MiIndex</td><td>specifies an index that will be used for addressing the MUX which is within the range [0 to 15]. </td></tr>
+    <tr><td class="paramname">SiIndex</td><td>specifies an index that will be used to identify, whether it is sourced. The range is [0 to 15].</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>TRUE, if MUX is sourced from SI.</li>
+<li>FALSE, if MUX is not sourced from SI.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Axis_Switch core connects up to 16 masters to 16 slaves. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config::BaseAddress</a>, <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch::Config</a>, <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">XAXIS_SCR_MI_MUX_START_OFFSET</a>, <a class="el" href="group__axis__switch__v1__0.html#ga06b31a381d36b949c68bbfaf92610bc3">XAXIS_SCR_MI_X_DISABLE_SHIFT</a>, <a class="el" href="group__axis__switch__v1__0.html#ga32f8940e49e11e5b238d5613ae4f667a">XAXIS_SCR_MI_X_MUX_MASK</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga68fcd4f0df5a838b218c7ebde0e6b152">XAxisScr_ReadReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#gad9c646b6e8d7f5d6c431c2985592fb4b">XAxisScr_SelfTest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa631f268bd77eca8acc9534775649df1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_axis___switch___config.html">XAxis_Switch_Config</a> * XAxisScr_LookupConfig </td>
+          <td>(</td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>DeviceId</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8h.html">xaxis_switch.h</a>&gt;</code></p>
+
+<p>This function returns a reference to an <a class="el" href="struct_x_axis___switch___config.html" title="This typedef contains configuration information for the AXI4-Stream Switch core. ">XAxis_Switch_Config</a> structure based on the core id, <em>DeviceId</em>. </p>
+<p>The return value will refer to an entry in the device configuration table defined in the <a class="el" href="xaxis__switch__g_8c.html">xaxis_switch_g.c</a> file.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DeviceId</td><td>is the unique core ID of the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core for the lookup operation.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XAxisScr_LookupConfig returns a reference to a config record in the configuration table (in <a class="el" href="xaxis__switch__g_8c.html">xaxis_switch_g.c</a>) corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1fcba7107d4ecb9955aa302c1b798729"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxisScr_MiPortDisable </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>MiIndex</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8c.html">xaxis_switch.c</a>&gt;</code></p>
+
+<p>This function disables the MUX port specified by a MI index and un-link SI, set previously. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">MiIndex</td><td>specifies an index that will be used for disabling MUX which is within the range [0 to 15].</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>MUX[MiIndex] is removed for SI[SiIndex]. Axis_Switch core connects up to 16 masters to 16 slaves. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config::BaseAddress</a>, <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch::Config</a>, <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">XAXIS_SCR_MI_MUX_START_OFFSET</a>, <a class="el" href="group__axis__switch__v1__0.html#ga34b4d7358d3edcf4103e2aa5e18d1e1f">XAXIS_SCR_MI_X_DISABLE_MASK</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga84a532ac4e377199c15802d84b43256e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxisScr_MiPortDisableAll </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8c.html">xaxis_switch.c</a>&gt;</code></p>
+
+<p>This function disables all the MUX port, in turn removes association with desired SI. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Axis_Switch core connects up to 16 masters to 16 slaves. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config::BaseAddress</a>, <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch::Config</a>, <a class="el" href="struct_x_axis___switch___config.html#a053a1f2027b8c3c2f81f6eaee1e5f824">XAxis_Switch_Config::MaxNumMI</a>, <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">XAXIS_SCR_MI_MUX_START_OFFSET</a>, <a class="el" href="group__axis__switch__v1__0.html#ga34b4d7358d3edcf4103e2aa5e18d1e1f">XAXIS_SCR_MI_X_DISABLE_MASK</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">XAxisScr_CfgInitialize()</a>, and <a class="el" href="group__axis__switch__v1__0.html#gad9c646b6e8d7f5d6c431c2985592fb4b">XAxisScr_SelfTest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga943a402b210b5f2901b6d6e7ae323d50"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAxisScr_MiPortEnable </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>MiIndex</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>SiIndex</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8c.html">xaxis_switch.c</a>&gt;</code></p>
+
+<p>This function enables the MUX port specified by a MI index and links with desired SI, indicated by a SiIndex. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance. </td></tr>
+    <tr><td class="paramname">MiIndex</td><td>specifies an index that will be used for enabling MUX which is within the range [0 to 15]. </td></tr>
+    <tr><td class="paramname">SiIndex</td><td>specifies an index that will be used as a source to MUX. The range is [0 to 15].</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>MUX[MiIndex] is sourced from SI[SiIndex]. Axis_Switch core connects up to 16 masters to 16 slaves. </dd></dl>
+
+<p>References <a class="el" href="struct_x_axis___switch___config.html#a4d4ae7097b966d999bcfaaad06bb4b13">XAxis_Switch_Config::BaseAddress</a>, <a class="el" href="struct_x_axis___switch.html#a972eb32655a31bf486774848eb2c408d">XAxis_Switch::Config</a>, <a class="el" href="group__axis__switch__v1__0.html#ga009bec9091359e44e8bf434e3528c2eb">XAXIS_SCR_MI_MUX_START_OFFSET</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga993bec85cbffd929a7f8418e65f293de">XAxisScr_WriteReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#gad9c646b6e8d7f5d6c431c2985592fb4b">XAxisScr_SelfTest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad9c646b6e8d7f5d6c431c2985592fb4b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">s32 XAxisScr_SelfTest </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xaxis__switch_8h.html">xaxis_switch.h</a>&gt;</code></p>
+
+<p>This function performs self test on AXI4-Stream Switch core registers. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axis___switch.html" title="The AXI4-Stream Switch driver instance data. ">XAxis_Switch</a> core instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>TRUE if self test passed.</li>
+<li>FALSE if self test failed.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">XAxisScr_MiPortEnable()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/index.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/index.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
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+<div class="header">
+  <div class="headertitle">
+<div class="title">axis_switch_v1_0 Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>This is the main header file for Xilinx AXI4-Stream Switch Control Router core. It is used for routing streams where masters in the system do not know final destination address.</p>
+<p><b>Core Features </b></p>
+<p>For a full description of AXI4-Stream Switch Control Router, please see the hardware specification.</p>
+<p><b>Software Initialization &amp; Configuration</b></p>
+<p>The application needs to do following steps in order for preparing the AXI4-Stream Switch Control Router core to be ready.</p>
+<ul>
+<li>Call XAxisScr_LookupConfig using a device ID to find the core configuration.</li>
+<li>Call XAxisScr_CfgInitialize to initialize the device and the driver instance associated with it.</li>
+</ul>
+<p><b>Interrupts </b></p>
+<p>This driver does not have interrupt mechanism.</p>
+<p><b> Virtual Memory </b></p>
+<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
+<p><b> Threads </b></p>
+<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
+<p><b> Asserts </b></p>
+<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
+<p><b> Building the driver </b></p>
+<p>The XAXI4-Stream Switch driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
+<pre>
+MODIFICATION HISTORY:</pre><pre>Ver   Who Date     Changes
+----- --- -------- --------------------------------------------------
+1.00  sha 01/28/15 Initial release.
+</pre> </div></div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/jquery.js b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/jquery.js
new file mode 100644
index 000000000..1f4d0b47c
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/jquery.js
@@ -0,0 +1,68 @@
+/*!
+ * jQuery JavaScript Library v1.7.1
+ * http://jquery.com/
+ *
+ * Copyright 2011, John Resig
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * Includes Sizzle.js
+ * http://sizzlejs.com/
+ * Copyright 2011, The Dojo Foundation
+ * Released under the MIT, BSD, and GPL Licenses.
+ *
+ * Date: Mon Nov 21 21:11:03 2011 -0500
+ */
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+/*!
+ * Sizzle CSS Selector Engine
+ *  Copyright 2011, The Dojo Foundation
+ *  Released under the MIT, BSD, and GPL Licenses.
+ *  More information: http://sizzlejs.com/
+ */
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+ * jQuery UI 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI
+ */
+(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:"1.8.18",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e==="number"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css("overflow")==="hidden"){return false}var e=(f&&f==="left")?"scrollLeft":"scrollTop",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!
+ * jQuery UI Widget 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Widget
+ */
+(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!
+ * jQuery UI Mouse 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Mouse
+ *
+ * Depends:
+ *	jquery.ui.widget.js
+ */
+(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e=="sw"){h.left=j.left+(f.width-h.width);h.top=null}if(e=="nw"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css("borderTopWidth"),h.css("borderRightWidth"),h.css("borderBottomWidth"),h.css("borderLeftWidth")],j=[h.css("paddingTop"),h.css("paddingRight"),h.css("paddingBottom"),h.css("paddingLeft")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(":hidden")||c(g).parents(":hidden").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var 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+  <div class="headertitle">
+<div class="title">APIs</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__axis__switch__v1__0.html" target="_self">Axis_switch_v1_0</a></td><td class="desc">This is the main file for Xilinx AXI4-Stream Switch Control Router core </td></tr>
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diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/struct_x_axis___switch.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/struct_x_axis___switch.html
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+<title>axis_switch_v1_0: XAxis_Switch Struct Reference</title>
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XAxis_Switch Struct Reference<div class="ingroups"><a class="el" href="group__axis__switch__v1__0.html">Axis_switch_v1_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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+          <td class="memname"><a class="el" href="struct_x_axis___switch___config.html">XAxis_Switch_Config</a> XAxis_Switch::Config</td>
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+
+<p>Hardware Configuration. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">XAxisScr_CfgInitialize()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">XAxisScr_IsMiPortDisabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">XAxisScr_MiPortDisable()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">XAxisScr_MiPortEnable()</a>.</p>
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+          <td class="memname">u32 XAxis_Switch::IsReady</td>
+        </tr>
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+
+<p>Core and the driver instance are initialized. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">XAxisScr_CfgInitialize()</a>.</p>
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+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+<div class="header">
+  <div class="headertitle">
+<div class="title">XAxis_Switch_Config Struct Reference<div class="ingroups"><a class="el" href="group__axis__switch__v1__0.html">Axis_switch_v1_0</a></div></div>  </div>
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+<div class="textblock"><p>Each AXI4-Stream Switch device should have a configuration structure associated. </p>
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+
+<p>BaseAddress is the physical base address of the core's registers. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#gaf89ec8c5b66d39cb09316a163c97c357">XAxisScr_CfgInitialize()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga993cbd838dd30de44a943c7f4a046101">XAxisScr_IsMiPortDisabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga35ef34ba6c57b57506741b4a04f87e75">XAxisScr_IsMiPortEnabled()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga1fcba7107d4ecb9955aa302c1b798729">XAxisScr_MiPortDisable()</a>, <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>, and <a class="el" href="group__axis__switch__v1__0.html#ga943a402b210b5f2901b6d6e7ae323d50">XAxisScr_MiPortEnable()</a>.</p>
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+<p>DeviceId is the unique ID of the AXI4- Stream Switch core. </p>
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+          <td class="memname">u8 XAxis_Switch_Config::MaxNumMI</td>
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+<p>Maximum number of Master interfaces. </p>
+
+<p>Referenced by <a class="el" href="group__axis__switch__v1__0.html#ga84a532ac4e377199c15802d84b43256e">XAxisScr_MiPortDisableAll()</a>.</p>
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+          <td class="memname">u8 XAxis_Switch_Config::MaxNumSI</td>
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+      </table>
+</div><div class="memdoc">
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+<p>Maximum number of Slave interfaces. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
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+</body>
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+  <td id="projectalign" style="padding-left: 0.5em;">
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+<tr class="separator:gad9c646b6e8d7f5d6c431c2985592fb4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/xaxis__switch__g_8c.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/xaxis__switch__g_8c.html
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axis_switch_v1_0
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+<div id="nav-path" class="navpath">
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+<div class="contents">
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_61559283180ce8c3b3bab0503f586775.html">axis_switch_v1_0</a></li><li class="navelem"><a class="el" href="dir_1e0861c8a2a5fa99d98e3f8ede87fb30.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxis_switch_selftest.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
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+<tr class="memitem:gad9c646b6e8d7f5d6c431c2985592fb4b"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axis__switch__v1__0.html#gad9c646b6e8d7f5d6c431c2985592fb4b">XAxisScr_SelfTest</a> (<a class="el" href="struct_x_axis___switch.html">XAxis_Switch</a> *InstancePtr)</td></tr>
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/xaxis__switch__sinit_8c.html b/thirdparty/xilinx/orig/axis_switch_v1_0/doc/html/api/xaxis__switch__sinit_8c.html
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+  <div id="navrow1" class="tabs">
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+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxis_switch_sinit.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
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diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/examples/index.html b/thirdparty/xilinx/orig/axis_switch_v1_0/examples/index.html
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index 000000000..42f12a36e
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+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/examples/index.html
@@ -0,0 +1,17 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>AXI4-Stream Switch driver example application</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Application for the driver axis_switch_v1_0 </h1>
+<HR>
+<ul>
+  <li>xaxis_switch_example.c <a href="xaxis_switch_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright ? 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/examples/xaxis_switch_example.c b/thirdparty/xilinx/orig/axis_switch_v1_0/examples/xaxis_switch_example.c
new file mode 100644
index 000000000..72c08ecc9
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/examples/xaxis_switch_example.c
@@ -0,0 +1,179 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_example.c
+*
+* This file demonstrates the use AXI4-Stream Switch Control Router driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xaxis_switch.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+* The following constants map to the XPAR parameters created in the
+* xparameters.h file. They are defined here such that a user can easily
+* change all the needed parameters in one place.
+*/
+#define XAXIS_SWITCH_DEVICE_ID		XPAR_AXIS_SWITCH_0_DEVICE_ID
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+int AxisSwitch_Example(u16 DeviceId);
+
+/************************** Variable Definitions *****************************/
+
+XAxis_Switch AxisSwitch;	/**< Instance of the AXI4-Stream Switch core */
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This is the main function for AXI4-Stream Switch example.
+*
+* @param	None.
+*
+* @return
+*		- XST_SUCCESS if AXI4-Stream Switch example ran successfully.
+*		- XST_FAILURE if AXI4-Stream Switch example failed.
+*
+* @note		Axis_Switch core connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	/* Call the AXI4-Stream Switch example */
+	Status = AxisSwitch_Example(XAXIS_SWITCH_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AXI4-Stream Switch driver example failed.\r\n");
+		return XST_FAILURE;
+	}
+
+	xil_printf("AXI4-Stream Switch driver example ran successfully.\r\n");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the use of AXI-Stream Switch driver functions.
+*
+* @param	DeviceId is the unique device id of the AXI4-Stream Switch
+*		core.
+*
+* @return
+*		- XST_SUCCESS if AXI4-Stream Switch example ran successfully.
+*		- XST_FAILURE if AXI4-Stream Switch example failed.
+*
+* @note		None.
+*
+****************************************************************************/
+int AxisSwitch_Example(u16 DeviceId)
+{
+	XAxis_Switch_Config *Config;
+	int Status;
+	u8 MiIndex;
+	u8 SiIndex;
+
+	/* Initialize the AXI4-Stream Switch driver so that it's ready to
+	 * use look up configuration in the config table, then
+	 * initialize it.
+	 */
+	Config = XAxisScr_LookupConfig(DeviceId);
+	if (NULL == Config) {
+		return XST_FAILURE;
+	}
+
+	Status = XAxisScr_CfgInitialize(&AxisSwitch, Config,
+						Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AXI4-Stream initialization failed.\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable register update */
+	XAxisScr_RegUpdateDisable(&AxisSwitch);
+
+	/* Disable all MI ports */
+	XAxisScr_MiPortDisableAll(&AxisSwitch);
+
+	/* Source SI[1] to MI[0] */
+	MiIndex = 0;
+	SiIndex = 1;
+	XAxisScr_MiPortEnable(&AxisSwitch, MiIndex, SiIndex);
+
+	/* Enable register update */
+	XAxisScr_RegUpdateEnable(&AxisSwitch);
+
+	/* Check for MI port enable */
+	Status = XAxisScr_IsMiPortEnabled(&AxisSwitch, MiIndex, SiIndex);
+	if (Status) {
+		xil_printf("MI[%d] is sourced from SI[%d].\r\n", MiIndex,
+				SiIndex);
+	}
+
+	/* Disable MI[MiIndex] */
+	XAxisScr_MiPortDisable(&AxisSwitch, MiIndex);
+
+	/* Check for MI port enable */
+	Status = XAxisScr_IsMiPortEnabled(&AxisSwitch, MiIndex, SiIndex);
+	if (!Status) {
+		xil_printf("MI[%d] is not sourced from SI[%d].\r\n", MiIndex,
+				SiIndex);
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/Makefile b/thirdparty/xilinx/orig/axis_switch_v1_0/src/Makefile
new file mode 100644
index 000000000..e9b0ff23d
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xaxis_switch_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling axis_switch"
+
+xaxis_switch_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xaxis_switch_includes
+
+xaxis_switch_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch.c b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch.c
new file mode 100644
index 000000000..6ce84a074
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch.c
@@ -0,0 +1,313 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch.c
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This is the main file for Xilinx AXI4-Stream Switch Control Router core.
+* Please see xaxis_switch.h for more details of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xaxis_switch.h"
+#include "string.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the AXI4-Stream Switch core. This function must
+* be called prior to using the core. Initialization of the core includes
+* setting up the instance data and ensuring the hardware is in a quiescent
+* state.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+* @param	CfgPtr points to the configuration structure associated with
+*		the AXI4-Stream Switch core.
+* @param	EffectiveAddr is the base address of the device. If address
+*		translation is being used, then this parameter must reflect the
+*		virtual base address. Otherwise, the physical address should be
+*		used.
+*
+* @return
+*		- XST_SUCCESS if XAxisScr_CfgInitialize was successful.
+*
+* @note		Axis_Switch core connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+s32 XAxisScr_CfgInitialize(XAxis_Switch *InstancePtr,
+			XAxis_Switch_Config *CfgPtr, u32 EffectiveAddr)
+{
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
+
+	/* Setup the instance */
+	(void)memset((void *)InstancePtr, 0, sizeof(XAxis_Switch));
+	(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
+					sizeof(XAxis_Switch_Config));
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	/* Make sure that all MI ports are disabled */
+	XAxisScr_MiPortDisableAll(InstancePtr);
+
+	/* Set the flag to indicate the driver is ready */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables the MUX port specified by a MI index and links with
+* desired SI, indicated by a SiIndex.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+* @param	MiIndex specifies an index that will be used for enabling MUX
+*		which is within the range [0 to 15].
+* @param	SiIndex specifies an index that will be used as a source to
+*		MUX. The range is [0 to 15].
+*
+* @return	None.
+*
+* @note		MUX[MiIndex] is sourced from SI[SiIndex]. Axis_Switch core
+*		connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+void XAxisScr_MiPortEnable(XAxis_Switch *InstancePtr, u8 MiIndex, u8 SiIndex)
+{
+	u32 MiPortAddr;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MiIndex < InstancePtr->Config.MaxNumMI);
+	Xil_AssertVoid(SiIndex < InstancePtr->Config.MaxNumSI);
+
+	/* Calculate MI port address to be enabled */
+	MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * MiIndex;
+
+	/* MUX[MiIndex] is sourced from SI[SiIndex] */
+	XAxisScr_WriteReg(InstancePtr->Config.BaseAddress, MiPortAddr,
+				SiIndex);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the MUX port specified by a MI index and un-link
+* SI, set previously.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+* @param	MiIndex specifies an index that will be used for disabling MUX
+*		which is within the range [0 to 15].
+*
+* @return	None.
+*
+* @note		MUX[MiIndex] is removed for SI[SiIndex]. Axis_Switch core
+*		connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+void XAxisScr_MiPortDisable(XAxis_Switch *InstancePtr, u8 MiIndex)
+{
+	u32 MiPortAddr;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MiIndex < InstancePtr->Config.MaxNumMI);
+
+
+	/* Calculate MI port address of which to be enabled */
+	MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * MiIndex;
+
+	XAxisScr_WriteReg(InstancePtr->Config.BaseAddress, MiPortAddr,
+				XAXIS_SCR_MI_X_DISABLE_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the status of whether MUX is sourced from desired SI.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+* @param	MiIndex specifies an index that will be used for addressing
+*		the MUX which is within the range [0 to 15].
+* @param	SiIndex specifies an index that will be used to identify,
+*		whether it is sourced. The range is [0 to 15].
+*
+* @return
+*		- TRUE, if MUX is sourced from SI.
+*		- FALSE, if MUX is not sourced from SI.
+*
+* @note		Axis_Switch core connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+s32 XAxisScr_IsMiPortEnabled(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex)
+{
+	u32 MiPortAddr;
+	u32 RegValue;
+	u8 Enable;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MiIndex < InstancePtr->Config.MaxNumMI);
+	Xil_AssertNonvoid(SiIndex < InstancePtr->Config.MaxNumSI);
+
+	/* Calculate MI port address to be enabled */
+	MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * MiIndex;
+
+	/* Read MI port data */
+	RegValue = XAxisScr_ReadReg(InstancePtr->Config.BaseAddress,
+			MiPortAddr);
+
+	/* Fetch enable bit */
+	Enable = RegValue >> XAXIS_SCR_MI_X_DISABLE_SHIFT;
+
+	/* Fetch SI value */
+	RegValue &= XAXIS_SCR_MI_X_MUX_MASK;
+
+
+	/* When SiIndex is zero */
+	if ((RegValue == SiIndex) && (!Enable)) {
+		RegValue = TRUE;
+	}
+	else if((RegValue & SiIndex) && (!Enable)) {
+		RegValue = TRUE;
+	}
+	else {
+		RegValue = FALSE;
+	}
+
+	return RegValue;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the status of whether MUX is disabled.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+* @param	MiIndex specifies an index that will be used for addressing
+*		the MUX which is within the range [0 to 15].
+*
+* @return
+*		- TRUE, if MUX is disabled.
+*		- FALSE, if MUX is enabled.
+*
+* @note		Axis_Switch core connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+s32 XAxisScr_IsMiPortDisabled(XAxis_Switch *InstancePtr, u8 MiIndex)
+{
+	u32 MiPortAddr;
+	u8 Disable;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MiIndex < InstancePtr->Config.MaxNumMI);
+
+	/* Calculate MI port address to be enabled */
+	MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * MiIndex;
+
+	/* Read MI port data */
+	Disable = XAxisScr_ReadReg(InstancePtr->Config.BaseAddress,
+			MiPortAddr) >> XAXIS_SCR_MI_X_DISABLE_SHIFT;
+
+	if (Disable) {
+		Disable = TRUE;
+	}
+
+	return Disable;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables all the MUX port, in turn removes association with
+* desired SI.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		Axis_Switch core connects up to 16 masters to 16 slaves.
+*
+******************************************************************************/
+void XAxisScr_MiPortDisableAll(XAxis_Switch *InstancePtr)
+{
+	u32 MiPortAddr;
+	u8 Index;
+
+	/* Verify argument. */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	for (Index = 0; Index < InstancePtr->Config.MaxNumMI; Index++) {
+
+		/* Calculate MI port address of which to be enabled */
+		MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * Index;
+
+		XAxisScr_WriteReg(InstancePtr->Config.BaseAddress, MiPortAddr,
+				XAXIS_SCR_MI_X_DISABLE_MASK);
+	}
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch.h b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch.h
new file mode 100644
index 000000000..604760916
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch.h
@@ -0,0 +1,208 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch.h
+* @addtogroup axis_switch_v1_0
+* @{
+* @details
+*
+* This is the main header file for Xilinx AXI4-Stream Switch Control Router
+* core. It is used for routing streams where masters in the system do not know
+* final destination address.
+*
+* <b>Core Features </b>
+*
+* For a full description of AXI4-Stream Switch Control Router, please see the
+* hardware specification.
+*
+* <b>Software Initialization & Configuration</b>
+*
+* The application needs to do following steps in order for preparing the
+* AXI4-Stream Switch Control Router core to be ready.
+*
+* - Call XAxisScr_LookupConfig using a device ID to find the core
+*   configuration.
+* - Call XAxisScr_CfgInitialize to initialize the device and the driver
+*   instance associated with it.
+*
+* <b>Interrupts </b>
+*
+* This driver does not have interrupt mechanism.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XAXI4-Stream Switch driver is composed of several source files. This
+* allows the user to build and link only those parts of the driver that are
+* necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XAXIS_SWITCH_H_
+#define XAXIS_SWITCH_H_		/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xaxis_switch_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+* This typedef contains configuration information for the AXI4-Stream Switch
+* core. Each AXI4-Stream Switch device should have a configuration structure
+* associated.
+*/
+typedef struct {
+	u16 DeviceId;		/**< DeviceId is the unique ID of the AXI4-
+				  *  Stream Switch core */
+	u32 BaseAddress;	/**< BaseAddress is the physical base address
+				  *  of the core's registers */
+	u8 MaxNumSI;		/**< Maximum number of Slave interfaces */
+	u8 MaxNumMI;		/**< Maximum number of Master interfaces */
+} XAxis_Switch_Config;
+
+/**
+* The AXI4-Stream Switch driver instance data. An instance must be allocated
+* for each core in use.
+*/
+typedef struct {
+	XAxis_Switch_Config Config;	/**< Hardware Configuration */
+	u32 IsReady;			/**< Core and the driver instance are
+					  *  initialized */
+} XAxis_Switch;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This macro enables register updates.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_RegUpdateEnable(XAxis_Switch *InstancePtr)
+*
+******************************************************************************/
+#define XAxisScr_RegUpdateEnable(InstancePtr) \
+	XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XAXIS_SCR_CTRL_OFFSET, \
+		XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAXIS_SCR_CTRL_OFFSET) | \
+				XAXIS_SCR_CTRL_REG_UPDATE_MASK)
+
+/*****************************************************************************/
+/**
+*
+* This macro disables register updates.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_RegUpdateDisable(XAxis_Switch *InstancePtr)
+*
+******************************************************************************/
+#define XAxisScr_RegUpdateDisable(InstancePtr) \
+	XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XAXIS_SCR_CTRL_OFFSET, \
+		XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAXIS_SCR_CTRL_OFFSET) & \
+				(~XAXIS_SCR_CTRL_REG_UPDATE_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization function in xaxis_switch_sinit.c */
+XAxis_Switch_Config *XAxisScr_LookupConfig(u16 DeviceId);
+
+/* Initialization and control functions in xaxis_switch.c */
+s32 XAxisScr_CfgInitialize(XAxis_Switch *InstancePtr,
+			XAxis_Switch_Config *CfgPtr, u32 EffectiveAddr);
+
+void XAxisScr_MiPortEnable(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex);
+void XAxisScr_MiPortDisable(XAxis_Switch *InstancePtr, u8 MiIndex);
+s32 XAxisScr_IsMiPortEnabled(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex);
+s32 XAxisScr_IsMiPortDisabled(XAxis_Switch *InstancePtr, u8 MiIndex);
+void XAxisScr_MiPortDisableAll(XAxis_Switch *InstancePtr);
+
+/* Self test function in xaxis_switch_selftest.c */
+s32 XAxisScr_SelfTest(XAxis_Switch *InstancePtr);
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_g.c b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_g.c
new file mode 100644
index 000000000..e8fdeef1a
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_g.c
@@ -0,0 +1,75 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_g.c
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This file gets generated automatically by HSI.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver  Who Date     Changes
+* ---- --- -------- -----------------------------------------------------
+* 1.00 sha 07/15/15 Added XPAR_XAXIS_SWITCH_NUM_INSTANCES macro to control
+*                   config table parameters. Modified copyright header.
+*                   Added doxygen tag and modification history.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xaxis_switch.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+* The configuration table for devices
+*/
+
+XAxis_Switch_Config XAxis_Switch_ConfigTable[] =
+{
+	{
+#if defined(XPAR_XAXIS_SWITCH_NUM_INSTANCES) && XPAR_XAXIS_SWITCH_NUM_INSTANCES > 0
+		XPAR_AXIS_SWITCH_0_DEVICE_ID,
+		XPAR_AXIS_SWITCH_0_BASEADDR,
+		XPAR_AXIS_SWITCH_0_NUM_SI,
+		XPAR_AXIS_SWITCH_0_NUM_MI
+#endif
+	}
+};
+/** @} */
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_hw.h b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_hw.h
new file mode 100644
index 000000000..f98227e19
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_hw.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_hw.h
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This header file contains identifiers and register-level core functions (or
+* macros) that can be used to access the Xilinx AXI4-Stream Switch Control
+* Router core.
+*
+* For more information about the operation of this core see the hardware
+* specification and documentation in the higher level driver
+* xaxis_switch.h file.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XAXIS_SWITCH_HW_H_
+#define XAXIS_SWITCH_HW_H_	/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name MI MUX register offsets
+*
+* @{
+*/
+#define XAXIS_SCR_CTRL_OFFSET		0x000	/**< Control Register offset */
+#define XAXIS_SCR_MI_MUX_START_OFFSET	0x040	/**< Start of MI MUX Register
+						  *  offset */
+#define XAXIS_SCR_MI_MUX_END_OFFSET	0x07C	/**< End of MI MUX Register
+						  *  offset */
+
+/*@}*/
+
+/** @name MI MUX Control register mask
+* @{
+*/
+#define XAXIS_SCR_CTRL_REG_UPDATE_MASK	0x02	/**< Register Update
+						  *  mask */
+/*@}*/
+
+/** @name MI MUX register mask
+*
+* It is applicable for MI[0...15] registers.
+* @{
+*/
+#define XAXIS_SCR_MI_X_MUX_MASK		0x0F		/**< MI MUX mask */
+#define XAXIS_SCR_MI_X_DISABLE_MASK	0x80000000	/**< MI Disable mask */
+#define XAXIS_SCR_MI_X_DISABLE_SHIFT	31	/**< MI Disable shift */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/** @name Register access macro definition
+* @{
+*/
+#define XAxisScr_In32		Xil_In32	/**< Input Operations */
+#define XAxisScr_Out32		Xil_Out32	/**< Output Operations */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads a value from a AXI4-Stream Switch register. A 32 bit read
+* is performed. If the component is implemented in a smaller width, only the
+* least significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param	BaseAddress is the base address of the XAxis_Switch core
+*		instance.
+* @param	RegOffset is the register offset of the register (defined at
+*		the top of this file).
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XAxisScr_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XAxisScr_ReadReg(BaseAddress, RegOffset) \
+	XAxisScr_In32((BaseAddress) + ((u32)RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes a value to a AXI4-Stream Switch register. A 32 bit write
+* is performed. If the component is implemented in a smaller width, only the
+* least significant data is written.
+*
+* @param	BaseAddress is the base address of the XAxis_Switch core
+*		instance.
+* @param	RegOffset is the register offset of the register (defined at
+*		the top of this file) to be written.
+* @param	Data is the 32-bit value to write into the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_WriteReg(u32 BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+******************************************************************************/
+#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data) \
+	XAxisScr_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
+/*@}*/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
\ No newline at end of file
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_selftest.c b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_selftest.c
new file mode 100644
index 000000000..69bb8427e
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_selftest.c
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_selftest.c
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This file contains self test function for the AXI4-Stream Source Control
+* Router core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xaxis_switch.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function performs self test on AXI4-Stream Switch core registers.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return
+*		- TRUE if self test passed.
+*		- FALSE if self test failed.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XAxisScr_SelfTest(XAxis_Switch *InstancePtr)
+{
+	u8 MiIndex;
+	u8 SiIndex;
+	s32 Status;
+
+	/* Verify argument. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Disable all MI ports */
+	XAxisScr_MiPortDisableAll(InstancePtr);
+
+	/* Source SI[1] to MI[0] */
+	MiIndex = 0;
+	SiIndex = 1;
+	XAxisScr_MiPortEnable(InstancePtr, MiIndex, SiIndex);
+
+	/* Check for MI port enable */
+	Status = XAxisScr_IsMiPortEnabled(InstancePtr, MiIndex, SiIndex);
+	if (Status) {
+		xil_printf("MI[%d] is sourced from SI[%d].\r\n", MiIndex,
+				SiIndex);
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_sinit.c b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_sinit.c
new file mode 100644
index 000000000..af38db75e
--- /dev/null
+++ b/thirdparty/xilinx/orig/axis_switch_v1_0/src/xaxis_switch_sinit.c
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_sinit.c
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This file contains static initialization method for Xilinx AXI4-Stream
+* Source Control Router core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* 1.00  sha 07/15/15 Defined macro XPAR_XAXIS_SWITCH_NUM_INSTANCES if not
+*                    defined in xparameters.h
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xaxis_switch.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+#ifndef XPAR_XAXIS_SWITCH_NUM_INSTANCES
+#define XPAR_XAXIS_SWITCH_NUM_INSTANCES			0
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function returns a reference to an XAxis_Switch_Config structure based
+* on the core id, <i>DeviceId</i>. The return value will refer to an entry in
+* the device configuration table defined in the xaxis_switch_g.c file.
+*
+* @param	DeviceId is the unique core ID of the XAxis_Switch core for
+*		the lookup operation.
+*
+* @return	XAxisScr_LookupConfig returns a reference to a config record
+*		in the configuration table (in xaxis_switch_g.c)
+*		corresponding to <i>DeviceId</i>, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XAxis_Switch_Config *XAxisScr_LookupConfig(u16 DeviceId)
+{
+	extern XAxis_Switch_Config
+		XAxis_Switch_ConfigTable[XPAR_XAXIS_SWITCH_NUM_INSTANCES];
+	XAxis_Switch_Config *CfgPtr = NULL;
+	u32 Index;
+
+	/* Checking for device id for which instance it is matching */
+	for (Index = (u32)0x0; Index < (u32)XPAR_XAXIS_SWITCH_NUM_INSTANCES;
+								Index++) {
+
+		/* Assigning address of config table if both device ids
+		 * are matched
+		 */
+		if (XAxis_Switch_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XAxis_Switch_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XAxis_Switch_Config *)CfgPtr;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/build/vxworks5_4/xtag_csp_common_v1_00_a.c b/thirdparty/xilinx/orig/common_v1_00_a/build/vxworks5_4/xtag_csp_common_v1_00_a.c
new file mode 100644
index 000000000..1b43eab3d
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/build/vxworks5_4/xtag_csp_common_v1_00_a.c
@@ -0,0 +1,53 @@
+/* xtag_csp_common_v1_00_a.c - Xilinx driver inclusion file */
+
+/*
+  XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+  AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+  SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+  OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+  APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+  THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+  AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+  FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+  WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+  IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+  REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+  INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+  FOR A PARTICULAR PURPOSE.
+
+  (c) Copyright 2002 Xilinx Inc.
+  All rights reserved.
+
+*/
+
+/*
+
+modification history
+--------------------
+01a,02apr02,rmm  First release. 
+
+*/
+
+/*
+DESCRIPTION
+This file is used to compile the common component of the Xilinx Chip Support
+Package (CSP).
+
+INCLUDE FILES:
+
+SEE ALSO:
+*/
+#include "vxWorks.h"
+#include "config.h"
+
+#ifdef INCLUDE_XCOMMON
+#  include "xbasic_types.c"
+#  include "xversion.c"
+#endif
+
+
+
+
+
+
+
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/data/common.mdd b/thirdparty/xilinx/orig/common_v1_00_a/data/common.mdd
new file mode 100644
index 000000000..a9c9e2883
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/data/common.mdd
@@ -0,0 +1,41 @@
+###############################################################################
+#
+# Copyright (C) 2004 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+OPTION psf_version = 2.1;
+
+BEGIN driver common 
+
+  OPTION VERSION = 1.00.a;
+  OPTION NAME = common;
+  OPTION supported_peripherals = ();
+
+END driver
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/doc/html/api/HTML_custom.css b/thirdparty/xilinx/orig/common_v1_00_a/doc/html/api/HTML_custom.css
new file mode 100644
index 000000000..26defe1a8
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/doc/html/api/HTML_custom.css
@@ -0,0 +1,1430 @@
+/* The standard CSS for doxygen 1.8.5 */
+
+body{
+	background: none repeat scroll 0 0 #FFFFFF;
+	color: #51626F;
+	font-family: arial,sans-serif !important;
+    	font-size: 75% !important;
+    	font-weight: normal !important;
+    	margin-left: 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+.contents, .textblock {
+font: 400 12px/15px arial,sans-serif;
+}
+.textblock ul, .contents ul{ 
+	margin: 5px 0;
+	padding: 0;
+}
+.textblockol {
+	margin:5px 15px; 
+	padding:0;
+	list-style-image: none; 
+}
+.textblock li, .contents li {
+	margin: 0 0 2px 15px;
+    	padding: 0 0 2px 2px;
+}
+
+/* For hiding RHS TOC 
+.toc{
+display:none;
+}*/
+/* For hiding RHS TOC*/ 
+
+For hiding Nav Bar
+.navpath, #nav-path{
+display:none;
+}
+/* For hiding Nav Bar*/
+/* For hiding extra navrows */
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+.title {
+	font: 400 14px/28px arial,sans-serif;
+	font-size: 150%;
+	font-weight: bold;
+	margin: 9px 2px;
+	text-align: left;
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+
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+    color: #E66A08 !important;
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+    font-size: 1.2em !important;
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+    color: #E66A08 !important;
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+}
+p {
+    padding-bottom: 0px !important;
+	font: 400 12px/15px arial,sans-serif;
+}
+li p {
+    padding-bottom: 0px !important;
+	margin: 0px;
+}
+
+h1, h2.groupheader {
+    clear: both !important;
+    color: #627178 !important;
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+dt {
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+/*Hiding Tabs - Tushar
+div.tabs 
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+} */
+
+div.multicol {
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+}
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+        text-align: center;
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+
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+
+pre.fragment {
+        border: 0px solid #C4CFE5;
+        background-color: #FFFFFF;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        font-size:  9pt;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 105%;
+}
+
+div.fragment {
+        padding: 0px;
+        margin: 0px;
+	background-color: #FFFFFF;
+	border: 0px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 13px;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+div.line.glow {
+	background-color: cyan;
+	box-shadow: 0 0 10px cyan;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #51626F
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: cyan;
+	box-shadow: 0 0 15px cyan;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
+        border-bottom: 1px solid #DEE4F0;
+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+	font-size: 80%;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+        -webkit-transition: box-shadow 0.5s linear;
+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
+        display: table !important;
+        width: 100%;
+}
+
+.memitem.glow {
+         box-shadow: 0 0 15px cyan;
+}
+
+.memname {
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memname td {
+	vertical-align: bottom;
+}
+
+.memproto, dl.reflist dt {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #E66A08 !important;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+.memdoc, dl.reflist dd {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 6px 10px 2px 10px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        background-image:url('nav_g.png');
+        background-repeat:repeat-x;
+        background-color: #FFFFFF;
+        /* opera specific markup */
+        border-bottom-left-radius: 4px;
+        border-bottom-right-radius: 4px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 4px;
+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 4px;
+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
+        margin: 0px 0px 10px 0px;
+        padding: 5px;
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+.paramname code {
+        line-height: 14px;
+}
+
+.params, .retval, .exception, .tparams {
+        margin-left: 0px;
+        padding-left: 0px;
+		font: 400 12px/15px arial,sans-serif;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+table.mlabels {
+	border-spacing: 0px;
+}
+
+td.mlabels-left {
+	width: 100%;
+	padding: 0px;
+}
+
+td.mlabels-right {
+	vertical-align: bottom;
+	padding: 0px;
+	white-space: nowrap;
+}
+
+span.mlabels {
+        margin-left: 8px;
+}
+
+span.mlabel {
+        background-color: #728DC1;
+        border-top:1px solid #5373B4;
+        border-left:1px solid #5373B4;
+        border-right:1px solid #C4CFE5;
+        border-bottom:1px solid #C4CFE5;
+	text-shadow: none;
+	color: white;
+	margin-right: 4px;
+	padding: 2px 3px;
+	border-radius: 3px;
+	font-size: 7pt;
+	white-space: nowrap;
+	vertical-align: middle;
+}
+
+
+
+/* @end */
+
+/* these are for tree view when not used as main index */
+
+div.directory {
+        margin: 10px 0px;
+        border-top: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        width: 100%;
+}
+
+.directory table {
+        border-collapse:collapse;
+}
+
+.directory td {
+        margin: 0px;
+        padding: 0px;
+	vertical-align: top;
+}
+
+.directory td.entry {
+        white-space: nowrap;
+        padding-right: 6px;
+	padding-top: 3px;
+}
+
+.directory td.entry a {
+        outline:none;
+}
+
+.directory td.entry a img {
+        border: none;
+}
+
+.directory td.desc {
+        width: 100%;
+        padding-left: 6px;
+	padding-right: 6px;
+	padding-top: 3px;
+	border-left: 1px solid rgba(0,0,0,0.05);
+}
+
+.directory tr.even {
+	padding-left: 6px;
+	background-color: #F7F8FB;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+.directory .levels {
+        white-space: nowrap;
+        width: 100%;
+        text-align: right;
+        font-size: 9pt;
+}
+
+.directory .levels span {
+        cursor: pointer;
+        padding-left: 2px;
+        padding-right: 2px;
+	color: #3D578C;
+}
+
+div.dynheader {
+        margin-top: 8px;
+	-webkit-touch-callout: none;
+	-webkit-user-select: none;
+	-khtml-user-select: none;
+	-moz-user-select: none;
+	-ms-user-select: none;
+	user-select: none;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+        margin-top: 4px;
+        margin-bottom: 4px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #CCCCCC;
+	color: #51626F;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+}
+table.fieldtable {
+        /*width: 100%;*/
+        margin-bottom: 10px;
+        border: 1px solid #A8B8D9;
+        border-spacing: 0px;
+        -moz-border-radius: 4px;
+        -webkit-border-radius: 4px;
+        border-radius: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+}
+
+.fieldtable td, .fieldtable th {
+        padding: 3px 7px 2px;
+}
+
+.fieldtable td.fieldtype, .fieldtable td.fieldname {
+        white-space: nowrap;
+        border-right: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        vertical-align: top;
+}
+
+.fieldtable td.fieldname {
+        padding-top: 3px;
+}
+
+.fieldtable td.fielddoc {
+        border-bottom: 1px solid #A8B8D9;
+        /*width: 100%;*/
+}
+
+.fieldtable td.fielddoc p:first-child {
+        margin-top: 0px;
+}       
+        
+.fieldtable td.fielddoc p:last-child {
+        margin-bottom: 2px;
+}
+
+.fieldtable tr:last-child td {
+        border-bottom: none;
+}
+
+.fieldtable th {
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        font-size: 90%;
+        color: #253555;
+        padding-bottom: 4px;
+        padding-top: 5px;
+        text-align:left;
+        -moz-border-radius-topleft: 4px;
+        -moz-border-radius-topright: 4px;
+        -webkit-border-top-left-radius: 4px;
+        -webkit-border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        border-top-right-radius: 4px;
+        border-bottom: 1px solid #A8B8D9;
+}
+
+
+.tabsearch {
+	top: 5px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	background-position: 0 -5px;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+	color: #283A5D;
+	font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;
+	text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+	text-decoration: none;        
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('');
+        background-repeat:repeat-x;
+	background-color: #FFFFFF;
+	margin:  0px;
+	border-bottom: 0px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */
+dl.section
+{
+	margin-left: 0px;
+	padding-left: 0px;
+}
+
+dl.note
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #505050;
+}
+
+dl.todo
+{
+        margin-left:-7px;
+        padding-left: 12px;
+        border-left:4px solid;
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #C08050;
+}
+
+dl.section dd {
+	margin-bottom: 6px;
+}
+
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+	padding: 12px;
+	
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 300% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 5px 0px;
+	text-align: right;
+	width: 100%;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 5px;
+	text-align: left;
+	width: 100%;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 11px solid #5373B4;
+}
+
+.image
+{
+        text-align: left;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
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+<tr class="memitem:ga34f8bacc03ca6dfb9340c96cd449bb1c"><td class="memItemLeft" align="right" valign="top">unsigned int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__common__v1__00__a.html#ga34f8bacc03ca6dfb9340c96cd449bb1c">XAssertStatus</a></td></tr>
+<tr class="separator:ga34f8bacc03ca6dfb9340c96cd449bb1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga70e19ad3b7f3f7facbe157e082614b83"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__common__v1__00__a.html#ga70e19ad3b7f3f7facbe157e082614b83">XWaitInAssert</a> = TRUE</td></tr>
+<tr class="separator:ga70e19ad3b7f3f7facbe157e082614b83"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga34f8bacc03ca6dfb9340c96cd449bb1c"><td class="memItemLeft" align="right" valign="top">unsigned int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__common__v1__00__a.html#ga34f8bacc03ca6dfb9340c96cd449bb1c">XAssertStatus</a></td></tr>
+<tr class="separator:ga34f8bacc03ca6dfb9340c96cd449bb1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="gacb16a9ce84634175b8be6eb6320e5d40"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XASSERT_NONVOID</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">expression</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{                                                  \</div>
+<div class="line">    if (expression)                                \</div>
+<div class="line">    {                                              \</div>
+<div class="line">        XAssertStatus = XASSERT_NONE;              \</div>
+<div class="line">    }                                              \</div>
+<div class="line">    else                                           \</div>
+<div class="line">    {                                              \</div>
+<div class="line">        XAssert(__FILE__, __LINE__);               \</div>
+<div class="line">                XAssertStatus = XASSERT_OCCURRED;  \</div>
+<div class="line">        return 0;                                  \</div>
+<div class="line">    }                                              \</div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>This assert macro is to be used for functions that do return a value. </p>
+<p>This in conjunction with the XWaitInAssert boolean can be used to accomodate tests so that asserts which fail allow execution to continue.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">expression</td><td>is the expression to evaluate. If it evaluates to false, the assert occurs.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns 0 unless the XWaitInAssert variable is true, in which case no return is made and an infinite loop is entered.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>Referenced by <a class="el" href="group__common__v1__00__a.html#ga5c11abd9381dbdec3f55a97b41323ddd">XUtil_MemoryTest16()</a>, <a class="el" href="group__common__v1__00__a.html#gab898ebdd11950907ac66e978d2bd8d92">XUtil_MemoryTest32()</a>, <a class="el" href="group__common__v1__00__a.html#ga777417fa2028d84d0f03ebb3570ea90f">XUtil_MemoryTest8()</a>, <a class="el" href="group__common__v1__00__a.html#gacc5446415b912932b8a428ca698094d5">XVersion_FromString()</a>, and <a class="el" href="group__common__v1__00__a.html#gab85b0654f0b4b643640c57369ecd3bf2">XVersion_IsEqual()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gafc46bd7c308a9f91dbea4b65802bebae"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XASSERT_NONVOID_ALWAYS</td>
+          <td>(</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{                                                  \</div>
+<div class="line">   XAssert(__FILE__, __LINE__);                    \</div>
+<div class="line">           XAssertStatus = XASSERT_OCCURRED;       \</div>
+<div class="line">   return 0;                                       \</div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>Always assert. </p>
+<p>This assert macro is to be used for functions that do return a value. Use for instances where an assert should always occur.</p>
+<dl class="section return"><dt>Returns</dt><dd>Returns void unless the XWaitInAssert variable is true, in which case no return is made and an infinite loop is entered.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1c87fc9274e19272996a00cfc7444693"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XASSERT_VOID</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">expression</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{                                                  \</div>
+<div class="line">    if (expression)                                \</div>
+<div class="line">    {                                              \</div>
+<div class="line">        XAssertStatus = XASSERT_NONE;              \</div>
+<div class="line">    }                                              \</div>
+<div class="line">    else                                           \</div>
+<div class="line">    {                                              \</div>
+<div class="line">        XAssert(__FILE__, __LINE__);               \</div>
+<div class="line">                XAssertStatus = XASSERT_OCCURRED;  \</div>
+<div class="line">        return;                                    \</div>
+<div class="line">    }                                              \</div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>This assert macro is to be used for functions that do not return anything (void). </p>
+<p>This in conjunction with the XWaitInAssert boolean can be used to accomodate tests so that asserts which fail allow execution to continue.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">expression</td><td>is the expression to evaluate. If it evaluates to false, the assert occurs.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns void unless the XWaitInAssert variable is true, in which case no return is made and an infinite loop is entered.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>Referenced by <a class="el" href="group__common__v1__00__a.html#gab2a1a40f520ee3c62f829d0e20581503">XVersion_Copy()</a>, and <a class="el" href="group__common__v1__00__a.html#ga20bcd31ada05091e23633264cb63d33c">XVersion_ToString()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaf6e6133cad2f067f155510cb4323b04b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XASSERT_VOID_ALWAYS</td>
+          <td>(</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{                                                  \</div>
+<div class="line">   XAssert(__FILE__, __LINE__);                    \</div>
+<div class="line">           XAssertStatus = XASSERT_OCCURRED;       \</div>
+<div class="line">   return;                                         \</div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>Always assert. </p>
+<p>This assert macro is to be used for functions that do not return anything (void). Use for instances where an assert should always occur.</p>
+<dl class="section return"><dt>Returns</dt><dd>Returns void unless the XWaitInAssert variable is true, in which case no return is made and an infinite loop is entered.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf1e439aeef84a0f2e1f0ad0937d3ccba"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XCOMPONENT_IS_READY&#160;&#160;&#160;0x11111111</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>component has been initialized </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8146fba914623632ff0d9edc2acc6a01"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XCOMPONENT_IS_STARTED&#160;&#160;&#160;0x22222222</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>component has been started </p>
+
+</div>
+</div>
+<a class="anchor" id="ga23d8f4edc8649a0ba9deded0dbb7b05b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_MEM_COPY</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DestPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">SrcPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__vxworks_8h.html">xenv_vxworks.h</a>&gt;</code></p>
+
+<p>Copies a non-overlapping block of memory. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DestPtr</td><td>Destination address to copy data to.</td></tr>
+    <tr><td class="paramname">SrcPtr</td><td>Source address to copy data from.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>Number of bytes to copy.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>XENV_MEM_COPY is deprecated. Use memcpy() instead. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga23d8f4edc8649a0ba9deded0dbb7b05b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_MEM_COPY</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DestPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">SrcPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;memcpy(DestPtr, SrcPtr, Bytes)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>Copies a non-overlapping block of memory. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DestPtr</td><td>Destination address to copy data to.</td></tr>
+    <tr><td class="paramname">SrcPtr</td><td>Source address to copy data from.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>Number of bytes to copy.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga23d8f4edc8649a0ba9deded0dbb7b05b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_MEM_COPY</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DestPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">SrcPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p>Copies a non-overlapping block of memory. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DestPtr</td><td>Destination address to copy data to.</td></tr>
+    <tr><td class="paramname">SrcPtr</td><td>Source address to copy data from.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>Number of bytes to copy.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.</dd>
+<dd>
+This implemention MAY BREAK work if source and target memory area are overlapping. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad29b4ad1407af9659a9295b4fab3e64e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_MEM_FILL</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DestPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Data, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;memset((void *) DestPtr, (int) Data, (size_t) Bytes)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__vxworks_8h.html">xenv_vxworks.h</a>&gt;</code></p>
+
+<p>Fills an area of memory with constant data. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DestPtr</td><td>Destination address to copy data to.</td></tr>
+    <tr><td class="paramname">Data</td><td>Value to set.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>Number of bytes to copy.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>XENV_MEM_FILL is deprecated. Use memset() instead. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad29b4ad1407af9659a9295b4fab3e64e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_MEM_FILL</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DestPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Data, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;memset(DestPtr, Data, Bytes)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>Fills an area of memory with constant data. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DestPtr</td><td>Destination address to copy data to.</td></tr>
+    <tr><td class="paramname">Data</td><td>Value to set.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>Number of bytes to copy.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad29b4ad1407af9659a9295b4fab3e64e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_MEM_FILL</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DestPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Data, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;memset((void *) DestPtr, (int) Data, (size_t) Bytes)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p>Fills an area of memory with constant data. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DestPtr</td><td>Destination address to copy data to.</td></tr>
+    <tr><td class="paramname">Data</td><td>Value to set.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>Number of bytes to copy.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>The use of XENV_MEM_FILL is deprecated. Use memset() instead. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadfc03b6e4724367a8e803700cf62c394"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_DELTA_MS</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp1Ptr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp2Ptr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__vxworks_8h.html">xenv_vxworks.h</a>&gt;</code></p>
+
+<p>This macro is not yet implemented and always returns 0. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Stamp1Ptr</td><td>is the first sampled time stamp. </td></tr>
+    <tr><td class="paramname">Stamp2Ptr</td><td>is the second sampled time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>0</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>None. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadfc03b6e4724367a8e803700cf62c394"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_DELTA_MS</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp1Ptr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp2Ptr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>This macro is not yet implemented and always returns 0. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Stamp1Ptr</td><td>is the first sampled time stamp. </td></tr>
+    <tr><td class="paramname">Stamp2Ptr</td><td>is the second sampled time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>0</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>This macro must be implemented by the user </p>
+
+</div>
+</div>
+<a class="anchor" id="gadfc03b6e4724367a8e803700cf62c394"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_DELTA_MS</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp1Ptr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp2Ptr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p>This macro is not yet implemented and always returns 0. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Stamp1Ptr</td><td>is the first sampled time stamp. </td></tr>
+    <tr><td class="paramname">Stamp2Ptr</td><td>is the second sampled time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>0</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>This macro must be implemented by the user. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4d013326acf8271a92f82d35fa0cf17d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_DELTA_US</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp1Ptr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp2Ptr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__vxworks_8h.html">xenv_vxworks.h</a>&gt;</code></p>
+
+<p>This macro is not yet implemented and always returns 0. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Stamp1Ptr</td><td>is the first sampled time stamp. </td></tr>
+    <tr><td class="paramname">Stamp2Ptr</td><td>is the second sampled time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>0</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga4d013326acf8271a92f82d35fa0cf17d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_DELTA_US</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp1Ptr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp2Ptr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>This macro is not yet implemented and always returns 0. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Stamp1Ptr</td><td>is the first sampled time stamp. </td></tr>
+    <tr><td class="paramname">Stamp2Ptr</td><td>is the second sampled time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>0</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>This macro must be implemented by the user. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4d013326acf8271a92f82d35fa0cf17d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_DELTA_US</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp1Ptr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Stamp2Ptr&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p>This macro is not yet implemented and always returns 0. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Stamp1Ptr</td><td>is the first sampled time stamp. </td></tr>
+    <tr><td class="paramname">Stamp2Ptr</td><td>is the second sampled time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>0</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>This macro must be implemented by the user. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4521b4e8caafa3b7a77e3fd0f77ec4d1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_GET</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">StampPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__vxworks_8h.html">xenv_vxworks.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{                                                       \</div>
+<div class="line">    vxTimeBaseGet((UINT32*)&amp;(StampPtr)-&gt;TimeBaseUpper,  \</div>
+<div class="line">                  (UINT32*)&amp;(StampPtr)-&gt;TimeBaseLower); \</div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>Time is derived from the 64 bit PPC timebase register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">StampPtr</td><td>is the storage for the retrieved time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Signature: void <a class="el" href="group__common__v1__00__a.html#ga4521b4e8caafa3b7a77e3fd0f77ec4d1" title="Time is derived from the 64 bit PPC timebase register. ">XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ga21fae7ca3043fbd3f73cd6b761afa230"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_GET</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">StampPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>Time is derived from the 64 bit PPC timebase register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">StampPtr</td><td>is the storage for the retrieved time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Signature: void <a class="el" href="group__common__v1__00__a.html#ga21fae7ca3043fbd3f73cd6b761afa230" title="Time is derived from the 64 bit PPC timebase register. ">XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)</a> <br />
+<br />
+ This macro must be implemented by the user. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga21fae7ca3043fbd3f73cd6b761afa230"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_TIME_STAMP_GET</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">StampPtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p>Time is derived from the 64 bit PPC timebase register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">StampPtr</td><td>is the storage for the retrieved time stamp.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Signature: void <a class="el" href="group__common__v1__00__a.html#ga21fae7ca3043fbd3f73cd6b761afa230" title="Time is derived from the 64 bit PPC timebase register. ">XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)</a> <br />
+<br />
+ This macro must be implemented by the user. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga45edf2c1128d69e881f9c54d8dcd6a26"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_USLEEP</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">delay</td><td>)</td>
+          <td>&#160;&#160;&#160;sysUsDelay(delay)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__vxworks_8h.html">xenv_vxworks.h</a>&gt;</code></p>
+
+<p>Delay the specified number of microseconds. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">delay</td><td>Number of microseconds to delay.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga45edf2c1128d69e881f9c54d8dcd6a26"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_USLEEP</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">delay</td><td>)</td>
+          <td>&#160;&#160;&#160;udelay(delay)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>Delay the specified number of microseconds. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">delay</td><td>Number of microseconds to delay.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>XENV_USLEEP is deprecated. Use udelay() instead. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga45edf2c1128d69e881f9c54d8dcd6a26"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XENV_USLEEP</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">delay</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p><a class="el" href="group__common__v1__00__a.html#ga45edf2c1128d69e881f9c54d8dcd6a26" title="XENV_USLEEP(unsigned delay) ">XENV_USLEEP(unsigned delay)</a> </p>
+<p>Delay the specified number of microseconds. Not implemented without OS support.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">delay</td><td>Number of microseconds to delay.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7ba08d136437c7da95f6825b2e976632"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XNULL&#160;&#160;&#160;NULL</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>Xilinx NULL, TRUE and FALSE legacy support. </p>
+<p>Deprecated. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga733ac6be9c7e9571dcea62d2ce65522c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XUINT64_LSW</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">x</td><td>)</td>
+          <td>&#160;&#160;&#160;((x).Lower)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>Return the least significant half of the 64 bit data type. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">x</td><td>is the 64 bit word.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The lower 32 bits of the 64 bit word.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga88f27d6c408105d63266828613c6c3e1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XUINT64_MSW</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">x</td><td>)</td>
+          <td>&#160;&#160;&#160;((x).Upper)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>Return the most significant half of the 64 bit data type. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">x</td><td>is the 64 bit word.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The upper 32 bits of the 64 bit word.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga93cc310a1d400abb7e4658d96c09d568"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XUT_ALLMEMTESTS&#160;&#160;&#160;0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xutil_8h.html">xutil.h</a>&gt;</code></p>
+
+<p>See the detailed description of the subtests in the file description. </p>
+
+<p>Referenced by <a class="el" href="group__common__v1__00__a.html#ga5c11abd9381dbdec3f55a97b41323ddd">XUtil_MemoryTest16()</a>, <a class="el" href="group__common__v1__00__a.html#gab898ebdd11950907ac66e978d2bd8d92">XUtil_MemoryTest32()</a>, and <a class="el" href="group__common__v1__00__a.html#ga777417fa2028d84d0f03ebb3570ea90f">XUtil_MemoryTest8()</a>.</p>
+
+</div>
+</div>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="ga053f552434ac021c5a2fc1ad3f925fa1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef void(* XAssertCallback) (char *FilenamePtr, int LineNumber)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>This data type defines a callback to be invoked when an assert occurs. </p>
+<p>The callback is invoked only when asserts are enabled </p>
+
+</div>
+</div>
+<a class="anchor" id="gad6b7af47c3b5bda2a5aaa98a2cad22d7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef unsigned long <a class="el" href="group__common__v1__00__a.html#gad6b7af47c3b5bda2a5aaa98a2cad22d7">Xboolean</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>boolean (XTRUE or XFALSE) </p>
+
+</div>
+</div>
+<a class="anchor" id="gae13dfc6253d3809555cb87f1ac76737a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int <a class="el" href="struct_x_e_n_v___t_i_m_e___s_t_a_m_p.html">XENV_TIME_STAMP</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__linux_8h.html">xenv_linux.h</a>&gt;</code></p>
+
+<p>A structure that contains a time stamp used by other time stamp macros defined below. </p>
+<p>This structure is processor dependent. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae13dfc6253d3809555cb87f1ac76737a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int <a class="el" href="struct_x_e_n_v___t_i_m_e___s_t_a_m_p.html">XENV_TIME_STAMP</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xenv__standalone_8h.html">xenv_standalone.h</a>&gt;</code></p>
+
+<p>A structure that contains a time stamp used by other time stamp macros defined below. </p>
+<p>This structure is processor dependent. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga3183d2e387fcb39c5086e023208e7841"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef void(* XExceptionHandler) (void *InstancePtr)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>This data type defines an exception handler for a processor. </p>
+<p>The argument points to the instance of the component </p>
+
+</div>
+</div>
+<a class="anchor" id="gab167b68461f2aa3c5c2312e73a0ba707"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef float <a class="el" href="group__common__v1__00__a.html#gab167b68461f2aa3c5c2312e73a0ba707">Xfloat32</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>32-bit floating point </p>
+
+</div>
+</div>
+<a class="anchor" id="ga152feebbf7fef5a26e0c26660861ab03"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef double <a class="el" href="group__common__v1__00__a.html#ga152feebbf7fef5a26e0c26660861ab03">Xfloat64</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>64-bit double precision FP </p>
+
+</div>
+</div>
+<a class="anchor" id="ga58a139daf1005fea667059c07dca7baf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef short <a class="el" href="group__common__v1__00__a.html#ga58a139daf1005fea667059c07dca7baf">Xint16</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>signed 16-bit </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf205dab7b2384df48b578ad185cae2a7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef long <a class="el" href="group__common__v1__00__a.html#gaf205dab7b2384df48b578ad185cae2a7">Xint32</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>signed 32-bit </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa2faa8fec5a68d8a05c5cb4cda20f0a6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef char <a class="el" href="group__common__v1__00__a.html#gaa2faa8fec5a68d8a05c5cb4cda20f0a6">Xint8</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>signed 8-bit </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2dca38379f0b9c154e743cfc6a8b9368"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef void(* XInterruptHandler) (void *InstancePtr)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>This data type defines an interrupt handler for a device. </p>
+<p>The argument points to the instance of the component </p>
+
+</div>
+</div>
+<a class="anchor" id="gab3e1c2e36c65f517dcda4ee482eaa749"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef unsigned short <a class="el" href="group__common__v1__00__a.html#gab3e1c2e36c65f517dcda4ee482eaa749">Xuint16</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>unsigned 16-bit </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8cf3b6d075db16e3c6499d3aa39cea86"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef unsigned long <a class="el" href="group__common__v1__00__a.html#ga8cf3b6d075db16e3c6499d3aa39cea86">Xuint32</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>unsigned 32-bit </p>
+
+</div>
+</div>
+<a class="anchor" id="gad12ffdd1f3aefbaab9c3a2e372b53e88"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef unsigned char <a class="el" href="group__common__v1__00__a.html#gad12ffdd1f3aefbaab9c3a2e372b53e88">Xuint8</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>unsigned 8-bit </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga15bbfbbbf84cb3f772dbbf22f7b07b75"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAssert </td>
+          <td>(</td>
+          <td class="paramtype">char *&#160;</td>
+          <td class="paramname"><em>File</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Line</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8c.html">xbasic_types.c</a>&gt;</code></p>
+
+<p>Implements assert. </p>
+<p>Currently, it calls a user-defined callback function if one has been set. Then, it potentially enters an infinite loop depending on the value of the XWaitInAssert variable.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">File</td><td>is the name of the filename of the source </td></tr>
+    <tr><td class="paramname">Line</td><td>is the linenumber within File</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#ga70e19ad3b7f3f7facbe157e082614b83">XWaitInAssert</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6843e75f679abd8d57f070219aa86fa1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XAssertSetCallback </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group__common__v1__00__a.html#ga053f552434ac021c5a2fc1ad3f925fa1">XAssertCallback</a>&#160;</td>
+          <td class="paramname"><em>Routine</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8c.html">xbasic_types.c</a>&gt;</code></p>
+
+<p>Sets up a callback function to be invoked when an assert occurs. </p>
+<p>If there was already a callback installed, then it is replaced.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Routine</td><td>is the callback to be invoked when an assert is taken</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>This function has no effect if NDEBUG is set </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaaecaabeb8ae29619054af3e4a0d6f508"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XNullHandler </td>
+          <td>(</td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>NullParameter</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8c.html">xbasic_types.c</a>&gt;</code></p>
+
+<p>Null handler function. </p>
+<p>This follows the XInterruptHandler signature for interrupt handlers. It can be used to assign a null handler (a stub) to an interrupt controller vector table.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">NullParameter</td><td>is an arbitrary void pointer and not used.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga5c11abd9381dbdec3f55a97b41323ddd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XUtil_MemoryTest16 </td>
+          <td>(</td>
+          <td class="paramtype">u16 *&#160;</td>
+          <td class="paramname"><em>Addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Words</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>Pattern</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Subtest</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xutil_8h.html">xutil.h</a>&gt;</code></p>
+
+<p>Performs a destructive 16-bit wide memory test. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Addr</td><td>is a pointer to the region of memory to be tested. </td></tr>
+    <tr><td class="paramname">Words</td><td>is the length of the block. </td></tr>
+    <tr><td class="paramname">Pattern</td><td>is the constant used for the constant pattern test, if 0, 0xDEADBEEF is used. </td></tr>
+    <tr><td class="paramname">Subtest</td><td>is the test selected. See <a class="el" href="xutil_8h.html">xutil.h</a> for possible values.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<ul>
+<li>XST_MEMTEST_FAILED is returned for a failure</li>
+<li>XST_SUCCESS is returned for a pass</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Used for spaces where the address range of the region is smaller than the data width. If the memory range is greater than 2 ** width, the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a boundry of a power of two making it more difficult to detect addressing errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same problem. Ideally, if large blocks of memory are to be tested, break them up into smaller regions of memory to allow the test patterns used not to repeat over the region tested. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#gacb16a9ce84634175b8be6eb6320e5d40">XASSERT_NONVOID</a>, and <a class="el" href="group__common__v1__00__a.html#ga93cc310a1d400abb7e4658d96c09d568">XUT_ALLMEMTESTS</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab898ebdd11950907ac66e978d2bd8d92"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XUtil_MemoryTest32 </td>
+          <td>(</td>
+          <td class="paramtype">u32 *&#160;</td>
+          <td class="paramname"><em>Addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Words</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Pattern</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Subtest</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xutil_8h.html">xutil.h</a>&gt;</code></p>
+
+<p>Performs a destructive 32-bit wide memory test. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Addr</td><td>is a pointer to the region of memory to be tested. </td></tr>
+    <tr><td class="paramname">Words</td><td>is the length of the block. </td></tr>
+    <tr><td class="paramname">Pattern</td><td>is the constant used for the constant pattern test, if 0, 0xDEADBEEF is used. </td></tr>
+    <tr><td class="paramname">Subtest</td><td>is the test selected. See <a class="el" href="xutil_8h.html">xutil.h</a> for possible values.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<ul>
+<li>XST_MEMTEST_FAILED is returned for a failure</li>
+<li>XST_SUCCESS is returned for a pass</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Used for spaces where the address range of the region is smaller than the data width. If the memory range is greater than 2 ** width, the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a boundry of a power of two making it more difficult to detect addressing errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same problem. Ideally, if large blocks of memory are to be tested, break them up into smaller regions of memory to allow the test patterns used not to repeat over the region tested. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#gacb16a9ce84634175b8be6eb6320e5d40">XASSERT_NONVOID</a>, and <a class="el" href="group__common__v1__00__a.html#ga93cc310a1d400abb7e4658d96c09d568">XUT_ALLMEMTESTS</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga777417fa2028d84d0f03ebb3570ea90f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XUtil_MemoryTest8 </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&#160;</td>
+          <td class="paramname"><em>Addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Words</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Pattern</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Subtest</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xutil_8h.html">xutil.h</a>&gt;</code></p>
+
+<p>Performs a destructive 8-bit wide memory test. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">Addr</td><td>is a pointer to the region of memory to be tested. </td></tr>
+    <tr><td class="paramname">Words</td><td>is the length of the block. </td></tr>
+    <tr><td class="paramname">Pattern</td><td>is the constant used for the constant pattern test, if 0, 0xDEADBEEF is used. </td></tr>
+    <tr><td class="paramname">Subtest</td><td>is the test selected. See <a class="el" href="xutil_8h.html">xutil.h</a> for possible values.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<ul>
+<li>XST_MEMTEST_FAILED is returned for a failure</li>
+<li>XST_SUCCESS is returned for a pass</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Used for spaces where the address range of the region is smaller than the data width. If the memory range is greater than 2 ** width, the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a boundry of a power of two making it more difficult to detect addressing errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same problem. Ideally, if large blocks of memory are to be tested, break them up into smaller regions of memory to allow the test patterns used not to repeat over the region tested. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#gacb16a9ce84634175b8be6eb6320e5d40">XASSERT_NONVOID</a>, and <a class="el" href="group__common__v1__00__a.html#ga93cc310a1d400abb7e4658d96c09d568">XUT_ALLMEMTESTS</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab2a1a40f520ee3c62f829d0e20581503"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XVersion_Copy </td>
+          <td>(</td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>VersionPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xversion_8c.html">xversion.c</a>&gt;</code></p>
+
+<p>Copies the contents of a version to another version. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>points to the version which is the source of data for the copy operation. </td></tr>
+    <tr><td class="paramname">VersionPtr</td><td>points to another version which is the destination of the copy operation.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<p>None.</p>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>None. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#ga1c87fc9274e19272996a00cfc7444693">XASSERT_VOID</a>.</p>
+
+<p>Referenced by <a class="el" href="group__common__v1__00__a.html#gacc5446415b912932b8a428ca698094d5">XVersion_FromString()</a>, and <a class="el" href="group__common__v1__00__a.html#ga20bcd31ada05091e23633264cb63d33c">XVersion_ToString()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gacc5446415b912932b8a428ca698094d5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XVersion_FromString </td>
+          <td>(</td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&#160;</td>
+          <td class="paramname"><em>StringPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xversion_8c.html">xversion.c</a>&gt;</code></p>
+
+<p>Initializes a version from a null terminated string. </p>
+<p>Since the string may not be a format which is compatible with the version, an error could occur.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>points to the version which is to be initialized. </td></tr>
+    <tr><td class="paramname">StringPtr</td><td>points to a null terminated string which will be converted to a version. The format of the string must match the version string format which is X.YYX where X = 0 - 9, YY = 00 - 99, Z = a - z.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<p>A status, XST_SUCCESS, indicating the conversion was accomplished successfully, or XST_INVALID_VERSION indicating the version string format was not valid.</p>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>None. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#gacb16a9ce84634175b8be6eb6320e5d40">XASSERT_NONVOID</a>, and <a class="el" href="group__common__v1__00__a.html#gab2a1a40f520ee3c62f829d0e20581503">XVersion_Copy()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab85b0654f0b4b643640c57369ecd3bf2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XVersion_IsEqual </td>
+          <td>(</td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>VersionPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xversion_8c.html">xversion.c</a>&gt;</code></p>
+
+<p>Determines if two versions are equal. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>points to the first version to be compared. </td></tr>
+    <tr><td class="paramname">VersionPtr</td><td>points to a second version to be compared.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<p>TRUE if the versions are equal, FALSE otherwise.</p>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>None. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#gacb16a9ce84634175b8be6eb6320e5d40">XASSERT_NONVOID</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae2f714e79a99e457e5fb3bb2e1f7b23f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XVersion_Pack </td>
+          <td>(</td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u16 *&#160;</td>
+          <td class="paramname"><em>PackedVersionPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xversion_8c.html">xversion.c</a>&gt;</code></p>
+
+<p>Packs a version into the specified packed version. </p>
+<p>Versions are packed into the configuration ROM to reduce the amount storage.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>points to the version to pack. </td></tr>
+    <tr><td class="paramname">PackedVersionPtr</td><td>points to the packed version which will receive the new packed version.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<p>A status, XST_SUCCESS, indicating the packing was accomplished successfully, or an error, XST_INVALID_VERSION, indicating the specified input version was not valid such that the pack did not occur <br />
+<br />
+ The packed version pointed to by PackedVersionPtr is modified with the new packed version if the status indicates success.</p>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>None. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga20bcd31ada05091e23633264cb63d33c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XVersion_ToString </td>
+          <td>(</td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&#160;</td>
+          <td class="paramname"><em>StringPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xversion_8c.html">xversion.c</a>&gt;</code></p>
+
+<p>Converts a version to a null terminated string. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>points to the version to convert. </td></tr>
+    <tr><td class="paramname">StringPtr</td><td>points to the string which will be the result of the conversion. This does not need to point to a null terminated string as an input, but must point to storage which is an adequate amount to hold the result string.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<p>The null terminated string is inserted at the location pointed to by StringPtr if the status indicates success.</p>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>It is necessary for the caller to have already allocated the storage to contain the string. The amount of memory necessary for the string is specified in the version header file. </p>
+
+<p>References <a class="el" href="group__common__v1__00__a.html#ga1c87fc9274e19272996a00cfc7444693">XASSERT_VOID</a>, and <a class="el" href="group__common__v1__00__a.html#gab2a1a40f520ee3c62f829d0e20581503">XVersion_Copy()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga0f04afc32d43f30b3d20498f7387b868"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XVersion_UnPack </td>
+          <td>(</td>
+          <td class="paramtype">XVersion *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>PackedVersion</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xversion_8c.html">xversion.c</a>&gt;</code></p>
+
+<p>Unpacks a packed version into the specified version. </p>
+<p>Versions are packed into the configuration ROM to reduce the amount storage. A packed version is a binary format as oppossed to a non-packed version which is implemented as a string.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>points to the version to unpack the packed version into. </td></tr>
+    <tr><td class="paramname">PackedVersion</td><td>contains the packed version to unpack.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<h2 class="groupheader">Variable Documentation</h2>
+<a class="anchor" id="ga34f8bacc03ca6dfb9340c96cd449bb1c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned int XAssertStatus</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8c.html">xbasic_types.c</a>&gt;</code></p>
+
+<p>This variable allows testing to be done easier with asserts. </p>
+<p>An assert sets this variable such that a driver can evaluate this variable to determine if an assert occurred. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga34f8bacc03ca6dfb9340c96cd449bb1c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned int XAssertStatus</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8h.html">xbasic_types.h</a>&gt;</code></p>
+
+<p>This variable allows testing to be done easier with asserts. </p>
+<p>An assert sets this variable such that a driver can evaluate this variable to determine if an assert occurred. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga70e19ad3b7f3f7facbe157e082614b83"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XWaitInAssert = TRUE</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xbasic__types_8c.html">xbasic_types.c</a>&gt;</code></p>
+
+<p>This variable allows the assert functionality to be changed for testing such that it does not wait infinitely. </p>
+<p>Use the debugger to disable the waiting during testing of asserts. </p>
+
+<p>Referenced by <a class="el" href="group__common__v1__00__a.html#ga15bbfbbbf84cb3f772dbbf22f7b07b75">XAssert()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">common_v1_00_a
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">common_v1_00_a Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
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+</html>
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+/*!
+ * jQuery JavaScript Library v1.7.1
+ * http://jquery.com/
+ *
+ * Copyright 2011, John Resig
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * Includes Sizzle.js
+ * http://sizzlejs.com/
+ * Copyright 2011, The Dojo Foundation
+ * Released under the MIT, BSD, and GPL Licenses.
+ *
+ * Date: Mon Nov 21 21:11:03 2011 -0500
+ */
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bB==="number"){bB+=""}else{if(b.isArray(bB)){bB=b.map(bB,function(bC){return bC==null?"":bC+""})}}}e=b.valHooks[this.nodeName.toLowerCase()]||b.valHooks[this.type];if(!e||!("set" in e)||e.set(this,bB,"value")===L){this.value=bB}})}});b.extend({valHooks:{option:{get:function(e){var bv=e.attributes.value;return !bv||bv.specified?e.value:e.text}},select:{get:function(e){var bA,bv,bz,bx,by=e.selectedIndex,bB=[],bC=e.options,bw=e.type==="select-one";if(by<0){return null}bv=bw?by:0;bz=bw?by+1:bC.length;for(;bv<bz;bv++){bx=bC[bv];if(bx.selected&&(b.support.optDisabled?!bx.disabled:bx.getAttribute("disabled")===null)&&(!bx.parentNode.disabled||!b.nodeName(bx.parentNode,"optgroup"))){bA=b(bx).val();if(bw){return bA}bB.push(bA)}}if(bw&&!bB.length&&bC.length){return b(bC[by]).val()}return bB},set:function(bv,bw){var e=b.makeArray(bw);b(bv).find("option").each(function(){this.selected=b.inArray(b(this).val(),e)>=0});if(!e.length){bv.selectedIndex=-1}return e}}},attrFn:{val:true,css:true,html:true,text:true,data:true,width:true,height:true,offset:true},attr:function(bA,bx,bB,bz){var bw,e,by,bv=bA.nodeType;if(!bA||bv===3||bv===8||bv===2){return}if(bz&&bx in b.attrFn){return b(bA)[bx](bB)}if(typeof bA.getAttribute==="undefined"){return b.prop(bA,bx,bB)}by=bv!==1||!b.isXMLDoc(bA);if(by){bx=bx.toLowerCase();e=b.attrHooks[bx]||(ao.test(bx)?aY:be)}if(bB!==L){if(bB===null){b.removeAttr(bA,bx);return}else{if(e&&"set" in e&&by&&(bw=e.set(bA,bB,bx))!==L){return bw}else{bA.setAttribute(bx,""+bB);return bB}}}else{if(e&&"get" in e&&by&&(bw=e.get(bA,bx))!==null){return bw}else{bw=bA.getAttribute(bx);return bw===null?L:bw}}},removeAttr:function(bx,bz){var by,bA,bv,e,bw=0;if(bz&&bx.nodeType===1){bA=bz.toLowerCase().split(af);e=bA.length;for(;bw<e;bw++){bv=bA[bw];if(bv){by=b.propFix[bv]||bv;b.attr(bx,bv,"");bx.removeAttribute(F?bv:by);if(ao.test(bv)&&by in bx){bx[by]=false}}}}},attrHooks:{type:{set:function(e,bv){if(g.test(e.nodeName)&&e.parentNode){b.error("type property can't be changed")}else{if(!b.support.radioValue&&bv==="radio"&&b.nodeName(e,"input")){var bw=e.value;e.setAttribute("type",bv);if(bw){e.value=bw}return bv}}}},value:{get:function(bv,e){if(be&&b.nodeName(bv,"button")){return be.get(bv,e)}return e in bv?bv.value:null},set:function(bv,bw,e){if(be&&b.nodeName(bv,"button")){return be.set(bv,bw,e)}bv.value=bw}}},propFix:{tabindex:"tabIndex",readonly:"readOnly","for":"htmlFor","class":"className",maxlength:"maxLength",cellspacing:"cellSpacing",cellpadding:"cellPadding",rowspan:"rowSpan",colspan:"colSpan",usemap:"useMap",frameborder:"frameBorder",contenteditable:"contentEditable"},prop:function(bz,bx,bA){var bw,e,by,bv=bz.nodeType;if(!bz||bv===3||bv===8||bv===2){return}by=bv!==1||!b.isXMLDoc(bz);if(by){bx=b.propFix[bx]||bx;e=b.propHooks[bx]}if(bA!==L){if(e&&"set" in e&&(bw=e.set(bz,bA,bx))!==L){return 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e=bw.getAttributeNode(bv);if(!e){e=av.createAttribute(bv);bw.setAttributeNode(e)}return(e.nodeValue=bx+"")}};b.attrHooks.tabindex.set=be.set;b.each(["width","height"],function(bv,e){b.attrHooks[e]=b.extend(b.attrHooks[e],{set:function(bw,bx){if(bx===""){bw.setAttribute(e,"auto");return bx}}})});b.attrHooks.contenteditable={get:be.get,set:function(bv,bw,e){if(bw===""){bw="false"}be.set(bv,bw,e)}}}if(!b.support.hrefNormalized){b.each(["href","src","width","height"],function(bv,e){b.attrHooks[e]=b.extend(b.attrHooks[e],{get:function(bx){var bw=bx.getAttribute(e,2);return bw===null?L:bw}})})}if(!b.support.style){b.attrHooks.style={get:function(e){return e.style.cssText.toLowerCase()||L},set:function(e,bv){return(e.style.cssText=""+bv)}}}if(!b.support.optSelected){b.propHooks.selected=b.extend(b.propHooks.selected,{get:function(bv){var e=bv.parentNode;if(e){e.selectedIndex;if(e.parentNode){e.parentNode.selectedIndex}}return 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bw){b.event.remove(bJ,bz+bE[bF],bv,bH,true)}continue}by=b.event.special[bz]||{};bz=(bH?by.delegateType:by.bindType)||bz;bD=bw[bz]||[];bA=bD.length;bC=bC?new RegExp("(^|\\.)"+bC.split(".").sort().join("\\.(?:.*\\.)?")+"(\\.|$)"):null;for(bG=0;bG<bD.length;bG++){e=bD[bG];if((bB||bL===e.origType)&&(!bv||bv.guid===e.guid)&&(!bC||bC.test(e.namespace))&&(!bH||bH===e.selector||bH==="**"&&e.selector)){bD.splice(bG--,1);if(e.selector){bD.delegateCount--}if(by.remove){by.remove.call(bJ,e)}}}if(bD.length===0&&bA!==bD.length){if(!by.teardown||by.teardown.call(bJ,bC)===false){b.removeEvent(bJ,bz,bI.handle)}delete bw[bz]}}if(b.isEmptyObject(bw)){bK=bI.handle;if(bK){bK.elem=null}b.removeData(bJ,["events","handle"],true)}},customEvent:{getData:true,setData:true,changeData:true},trigger:function(bv,bD,bA,bJ){if(bA&&(bA.nodeType===3||bA.nodeType===8)){return}var bG=bv.type||bv,bx=[],e,bw,bC,bH,bz,by,bF,bE,bB,bI;if(T.test(bG+b.event.triggered)){return}if(bG.indexOf("!")>=0){bG=bG.slice(0,-1);bw=true}if(bG.indexOf(".")>=0){bx=bG.split(".");bG=bx.shift();bx.sort()}if((!bA||b.event.customEvent[bG])&&!b.event.global[bG]){return}bv=typeof bv==="object"?bv[b.expando]?bv:new b.Event(bG,bv):new b.Event(bG);bv.type=bG;bv.isTrigger=true;bv.exclusive=bw;bv.namespace=bx.join(".");bv.namespace_re=bv.namespace?new RegExp("(^|\\.)"+bx.join("\\.(?:.*\\.)?")+"(\\.|$)"):null;by=bG.indexOf(":")<0?"on"+bG:"";if(!bA){e=b.cache;for(bC in e){if(e[bC].events&&e[bC].events[bG]){b.event.trigger(bv,bD,e[bC].handle.elem,true)}}return}bv.result=L;if(!bv.target){bv.target=bA}bD=bD!=null?b.makeArray(bD):[];bD.unshift(bv);bF=b.event.special[bG]||{};if(bF.trigger&&bF.trigger.apply(bA,bD)===false){return}bB=[[bA,bF.bindType||bG]];if(!bJ&&!bF.noBubble&&!b.isWindow(bA)){bI=bF.delegateType||bG;bH=T.test(bI+bG)?bA:bA.parentNode;bz=null;for(;bH;bH=bH.parentNode){bB.push([bH,bI]);bz=bH}if(bz&&bz===bA.ownerDocument){bB.push([bz.defaultView||bz.parentWindow||bb,bI])}}for(bC=0;bC<bB.length&&!bv.isPropagationStopped();bC++){bH=bB[bC][0];bv.type=bB[bC][1];bE=(b._data(bH,"events")||{})[bv.type]&&b._data(bH,"handle");if(bE){bE.apply(bH,bD)}bE=by&&bH[by];if(bE&&b.acceptData(bH)&&bE.apply(bH,bD)===false){bv.preventDefault()}}bv.type=bG;if(!bJ&&!bv.isDefaultPrevented()){if((!bF._default||bF._default.apply(bA.ownerDocument,bD)===false)&&!(bG==="click"&&b.nodeName(bA,"a"))&&b.acceptData(bA)){if(by&&bA[bG]&&((bG!=="focus"&&bG!=="blur")||bv.target.offsetWidth!==0)&&!b.isWindow(bA)){bz=bA[by];if(bz){bA[by]=null}b.event.triggered=bG;bA[bG]();b.event.triggered=L;if(bz){bA[by]=bz}}}}return bv.result},dispatch:function(e){e=b.event.fix(e||bb.event);var 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+/*!
+ * Sizzle CSS Selector Engine
+ *  Copyright 2011, The Dojo Foundation
+ *  Released under the MIT, BSD, and GPL Licenses.
+ *  More information: http://sizzlejs.com/
+ */
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bw=e.offsetTop,bv=e.offsetLeft;if(b.support.doesNotIncludeMarginInBodyOffset){bw+=parseFloat(b.css(e,"marginTop"))||0;bv+=parseFloat(b.css(e,"marginLeft"))||0}return{top:bw,left:bv}},setOffset:function(bx,bG,bA){var bB=b.css(bx,"position");if(bB==="static"){bx.style.position="relative"}var bz=b(bx),bv=bz.offset(),e=b.css(bx,"top"),bE=b.css(bx,"left"),bF=(bB==="absolute"||bB==="fixed")&&b.inArray("auto",[e,bE])>-1,bD={},bC={},bw,by;if(bF){bC=bz.position();bw=bC.top;by=bC.left}else{bw=parseFloat(e)||0;by=parseFloat(bE)||0}if(b.isFunction(bG)){bG=bG.call(bx,bA,bv)}if(bG.top!=null){bD.top=(bG.top-bv.top)+bw}if(bG.left!=null){bD.left=(bG.left-bv.left)+by}if("using" in bG){bG.using.call(bx,bD)}else{bz.css(bD)}}};b.fn.extend({position:function(){if(!this[0]){return null}var bw=this[0],bv=this.offsetParent(),bx=this.offset(),e=ad.test(bv[0].nodeName)?{top:0,left:0}:bv.offset();bx.top-=parseFloat(b.css(bw,"marginTop"))||0;bx.left-=parseFloat(b.css(bw,"marginLeft"))||0;e.top+=parseFloat(b.css(bv[0],"borderTopWidth"))||0;e.left+=parseFloat(b.css(bv[0],"borderLeftWidth"))||0;return{top:bx.top-e.top,left:bx.left-e.left}},offsetParent:function(){return this.map(function(){var e=this.offsetParent||av.body;while(e&&(!ad.test(e.nodeName)&&b.css(e,"position")==="static")){e=e.offsetParent}return e})}});b.each(["Left","Top"],function(bv,e){var bw="scroll"+e;b.fn[bw]=function(bz){var bx,by;if(bz===L){bx=this[0];if(!bx){return null}by=aK(bx);return by?("pageXOffset" in by)?by[bv?"pageYOffset":"pageXOffset"]:b.support.boxModel&&by.document.documentElement[bw]||by.document.body[bw]:bx[bw]}return this.each(function(){by=aK(this);if(by){by.scrollTo(!bv?bz:b(by).scrollLeft(),bv?bz:b(by).scrollTop())}else{this[bw]=bz}})}});function aK(e){return b.isWindow(e)?e:e.nodeType===9?e.defaultView||e.parentWindow:false}b.each(["Height","Width"],function(bv,e){var bw=e.toLowerCase();b.fn["inner"+e]=function(){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,"padding")):this[bw]():null};b.fn["outer"+e]=function(by){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,by?"margin":"border")):this[bw]():null};b.fn[bw]=function(bz){var bA=this[0];if(!bA){return bz==null?null:this}if(b.isFunction(bz)){return this.each(function(bE){var bD=b(this);bD[bw](bz.call(this,bE,bD[bw]()))})}if(b.isWindow(bA)){var bB=bA.document.documentElement["client"+e],bx=bA.document.body;return bA.document.compatMode==="CSS1Compat"&&bB||bx&&bx["client"+e]||bB}else{if(bA.nodeType===9){return Math.max(bA.documentElement["client"+e],bA.body["scroll"+e],bA.documentElement["scroll"+e],bA.body["offset"+e],bA.documentElement["offset"+e])}else{if(bz===L){var bC=b.css(bA,bw),by=parseFloat(bC);return b.isNumeric(by)?by:bC}else{return this.css(bw,typeof bz==="string"?bz:bz+"px")}}}}});bb.jQuery=bb.$=b;if(typeof define==="function"&&define.amd&&define.amd.jQuery){define("jquery",[],function(){return b})}})(window);/*!
+ * jQuery UI 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI
+ */
+(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:"1.8.18",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e==="number"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css("overflow")==="hidden"){return false}var e=(f&&f==="left")?"scrollLeft":"scrollTop",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!
+ * jQuery UI Widget 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Widget
+ */
+(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!
+ * jQuery UI Mouse 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Mouse
+ *
+ * Depends:
+ *	jquery.ui.widget.js
+ */
+(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e=="sw"){h.left=j.left+(f.width-h.width);h.top=null}if(e=="nw"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css("borderTopWidth"),h.css("borderRightWidth"),h.css("borderBottomWidth"),h.css("borderLeftWidth")],j=[h.css("paddingTop"),h.css("paddingRight"),h.css("paddingBottom"),h.css("paddingLeft")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(":hidden")||c(g).parents(":hidden").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var o={width:parseInt(p.element.css("width"),10),height:parseInt(p.element.css("height"),10),top:parseInt(p.element.css("top"),10),left:parseInt(p.element.css("left"),10)};if(h&&h.length){c(h[0]).css({width:o.width,height:o.height})}p._updateCache(o);p._propagate("resize",i)}})}});c.ui.plugin.add("resizable","containment",{start:function(f,r){var t=c(this).data("resizable"),j=t.options,l=t.element;var g=j.containment,k=(g instanceof c)?g.get(0):(/parent/.test(g))?l.parent().get(0):g;if(!k){return}t.containerElement=c(k);if(/document/.test(g)||g==document){t.containerOffset={left:0,top:0};t.containerPosition={left:0,top:0};t.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var n=c(k),i=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){i[p]=b(n.css("padding"+o))});t.containerOffset=n.offset();t.containerPosition=n.position();t.containerSize={height:(n.innerHeight()-i[3]),width:(n.innerWidth()-i[1])};var q=t.containerOffset,e=t.containerSize.height,m=t.containerSize.width,h=(c.ui.hasScroll(k,"left")?k.scrollWidth:m),s=(c.ui.hasScroll(k)?k.scrollHeight:e);t.parentData={element:k,left:q.left,top:q.top,width:h,height:s}}},resize:function(g,q){var t=c(this).data("resizable"),i=t.options,f=t.containerSize,p=t.containerOffset,m=t.size,n=t.position,r=t._aspectRatio||g.shiftKey,e={top:0,left:0},h=t.containerElement;if(h[0]!=document&&(/static/).test(h.css("position"))){e=p}if(n.left<(t._helper?p.left:0)){t.size.width=t.size.width+(t._helper?(t.position.left-p.left):(t.position.left-e.left));if(r){t.size.height=t.size.width/i.aspectRatio}t.position.left=i.helper?p.left:0}if(n.top<(t._helper?p.top:0)){t.size.height=t.size.height+(t._helper?(t.position.top-p.top):t.position.top);if(r){t.size.width=t.size.height*i.aspectRatio}t.position.top=t._helper?p.top:0}t.offset.left=t.parentData.left+t.position.left;t.offset.top=t.parentData.top+t.position.top;var l=Math.abs((t._helper?t.offset.left-e.left:(t.offset.left-e.left))+t.sizeDiff.width),s=Math.abs((t._helper?t.offset.top-e.top:(t.offset.top-p.top))+t.sizeDiff.height);var k=t.containerElement.get(0)==t.element.parent().get(0),j=/relative|absolute/.test(t.containerElement.css("position"));if(k&&j){l-=t.parentData.left}if(l+t.size.width>=t.parentData.width){t.size.width=t.parentData.width-l;if(r){t.size.height=t.size.width/t.aspectRatio}}if(s+t.size.height>=t.parentData.height){t.size.height=t.parentData.height-s;if(r){t.size.width=t.size.height*t.aspectRatio}}},stop:function(f,n){var q=c(this).data("resizable"),g=q.options,l=q.position,m=q.containerOffset,e=q.containerPosition,i=q.containerElement;var j=c(q.helper),r=j.offset(),p=j.outerWidth()-q.sizeDiff.width,k=j.outerHeight()-q.sizeDiff.height;if(q._helper&&!g.animate&&(/relative/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}if(q._helper&&!g.animate&&(/static/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}}});c.ui.plugin.add("resizable","ghost",{start:function(g,h){var e=c(this).data("resizable"),i=e.options,f=e.size;e.ghost=e.originalElement.clone();e.ghost.css({opacity:0.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof i.ghost=="string"?i.ghost:"");e.ghost.appendTo(e.helper)},resize:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost){e.ghost.css({position:"relative",height:e.size.height,width:e.size.width})}},stop:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost&&e.helper){e.helper.get(0).removeChild(e.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(e,m){var p=c(this).data("resizable"),h=p.options,k=p.size,i=p.originalSize,j=p.originalPosition,n=p.axis,l=h._aspectRatio||e.shiftKey;h.grid=typeof h.grid=="number"?[h.grid,h.grid]:h.grid;var g=Math.round((k.width-i.width)/(h.grid[0]||1))*(h.grid[0]||1),f=Math.round((k.height-i.height)/(h.grid[1]||1))*(h.grid[1]||1);if(/^(se|s|e)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f}else{if(/^(ne)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f;p.position.top=j.top-f}else{if(/^(sw)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f;p.position.left=j.left-g}else{p.size.width=i.width+g;p.size.height=i.height+f;p.position.top=j.top-f;p.position.left=j.left-g}}}}});var b=function(e){return parseInt(e,10)||0};var a=function(e){return !isNaN(parseInt(e,10))}})(jQuery);/*!
+ * jQuery hashchange event - v1.3 - 7/21/2010
+ * http://benalman.com/projects/jquery-hashchange-plugin/
+ * 
+ * Copyright (c) 2010 "Cowboy" Ben Alman
+ * Dual licensed under the MIT and GPL licenses.
+ * http://benalman.com/about/license/
+ */
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">APIs</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__common__v1__00__a.html" target="_self">Common_v1_00_a</a></td><td class="desc">This file contains basic functions for Xilinx software IP </td></tr>
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+</html>
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+<title>common_v1_00_a: XENV_TIME_STAMP Struct Reference</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+  <div id="navrow2" class="tabs2">
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XENV_TIME_STAMP Struct Reference<div class="ingroups"><a class="el" href="group__common__v1__00__a.html">Common_v1_00_a</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/Makefile
@@ -0,0 +1,28 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o 
+
+LIBSOURCES=*.c
+INCLUDEFILES=xbasic_types.h xenv.h xenv_none.h xenv_standalone.h xenv_vxworks.h xstatus.h xutil.h xversion.h xdebug.h
+
+libs:
+	echo "Compiling common"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf $(OUTS)
+
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xbasic_types.c b/thirdparty/xilinx/orig/common_v1_00_a/src/xbasic_types.c
new file mode 100644
index 000000000..e371e4c10
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xbasic_types.c
@@ -0,0 +1,150 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.c
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains basic functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a bss  13/01/12 Removed a compiler warning in XNullHandler;
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+unsigned int XAssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+int XWaitInAssert = TRUE;
+
+/* The callback function to be invoked when an assert is taken */
+static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implements assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the XWaitInAssert variable.
+*
+* @param    File is the name of the filename of the source
+* @param    Line is the linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XAssert(char *File, int Line)
+{
+	/* if the callback has been set then invoke it */
+	if (XAssertCallbackRoutine != NULL) {
+		(*XAssertCallbackRoutine) (File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (XWaitInAssert) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    Routine is the callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void XAssertSetCallback(XAssertCallback Routine)
+{
+	XAssertCallbackRoutine = Routine;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void) NullParameter;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xbasic_types.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xbasic_types.h
new file mode 100644
index 000000000..7213c7bcc
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xbasic_types.h
@@ -0,0 +1,315 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains basic types for Xilinx software IP.  These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*       rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*                     compiler warnings
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* 1.00a rpm  07/21/04 Added XExceptionHandler typedef for processor exceptions
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a wre  01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE
+* 1.00a rpm  04/02/07 Added ifndef KERNEL around u32, u16, u8 data types
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1
+#endif
+
+#ifndef FALSE
+#  define FALSE		0
+#endif
+
+#ifndef NULL
+#define NULL		0
+#endif
+
+/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+
+#define XCOMPONENT_IS_READY     0x11111111  /**< component has been initialized */
+#define XCOMPONENT_IS_STARTED   0x22222222  /**< component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED    0
+#define XTEST_FAILED    1
+
+#define XASSERT_NONE     0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+#include <stdint.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t		Xuint8;		/**< unsigned 8-bit */
+typedef int8_t		Xint8;		/**< signed 8-bit */
+typedef uint16_t	Xuint16;	/**< unsigned 16-bit */
+typedef int16_t		Xint16;		/**< signed 16-bit */
+typedef uint32_t	Xuint32;	/**< unsigned 32-bit */
+typedef int32_t		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the XWaitInAssert variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression)                   \
+{                                                  \
+    if (expression)                                \
+    {                                              \
+        XAssertStatus = XASSERT_NONE;              \
+    }                                              \
+    else                                           \
+    {                                              \
+        XAssert(__FILE__, __LINE__);               \
+                XAssertStatus = XASSERT_OCCURRED;  \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the XWaitInAssert variable is true, in which case
+*           no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression)                \
+{                                                  \
+    if (expression)                                \
+    {                                              \
+        XAssertStatus = XASSERT_NONE;              \
+    }                                              \
+    else                                           \
+    {                                              \
+        XAssert(__FILE__, __LINE__);               \
+                XAssertStatus = XASSERT_OCCURRED;  \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+*         no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS()                      \
+{                                                  \
+   XAssert(__FILE__, __LINE__);                    \
+           XAssertStatus = XASSERT_OCCURRED;       \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+*         no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS()                   \
+{                                                  \
+   XAssert(__FILE__, __LINE__);                    \
+           XAssertStatus = XASSERT_OCCURRED;       \
+   return 0;                                       \
+}
+
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+void XNullHandler(void *NullParameter);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xenv.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv.h
new file mode 100644
index 000000000..54d24f476
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_linux.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_linux.h
new file mode 100644
index 000000000..e1edc618a
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_linux.h
@@ -0,0 +1,255 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_linux.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a ch   10/24/02 First release
+* 1.10a wgr  03/22/07 Converted to new coding style.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_LINUX_H
+#define XENV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include <asm/cache.h>
+#include <asm/cacheflush.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * Those macros are defined to catch legacy code in Xilinx drivers. The
+ * XENV_MEM_COPY and XENV_MEM_FILL macros were used in early Xilinx driver
+ * code. They are being replaced by memcpy() and memset() function calls. These
+ * macros are defined to catch any remaining occurences of those macros.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+		memcpy(DestPtr, SrcPtr, Bytes)
+/*		do_not_use_XENV_MEM_COPY_use_memcpy_instead */
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+		memset(DestPtr, Data, Bytes)
+/*		do_not_use_XENV_MEM_FILL_use_memset_instead */
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ * @note	XENV_USLEEP is deprecated. Use udelay() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_USLEEP(delay)	udelay(delay)
+/*		do_not_use_XENV_MEM_COPY_use_memcpy_instead */
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ * The implementation of the cache handling functions can be found in
+ * arch/microblaze.
+ *
+ * These #defines are simple mappings to the Linux API.
+ *
+ * The underlying Linux implementation will take care of taking the right
+ * actions depending on the configuration of the MicroBlaze processor in the
+ * system.
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_DCACHE()		__enable_dcache()
+#define XCACHE_DISABLE_DCACHE()		__disable_dcache()
+#define XCACHE_ENABLE_ICACHE()		__enable_icache()
+#define XCACHE_DISABLE_ICACHE()		__disable_icache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) invalidate_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)      flush_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
+
+#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) "XCACHE_INVALIDATE_ICACHE_RANGE unsupported"
+#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len)      flush_icache_range(Addr, Len)
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_none.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_none.h
new file mode 100644
index 000000000..e0ff47a01
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_none.h
@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_none.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This is a legacy file kept for backwards compatibility.
+*
+* Please modify your code to #include "xenv_standalone.h" instead.
+*
+*
+******************************************************************************/
+
+#warning ********************************************************************
+#warning *
+#warning * Use of xenv_none.h deprecated.
+#warning * Please include the new xenv_standalone.h file instead.
+#warning *
+#warning ********************************************************************
+
+#include "xenv_standalone.h"
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_standalone.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_standalone.h
new file mode 100644
index 000000000..14a83b05c
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_standalone.h
@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((int)(Addr), (int)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_vxworks.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_vxworks.h
new file mode 100644
index 000000000..1254a6bdc
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xenv_vxworks.h
@@ -0,0 +1,272 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_vxworks.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+*       rmm  09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL
+*       rmm  10/24/02 Added XENV_USLEEP macro
+* 1.00a rmm  07/16/01 First release
+* 1.10a wgr  03/22/07 Converted to new coding style.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_VXWORKS_H
+#define XENV_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+#include <string.h>
+
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note	XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note	XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+#if (CPU_FAMILY==PPC)
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef struct
+{
+	u32 TimeBaseUpper;
+	u32 TimeBaseLower;
+} XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)                   \
+{                                                       \
+    vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper,  \
+                  (UINT32*)&(StampPtr)->TimeBaseLower); \
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note    None.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * None.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+
+/* For non-PPC systems the above macros are not defined. Generate a error to
+ * make the developer aware of the problem.
+ */
+#else
+#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting."
+#endif
+
+
+/*****************************************************************************/
+/**
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_USLEEP(delay)	sysUsDelay(delay)
+
+#define udelay(delay)	sysUsDelay(delay)
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ ******************************************************************************/
+
+#if (CPU_FAMILY==PPC)
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+#define XCACHE_ENABLE_DCACHE()		cacheEnable(DATA_CACHE)
+#define XCACHE_DISABLE_DCACHE()		cacheDisable(DATA_CACHE)
+#define XCACHE_ENABLE_ICACHE()		cacheEnable(INSTRUCTION_CACHE)
+#define XCACHE_DISABLE_ICACHE()		cacheDisable(INSTRUCTION_CACHE)
+
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \
+		cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifdef XENV_VXWORKS_H */
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xparameters.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xparameters.h
new file mode 100644
index 000000000..5fb911eae
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xparameters.h
@@ -0,0 +1,731 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xparameters.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains system parameters for the Xilinx device driver environment.
+* It is a representation of the system in that it contains the number of each
+* device in the system as well as the parameters and memory map for each
+* device.  The user can view this file to obtain a summary of the devices in
+* their system and the device parameters.
+*
+* This file may be automatically generated by a design tool such as System
+* Generator.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#ifndef XPARAMETERS_H    /* prevent circular inclusions */
+#define XPARAMETERS_H    /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* unifying driver changes
+
+added XPAR_INTC_0_ACK_BEFORE, XPAR_INTC_1_ACK_BEFORE
+changed XPAR_INTC_MAX_ID to XPAR_INTC_MAX_NUM_INTR_INPUTS
+deleted XPAR_INTC_0_MAX_ID, XPAR_INTC_1_MAX_ID
+
+*/
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants are for each device.
+ *
+ * An instance must exist for each physical device that exists in the system.
+ * The device IDs in the following constants are unique between all devices to
+ * allow device IDs to be searched in the future.
+ */
+
+/*****************************************************************************
+ *
+ * System Level defines. These constants are for devices that do not require
+ * a device driver. Examples of these types of devices include volatile RAM
+ * devices.
+ */
+#define XPAR_ZBT_NUM_INSTANCES   1
+#define XPAR_ZBT_0_BASE          0x00000000
+#define XPAR_ZBT_0_SIZE          0x00100000
+
+#define XPAR_SRAM_NUM_INSTANCES  1
+#define XPAR_SRAM_0_BASE         0x00100000
+#define XPAR_SRAM_0_SIZE         0x00200000
+
+#define XPAR_DDR_NUM_INSTANCES   1
+#define XPAR_DDR_0_BASE          0xF0000000
+#define XPAR_DDR_0_SIZE          0x01000000
+
+#define XPAR_CORE_CLOCK_FREQ_HZ  12500000
+
+#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ  XPAR_CORE_CLOCK_FREQ_HZ
+
+/*****************************************************************************
+ *
+ * Interrupt Controller (Intc) defines.
+ * DeviceID starts at 0
+ */
+#define XPAR_XINTC_NUM_INSTANCES      2          /* Number of instances */
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 31         /* max # inputs of all */
+#define XPAR_INTC_SINGLE_BASEADDR     0x70800000 /* low level driver base */
+#define XPAR_INTC_SINGLE_DEVICE_ID    0          /* single instance ID */
+#define XPAR_INTC_SINGLE_ACK_BEFORE   0xFFFF00FF /* low level driver */
+
+#define XPAR_INTC_0_DEVICE_ID         1          /* Device ID for instance */
+#define XPAR_INTC_0_ACK_BEFORE        0xFFFF00FF /* Ack timing, before/after */
+#define XPAR_INTC_0_BASEADDR          0x70800000 /* Register base address */
+
+#define XPAR_INTC_0_UARTLITE_0_VEC_ID  4     /* Interrupt source for vector */
+#define XPAR_INTC_0_WDTTB_0_VEC_ID     5     /* Interrupt source for vector */
+#define XPAR_INTC_0_WD_0_VEC_ID        6     /* Interrupt source for vector */
+#define XPAR_INTC_0_TMRCTR_0_VEC_ID    7     /* Interrupt source for vector */
+#define XPAR_INTC_0_SPI_0_VEC_ID       11    /* Interrupt source for vector */
+#define XPAR_INTC_0_IIC_0_VEC_ID       12    /* Interrupt source for vector */
+#define XPAR_INTC_0_UARTNS550_0_VEC_ID 13    /* Interrupt source for vector */
+#define XPAR_INTC_0_UARTNS550_1_VEC_ID 14    /* Interrupt source for vector */
+#define XPAR_INTC_0_EMAC_0_VEC_ID      15    /* Interrupt source for vector */
+
+#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID 16 /* Intr ID for AXIDMA rx */
+#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID 17 /* Intr ID for AXIDMA tx */
+
+#define XPAR_INTC_0_AXICDMA_0_VEC_ID   18    /* Intr ID for AXICDMA */
+
+#define XPAR_INTC_0_AXIVDMA_0_S2MM_INTROUT_VEC_ID  19 /* AXIVDMA write intr */
+#define XPAR_INTC_0_AXIVDMA_0_MM2S_INTROUT_VEC_ID  20 /* AXIVDMA read intr */
+
+#define XPAR_INTC_1_DEVICE_ID          2     /* Device ID for instance */
+#define XPAR_INTC_1_ACK_BEFORE        0xFFFF00FF /* Ack timing, before/after */
+#define XPAR_INTC_1_BASEADDR          0x70800020 /* Register base address */
+
+#define XPAR_INTC_1_OPB_TO_PLB_ERR_VEC_ID 0  /* Interrupt source for vector */
+#define XPAR_INTC_1_PLB_TO_OPB_ERR_VEC_ID 1  /* Interrupt source for vector */
+
+/*****************************************************************************
+ *
+ * AXI DMA defines
+ */
+
+#define XPAR_XAXIDMA_NUM_INSTANCES 1
+
+#define XPAR_AXI_DMA_0_DEVICE_ID 0
+#define XPAR_AXI_DMA_0_BASEADDR 0x40000000
+#define XPAR_AXI_DMA_0_HIGHADDR 0x4000007F
+#define XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM 1
+#define XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE 1
+#define XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE 1
+#define XPAR_AXI_DMA_0_INCLUDE_MM2S 1
+#define XPAR_AXI_DMA_0_INCLUDE_S2MM 1
+#define XPAR_AXI_DMA_0_M_AXIS_MM2S_DATA_WIDTH 32
+#define XPAR_AXI_DMA_0_S_AXIS_S2MM_DATA_WIDTH 32
+
+/*****************************************************************************
+ *
+ * AXI Central DMA defines
+ */
+
+#define XPAR_XAXICDMA_NUM_INSTANCES 1
+
+#define XPAR_AXI_CDMA_0_DEVICE_ID 0
+#define XPAR_AXI_CDMA_0_BASEADDR 0x40001000
+#define XPAR_AXI_CDMA_0_HIGHADDR 0x4000107F
+#define XPAR_AXI_CDMA_0_INCLUDE_DRE 1
+#define XPAR_AXI_CDMA_0_USE_DATAMOVER_LITE 0
+#define XPAR_AXI_CDMA_0_M_AXI_DATA_WIDTH 32
+
+/*****************************************************************************
+ *
+ * AXI Video DMA defines
+ */
+#define XPAR_XAXIVDMA_NUM_INSTANCES 1
+
+#define XPAR_AXI_VDMA_0_DEVICE_ID 0
+#define XPAR_AXI_VDMA_0_BASEADDR  0x40002000
+#define XPAR_AXI_VDMA_0_NUM_FSTORES 16
+#define XPAR_AXI_VDMA_0_INCLUDE_MM2S 1
+#define XPAR_AXI_VDMA_0_INCLUDE_MM2S_DRE 1
+#define XPAR_AXI_VDMA_0_M_AXIS_MM2S_DATA_WIDTH 32
+#define	XPAR_AXI_VDMA_0_INCLUDE_S2MM 1
+#define XPAR_AXI_VDMA_0_INCLUDE_S2MM_DRE 1
+#define XPAR_AXI_VDMA_0_S_AXIS_S2MM_DATA_WIDTH 32
+
+/*****************************************************************************
+ *
+ * Ethernet 10/100 MAC defines.
+ * DeviceID starts at 10
+ */
+#define XPAR_XEMAC_NUM_INSTANCES     1          /* Number of instances */
+
+#define XPAR_EMAC_0_DEVICE_ID        10        /* Device ID for instance */
+#define XPAR_EMAC_0_BASEADDR         0x60000000/* Device base address */
+#define XPAR_EMAC_0_DMA_PRESENT      FALSE     /* Does device have DMA? */
+#define XPAR_EMAC_0_ERR_COUNT_EXIST  TRUE      /* Does device have counters? */
+#define XPAR_EMAC_0_MII_EXIST        TRUE      /* Does device support MII? */
+
+/*****************************************************************************
+ *
+ * NS16550 UART defines.
+ * DeviceID starts at 20
+ */
+#define XPAR_XUARTNS550_NUM_INSTANCES 1         /* Number of instances */
+
+#define XPAR_UARTNS550_0_DEVICE_ID   20         /* Device ID for instance */
+#define XPAR_UARTNS550_0_BASEADDR    0xA0010000 /* IPIF base address */
+#define XPAR_UARTNS550_0_CLOCK_HZ    (66000000L)/* 66 MHz clock */
+
+#define XPAR_UARTNS550_1_DEVICE_ID   21         /* Device ID for instance */
+#define XPAR_UARTNS550_1_BASEADDR    0xA0000000 /* IPIF base address */
+#define XPAR_UARTNS550_1_CLOCK_HZ    (66000000L)/* 66 MHz clock */
+
+/*****************************************************************************
+ *
+ * UartLite defines.
+ * DeviceID starts at 30
+ */
+#define XPAR_XUARTLITE_NUM_INSTANCES 1         /* Number of instances */
+
+#define XPAR_UARTLITE_0_DEVICE_ID   30         /* Device ID for instance */
+#define XPAR_UARTLITE_0_BASEADDR    0xA0020000 /* Device base address */
+#define XPAR_UARTLITE_0_BAUDRATE    19200      /* Baud rate */
+#define XPAR_UARTLITE_0_USE_PARITY  FALSE      /* Parity generator enabled */
+#define XPAR_UARTLITE_0_ODD_PARITY  FALSE      /* Type of parity generated */
+#define XPAR_UARTLITE_0_DATA_BITS   8          /* Data bits */
+
+/*****************************************************************************
+ *
+ * ATM controller defines.
+ * DeviceID starts at 40
+ */
+#define XPAR_XATMC_NUM_INSTANCES    1          /* Number of instances */
+
+#define XPAR_ATMC_0_DEVICE_ID       40         /* Device ID for instance */
+#define XPAR_ATMC_0_BASEADDR        0x70000000 /* Device base address */
+#define XPAR_ATMC_0_DMA_PRESENT     FALSE      /* Does device have DMA? */
+
+/*****************************************************************************
+ *
+ * Serial Peripheral Interface (SPI) defines.
+ * DeviceID starts at 50
+ */
+#define XPAR_XSPI_NUM_INSTANCES      2         /* Number of instances */
+
+#define XPAR_SPI_0_DEVICE_ID        50         /* Device ID for instance */
+#define XPAR_SPI_0_BASEADDR         0x50000000 /* Device base address */
+#define XPAR_SPI_0_FIFO_EXIST       TRUE       /* Does device have FIFOs? */
+#define XPAR_SPI_0_SLAVE_ONLY       FALSE      /* Is the device slave only? */
+#define XPAR_SPI_0_NUM_SS_BITS      32         /* Number of slave select bits */
+
+#define XPAR_SPI_1_DEVICE_ID        51         /* Device ID for instance */
+#define XPAR_SPI_1_BASEADDR         0x50000100 /* IPIF base address */
+#define XPAR_SPI_1_FIFO_EXIST       TRUE       /* Does device have FIFOs? */
+#define XPAR_SPI_1_SLAVE_ONLY       FALSE      /* Is the device slave only? */
+#define XPAR_SPI_1_NUM_SS_BITS      32         /* Number of slave select bits */
+
+/*****************************************************************************
+ *
+ * OPB Arbiter defines.
+ * DeviceID starts at 60
+ */
+#define XPAR_XOPBARB_NUM_INSTANCES 1          /* Number of instances */
+
+#define XPAR_OPBARB_0_DEVICE_ID    60         /* Device ID for instance */
+#define XPAR_OPBARB_0_BASEADDR     0x80000000 /* Register base address */
+#define XPAR_OPBARB_0_NUM_MASTERS  8          /* Number of masters on bus */
+
+/*****************************************************************************
+ *
+ * Watchdog timer/timebase (WdtTb) defines.
+ * DeviceID starts at 70
+ */
+#define XPAR_XWDTTB_NUM_INSTANCES   1          /* Number of instances */
+
+#define XPAR_WDTTB_0_DEVICE_ID      70         /* Device ID for instance */
+#define XPAR_WDTTB_0_BASEADDR       0x70800040 /* Register base address */
+
+/*****************************************************************************
+ *
+ * Timer Counter (TmrCtr) defines.
+ * DeviceID starts at 80
+ */
+#define XPAR_XTMRCTR_NUM_INSTANCES  2          /* Number of instances */
+
+#define XPAR_TMRCTR_0_DEVICE_ID     80         /* Device ID for instance */
+#define XPAR_TMRCTR_0_BASEADDR      0x70800100 /* Register base address */
+
+/*****************************************************************************
+ *
+ * IIC defines.
+ * DeviceID starts at 90
+ */
+#define XPAR_XIIC_NUM_INSTANCES     2          /* Number of instances */
+
+#define XPAR_IIC_0_DEVICE_ID        90         /* Device ID for instance */
+#define XPAR_IIC_0_BASEADDR         0xA8000000 /* Device base address */
+#define XPAR_IIC_0_TEN_BIT_ADR      TRUE       /* Supports 10 bit addresses */
+
+#define XPAR_IIC_1_DEVICE_ID        91         /* Device ID for instance */
+#define XPAR_IIC_1_BASEADDR         0xA8000000 /* Device base address */
+#define XPAR_IIC_1_TEN_BIT_ADR      TRUE       /* Supports 10 bit addresses */
+
+/*****************************************************************************
+ *
+ * Flash defines.
+ * DeviceID starts at 100
+ */
+#define XPAR_XFLASH_NUM_INSTANCES   1          /* Number of instances */
+#define XPAR_FLASH_INTEL_SUPPORT               /* Include intel flash support */
+
+#define XPAR_FLASH_0_DEVICE_ID      100        /* Device ID for first instance
+*/
+#define XPAR_FLASH_0_BASEADDR       0xFF000000 /* Base address of parts */
+#define XPAR_FLASH_0_NUM_PARTS      2          /* Number of parts in array */
+#define XPAR_FLASH_0_PART_WIDTH     2          /* Width of each part in bytes */
+#define XPAR_FLASH_0_PART_MODE      2          /* Mode of each part in bytes */
+
+/*****************************************************************************
+ *
+ * GPIO defines.
+ * DeviceID starts at 110
+ */
+#define XPAR_XGPIO_NUM_INSTANCES    1
+
+#define XPAR_GPIO_0_DEVICE_ID       110        /* Device ID for instance */
+#define XPAR_GPIO_0_BASEADDR        0x90000000 /* Register base address */
+#define XPAR_GPIO_0_INTERRUPT_PRESENT   0      /* Interrupts supported? */
+#define XPAR_GPIO_0_IS_DUAL             0      /* Dual channels supported? */
+
+/*****************************************************************************
+ *
+ * EMC defines.
+ * DeviceID starts at 120
+ */
+#define XPAR_XEMC_NUM_INSTANCES     1
+
+#define XPAR_EMC_0_DEVICE_ID       120         /* Device ID for instance */
+#define XPAR_EMC_0_BASEADDR        0xE0000000  /* Register base address */
+#define XPAR_EMC_0_NUM_BANKS_MEM   3           /* Number of banks */
+
+/*****************************************************************************
+ *
+ * PLB Arbiter defines.
+ * DeviceID starts at 130
+ */
+#define XPAR_XPLBARB_NUM_INSTANCES     1
+
+#define XPAR_PLBARB_0_DEVICE_ID       130         /* Device ID for instance */
+#define XPAR_PLBARB_0_BASEADDR        0x300       /* Register base address */
+#define XPAR_PLBARB_0_NUM_MASTERS     1           /* Number of masters on bus */
+
+/*****************************************************************************
+ *
+ * PLB To OPB Bridge defines.
+ * DeviceID starts at 140
+ */
+#define XPAR_XPLB2OPB_NUM_INSTANCES     1
+
+#define XPAR_PLB2OPB_0_DEVICE_ID       140         /* Device ID for instance */
+#define XPAR_PLB2OPB_0_DCR_BASEADDR    0x0         /* DCR Register base address
+*/
+#define XPAR_PLB2OPB_0_NUM_MASTERS       1         /* Number of masters on bus
+*/
+
+
+/*****************************************************************************
+ *
+ * OPB To PLB Bridge defines.
+ * DeviceID starts at 150
+ */
+#define XPAR_XOPB2PLB_NUM_INSTANCES     1
+#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF       /* Accessible from OPB, not DCR */
+
+#define XPAR_OPB2PLB_0_DEVICE_ID       150   /* Device ID for instance */
+#define XPAR_OPB2PLB_0_OPB_BASEADDR    0x0   /* Register base address */
+#define XPAR_OPB2PLB_0_DCR_BASEADDR    0x0   /* DCR Register base address */
+
+
+/*****************************************************************************
+ *
+ * System ACE defines.
+ * DeviceID starts at 160
+ */
+#define XPAR_XSYSACE_NUM_INSTANCES    1
+
+#define XPAR_SYSACE_0_DEVICE_ID       160         /* Device ID for instance */
+#define XPAR_SYSACE_0_BASEADDR        0xCF000000  /* Register base address */
+
+
+/*****************************************************************************
+ *
+ * HDLC defines.
+ * DeviceID starts at 170
+ */
+#define XPAR_XHDLC_NUM_INSTANCES     1
+
+#define XPAR_HDLC_0_DEVICE_ID       170             /* Device ID for instance */
+#define XPAR_HDLC_0_BASEADDR        0x60010000      /* Register base address */
+#define XPAR_HDLC_0_TX_MEM_DEPTH    2048            /* Tx FIFO depth (bytes) */
+#define XPAR_HDLC_0_RX_MEM_DEPTH    2048            /* Rx FIFO depth (bytes) */
+#define XPAR_HDLC_0_DMA_PRESENT     3               /* DMA SG in hardware */
+
+
+/*****************************************************************************
+ *
+ * PS2 Reference driver defines.
+ * DeviceID starts at 180
+ */
+#define XPAR_XPS2_NUM_INSTANCES    2
+
+#define XPAR_PS2_0_DEVICE_ID       180             /* Device ID for instance */
+#define XPAR_PS2_0_BASEADDR        0x40010000      /* Register base address */
+
+#define XPAR_PS2_1_DEVICE_ID       181             /* Device ID for instance */
+#define XPAR_PS2_1_BASEADDR        0x40020000      /* Register base address */
+
+/*****************************************************************************
+ *
+ * Rapid IO defines.
+ * DeviceID starts at 190
+ */
+#define XPAR_XRAPIDIO_NUM_INSTANCES    1
+
+#define XPAR_RAPIDIO_0_DEVICE_ID       190             /* Device ID for instance */
+#define XPAR_RAPIDIO_0_BASEADDR        0x60000000      /* Register base address */
+
+
+/*****************************************************************************
+ *
+ * PCI defines.
+ * DeviceID starts at 200
+ */
+#define XPAR_XPCI_NUM_INSTANCES                      1
+#define XPAR_OPB_PCI_1_DEVICE_ID                     200
+#define XPAR_OPB_PCI_1_BASEADDR                      0x86000000
+#define XPAR_OPB_PCI_1_HIGHADDR                      0x860001FF
+#define XPAR_OPB_PCI_1_PCIBAR_0                      0x10000000
+#define XPAR_OPB_PCI_1_PCIBAR_LEN_0                  27
+#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0                 0xF0000000
+#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0  0
+#define XPAR_OPB_PCI_1_PCI_PREFETCH_0                1
+#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0               1
+#define XPAR_OPB_PCI_1_PCIBAR_1                      0x3F000000
+#define XPAR_OPB_PCI_1_PCIBAR_LEN_1                  15
+#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1                 0xC0FF8000
+#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1  0
+#define XPAR_OPB_PCI_1_PCI_PREFETCH_1                1
+#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1               1
+#define XPAR_OPB_PCI_1_PCIBAR_2                      0x5F000000
+#define XPAR_OPB_PCI_1_PCIBAR_LEN_2                  16
+#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2                 0x00000000
+#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2  0
+#define XPAR_OPB_PCI_1_PCI_PREFETCH_2                1
+#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2               1
+#define XPAR_OPB_PCI_1_IPIFBAR_0                     0x80000000
+#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0               0x81FFFFFF
+#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0                 0xF0000000
+#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0
+#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0               1
+#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0              1
+#define XPAR_OPB_PCI_1_IPIFBAR_1                     0x82000000
+#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1               0x820007FF
+#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1                 0xCE000000
+#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
+#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1               1
+#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1              1
+#define XPAR_OPB_PCI_1_IPIFBAR_2                     0x82320000
+#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2               0x8232FFFF
+#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2                 0x00010000
+#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
+#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2               1
+#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2              1
+#define XPAR_OPB_PCI_1_IPIFBAR_3                     0x82330000
+#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3               0x8233FFFF
+#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3                 0x00010000
+#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
+#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3               1
+#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3              0
+#define XPAR_OPB_PCI_1_IPIFBAR_4                     0x82340000
+#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4               0x8234FFFF
+#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4                 0x00010000
+#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
+#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4               0
+#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4              0
+#define XPAR_OPB_PCI_1_IPIFBAR_5                     0x82350000
+#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5               0x8235FFFF
+#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5                 0x00010000
+#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
+#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5               1
+#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5              1
+#define XPAR_OPB_PCI_1_DMA_BASEADDR                  0x87000000
+#define XPAR_OPB_PCI_1_DMA_HIGHADDR                  0x8700007F
+#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE                 0
+#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH              11
+
+/*****************************************************************************
+ *
+ * GEmac defines.
+ * DeviceID starts at 210
+ */
+#define XPAR_XGEMAC_NUM_INSTANCES    1
+#define XPAR_GEMAC_0_DEVICE_ID       210
+#define XPAR_GEMAC_0_BASEADDR        0x61000000
+#define XPAR_GEMAC_0_DMA_TYPE        9
+#define XPAR_GEMAC_0_MIIM_EXIST      0
+#define XPAR_GEMAC_0_INCLUDE_STATS   0
+
+
+/*****************************************************************************
+ *
+ * Touchscreen defines .
+ * DeviceID starts at 220
+ */
+#define XPAR_XTOUCHSCREEN_NUM_INSTANCES  1
+#define XPAR_TOUCHSCREEN_0_DEVICE_ID     220
+#define XPAR_TOUCHSCREEN_0_BASEADDR      0x70000000
+
+
+/*****************************************************************************
+ *
+ * DDR defines .
+ * DeviceID starts at 230
+ */
+#define XPAR_XDDR_NUM_INSTANCES         1
+#define XPAR_DDR_0_DEVICE_ID            230
+#define XPAR_DDR_0_BASEADDR             0
+#define XPAR_DDR_0_INTERRUPT_PRESENT    0
+
+/*****************************************************************************
+ *
+ * EmacLite defines .
+ * DeviceID starts at 240
+ */
+#define XPAR_XEMACLITE_NUM_INSTANCES    1
+#define XPAR_EMACLITE_0_DEVICE_ID       240
+#define XPAR_EMACLITE_0_BASEADDR        0
+#define XPAR_EMACLITE_0_TX_PING_PONG    0
+#define XPAR_EMACLITE_0_RX_PING_PONG    0
+
+/*****************************************************************************
+ *
+ * DSDAC defines .
+ * DeviceID starts at 250
+ */
+#define XPAR_XDSDAC_NUM_INSTANCES       1
+#define XPAR_DSDAC_0_DEVICE_ID          250
+#define XPAR_DSDAC_0_BASEADDR           0
+
+/*****************************************************************************
+ *
+ * DSADC defines .
+ * DeviceID starts at 260
+ */
+#define XPAR_XDSADC_NUM_INSTANCES       1
+#define XPAR_DSADC_0_DEVICE_ID          260
+#define XPAR_DSADC_0_BASEADDR           0
+
+/*****************************************************************************
+ *
+ * PCI Arbiter defines.
+ * DeviceID starts at 270
+ */
+#define XPAR_XPCIARB_NUM_INSTANCES     1
+#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID     270
+#define XPAR_OPB_PCI_ARBITER_0_BASEADDR      0
+#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2
+
+/*****************************************************************************
+ *
+ * TEMAC defines .
+ * DeviceID starts at 280
+ */
+#define XPAR_XTEMAC_NUM_INSTANCES       1
+#define XPAR_TEMAC_0_DEVICE_ID          280
+#define XPAR_TEMAC_0_BASEADDR           0
+#define XPAR_TEMAC_0_DMA_TYPE        3
+#define XPAR_TEMAC_0_RDFIFO_DEPTH    131072
+#define XPAR_TEMAC_0_WRFIFO_DEPTH    131072
+#define XPAR_TEMAC_0_MAC_FIFO_DEPTH  16
+#define XPAR_TEMAC_0_TEMAC_DCR_HOST  0
+#define XPAR_TEMAC_0_DRE             0
+
+/*****************************************************************************
+ *
+ * DMACENTRAL defines .
+ * DeviceID starts at 290
+ */
+#define XPAR_XDMACENTRAL_NUM_INSTANCES       1
+#define XPAR_DMACENTRAL_0_DEVICE_ID          290
+#define XPAR_DMACENTRAL_0_BASEADDR           0
+#define XPAR_DMACENTRAL_0_READ_OPTIONAL_REGS 0
+
+/*****************************************************************************
+ *
+ * CAN defines
+ * DeviceID starts at 300
+ */
+#define XPAR_XCAN_NUM_INSTANCES  1
+#define XPAR_CAN_0_DEVICE_ID     300
+
+/* Definitions for FLEXRAY Driver */
+#define XPAR_XFLEXRAY_NUM_INSTANCES 1
+#define XPAR_OPB_FLEXRAY_0_DEVICE_ID    0
+#define XPAR_OPB_FLEXRAY_0_BASEADDR  0x7D80E000
+#define XPAR_OPB_FLEXRAY_MAX_PAYLOAD_SIZE 254
+#define XPAR_OPB_FLEXRAY_NO_OF_TX_BUFFERS   128
+#define XPAR_OPB_FLEXRAY_NO_OF_RX_BUFFERS   128
+#define XPAR_OPB_FLEXRAY_RX_FIFO_DEPTH      16
+
+/* Definitions for MOST driver */
+#define XPAR_XMOST_NUM_INSTANCES 1
+#define XPAR_MOST_0_DEVICE_ID 0
+#define XPAR_MOST_0_BASEADDR 0x7D810000
+#define XPAR_MOST_OPMODE	0
+#define XPAR_MOST_FWC 16
+#define XPAR_MOST_EWC 16
+
+/* Definitions for USB driver */
+#define XPAR_XUSB_NUM_INSTANCES	1
+#define XPAR_USB_0_DEVICE_ID	0
+#define XPAR_USB_0_BASEADDR	0x7D813000
+
+/*****************************************************************************
+ *
+ * HWICAP defines .
+ */
+#define XPAR_XHWICAP_NUM_INSTANCES       1
+#define XPAR_OPB_HWICAP_0_DEVICE_ID      0
+#define XPAR_OPB_HWICAP_0_BASEADDR        0xFFFFFFFF
+
+/*****************************************************************************
+ *
+ * LLTEMAC and LLFIFO defines .
+ */
+#define XPAR_XLLTEMAC_NUM_INSTANCES      1
+#define XPAR_XLLFIFO_NUM_INSTANCES       1
+
+/*****************************************************************************
+ *
+ * PCIe defines .
+ */
+#define XPAR_XPCIE_NUM_INSTANCES       1
+
+/*****************************************************************************
+ *
+ * MPMC defines .
+ */
+#define XPAR_XMPMC_NUM_INSTANCES         1
+
+/*****************************************************************************
+ *
+ * SYSMON defines .
+ */
+#define XPAR_XSYSMON_NUM_INSTANCES         1
+
+
+/*****************************************************************************
+ *
+ * AXI Ethernet defines .
+ */
+#define XPAR_XAXIETHERNET_NUM_INSTANCES         1
+
+/*****************************************************************************
+ *
+ * TFT defines .
+ */
+#define XPAR_XTFT_NUM_INSTANCES		1
+
+/*****************************************************************************
+ *
+ * MBox defines .
+ */
+#define XPAR_XMBOX_NUM_INSTANCES         	1
+#define XPAR_XMBOX_0_DEVICE_ID				0
+#define XPAR_XMBOX_0_BASEADDR				0x7D814000
+#define XPAR_XMBOX_0_NUM_CHANNELS			1
+#define XPAR_XMBOX_0_USE_FSL				0
+
+
+/*****************************************************************************
+ *
+ * Mutex defines .
+ */
+#define XPAR_XMUTEX_NUM_INSTANCES         	1
+#define XPAR_XMUTEX_0_DEVICE_ID				0
+#define XPAR_XMUTEX_0_BASEADDR				0x7D815000
+#define XPAR_XMUTEX_0_NUM_MUTEX				2
+#define XPAR_XMUTEX_0_ENABLE_USER			1
+
+/*
+ * MicroBlaze sets this define but for the build check to
+ * function it needs to be set here
+ */
+#define XPAR_CPU_ID 0
+
+
+/*****************************************************************************
+ *
+ * BRAM defines .
+ */
+#define XPAR_XBRAM_NUM_INSTANCES         	1
+
+
+/*****************************************************************************
+ *
+ * AXI PCIE defines .
+ */
+#define XPAR_XAXIPCIE_NUM_INSTANCES         	1
+
+/*****************************************************************************
+ *
+ * V6 DDRX efines .
+ */
+#define XPAR_XV6DDR_NUM_INSTANCES         	1
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif              /* end of protection macro */
+
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xstatus.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xstatus.h
new file mode 100644
index 000000000..a8caf2f4e
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xstatus.h
@@ -0,0 +1,432 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xutil.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xutil.h
new file mode 100644
index 000000000..082738e34
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xutil.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xutil.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains utility functions such as memory test functions.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* <pre>
+* XUT_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XUT_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing
+*       value as the test value for memory.
+*
+* XUT_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XUT_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XUT_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XUT_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* </pre>
+*
+* <i>WARNING</i>
+*
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+*
+* The address, Addr, provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
+* boundry of a power of two making it more difficult to detect addressing
+* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
+* problem. Ideally, if large blocks of memory are to be tested, break
+* them up into smaller regions of memory to allow the test patterns used
+* not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  11/01/01 First release
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XUTIL_H			/* prevent circular inclusions */
+#define XUTIL_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XUT_MEMTEST_INIT_VALUE  1
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XUT_ALLMEMTESTS     0
+#define XUT_INCREMENT       1
+#define XUT_WALKONES        2
+#define XUT_WALKZEROS       3
+#define XUT_INVERSEADDR     4
+#define XUT_FIXEDPATTERN    5
+#define XUT_MAXTEST         XUT_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_memtest prototypes */
+
+int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xutil_memtest.c b/thirdparty/xilinx/orig/common_v1_00_a/src/xutil_memtest.c
new file mode 100644
index 000000000..374e8bdf5
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xutil_memtest.c
@@ -0,0 +1,1186 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xutil_memtest.c
+* @addtogroup common_v1_00_a
+* @{
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  11/01/01 First release
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xutil.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* Performs a destructive 32-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xutil.h for possible values.
+*
+* @return
+*
+* - XST_MEMTEST_FAILED is returned for a failure
+* - XST_SUCCESS is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
+* boundry of a power of two making it more difficult to detect addressing
+* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
+* problem. Ideally, if large blocks of memory are to be tested, break
+* them up into smaller regions of memory to allow the test patterns used
+* not to repeat over the region tested.
+*
+*****************************************************************************/
+int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 i;
+	u32 j;
+	u32 Val = XUT_MEMTEST_INIT_VALUE;
+	u32 FirstVal = XUT_MEMTEST_INIT_VALUE;
+	u32 Word;
+
+	XASSERT_NONVOID(Words != 0);
+	XASSERT_NONVOID(Subtest <= XUT_MAXTEST);
+
+	/*
+	 * Select the proper Subtest
+	 */
+
+
+	switch (Subtest) {
+
+	case XUT_ALLMEMTESTS:
+
+		/* this case executes all of the Subtests */
+
+		/* fall through case statement */
+
+	case XUT_INCREMENT:
+		{
+
+			/*
+			 * Fill the memory with incrementing
+			 * values starting from 'FirstVal'
+			 */
+			for (i = 0L; i < Words; i++) {
+				Addr[i] = Val;
+
+				/* write memory location */
+
+				Val++;
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = FirstVal;
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory and compare it
+			 * with the incrementing reference
+			 * Val
+			 */
+
+			for (i = 0L; i < Words; i++) {
+				Word = Addr[i];
+
+				if (Word != Val) {
+					return XST_MEMTEST_FAILED;
+				}
+
+				Val++;
+			}
+
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 1 */
+
+		/* fall through case statement */
+
+	case XUT_WALKONES:
+		{
+			/*
+			 * set up to cycle through all possible initial
+			 * test Patterns for walking ones test
+			 */
+
+			for (j = 0L; j < 32; j++) {
+				/*
+				 * Generate an initial value for walking ones test to test for bad
+				 * data bits
+				 */
+
+				Val = 1 << j;
+
+				/*
+				 * START walking ones test
+				 * Write a one to each data bit indifferent locations
+				 */
+
+				for (i = 0L; i < 32; i++) {
+
+					/* write memory location */
+
+					Addr[i] = Val;
+					Val = (u32) RotateLeft(Val, 32);
+
+				}
+
+				/*
+				 * Restore the reference 'Val' to the
+				 * initial value
+				 */
+				Val = 1 << j;
+
+				/* Read the values from each location that was written */
+
+				for (i = 0L; i < 32; i++) {
+					/* read memory location */
+
+					Word = Addr[i];
+
+					if (Word != Val) {
+						return XST_MEMTEST_FAILED;
+					}
+
+					Val = (u32) RotateLeft(Val, 32);
+
+				}
+
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 2 */
+
+		/* fall through case statement */
+
+	case XUT_WALKZEROS:
+		{
+			/*
+			 * set up to cycle through all possible
+			 * initial test Patterns for walking zeros test
+			 */
+
+			for (j = 0L; j < 32; j++) {
+
+				/*
+				 * Generate an initial value for walking ones test to test for
+				 * bad data bits
+				 */
+
+				Val = ~(1 << j);
+
+				/*
+				 * START walking zeros test
+				 * Write a one to each data bit indifferent locations
+				 */
+
+				for (i = 0L; i < 32; i++) {
+
+					/* write memory location */
+
+					Addr[i] = Val;
+					Val = ~((u32) RotateLeft(~Val, 32));
+
+				}
+
+				/*
+				 * Restore the reference 'Val' to the
+				 * initial value
+				 */
+
+				Val = ~(1 << j);
+
+				/* Read the values from each location that was written */
+
+				for (i = 0L; i < 32; i++) {
+
+					/* read memory location */
+
+					Word = Addr[i];
+
+					if (Word != Val) {
+						return XST_MEMTEST_FAILED;
+					}
+
+					Val = ~((u32) RotateLeft(~Val, 32));
+
+				}
+
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 3 */
+
+		/* fall through case statement */
+
+	case XUT_INVERSEADDR:
+		{
+
+			/* Fill the memory with inverse of address */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* write memory location */
+
+				Val = (u32) (~((u32) (&Addr[i])));
+
+				Addr[i] = Val;
+
+			}
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* Read the location */
+
+				Word = Addr[i];
+
+				Val = (u32) (~((u32) (&Addr[i])));
+
+				if ((Word ^ Val) != 0x00000000) {
+					return XST_MEMTEST_FAILED;
+				}
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 4 */
+
+
+		/* fall through case statement */
+
+	case XUT_FIXEDPATTERN:
+		{
+
+			/*
+			 * Generate an initial value for
+			 * memory testing
+			 */
+
+			if (Pattern == 0) {
+				Val = 0xDEADBEEF;
+
+			}
+			else {
+				Val = Pattern;
+
+			}
+
+			/*
+			 * Fill the memory with fixed pattern
+			 */
+
+			for (i = 0L; i < Words; i++) {
+				/* write memory location */
+
+				Addr[i] = Val;
+
+			}
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory and compare it
+			 * with the fixed pattern
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				if (Word != Val) {
+					return XST_MEMTEST_FAILED;
+				}
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 5 */
+
+		/* this break is for the prior fall through case statements */
+
+		break;
+
+	default:
+		{
+			return XST_MEMTEST_FAILED;
+		}
+
+	}			/* end of switch */
+
+	/* Successfully passed memory test ! */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs a destructive 16-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xutil.h for possible values.
+*
+* @return
+*
+* - XST_MEMTEST_FAILED is returned for a failure
+* - XST_SUCCESS is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
+* boundry of a power of two making it more difficult to detect addressing
+* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
+* problem. Ideally, if large blocks of memory are to be tested, break
+* them up into smaller regions of memory to allow the test patterns used
+* not to repeat over the region tested.
+*
+*****************************************************************************/
+int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 i;
+	u32 j;
+	u16 Val = XUT_MEMTEST_INIT_VALUE;
+	u16 FirstVal = XUT_MEMTEST_INIT_VALUE;
+	u16 Word;
+
+	XASSERT_NONVOID(Words != 0);
+	XASSERT_NONVOID(Subtest <= XUT_MAXTEST);
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	switch (Subtest) {
+
+	case XUT_ALLMEMTESTS:
+
+		/* this case executes all of the Subtests */
+
+		/* fall through case statement */
+
+	case XUT_INCREMENT:
+		{
+
+			/*
+			 * Fill the memory with incrementing
+			 * values starting from 'FirstVal'
+			 */
+			for (i = 0L; i < Words; i++) {
+				/* write memory location */
+
+				Addr[i] = Val;
+
+				Val++;
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = FirstVal;
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory and compare it
+			 * with the incrementing reference
+			 * Val
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				if (Word != Val) {
+					return XST_MEMTEST_FAILED;
+				}
+				Val++;
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 1 */
+
+		/* fall through case statement */
+
+	case XUT_WALKONES:
+		{
+			/*
+			 * set up to cycle through all possible initial test
+			 * Patterns for walking ones test
+			 */
+
+			for (j = 0L; j < 16; j++) {
+				/*
+				 * Generate an initial value for walking ones test to test for bad
+				 * data bits
+				 */
+
+				Val = 1 << j;
+
+				/*
+				 * START walking ones test
+				 * Write a one to each data bit indifferent locations
+				 */
+
+				for (i = 0L; i < 16; i++) {
+
+					/* write memory location */
+
+					Addr[i] = Val;
+
+					Val = (u16) RotateLeft(Val, 16);
+
+				}
+
+				/*
+				 * Restore the reference 'Val' to the
+				 * initial value
+				 */
+
+				Val = 1 << j;
+
+				/* Read the values from each location that was written */
+
+				for (i = 0L; i < 16; i++) {
+
+					/* read memory location */
+
+					Word = Addr[i];
+
+					if (Word != Val) {
+						return XST_MEMTEST_FAILED;
+					}
+
+					Val = (u16) RotateLeft(Val, 16);
+
+				}
+
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 2 */
+
+		/* fall through case statement */
+
+	case XUT_WALKZEROS:
+		{
+			/*
+			 * set up to cycle through all possible initial
+			 * test Patterns for walking zeros test
+			 */
+
+			for (j = 0L; j < 16; j++) {
+
+				/*
+				 * Generate an initial value for walking ones
+				 * test to test for bad
+				 * data bits
+				 */
+
+				Val = ~(1 << j);
+
+				/*
+				 * START walking zeros test
+				 * Write a one to each data bit indifferent locations
+				 */
+
+				for (i = 0L; i < 16; i++) {
+
+
+					/* write memory location */
+
+					Addr[i] = Val;
+					Val = ~((u16) RotateLeft(~Val, 16));
+
+				}
+
+				/*
+				 * Restore the reference 'Val' to the
+				 * initial value
+				 */
+
+				Val = ~(1 << j);
+
+				/* Read the values from each location that was written */
+
+				for (i = 0L; i < 16; i++) {
+
+					/* read memory location */
+
+					Word = Addr[i];
+
+					if (Word != Val) {
+						return XST_MEMTEST_FAILED;
+					}
+
+					Val = ~((u16) RotateLeft(~Val, 16));
+
+				}
+
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 3 */
+
+		/* fall through case statement */
+
+	case XUT_INVERSEADDR:
+		{
+
+			/* Fill the memory with inverse of address */
+
+			for (i = 0L; i < Words; i++) {
+				/* write memory location */
+
+				Val = (u16) (~((u32) (&Addr[i])));
+				Addr[i] = Val;
+
+			}
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				Val = (u16) (~((u32) (&Addr[i])));
+
+				if ((Word ^ Val) != 0x0000) {
+					return XST_MEMTEST_FAILED;
+				}
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 4 */
+
+
+		/* fall through case statement */
+
+	case XUT_FIXEDPATTERN:
+		{
+
+			/*
+			 * Generate an initial value for
+			 * memory testing
+			 */
+
+			if (Pattern == 0) {
+				Val = 0xDEAD;
+
+			}
+			else {
+				Val = Pattern;
+
+			}
+
+			/*
+			 * Fill the memory with fixed pattern
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* write memory location */
+
+				Addr[i] = Val;
+
+			}
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory and compare it
+			 * with the fixed pattern
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				if (Word != Val) {
+					return XST_MEMTEST_FAILED;
+				}
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 5 */
+
+		/* this break is for the prior fall through case statements */
+
+		break;
+
+	default:
+		{
+			return XST_MEMTEST_FAILED;
+		}
+
+	}			/* end of switch */
+
+	/* Successfully passed memory test ! */
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Performs a destructive 8-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xutil.h for possible values.
+*
+* @return
+*
+* - XST_MEMTEST_FAILED is returned for a failure
+* - XST_SUCCESS is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
+* boundry of a power of two making it more difficult to detect addressing
+* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
+* problem. Ideally, if large blocks of memory are to be tested, break
+* them up into smaller regions of memory to allow the test patterns used
+* not to repeat over the region tested.
+*
+*****************************************************************************/
+int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 i;
+	u32 j;
+	u8 Val = XUT_MEMTEST_INIT_VALUE;
+	u8 FirstVal = XUT_MEMTEST_INIT_VALUE;
+	u8 Word;
+
+	XASSERT_NONVOID(Words != 0);
+	XASSERT_NONVOID(Subtest <= XUT_MAXTEST);
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	switch (Subtest) {
+
+	case XUT_ALLMEMTESTS:
+
+		/* this case executes all of the Subtests */
+
+		/* fall through case statement */
+
+	case XUT_INCREMENT:
+		{
+
+			/*
+			 * Fill the memory with incrementing
+			 * values starting from 'FirstVal'
+			 */
+			for (i = 0L; i < Words; i++) {
+
+				/* write memory location */
+
+				Addr[i] = Val;
+				Val++;
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = FirstVal;
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory and compare it
+			 * with the incrementing reference
+			 * Val
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				if (Word != Val) {
+					return XST_MEMTEST_FAILED;
+				}
+				Val++;
+			}
+
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 1 */
+
+		/* fall through case statement */
+
+	case XUT_WALKONES:
+		{
+			/*
+			 * set up to cycle through all possible initial
+			 * test Patterns for walking ones test
+			 */
+
+			for (j = 0L; j < 8; j++) {
+				/*
+				 * Generate an initial value for walking ones test to test
+				 * for bad data bits
+				 */
+
+				Val = 1 << j;
+
+				/*
+				 * START walking ones test
+				 * Write a one to each data bit indifferent locations
+				 */
+
+				for (i = 0L; i < 8; i++) {
+
+					/* write memory location */
+
+					Addr[i] = Val;
+					Val = (u8) RotateLeft(Val, 8);
+				}
+
+				/*
+				 * Restore the reference 'Val' to the
+				 * initial value
+				 */
+				Val = 1 << j;
+
+				/* Read the values from each location that was written */
+
+				for (i = 0L; i < 8; i++) {
+
+					/* read memory location */
+
+					Word = Addr[i];
+
+					if (Word != Val) {
+						return XST_MEMTEST_FAILED;
+					}
+
+					Val = (u8) RotateLeft(Val, 8);
+
+				}
+
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 2 */
+
+		/* fall through case statement */
+
+	case XUT_WALKZEROS:
+		{
+			/*
+			 * set up to cycle through all possible initial test
+			 * Patterns for walking zeros test
+			 */
+
+			for (j = 0L; j < 8; j++) {
+
+				/*
+				 * Generate an initial value for walking ones test to test
+				 * for bad data bits
+				 */
+
+				Val = ~(1 << j);
+
+				/*
+				 * START walking zeros test
+				 * Write a one to each data bit indifferent locations
+				 */
+
+				for (i = 0L; i < 8; i++) {
+
+
+					/* write memory location */
+
+					Addr[i] = Val;
+					Val = ~((u8) RotateLeft(~Val, 8));
+
+				}
+
+				/*
+				 * Restore the reference 'Val' to the
+				 * initial value
+				 */
+
+				Val = ~(1 << j);
+
+				/* Read the values from each location that was written */
+
+				for (i = 0L; i < 8; i++) {
+
+					/* read memory location */
+
+					Word = Addr[i];
+
+					if (Word != Val) {
+						return XST_MEMTEST_FAILED;
+					}
+
+					Val = ~((u8) RotateLeft(~Val, 8));
+
+				}
+
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 3 */
+
+		/* fall through case statement */
+
+	case XUT_INVERSEADDR:
+		{
+
+			/* Fill the memory with inverse of address */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* write memory location */
+
+				Val = (u8) (~((u32) (&Addr[i])));
+				Addr[i] = Val;
+
+			}
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				Val = (u8) (~((u32) (&Addr[i])));
+
+				if ((Word ^ Val) != 0x00) {
+					return XST_MEMTEST_FAILED;
+				}
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+
+		}		/* end of case 4 */
+
+
+		/* fall through case statement */
+
+	case XUT_FIXEDPATTERN:
+		{
+
+			/*
+			 * Generate an initial value for
+			 * memory testing
+			 */
+
+			if (Pattern == 0) {
+				Val = 0xA5;
+
+			}
+			else {
+				Val = Pattern;
+
+			}
+
+			/*
+			 * Fill the memory with fixed pattern
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* write memory location */
+
+				Addr[i] = Val;
+
+			}
+
+			/*
+			 * Check every word within the Words
+			 * of tested memory and compare it
+			 * with the fixed pattern
+			 */
+
+			for (i = 0L; i < Words; i++) {
+
+				/* read memory location */
+
+				Word = Addr[i];
+
+				if (Word != Val) {
+					return XST_MEMTEST_FAILED;
+				}
+			}
+
+			if (Subtest != XUT_ALLMEMTESTS) {
+				return XST_SUCCESS;
+			}
+
+		}		/* end of case 5 */
+
+		/* this break is for the prior fall through case statements */
+
+		break;
+
+	default:
+		{
+			return XST_MEMTEST_FAILED;
+		}
+
+	}			/* end of switch */
+
+	/* Successfully passed memory test ! */
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting unsigned long value of the rotate left
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1 << (Width - 1);
+
+	WidthMask = (MsbMask << 1) - 1;
+
+	/*
+	 * set the width of the Input to the correct width
+	 */
+
+	Input = Input & WidthMask;
+
+	Msb = Input & MsbMask;
+
+	ReturnVal = Input << 1;
+
+	if (Msb != 0x00000000) {
+		ReturnVal = ReturnVal | 0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return (ReturnVal);
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the right one bit position
+*
+* @param    Input is value to be rotated to the right
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting u32 value of the rotate right
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1 << (Width - 1);
+
+	WidthMask = (MsbMask << 1) - 1;
+
+	/*
+	 * set the width of the Input to the correct width
+	 */
+
+	Input = Input & WidthMask;
+
+	ReturnVal = Input >> 1;
+
+	Lsb = Input & 0x00000001;
+
+	if (Lsb != 0x00000000) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return (ReturnVal);
+
+}
+#endif /* ROTATE_RIGHT */
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xversion.c b/thirdparty/xilinx/orig/common_v1_00_a/src/xversion.c
new file mode 100644
index 000000000..81935aa6e
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xversion.c
@@ -0,0 +1,357 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xversion.c
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains the implementation of the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a xd   11/03/04 Improved support for doxygen.
+</pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants define the masks and shift values to allow the
+ * revisions to be packed and unpacked, a packed version is packed into a 16
+ * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
+ * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
+ * revision
+ */
+#define XVE_MAJOR_SHIFT_VALUE       12
+#define XVE_MINOR_ONLY_MASK         0x0FE0
+#define XVE_MINOR_SHIFT_VALUE       5
+#define XVE_COMP_ONLY_MASK          0x001F
+
+/* the following constants define the specific characters of a version string
+ * for each character of the revision, a version string is in the following
+ * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
+ * revision (00 - 99), and Z is the compatability revision (a - z)
+ */
+#define XVE_MAJOR_CHAR      0	/* major revision 0 - 9 */
+#define XVE_MINOR_TENS_CHAR 2	/* minor revision tens 0 - 9 */
+#define XVE_MINOR_ONES_CHAR 3	/* minor revision ones 0 - 9 */
+#define XVE_COMP_CHAR       4	/* compatability revision a - z */
+#define XVE_END_STRING_CHAR 5
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+static int IsVersionStringValid(char *StringPtr);
+
+/*****************************************************************************/
+/**
+*
+* Unpacks a packed version into the specified version. Versions are packed
+* into the configuration ROM to reduce the amount storage. A packed version
+* is a binary format as oppossed to a non-packed version which is implemented
+* as a string.
+*
+* @param    InstancePtr points to the version to unpack the packed version into.
+* @param    PackedVersion contains the packed version to unpack.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion)
+{
+	(void) InstancePtr;
+	(void) PackedVersion;
+	/* not implemented yet since CROM related */
+}
+
+/*****************************************************************************/
+/**
+*
+* Packs a version into the specified packed version. Versions are packed into
+* the configuration ROM to reduce the amount storage.
+*
+* @param    InstancePtr points to the version to pack.
+* @param    PackedVersionPtr points to the packed version which will receive
+*           the new packed version.
+*
+* @return
+*
+* A status, XST_SUCCESS, indicating the packing was accomplished
+* successfully, or an error, XST_INVALID_VERSION, indicating the specified
+* input version was not valid such that the pack did not occur
+* <br><br>
+* The packed version pointed to by PackedVersionPtr is modified with the new
+* packed version if the status indicates success.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersionPtr)
+{
+	/* not implemented yet since CROM related */
+	(void) InstancePtr;
+	(void) PackedVersionPtr;
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Determines if two versions are equal.
+*
+* @param    InstancePtr points to the first version to be compared.
+* @param    VersionPtr points to a second version to be compared.
+*
+* @return
+*
+* TRUE if the versions are equal, FALSE otherwise.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr)
+{
+	u8 *Version1 = (u8 *) InstancePtr;
+	u8 *Version2 = (u8 *) VersionPtr;
+	u32 Index;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(VersionPtr != NULL);
+
+	/* check each byte of the versions to see if they are the same,
+	 * return at any point a byte differs between them
+	 */
+	for (Index = 0; Index < sizeof(XVersion); Index++) {
+		if (Version1[Index] != Version2[Index]) {
+			return FALSE;
+		}
+	}
+
+	/* No byte was found to be different between the versions, so indicate
+	 * the versions are equal
+	 */
+	return TRUE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Converts a version to a null terminated string.
+*
+* @param    InstancePtr points to the version to convert.
+* @param    StringPtr points to the string which will be the result of the
+*           conversion. This does not need to point to a null terminated
+*           string as an input, but must point to storage which is an adequate
+*           amount to hold the result string.
+*
+* @return
+*
+* The null terminated string is inserted at the location pointed to by
+* StringPtr if the status indicates success.
+*
+* @note
+*
+* It is necessary for the caller to have already allocated the storage to
+* contain the string.  The amount of memory necessary for the string is
+* specified in the version header file.
+*
+******************************************************************************/
+void XVersion_ToString(XVersion *InstancePtr, char *StringPtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(StringPtr != NULL);
+
+	/* since version is implemented as a string, just copy the specified
+	 * input into the specified output
+	 */
+	XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes a version from a null terminated string. Since the string may not
+* be a format which is compatible with the version, an error could occur.
+*
+* @param    InstancePtr points to the version which is to be initialized.
+* @param    StringPtr points to a null terminated string which will be
+*           converted to a version.  The format of the string must match the
+*           version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
+*           Z = a - z.
+*
+* @return
+*
+* A status, XST_SUCCESS, indicating the conversion was accomplished
+* successfully, or XST_INVALID_VERSION indicating the version string format
+* was not valid.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+int XVersion_FromString(XVersion *InstancePtr, char *StringPtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(StringPtr != NULL);
+
+	/* if the version string specified is not valid, return an error */
+
+	if (!IsVersionStringValid(StringPtr)) {
+		return XST_INVALID_VERSION;
+	}
+
+	/* copy the specified string into the specified version and indicate the
+	 * conversion was successful
+	 */
+	XVersion_Copy((XVersion *) StringPtr, InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Copies the contents of a version to another version.
+*
+* @param    InstancePtr points to the version which is the source of data for
+*           the copy operation.
+* @param    VersionPtr points to another version which is the destination of
+*           the copy operation.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr)
+{
+	u8 *Source = (u8 *) InstancePtr;
+	u8 *Destination = (u8 *) VersionPtr;
+	u32 Index;
+
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(VersionPtr != NULL);
+
+	/* copy each byte of the source version to the destination version */
+
+	for (Index = 0; Index < sizeof(XVersion); Index++) {
+		Destination[Index] = Source[Index];
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Determines if the specified version is valid.
+*
+* @param    StringPtr points to the string to be validated.
+*
+* @return
+*
+* TRUE if the version string is a valid format, FALSE otherwise.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static int IsVersionStringValid(char *StringPtr)
+{
+	/* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
+	 * YY = 00 - 99, and Z = a - z, then indicate it's not valid
+	 */
+	if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
+	    (StringPtr[XVE_MAJOR_CHAR] > '9') ||
+	    (StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
+	    (StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
+	    (StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
+	    (StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
+	    (StringPtr[XVE_COMP_CHAR] < 'a') ||
+	    (StringPtr[XVE_COMP_CHAR] > 'z')) {
+		return FALSE;
+	}
+
+	return TRUE;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/common_v1_00_a/src/xversion.h b/thirdparty/xilinx/orig/common_v1_00_a/src/xversion.h
new file mode 100644
index 000000000..8dad9824c
--- /dev/null
+++ b/thirdparty/xilinx/orig/common_v1_00_a/src/xversion.h
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xversion.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains the interface for the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XVERSION_H		/* prevent circular inclusions */
+#define XVERSION_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+typedef char XVersion[6];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion);
+
+int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion);
+
+int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr);
+
+void XVersion_ToString(XVersion *InstancePtr, char *StringPtr);
+
+int XVersion_FromString(XVersion *InstancePtr, char *StringPtr);
+
+void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/data/intc.mdd b/thirdparty/xilinx/orig/intc_v3_4/data/intc.mdd
new file mode 100644
index 000000000..03183441d
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/data/intc.mdd
@@ -0,0 +1,73 @@
+###############################################################################
+#
+# Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+#
+# Ver      Who    Date     Changes
+# -------- ------ -------- --------------------------------------------------
+# 3.0     adk    10/12/13  Removed support for dcr_intc intc_core xps_intc
+##############################################################################
+
+## @BEGIN_CHANGELOG EDK_M
+##
+## 11/18/09 ktn  Removed support for opb_intc
+##
+## @END_CHANGELOG
+
+## @BEGIN_CHANGELOG EDK_MS3
+##
+## 06/16/10 sv Added support for axi_intc
+##
+## @END_CHANGELOG
+
+
+OPTION psf_version = 2.1;
+
+BEGIN driver intc
+
+OPTION DRC = intc_drc;
+OPTION supported_peripherals = (axi_intc);
+OPTION driver_state = ACTIVE;
+OPTION copyfiles = all;
+OPTION VERSION = 3.4;
+OPTION NAME = intc;
+OPTION INTC_TYPE = XIntc;
+
+BEGIN ARRAY interrupt_handler
+PROPERTY desc = "Interrupt Handler";
+PROPERTY size = 1, permit = none;
+PROPERTY state = deprecated;
+PARAM name = int_handler, default = XIntc_DeviceInterruptHandler, desc = "Interrupt Handler", type = string;
+PARAM name = int_port, default = Irq, desc = "Interrupt pin associated with the interrupt handler", permit=none;
+PARAM name = int_handler_arg, desc = "Argument type to Handler function", type = enum, values= ("Use baseaddress"=C_BASEADDR, "Use device id"=DEVICE_ID), default = DEVICE_ID ;
+END ARRAY
+
+
+END driver
diff --git a/thirdparty/xilinx/orig/intc_v3_4/data/intc.tcl b/thirdparty/xilinx/orig/intc_v3_4/data/intc.tcl
new file mode 100644
index 000000000..ba10451f1
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/data/intc.tcl
@@ -0,0 +1,692 @@
+###############################################################################
+#
+# Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ------------------------------------
+# 3.0      adk    12/10/13 Updated as per the New Tcl API's
+##############################################################################
+
+## @BEGIN_CHANGELOG
+##
+##     09/17/07 ecm  Removed the PCI specific connections
+##              Moved to the Linux MLD.
+##     10/24/07 rpm  Fixed KIND_OF_INTR bug in canonicals and
+##              also generalized match on external interrupts
+##     06/25/09 sdm  Updated so that canonical definitions are
+##              not generated when instance name matches
+##              canonical name
+##     04/27/10 sdm Updated the tcl so that the defintions are generated in
+##		the xparameters.h to know whether the optional registers
+##		SIE, CIE and IVR are enabled in the HW - Refer CR 555392
+##     05/24/11 hvm updated tcl to generate vector ids for external interrupts
+##		CR565336
+##     06/15/11 hvm Updated tcl with bypassing the external interrupt definition
+##		in xredefine_intc function. CR613925.
+##     01/19/12 Updated the intc_define_use_dcr function so that it doesnot
+##              error out if there is more than one bus interface to the
+##              intc controller. The new common::version of the AXI_INTC can have two
+##              bus interfaces to support the fast interrupt for MicroBlaze.
+##              Updated for the generation of the C_HAS_FAST xparameters
+##     08/16/12 bss added generation of C_IVAR_RESET_VALUE xparameters
+##
+##     01/29/13 bss Added check_cascade and get_intctype to support
+##		    Cascade mode. Modified intc_define_vector_table procedure
+##		    to generate interrupt IDs as 32..63 and 64..95 and so on
+##		    for Slave controllers in Cascade mode
+##     01/22/14 bss Modified check_cascade to fix CR#764865
+##     17/02/14 adk Fixed the CR:771287 in intc_define_vector_table
+##		    if number of interrupt ports not equal to total numer of
+##		    interrupts returning immediatly.And in the xredefine_intc
+##		    if there is not interrupt source returining immediately.
+##     4/8/14   bss Modified xredefine_intc to handle external interrupt pins
+##		    correctly (CR#799609).
+##     11/3/14 adk  added generation of C_HAS_ILR parameter to xparameters.h
+##		    (CR#828046).
+##
+##
+##
+## @END_CHANGELOG
+
+############################################################
+# Global interrupt handlers array, default handler routine
+############################################################
+array set interrupt_handlers ""
+set default_interrupt_handler "XNullHandler"
+set cascade 0
+set intrid 0
+
+array set source_port_name         ""
+array set source_name              ""
+array set source_port_type         ""
+array set source_driver            ""
+array set source_interrupt_handler ""
+array set source_interrupt_id      ""
+set total_source_intrs             0
+
+############################################################
+# DRC procedure
+############################################################
+proc intc_drc {drv_handle} {
+
+}
+
+
+############################################################
+# "generate" procedure
+############################################################
+proc generate {drv_handle} {
+
+	# Generate the following definitions in xparameters.h
+	# 2. BASEADDR, HIGHADDR, C_NUM_INTR_INPUTS, XPAR_INTC_MAX_NUM_INTR_INPUTS
+
+	set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
+    set count [llength $periphs]
+    variable cascade
+
+	if {$count > 1} {
+		set cascade [check_cascade $drv_handle]
+	}
+
+	if {$cascade == 0} {
+		::hsi::utils::define_max $drv_handle "xparameters.h" "XPAR_INTC_MAX_NUM_INTR_INPUTS" "C_NUM_INTR_INPUTS"
+	} else {
+		set maxintrs 0
+		foreach periph $periphs {
+			set intrs [common::get_property CONFIG.C_NUM_INTR_INPUTS $periph]
+			set maxintrs [expr "$maxintrs + $intrs"]
+		}
+		set file_handle [::hsi::utils::open_include_file "xparameters.h"]
+		puts $file_handle "#define XPAR_INTC_MAX_NUM_INTR_INPUTS $maxintrs"
+        close $file_handle
+	}
+
+	foreach periph $periphs {
+		set fast [::hsi::utils::get_param_value $periph "C_HAS_FAST"]
+		set nested [::hsi::utils::get_param_value $periph "C_HAS_ILR"]
+	        if {$fast == 1 && $nested == 1} {
+				 puts "ERROR: Internal error: Interrupt Controller Driver has no support for nesting fast interrupts"
+	        }
+	        if {$cascade == 1 && $nested == 1} {
+			puts "ERROR: Internal error: Interrupt Controller Driver has no support for nesting interrupts in Cascaded mode"
+	        }
+	}
+
+	::hsi::utils::define_if_all $drv_handle "xparameters.h" "XIntc" "C_HAS_IPR" "C_HAS_SIE" "C_HAS_CIE" "C_HAS_IVR" "C_HAS_ILR"
+	::hsi::utils::define_include_file $drv_handle "xparameters.h" "XIntc" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_KIND_OF_INTR" "C_HAS_FAST" "C_IVAR_RESET_VALUE" "C_NUM_INTR_INPUTS"
+
+
+	# Define XPAR_SINGLE_DEVICE_ID
+
+	if {$count == 1} {
+	    ::hsi::utils::define_with_names $drv_handle [::hsi::utils::get_common_driver_ips $drv_handle] "xparameters.h" "XPAR_INTC_SINGLE_BASEADDR" "C_BASEADDR" "XPAR_INTC_SINGLE_HIGHADDR" "C_HIGHADDR" "XPAR_INTC_SINGLE_DEVICE_ID" "DEVICE_ID"
+	}
+
+
+	set config_inc [::hsi::utils::open_include_file "xparameters.h"]
+
+	# Generate config table, vector tables
+	intc_define_config_file $drv_handle $periphs $config_inc
+
+	close $config_inc
+
+	# Generate canonical xparameters
+	xdefine_canonical_xpars $drv_handle "xparameters.h" "Intc" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_KIND_OF_INTR" "C_HAS_FAST" "C_IVAR_RESET_VALUE" "C_NUM_INTR_INPUTS"
+}
+
+
+##########################################################################
+# Generate Configuration C file xintc_g.c
+# This file has the Config Table and vector tables for each intc instance
+# as required by Xilinx intc driver
+##########################################################################
+
+proc intc_define_config_file {drv_handle periphs config_inc} {
+
+	variable interrupt_handlers
+	variable default_interrupt_handler
+	variable cascade
+
+	# set isr_options to be XIN_SVC_SGL_ISR_OPTION as defined in xintc.h
+	set isr_options XIN_SVC_SGL_ISR_OPTION
+	set file_name "xintc_g.c"
+	set drv_string "XIntc"
+	set args [list "DEVICE_ID" "C_BASEADDR" "C_KIND_OF_INTR" "C_HAS_FAST" "C_IVAR_RESET_VALUE" "C_NUM_INTR_INPUTS"]
+	set filename [file join "src" $file_name]
+	file delete $filename
+	set config_file [open $filename w]
+	::hsi::utils::write_c_header $config_file "Driver configuration"
+	puts $config_file "#include \"xparameters.h\""
+	puts $config_file "#include \"[string tolower $drv_string].h\""
+	puts $config_file "\n"
+
+	set tmp_filename [file join "src" "tmpconfig.c"]
+    set tmp_config_file [open $tmp_filename w]
+
+    puts $tmp_config_file "\n/*"
+    puts $tmp_config_file "* The configuration table for devices"
+    puts $tmp_config_file "*/\n"
+    puts $tmp_config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string]
+    puts $tmp_config_file "\{"
+
+    set start_comma ""
+    foreach periph $periphs {
+        set periph_name [string toupper [get_property NAME $periph ]]
+	set xpar_periph_name [::hsi::utils::format_xparam_name $periph_name]
+
+	if {$cascade == 1} {
+            puts $config_inc [format "#define XPAR_%s_%s %d" [string toupper [common::get_property NAME $periph ]] "TYPE" [get_intctype $periph]]
+        } else {
+            puts $config_inc [format "#define XPAR_%s_%s %d" [string toupper [common::get_property NAME $periph ]] "TYPE" $cascade]
+        }
+        puts $tmp_config_file [format "%s\t\{" $start_comma]
+            set comma ""
+            foreach arg $args {
+                # Check if this is a driver parameter or a peripheral parameter
+                set value [common::get_property CONFIG.$arg $drv_handle ]
+            if {[llength $value] == 0} {
+                puts -nonewline $tmp_config_file [format "%s\t\t%s" $comma [::hsi::utils::get_ip_param_name $periph $arg]]
+            } else {
+                puts -nonewline $tmp_config_file [format "%s\t\t%s" $comma [::hsi::utils::get_driver_param_name $drv_string $arg]]
+            }
+            set comma ",\n"
+        }
+        # add the OPTIONS as an arg to the config table - default OPTIONS value is XIN_SVC_SGL_ISR_OPTION
+		puts -nonewline $tmp_config_file [format "%s\t\t%s" $comma $isr_options]
+		puts -nonewline $tmp_config_file ",\n\t\t"
+		puts -nonewline $tmp_config_file [format "XPAR_%s_%s" [string toupper [common::get_property NAME $periph]] "TYPE"]
+
+		# generate the vector table for this intc instance
+		intc_define_vector_table $periph $config_inc $tmp_config_file
+
+		puts $config_inc "\n/******************************************************************/\n"
+
+		puts -nonewline $tmp_config_file "\n\t\}"
+		set start_comma ",\n"
+    }
+	puts $tmp_config_file "\n\};"
+	close $tmp_config_file
+
+	# Write out the extern definitions of handlers...
+	foreach elem [array names interrupt_handlers] {
+		puts $config_file [format "extern void %s (void *);" $elem ]
+	}
+
+	# copy over the tmp_config_file contents to config_file
+	set tmp_config_file [open $tmp_filename r]
+	while {![eof $tmp_config_file]} {
+		gets $tmp_config_file line
+	puts $config_file $line
+	}
+	close $tmp_config_file
+	file delete -force $tmp_filename
+
+	close $config_file
+	}
+
+proc intc_define_vector_table {periph config_inc config_file} {
+
+	variable interrupt_handlers
+	variable default_interrupt_handler
+	variable cascade
+    variable source_port_name
+    variable source_name
+    variable source_port_type
+    variable source_driver
+    variable source_interrupt_handler
+    variable source_interrupt_id
+    variable total_source_intrs
+
+    #update global array of Interrupt sources for this periph
+    intc_update_source_array $periph
+
+	set periph_name [common::get_property NAME $periph]
+    set interrupt_pin [hsi::get_pins -of_objects $periph intr]
+
+    # Get pins/ports that are driving the interrupt
+	lappend source_pins
+	set source_pins [::hsi::utils::get_source_pins $interrupt_pin]
+
+    set num_intr_inputs [common::get_property CONFIG.C_NUM_INTR_INPUTS $periph]
+    #calculate the total interrupt sources
+
+    set total_intr_ports [::hsi::utils::get_connected_pin_count $interrupt_pin]
+
+    if {$num_intr_inputs != $total_intr_ports} {
+        puts "ERROR: Internal error: Num intr inputs $num_intr_inputs not the same as length of ::hsi::utils::get_interrupt_sources [llength $source_pins] hsi_error"
+	return
+    }
+
+    #Check if default_interrupt_handler has to have an extern definition
+    if {[array size interrupt_handlers] < $total_source_intrs } {
+        intc_add_handler $default_interrupt_handler
+    }
+
+    puts -nonewline $config_file ",\n\t\t\{"
+    set comma "\n"
+
+    for {set i 0} {$i < $total_source_intrs} {incr i} {
+        set source_ip $source_name($i)
+        if { [llength $source_ip] != 0 && [llength [hsi::get_cells -hier $source_ip]] != 0} {
+           set ip_name [common::get_property IP_NAME [hsi::get_cells -hier $source_ip]]
+           if { [string compare -nocase $ip_name "xlconstant"] == 0 } {
+              #do no generate interrupt handler entries for xlconstant
+              continue
+           }
+        }
+        puts $config_file [format "%s\t\t\t\{" $comma ]
+        puts $config_file [format "\t\t\t\t%s," $source_interrupt_handler($i) ]
+        if {[llength $source_name($i)] == 0} {
+            puts $config_file "\t\t\t\t(void *)XNULL"
+        } else {
+            set sname [string toupper $source_name($i)]
+	    set source_xparam_name [::hsi::utils::format_xparam_name $sname]
+	    set pname [string toupper $periph_name]
+	    set periph_xparam_name [::hsi::utils::format_xparam_name $pname]
+	    puts $config_inc [format "#define XPAR_%s_%s_MASK %#08X" $source_xparam_name [string toupper $source_port_name($i)] [expr 1 << $i]]
+	    if {$cascade ==1} {
+                puts $config_inc [format "#define XPAR_%s_%s_%s_INTR %d" [string toupper $periph_name] [string toupper $source_name($i)] [string toupper $source_port_name($i)] $source_interrupt_id($i)]
+            } else {
+                puts $config_inc [format "#define XPAR_%s_%s_%s_INTR %d" [string toupper $periph_name] [string toupper $source_name($i)] [string toupper $source_port_name($i)] $i]
+            }
+            if {[string compare -nocase "global" $source_port_type($i) ] != 0 && \
+                [string compare $source_interrupt_handler($i) $default_interrupt_handler ] != 0} {
+                puts $config_file [format "\t\t\t\t(void *) %s" $source_handler_arg($i)]
+            } else {
+                puts $config_file "\t\t\t\t(void *) XNULL"
+            }
+        }
+        puts -nonewline $config_file "\t\t\t\}"
+        set comma ",\n"
+    }
+    puts $config_file "\n\t\t\}"
+}
+
+################################################
+# This procedure creates a unique list of
+# handlers that needs to have an extern defn.
+# in xparameters.h
+################################################
+proc intc_add_handler {handler} {
+
+    variable interrupt_handlers
+
+    set interrupt_handlers($handler) 1
+}
+
+
+#
+# Given a list of arguments, define each as a canonical constant name, using
+# the driver name, in an include file.
+#
+proc xdefine_canonical_xpars {drv_handle file_name drv_string args} {
+
+   variable cascade
+
+   # Open include file
+    set file_handle [::hsi::utils::open_include_file $file_name]
+
+    # Get all the peripherals connected to this driver
+    set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
+
+    # Get the names of all the peripherals connected to this driver
+    foreach periph $periphs {
+        set peripheral_name [string toupper [common::get_property NAME $periph]]
+        lappend peripherals $peripheral_name
+    }
+
+    # Get possible canonical names for all the peripherals connected to this driver
+    set device_id 0
+    foreach periph $periphs {
+        set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]]
+        lappend canonicals $canonical_name
+
+        # Create a list of IDs of the peripherals whose hardware instance name
+        # doesn't match the canonical name. These IDs can be used later to
+        # generate canonical definitions
+        if { [lsearch $peripherals $canonical_name] < 0 } {
+              lappend indices $device_id
+        }
+        incr device_id
+    }
+
+    set i 0
+    foreach periph $periphs {
+        set periph_name [string toupper [common::get_property NAME $periph]]
+
+        # Generate canonical definitions only for the peripherals whose
+        # canonical name is not the same as hardware instance name
+        if { [lsearch $canonicals $periph_name] < 0 } {
+            puts $file_handle "/* Canonical definitions for peripheral $periph_name */"
+            set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]]
+
+            foreach arg $args {
+                set lvalue [::hsi::utils::get_driver_param_name $canonical_name $arg]
+
+    # The commented out rvalue is the name of the instance-specific constant
+    #           set rvalue [::hsi::utils::get_ip_param_name $periph $arg]
+
+                # The rvalue set below is the actual value of the parameter
+                set rvalue [::hsi::utils::get_param_value $periph $arg]
+                if {[llength $rvalue] == 0} {
+                     set rvalue 0
+                }
+                set rvalue [::hsi::utils::format_addr_string $rvalue $arg]
+
+                puts $file_handle "#define $lvalue $rvalue"
+
+            }
+            if {$cascade == 1} {
+		puts $file_handle "#define [::hsi::utils::get_driver_param_name $canonical_name "INTC_TYPE"] [get_intctype $periph]"
+            } else {
+		puts $file_handle "#define [::hsi::utils::get_driver_param_name $canonical_name "INTC_TYPE"] $cascade"
+            }
+            puts $file_handle ""
+            incr i
+        }
+    }
+
+    #
+    # Now redefine the Interrupt ID constants
+    #
+    xredefine_intc $drv_handle $file_handle
+
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+################################################
+#
+# intc redefines
+#
+################################################
+proc xredefine_intc {drvhandle config_inc} {
+    variable source_port_name
+    variable source_name
+    variable source_port_type
+    variable source_driver
+    variable source_interrupt_handler
+    variable source_interrupt_id
+    variable total_source_intrs
+
+
+    # Next define interrupt IDs for each connected peripheral
+
+    set periphs [::hsi::utils::get_common_driver_ips $drvhandle]
+    set device_id 0
+    set periph_name [string toupper "intc"]
+
+    foreach periph $periphs {
+        #update global array of Interrupt sources for this periph
+        intc_update_source_array $periph
+
+        lappend source_list
+        for {set j 0 } { $j < $total_source_intrs   } { incr j} {
+            lappend source_list $source_name($j)
+        }
+
+
+        # Get the edk based name of peripheral for printing redefines
+        set periph_ip_name [common::get_property NAME $periph]
+
+        set num_intr_inputs [common::get_property CONFIG.C_NUM_INTR_INPUTS $periph]
+        for {set i 0} {$i < $num_intr_inputs} {incr i} {
+
+            if {[string compare -nocase $source_name($i) "system"] == 0} {
+                continue
+            }
+            set drv [hsi::get_drivers -filter "HW_INSTANCE==$source_name($i)"]
+
+            if {[llength $source_name($i)] != 0 && [llength $drv] != 0} {
+
+                set instance [xfind_instance $drv $source_name($i)]
+                set drvname [common::get_property NAME $drv]
+
+                #
+                # Handle reference cores, which have non-reference driver names
+                #
+                if {[string compare -nocase $drvname "touchscreen_ref"] == 0} {
+                    set drvname "touchscreen"
+                } elseif {[string compare -nocase $drvname "ps2_ref"] == 0} {
+                    set drvname "ps2"
+                    set instance [expr $instance*2]
+                    if {[string match -nocase  "*SYS_INTR2" $source_port_name($i)] == 1} {
+                        incr instance
+                    }
+                }
+
+                #
+                # Define the interrupt vector IDs in xparameters.h for each core
+                # that is connected to this intc.
+                #
+                set drvname [string toupper $drvname]
+
+                #
+                # Treat sources with multiple interrupt ports slightly different
+                # by including the interrupt port name in the canonical constant
+                # name
+                #
+                if { [lcount $source_list $source_name($i)] > 1} {
+                    set port_name [string toupper $source_port_name($i)]
+
+                    #
+                    # If there are multiple interrupt ports for axi_ethernet, do not include
+                    # the port name in the canonical name, for the port "INTERRUPT". Other ports
+                    # will have the port name in the canonical name. This is to make sure that
+                    # the canonical name for the port INTERRUPT will remain same irrespective of
+                    # whether the design has a single interrupt port or multiple interrupt ports
+                    #
+                    if {[string compare -nocase $drvname "axiethernet"] == 0} {
+                        if {[string compare -nocase $port_name "INTERRUPT"] == 0} {
+                            set first_part [format "#define XPAR_%s_%s_%s_%s_VEC_ID" $periph_name $device_id $drvname $instance]
+                        } else {
+                            set first_part [format "#define XPAR_%s_%s_%s_%s_%s_VEC_ID" $periph_name $device_id $drvname $instance $port_name]
+                        }
+                    } else {
+                        set first_part [format "#define XPAR_%s_%s_%s_%s_%s_VEC_ID" $periph_name $device_id $drvname $instance $port_name]
+                    }
+                } else {
+                    set first_part [format "#define XPAR_%s_%s_%s_%s_VEC_ID" $periph_name $device_id $drvname $instance]
+                }
+	        set second_part [format "XPAR_%s_%s_%s_INTR" [string toupper $periph_ip_name] [string toupper $source_name($i)] [string toupper $source_port_name($i)] ]
+
+                if {[string compare -nocase $drvname "generic"] != 0} {
+                    set first_part_xparam_name [::hsi::utils::format_xparam_name $first_part]
+                    set second_part_xparam_name [::hsi::utils::format_xparam_name $second_part]
+                    puts $config_inc "$first_part_xparam_name $second_part_xparam_name"
+                }
+            }
+        }
+        incr device_id
+    }
+}
+
+###################################################################
+#
+# Get the number of elements in the given list that match the
+# given entry.  Assume elements are strings.
+#
+###################################################################
+proc lcount {list match_entry} {
+
+    set len [llength $list]
+    set count 0
+
+    for {set i 0} {$i < $len} {incr i} {
+        set entry [lindex $list $i]
+        if { [string compare -nocase $entry $match_entry] == 0} {
+            incr count
+        }
+    }
+
+    return $count
+}
+
+
+###################################################################
+#
+# Get the HW instance number for a particular device. This will be used to enumerate
+# the vector ID defines if more than one interrupt from the core is connected to the
+# interrupt controller.
+#
+###################################################################
+proc xfind_instance {drvhandle instname} {
+
+    set instlist [::hsi::utils::get_common_driver_ips $drvhandle]
+    set i 0
+    foreach inst $instlist {
+        set name [common::get_property NAME $inst]
+        if {[string compare -nocase $instname $name] == 0} {
+            return $i
+        }
+        incr i
+    }
+    set i 0
+    return $i
+}
+
+###################################################################################
+#
+# Checks whether system has Cascade interrupt controllers
+#
+###################################################################################
+proc check_cascade {drv_handle} {
+	set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
+    foreach periph $periphs {
+		set i 0
+		set source_pins [::hsi::utils::get_interrupt_sources $periph]
+        foreach source_pin $source_pins {
+            set source_pin_name($i) [common::get_property NAME $source_pin]
+            if { [::hsi::utils::is_external_pin $source_pin] } {
+                continue
+            }
+            set source_periph [hsi::get_cells -of_objects $source_pin ]
+            set source_type [common::get_property IP_TYPE $source_periph]
+            if {[string compare -nocase $source_type "INTERRUPT_CNTLR"] == 0} {
+		return 1
+            }
+        }
+    }
+	return 0
+}
+
+##################################################################
+#
+# Returns Interrupt controller type
+# 1 - primary instance
+# 2 - secondary instance
+# 3 - last instance
+#
+##################################################################
+
+proc get_intctype {periph} {
+		set iscascade [::hsi::utils::get_param_value $periph "C_EN_CASCADE_MODE"]
+		set ismaster [::hsi::utils::get_param_value $periph "C_CASCADE_MASTER"]
+		if {$iscascade == 1 && $ismaster == 1} {
+			set retval 1
+		} elseif {$iscascade == 1 && $ismaster == 0} {
+			 set retval 2
+		} elseif {$iscascade == 0 && $ismaster == 0} {
+			 set retval 3
+		} else {
+			error "ERROR: The C_CASCADE_MASTER is allowed to set only when the C_EN_CASCADE_MODE is set to 1"
+		}
+
+		return $retval
+}
+
+###############################################################################
+# this proc traverse all the interrupt source of peripheral and create a array
+# will the the details
+###############################################################################
+proc intc_update_source_array {periph} {
+    variable default_interrupt_handler
+    variable source_port_name
+    variable source_name
+    variable source_port_type
+    variable source_driver
+    variable source_interrupt_handler
+    variable source_interrupt_id
+    variable total_source_intrs
+
+    array unset source_port_name
+    array unset source_name
+    array unset source_port_type
+    array unset source_driver
+    array unset source_interrupt_handler
+    array unset source_interrupt_id
+
+	lappend source_pins
+	set source_pins [::hsi::utils::get_interrupt_sources $periph]
+    set intr_cnt 0
+    foreach source_pin $source_pins {
+        #default value as per external processor
+        set t_source_port_name          [common::get_property NAME $source_pin]
+        set t_source_name               "system"
+        set t_ip_name                   ""
+        set t_port_type                 "global"
+        set t_source_driver             ""
+        set t_source_interrupt_handler  $default_interrupt_handler
+        set t_source_intrrupt_id        "-1"
+
+        #if interrupt is coming from IP, update it.
+        if { [::hsi::utils::is_external_pin $source_pin] == 0} {
+            set source_periph   [hsi::get_cells -of_objects $source_pin]
+            set t_source_name   [common::get_property NAME $source_periph]
+            set t_ip_name       $t_source_name
+            set t_port_type     "local"
+            set t_source_driver [hsi::get_drivers -filter "HW_INSTANCE==$t_source_name"]
+        }
+        set port_intr_id [::hsi::utils::get_interrupt_id $t_ip_name $source_pin]
+        if { [llength $port_intr_id ] > 1 } {
+            #this is the case of vector interrupt port
+            set j 0
+            foreach pin_id $port_intr_id {
+                set source_port_name($intr_cnt)         "${t_source_port_name}_$j"
+                set source_name($intr_cnt)              $t_source_name
+                set source_port_type($intr_cnt)         $t_port_type
+                set source_driver($intr_cnt)            $t_source_driver
+                set source_interrupt_handler($intr_cnt) $t_source_interrupt_handler
+                set source_interrupt_id($intr_cnt)      $pin_id
+                incr intr_cnt
+                incr j
+            }
+        } else {
+            set source_port_name($intr_cnt)         "${t_source_port_name}"
+            set source_name($intr_cnt)              $t_source_name
+            set source_port_type($intr_cnt)          $t_port_type
+            set source_driver($intr_cnt)            $t_source_driver
+            set source_interrupt_handler($intr_cnt) $t_source_interrupt_handler
+            set source_interrupt_id($intr_cnt)      $port_intr_id
+            incr intr_cnt
+        }
+    }
+    set total_source_intrs $intr_cnt
+}
diff --git a/thirdparty/xilinx/orig/intc_v3_4/data/intc_header.h b/thirdparty/xilinx/orig/intc_v3_4/data/intc_header.h
new file mode 100644
index 000000000..4a2e393e1
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/data/intc_header.h
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef INTC_HEADER_H		/* prevent circular inclusions */
+#define INTC_HEADER_H		/* by using protection macros */
+
+#include "xil_assert.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+int IntcSelfTestExample(u16 DeviceId);
+int IntcInterruptSetup(XIntc *IntcInstancePtr, u16 DeviceId);
+
+#endif
diff --git a/thirdparty/xilinx/orig/intc_v3_4/data/intc_tapp.tcl b/thirdparty/xilinx/orig/intc_v3_4/data/intc_tapp.tcl
new file mode 100644
index 000000000..5fd38a4d1
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/data/intc_tapp.tcl
@@ -0,0 +1,206 @@
+###############################################################################
+#
+# Copyright (C) 2004 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ------------------------------------
+# 3.0      adk    12/10/13 Updated as per the New Tcl API's
+# 3.1      adk    8/4/14   Fix the CR:783248 Modified the Cascade logic
+#			   in the app tcl
+##############################################################################
+
+## @BEGIN_CHANGELOG EDK_I_SP1
+##
+##  - Initial Revision
+##
+## 01/30/13 bss Modified script to skip tests for Slave controllers in Cascade
+##              mode
+## 02/26/13 bss Modified get_intr procedure to support Vivado designs
+##
+## @END_CHANGELOG
+
+# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
+
+# -----------------------------------------------------------------
+# Software Project Types (swproj):
+#   0 : MemoryTest - Calls basic  memorytest routines from common driver dir
+#   1 : PeripheralTest - Calls any existing polled_example and/or selftest
+# -----------------------------------------------------------------
+
+# -----------------------------------------------------------------
+# TCL Procedures:
+# -----------------------------------------------------------------
+
+
+
+
+proc gen_include_files {swproj mhsinst} {
+
+   if {$swproj == 0} {
+	return ""
+    }
+
+    if {$swproj == 1} {
+	    set inc_file_lines {xintc.h intc_header.h}
+	    return $inc_file_lines
+    }
+}
+
+proc gen_src_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {examples/xintc_tapp_example.c data/intc_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_testfunc_def {swproj mhsinst} {
+    return ""
+}
+
+proc gen_init_code {swproj mhsinst} {
+  return ""
+}
+
+proc gen_testfunc_call {swproj mhsinst} {
+
+  if {$swproj == 0} {
+    return ""
+  }
+
+set cascade [check_cascade $mhsinst]
+if {$cascade == 1} {
+	set iscascade [common::get_property CONFIG.C_EN_CASCADE_MODE $mhsinst]
+	set ismaster [common::get_property CONFIG.C_CASCADE_MASTER $mhsinst]
+	if {!($iscascade == 1 && $ismaster == 1)} {
+		return ""
+	}
+ }
+
+  set ipname [common::get_property NAME  $mhsinst]
+  set deviceid [::hsi::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
+  set stdout [common::get_property CONFIG.STDOUT [hsi::get_os]]
+  if { $stdout == "" || $stdout == "none" } {
+       set hasStdout 0
+  } else {
+       set hasStdout 1
+  }
+  set intcvar intc
+  set testfunc_call ""
+
+  if {${hasStdout} == 0} {
+
+      append testfunc_call "
+
+   {
+      int status;
+
+      status = IntcSelfTestExample(${deviceid});
+
+   }"
+
+      set ifintr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
+      if {$ifintr != 0} {
+          append testfunc_call "
+
+   {
+       int Status;
+
+       Status = IntcInterruptSetup(&${intcvar}, ${deviceid});
+
+   }"
+      }
+
+  } else {
+
+      append testfunc_call "
+
+   {
+      int status;
+
+      print(\"\\r\\n Running IntcSelfTestExample() for ${ipname}...\\r\\n\");
+
+      status = IntcSelfTestExample(${deviceid});
+
+      if (status == 0) {
+         print(\"IntcSelfTestExample PASSED\\r\\n\");
+      }
+      else {
+         print(\"IntcSelfTestExample FAILED\\r\\n\");
+      }
+   }"
+
+      set ifintr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
+      if {$ifintr != 0} {
+
+          append testfunc_call "
+
+   {
+       int Status;
+
+       Status = IntcInterruptSetup(&${intcvar}, ${deviceid});
+       if (Status == 0) {
+          print(\"Intc Interrupt Setup PASSED\\r\\n\");
+       }
+       else {
+         print(\"Intc Interrupt Setup FAILED\\r\\n\");
+      }
+   }"
+
+      }
+  }
+
+  return $testfunc_call
+
+}
+
+
+proc check_cascade {mhsinst} {
+	set periphs [::hsi::utils::get_common_driver_ips $mhsinst]
+    foreach periph $periphs {
+		set i 0
+		set source_pins [::hsi::utils::get_interrupt_sources $periph]
+        foreach source_pin $source_pins {
+            set source_pin_name($i) [common::get_property NAME $source_pin]
+            if { [::hsi::utils::is_external_pin $source_pin] } {
+                continue
+            }
+            set source_periph [hsi::get_cells -of_objects $source_pin ]
+            set source_type [common::get_property IP_TYPE $source_periph]
+            if {[string compare -nocase $source_type "INTERRUPT_CNTLR"] == 0} {
+		return 1
+            }
+        }
+    }
+	return 0
+}
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/HTML_custom.css b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/HTML_custom.css
new file mode 100644
index 000000000..26defe1a8
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/HTML_custom.css
@@ -0,0 +1,1430 @@
+/* The standard CSS for doxygen 1.8.5 */
+
+body{
+	background: none repeat scroll 0 0 #FFFFFF;
+	color: #51626F;
+	font-family: arial,sans-serif !important;
+    	font-size: 75% !important;
+    	font-weight: normal !important;
+    	margin-left: 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+.contents, .textblock {
+font: 400 12px/15px arial,sans-serif;
+}
+.textblock ul, .contents ul{ 
+	margin: 5px 0;
+	padding: 0;
+}
+.textblockol {
+	margin:5px 15px; 
+	padding:0;
+	list-style-image: none; 
+}
+.textblock li, .contents li {
+	margin: 0 0 2px 15px;
+    	padding: 0 0 2px 2px;
+}
+
+/* For hiding RHS TOC 
+.toc{
+display:none;
+}*/
+/* For hiding RHS TOC*/ 
+
+For hiding Nav Bar
+.navpath, #nav-path{
+display:none;
+}
+/* For hiding Nav Bar*/
+/* For hiding extra navrows */
+#navrow2, #navrow3, #navrow4, #navrow5 {
+display:none;
+}
+/* @group Heading Levels */
+
+.title {
+	font: 400 14px/28px arial,sans-serif;
+	font-size: 150%;
+	font-weight: bold;
+	margin: 9px 2px;
+	text-align: left;
+}
+
+h2, h3 {
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+    text-indent: 0 !important;
+}
+h4, h5{
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+}
+h5{
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+h6{
+    color: #E66A08 !important;
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+p {
+    padding-bottom: 0px !important;
+	font: 400 12px/15px arial,sans-serif;
+}
+li p {
+    padding-bottom: 0px !important;
+	margin: 0px;
+}
+
+h1, h2.groupheader {
+    clear: both !important;
+    color: #627178 !important;
+    font-size: 1.4em !important;
+    font-weight: bold !important;
+    line-height: 28px !important;
+    margin-top: 0.6em !important;
+}
+
+h1, h2, h3, h4, h5, h6 {
+	-webkit-transition: text-shadow 0.5s linear;
+	-moz-transition: text-shadow 0.5s linear;
+	-ms-transition: text-shadow 0.5s linear;
+	-o-transition: text-shadow 0.5s linear;
+	transition: text-shadow 0.5s linear;
+	margin-right: 15px;
+}
+
+h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {
+	text-shadow: 0 0 15px cyan;
+}
+
+dt {
+	font-weight: bold;
+}
+
+
+/*Hiding Tabs - Tushar
+div.tabs 
+{ 
+    visibility: hidden; 
+} */
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #017bba;
+	font-weight: normal;
+	text-decoration: none;
+	/*font: 400 12px/15px;*/
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code, a.code:visited, a.line, a.line:visited {
+	color: #4665A2;
+}
+
+a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {
+	color: #4665A2; 
+	/*font: 400 12px/15px;*/
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+pre.fragment {
+        border: 0px solid #C4CFE5;
+        background-color: #FFFFFF;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        font-size:  9pt;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 105%;
+}
+
+div.fragment {
+        padding: 0px;
+        margin: 0px;
+	background-color: #FFFFFF;
+	border: 0px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 13px;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+div.line.glow {
+	background-color: cyan;
+	box-shadow: 0 0 10px cyan;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #51626F
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: cyan;
+	box-shadow: 0 0 15px cyan;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
+        border-bottom: 1px solid #DEE4F0;
+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+	font-size: 80%;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+        -webkit-transition: box-shadow 0.5s linear;
+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
+        display: table !important;
+        width: 100%;
+}
+
+.memitem.glow {
+         box-shadow: 0 0 15px cyan;
+}
+
+.memname {
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memname td {
+	vertical-align: bottom;
+}
+
+.memproto, dl.reflist dt {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #E66A08 !important;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+.memdoc, dl.reflist dd {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 6px 10px 2px 10px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        background-image:url('nav_g.png');
+        background-repeat:repeat-x;
+        background-color: #FFFFFF;
+        /* opera specific markup */
+        border-bottom-left-radius: 4px;
+        border-bottom-right-radius: 4px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 4px;
+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 4px;
+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
+        margin: 0px 0px 10px 0px;
+        padding: 5px;
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+.paramname code {
+        line-height: 14px;
+}
+
+.params, .retval, .exception, .tparams {
+        margin-left: 0px;
+        padding-left: 0px;
+		font: 400 12px/15px arial,sans-serif;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+table.mlabels {
+	border-spacing: 0px;
+}
+
+td.mlabels-left {
+	width: 100%;
+	padding: 0px;
+}
+
+td.mlabels-right {
+	vertical-align: bottom;
+	padding: 0px;
+	white-space: nowrap;
+}
+
+span.mlabels {
+        margin-left: 8px;
+}
+
+span.mlabel {
+        background-color: #728DC1;
+        border-top:1px solid #5373B4;
+        border-left:1px solid #5373B4;
+        border-right:1px solid #C4CFE5;
+        border-bottom:1px solid #C4CFE5;
+	text-shadow: none;
+	color: white;
+	margin-right: 4px;
+	padding: 2px 3px;
+	border-radius: 3px;
+	font-size: 7pt;
+	white-space: nowrap;
+	vertical-align: middle;
+}
+
+
+
+/* @end */
+
+/* these are for tree view when not used as main index */
+
+div.directory {
+        margin: 10px 0px;
+        border-top: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        width: 100%;
+}
+
+.directory table {
+        border-collapse:collapse;
+}
+
+.directory td {
+        margin: 0px;
+        padding: 0px;
+	vertical-align: top;
+}
+
+.directory td.entry {
+        white-space: nowrap;
+        padding-right: 6px;
+	padding-top: 3px;
+}
+
+.directory td.entry a {
+        outline:none;
+}
+
+.directory td.entry a img {
+        border: none;
+}
+
+.directory td.desc {
+        width: 100%;
+        padding-left: 6px;
+	padding-right: 6px;
+	padding-top: 3px;
+	border-left: 1px solid rgba(0,0,0,0.05);
+}
+
+.directory tr.even {
+	padding-left: 6px;
+	background-color: #F7F8FB;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+.directory .levels {
+        white-space: nowrap;
+        width: 100%;
+        text-align: right;
+        font-size: 9pt;
+}
+
+.directory .levels span {
+        cursor: pointer;
+        padding-left: 2px;
+        padding-right: 2px;
+	color: #3D578C;
+}
+
+div.dynheader {
+        margin-top: 8px;
+	-webkit-touch-callout: none;
+	-webkit-user-select: none;
+	-khtml-user-select: none;
+	-moz-user-select: none;
+	-ms-user-select: none;
+	user-select: none;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+        margin-top: 4px;
+        margin-bottom: 4px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #CCCCCC;
+	color: #51626F;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+}
+table.fieldtable {
+        /*width: 100%;*/
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: File List</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li class="current"><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">File List</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xintc_8c.html" target="_self">xintc.c</a></td><td class="desc"></td></tr>
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+<tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xintc__g_8c.html" target="_self">xintc_g.c</a></td><td class="desc"></td></tr>
+<tr id="row_3_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xintc__i_8h.html" target="_self">xintc_i.h</a></td><td class="desc"></td></tr>
+<tr id="row_4_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xintc__intr_8c.html" target="_self">xintc_intr.c</a></td><td class="desc"></td></tr>
+<tr id="row_5_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xintc__l_8c.html" target="_self">xintc_l.c</a></td><td class="desc"></td></tr>
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+<tr id="row_8_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xintc__selftest_8c.html" target="_self">xintc_selftest.c</a></td><td class="desc"></td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/functions.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/functions.html
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+++ b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/functions.html
@@ -0,0 +1,103 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="functions.html"><span>All</span></a></li>
+      <li><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div><ul>
+<li>AckBeforeService
+: <a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">XIntc_Config</a>
+</li>
+<li>BaseAddress
+: <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc</a>
+, <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config</a>
+</li>
+<li>CfgPtr
+: <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc</a>
+</li>
+<li>DeviceId
+: <a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config</a>
+</li>
+<li>FastIntr
+: <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config</a>
+</li>
+<li>HandlerTable
+: <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config</a>
+</li>
+<li>IntcType
+: <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config</a>
+</li>
+<li>IntVectorAddr
+: <a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc</a>
+</li>
+<li>IsStarted
+: <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc</a>
+</li>
+<li>NumberofIntrs
+: <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config</a>
+</li>
+<li>Options
+: <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config</a>
+</li>
+<li>UnhandledInterrupts
+: <a class="el" href="struct_x_intc.html#abf06c903e68a5569cdf238b185d83ff5">XIntc</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/functions_vars.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/functions_vars.html
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+++ b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/functions_vars.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: Data Fields - Variables</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>AckBeforeService
+: <a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">XIntc_Config</a>
+</li>
+<li>BaseAddress
+: <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc</a>
+, <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config</a>
+</li>
+<li>CfgPtr
+: <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc</a>
+</li>
+<li>DeviceId
+: <a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config</a>
+</li>
+<li>FastIntr
+: <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config</a>
+</li>
+<li>HandlerTable
+: <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config</a>
+</li>
+<li>IntcType
+: <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config</a>
+</li>
+<li>IntVectorAddr
+: <a class="el" href="struct_x_intc___config.html#a3680484ddceab0bc26f7a4ac2e3b7852">XIntc_Config</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc</a>
+</li>
+<li>IsStarted
+: <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc</a>
+</li>
+<li>NumberofIntrs
+: <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config</a>
+</li>
+<li>Options
+: <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config</a>
+</li>
+<li>UnhandledInterrupts
+: <a class="el" href="struct_x_intc.html#abf06c903e68a5569cdf238b185d83ff5">XIntc</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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@@ -0,0 +1,157 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XIN_REAL_MODE
+: <a class="el" href="group__intc__v3__4.html#ga56b4aa3cb483ea5c882e2e36a4800af2">xintc.h</a>
+</li>
+<li>XIN_SIMULATION_MODE
+: <a class="el" href="group__intc__v3__4.html#gaefd5527cecdc1a6444b624d1e1a2514f">xintc.h</a>
+</li>
+<li>XIN_SVC_SGL_ISR_OPTION
+: <a class="el" href="group__intc__v3__4.html#gaf4bce8e2035f391b702686e49c66c839">xintc.h</a>
+</li>
+<li>XIntc_AckIntr
+: <a class="el" href="group__intc__v3__4.html#ga4f699042980f8453713171959183fc49">xintc_l.h</a>
+</li>
+<li>XIntc_Acknowledge()
+: <a class="el" href="group__intc__v3__4.html#ga8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.c</a>
+</li>
+<li>XIntc_ConfigTable
+: <a class="el" href="group__intc__v3__4.html#ga2187e69fdc39ef945a992d2602d0c1c1">xintc_g.c</a>
+, <a class="el" href="group__intc__v3__4.html#ga6afbe6b28aa729c753744cba40ecf5b3">xintc_i.h</a>
+</li>
+<li>XIntc_Connect()
+: <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084">xintc.c</a>
+</li>
+<li>XIntc_ConnectFastHandler()
+: <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">xintc.c</a>
+</li>
+<li>XIntc_DeviceInterruptHandler()
+: <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">xintc_l.c</a>
+</li>
+<li>XIntc_Disable()
+: <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">xintc.c</a>
+</li>
+<li>XIntc_DisableIntr
+: <a class="el" href="group__intc__v3__4.html#ga5df77bd3561a105f1d6b1837762db956">xintc_l.h</a>
+</li>
+<li>XIntc_Disconnect()
+: <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">xintc.c</a>
+</li>
+<li>XIntc_Enable()
+: <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">xintc.c</a>
+</li>
+<li>XIntc_EnableIntr
+: <a class="el" href="group__intc__v3__4.html#gad35ec3b9b658f26d989b19783954683e">xintc_l.h</a>
+</li>
+<li>XIntc_GetIntrStatus
+: <a class="el" href="group__intc__v3__4.html#ga13c828dcbbdc3441c8abaded5cda888b">xintc_l.h</a>
+</li>
+<li>XIntc_GetOptions()
+: <a class="el" href="group__intc__v3__4.html#ga6fdbe96b1db87f0c78e68da8bc767a69">xintc.h</a>
+</li>
+<li>XIntc_Initialize()
+: <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">xintc.c</a>
+</li>
+<li>XIntc_InterruptHandler()
+: <a class="el" href="group__intc__v3__4.html#ga635187ed756cee70b4b4051560cbd7bc">xintc.h</a>
+</li>
+<li>XIntc_LookupConfig()
+: <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">xintc.c</a>
+</li>
+<li>XIntc_MasterDisable
+: <a class="el" href="group__intc__v3__4.html#ga93be82188a607b0a13a13a96c5787bb6">xintc_l.h</a>
+</li>
+<li>XIntc_MasterEnable
+: <a class="el" href="group__intc__v3__4.html#gaf2aeec4bbc6e0c5ca2268e5d7c7dd5ce">xintc_l.h</a>
+</li>
+<li>XIntc_RegisterFastHandler()
+: <a class="el" href="group__intc__v3__4.html#gaed2ddee41f0861539f959522ce2f44af">xintc_l.c</a>
+</li>
+<li>XIntc_RegisterHandler()
+: <a class="el" href="group__intc__v3__4.html#gad1f8540fa2171b00a3af03329677f684">xintc_l.c</a>
+</li>
+<li>XIntc_SelfTest()
+: <a class="el" href="group__intc__v3__4.html#gaf9a9a16180b363930d21bc94dfe71147">xintc.h</a>
+</li>
+<li>XIntc_SetIntrSvcOption()
+: <a class="el" href="group__intc__v3__4.html#gab8e5767995d6318e6fc5cf114cda7b68">xintc_l.c</a>
+</li>
+<li>XIntc_SetNormalIntrMode()
+: <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">xintc.c</a>
+</li>
+<li>XIntc_SetOptions()
+: <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">xintc.h</a>
+</li>
+<li>XIntc_SimulateIntr()
+: <a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">xintc.h</a>
+</li>
+<li>XIntc_Start()
+: <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.c</a>
+</li>
+<li>XIntc_Stop()
+: <a class="el" href="group__intc__v3__4.html#gafabb05cf2e5b62031524a33d1f88f405">xintc.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/globals_defs.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/globals_defs.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XIN_REAL_MODE
+: <a class="el" href="group__intc__v3__4.html#ga56b4aa3cb483ea5c882e2e36a4800af2">xintc.h</a>
+</li>
+<li>XIN_SIMULATION_MODE
+: <a class="el" href="group__intc__v3__4.html#gaefd5527cecdc1a6444b624d1e1a2514f">xintc.h</a>
+</li>
+<li>XIN_SVC_SGL_ISR_OPTION
+: <a class="el" href="group__intc__v3__4.html#gaf4bce8e2035f391b702686e49c66c839">xintc.h</a>
+</li>
+<li>XIntc_AckIntr
+: <a class="el" href="group__intc__v3__4.html#ga4f699042980f8453713171959183fc49">xintc_l.h</a>
+</li>
+<li>XIntc_DisableIntr
+: <a class="el" href="group__intc__v3__4.html#ga5df77bd3561a105f1d6b1837762db956">xintc_l.h</a>
+</li>
+<li>XIntc_EnableIntr
+: <a class="el" href="group__intc__v3__4.html#gad35ec3b9b658f26d989b19783954683e">xintc_l.h</a>
+</li>
+<li>XIntc_GetIntrStatus
+: <a class="el" href="group__intc__v3__4.html#ga13c828dcbbdc3441c8abaded5cda888b">xintc_l.h</a>
+</li>
+<li>XIntc_MasterDisable
+: <a class="el" href="group__intc__v3__4.html#ga93be82188a607b0a13a13a96c5787bb6">xintc_l.h</a>
+</li>
+<li>XIntc_MasterEnable
+: <a class="el" href="group__intc__v3__4.html#gaf2aeec4bbc6e0c5ca2268e5d7c7dd5ce">xintc_l.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/globals_func.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/globals_func.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XIntc_Acknowledge()
+: <a class="el" href="group__intc__v3__4.html#ga8604653ac3a24bbb49c5fecb6a9ebfc7">xintc.c</a>
+</li>
+<li>XIntc_Connect()
+: <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084">xintc.c</a>
+</li>
+<li>XIntc_ConnectFastHandler()
+: <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">xintc.c</a>
+</li>
+<li>XIntc_DeviceInterruptHandler()
+: <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">xintc_l.c</a>
+</li>
+<li>XIntc_Disable()
+: <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">xintc.c</a>
+</li>
+<li>XIntc_Disconnect()
+: <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">xintc.c</a>
+</li>
+<li>XIntc_Enable()
+: <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">xintc.c</a>
+</li>
+<li>XIntc_GetOptions()
+: <a class="el" href="group__intc__v3__4.html#ga6fdbe96b1db87f0c78e68da8bc767a69">xintc.h</a>
+</li>
+<li>XIntc_Initialize()
+: <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">xintc.c</a>
+</li>
+<li>XIntc_InterruptHandler()
+: <a class="el" href="group__intc__v3__4.html#ga635187ed756cee70b4b4051560cbd7bc">xintc.h</a>
+</li>
+<li>XIntc_LookupConfig()
+: <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">xintc.c</a>
+</li>
+<li>XIntc_RegisterFastHandler()
+: <a class="el" href="group__intc__v3__4.html#gaed2ddee41f0861539f959522ce2f44af">xintc_l.c</a>
+</li>
+<li>XIntc_RegisterHandler()
+: <a class="el" href="group__intc__v3__4.html#gad1f8540fa2171b00a3af03329677f684">xintc_l.c</a>
+</li>
+<li>XIntc_SelfTest()
+: <a class="el" href="group__intc__v3__4.html#gaf9a9a16180b363930d21bc94dfe71147">xintc.h</a>
+</li>
+<li>XIntc_SetIntrSvcOption()
+: <a class="el" href="group__intc__v3__4.html#gab8e5767995d6318e6fc5cf114cda7b68">xintc_l.c</a>
+</li>
+<li>XIntc_SetNormalIntrMode()
+: <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">xintc.c</a>
+</li>
+<li>XIntc_SetOptions()
+: <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">xintc.h</a>
+</li>
+<li>XIntc_SimulateIntr()
+: <a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">xintc.h</a>
+</li>
+<li>XIntc_Start()
+: <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">xintc.c</a>
+</li>
+<li>XIntc_Stop()
+: <a class="el" href="group__intc__v3__4.html#gafabb05cf2e5b62031524a33d1f88f405">xintc.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/globals_vars.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/globals_vars.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+<li>XIntc_ConfigTable
+: <a class="el" href="group__intc__v3__4.html#ga2187e69fdc39ef945a992d2602d0c1c1">xintc_g.c</a>
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+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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+</div><!--header-->
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+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp50f33d14f129e4548c1c270fd6725a78"></a>These options are used in <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56" title="Set the options for the interrupt controller driver. ">XIntc_SetOptions()</a> to configure the device. </p>
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+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga56b4aa3cb483ea5c882e2e36a4800af2"></a>
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+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Real mode, no simulation allowed, hardware interrupts recognized. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaefd5527cecdc1a6444b624d1e1a2514f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIN_SIMULATION_MODE&#160;&#160;&#160;0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Simulation only mode, no hardware interrupts recognized. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaf4bce8e2035f391b702686e49c66c839"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIN_SVC_SGL_ISR_OPTION&#160;&#160;&#160;1UL</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+<pre>
+XIN_SVC_SGL_ISR_OPTION	Service the highest priority pending interrupt
+     			and then return.
+XIN_SVC_ALL_ISRS_OPTION	Service all of the pending interrupts and then
+     			return.
+</pre> 
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, and <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga4f699042980f8453713171959183fc49"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIntc_AckIntr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">AckMask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&gt;</code></p>
+
+<p>Acknowledge specific interrupt(s) in the interrupt controller. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
+    <tr><td class="paramname">AckMask</td><td>is the 32-bit value to write to the acknowledge register. Each bit of the mask corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Only the bits which are set in the mask will acknowledge interrupts.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__intc__v3__4.html#ga4f699042980f8453713171959183fc49" title="Acknowledge specific interrupt(s) in the interrupt controller. ">XIntc_AckIntr(u32 BaseAddress, u32 AckMask)</a>; </dd></dl>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga5df77bd3561a105f1d6b1837762db956"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIntc_DisableIntr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">DisableMask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&gt;</code></p>
+
+<p>Disable specific interrupt(s) in the interrupt controller. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
+    <tr><td class="paramname">DisableMask</td><td>is the 32-bit value to write to the enable register. Each bit of the mask corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Only the bits which are set in the mask will disable interrupts.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__intc__v3__4.html#ga5df77bd3561a105f1d6b1837762db956" title="Disable specific interrupt(s) in the interrupt controller. ">XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad35ec3b9b658f26d989b19783954683e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIntc_EnableIntr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">EnableMask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&gt;</code></p>
+
+<p>Enable specific interrupt(s) in the interrupt controller. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
+    <tr><td class="paramname">EnableMask</td><td>is the 32-bit value to write to the enable register. Each bit of the mask corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Only the bits which are set in the mask will enable interrupts.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__intc__v3__4.html#gad35ec3b9b658f26d989b19783954683e" title="Enable specific interrupt(s) in the interrupt controller. ">XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga13c828dcbbdc3441c8abaded5cda888b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIntc_GetIntrStatus</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) &amp; \</div>
+<div class="line">        XIntc_In32((BaseAddress) + XIN_IER_OFFSET))</div>
+</div><!-- fragment -->
+<p>Get the interrupt status from the interrupt controller which indicates which interrupts are active and enabled. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The 32-bit contents of the interrupt status register. Each bit corresponds to an interrupt input signal that is connected to the interrupt controller (INT0 = LSB). Bits which are set indicate an active interrupt which is also enabled.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__intc__v3__4.html#ga13c828dcbbdc3441c8abaded5cda888b" title="Get the interrupt status from the interrupt controller which indicates which interrupts are active an...">XIntc_GetIntrStatus(u32 BaseAddress)</a>; </dd></dl>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga93be82188a607b0a13a13a96c5787bb6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIntc_MasterDisable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress</td><td>)</td>
+          <td>&#160;&#160;&#160;XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&gt;</code></p>
+
+<p>Disable all interrupts in the Master Enable register of the interrupt controller. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__intc__v3__4.html#ga93be82188a607b0a13a13a96c5787bb6" title="Disable all interrupts in the Master Enable register of the interrupt controller. ...">XIntc_MasterDisable(u32 BaseAddress)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf2aeec4bbc6e0c5ca2268e5d7c7dd5ce"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XIntc_MasterEnable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8h.html">xintc_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \</div>
+<div class="line">        XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)</div>
+</div><!-- fragment -->
+<p>Enable all interrupts in the Master Enable register of the interrupt controller. </p>
+<p>The interrupt controller defaults to all interrupts disabled from reset such that this macro must be used to enable interrupts.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__intc__v3__4.html#gaf2aeec4bbc6e0c5ca2268e5d7c7dd5ce" title="Enable all interrupts in the Master Enable register of the interrupt controller. ">XIntc_MasterEnable(u32 BaseAddress)</a>; </dd></dl>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga8604653ac3a24bbb49c5fecb6a9ebfc7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_Acknowledge </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Acknowledges the interrupt source provided as the argument Id. </p>
+<p>When the interrupt is acknowledged, it causes the interrupt controller to clear its interrupt condition.In Cascade mode, acknowledges corresponding interrupt source of Slave controllers depending on the Id.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaee9ec5873a764994d64b4da35a110084"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_Connect </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XInterruptHandler&#160;</td>
+          <td class="paramname"><em>Handler</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>CallBackRef</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. </p>
+<p>The argument provided in this call as the Callbackref is used as the argument for the handler when it is called. In Cascade mode, connects handler to Slave controller handler table depending on the interrupt Id.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt. </td></tr>
+    <tr><td class="paramname">Handler</td><td>to the handler for that interrupt. </td></tr>
+    <tr><td class="paramname">CallBackRef</td><td>is the callback reference, usually the instance pointer of the connecting driver.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<ul>
+<li>XST_SUCCESS if the handler was connected correctly.</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>WARNING: The handler provided as an argument will overwrite any handler that was previously connected. </p>
+
+<p>References <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga24a344d15b12b8acd82cd4c49a020d74"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_ConnectFastHandler </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XFastInterruptHandler&#160;</td>
+          <td class="paramname"><em>Handler</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.In Cascade mode, connects handler to corresponding Slave controller IVAR register depending on the Id and sets all interrupt sources of the Slave controller as fast interrupts. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt. </td></tr>
+    <tr><td class="paramname">Handler</td><td>to the handler for that interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Slave controllers in Cascade Mode should have all as Fast interrupts or Normal interrupts, mixed interrupts are not supported</dd></dl>
+<p>WARNING: The handler provided as an argument will overwrite any handler that was previously connected. </p>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config::FastIntr</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">XIntc_Disable()</a>, <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable()</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gace91a1aeaf1a88e1b769decb4ac4a818"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_DeviceInterruptHandler </td>
+          <td>(</td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>DeviceId</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8c.html">xintc_l.c</a>&gt;</code></p>
+
+<p>This is the interrupt handler for the driver interface provided in this file when there can be no argument passed to the handler. </p>
+<p>In this case, we just use the globally defined device ID for the interrupt controller. This function is provided mostly for backward compatibility. The user should use <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818" title="This is the interrupt handler for the driver interface provided in this file when there can be no arg...">XIntc_DeviceInterruptHandler()</a> if possible.</p>
+<p>This function does not support multiple interrupt controller instances to be handled.</p>
+<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver compilation.</p>
+<p>This function is the primary interrupt handler for the driver. It must be connected to the interrupt source such that is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the AckBeforeService flag in the configuration data to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first. This function assumes that an interrupt vector table has been previously initialized.It does not verify that entries in the table are valid before calling an interrupt handler. In Cascade mode this function calls XIntc_CascadeHandler to handle interrupts of Master and Slave controllers. This functions also handles interrupts nesting by saving and restoring link register of Microblaze and Interrupt Level register of interrupt controller properly.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DeviceId</td><td>is the zero-based device ID defined in xparameters.h of the interrupting interrupt controller. It is used as a direct index into the configuration data, which contains the vector table for the interrupt controller. Note that even though the argument is a void pointer, the value is not a pointer but the actual device ID. The void pointer type is necessary to meet the XInterruptHandler typedef for interrupt handlers.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>For nested interrupts, this function saves microblaze r14 register on entry and restores on exit. This is required since compiler does not support nesting. This function enables Microblaze interrupts after blocking further interrupts from the current interrupt number and interrupts below current interrupt proirity by writing to Interrupt Level Register of INTC on entry. On exit, it disables microblaze interrupts and restores ILR register default value(0xFFFFFFFF)back. It is recommended to increase STACK_SIZE in linker script for nested interrupts. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#a172cd1cd58904502d6f3cec734db1d6b">XIntc_Config::AckBeforeService</a>, <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config::FastIntr</a>, <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>, <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a>, <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config::NumberofIntrs</a>, <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a>, <a class="el" href="group__intc__v3__4.html#gaf4bce8e2035f391b702686e49c66c839">XIN_SVC_SGL_ISR_OPTION</a>, <a class="el" href="group__intc__v3__4.html#ga4f699042980f8453713171959183fc49">XIntc_AckIntr</a>, <a class="el" href="group__intc__v3__4.html#ga2187e69fdc39ef945a992d2602d0c1c1">XIntc_ConfigTable</a>, and <a class="el" href="group__intc__v3__4.html#ga13c828dcbbdc3441c8abaded5cda888b">XIntc_GetIntrStatus</a>.</p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga635187ed756cee70b4b4051560cbd7bc">XIntc_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaea44ec361097925f2994558d402988ab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_Disable </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Disables the interrupt source provided as the argument Id such that the interrupt controller will not cause interrupts for the specified Id. </p>
+<p>The interrupt controller will continue to hold an interrupt condition for the Id, but will not cause an interrupt.In Cascade mode, disables corresponding interrupt of Slave controllers depending on the Id.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, and <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga8f7caaeb26b6b264fffefbd32f90f855"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_Disconnect </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Id. </p>
+<p>This effectively disconnects that interrupt source from any handler. The interrupt is disabled also. In Cascade mode, disconnects handler from Slave controller handler table depending on the interrupt Id.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac7f59192d3b3ba2e2283a264677577b8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_Enable </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Enables the interrupt source provided as the argument Id. </p>
+<p>Any pending interrupt condition for the specified Id will occur after this function is called. In Cascade mode, enables corresponding interrupt of Slave controllers depending on the Id.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, and <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6fdbe96b1db87f0c78e68da8bc767a69"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc_GetOptions </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Return the currently set options. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The currently set options. The options are described in <a class="el" href="xintc_8h.html">xintc.h</a>.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa7adc53d40c41e1a714ef8857329043d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_Initialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>DeviceId</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Initialize a specific interrupt controller instance/driver. </p>
+<p>The initialization entails:</p>
+<ul>
+<li>Initialize fields of the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> structure</li>
+<li>Initial vector table with stub function calls</li>
+<li>All interrupt sources are disabled</li>
+<li>Interrupt output is disabled</li>
+</ul>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">DeviceId</td><td>is the unique id of the device controlled by this <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance. Passing in a device id associates the generic <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to a specific device, as chosen by the caller or application developer.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if initialization was successful</li>
+<li>XST_DEVICE_IS_STARTED if the device has already been started</li>
+<li>XST_DEVICE_NOT_FOUND if device configuration information was not found for a device with the supplied device ID.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>In Cascade mode this function calls XIntc_InitializeSlaves to initialiaze Slave Interrupt controllers. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config::FastIntr</a>, <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>, <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc::IsStarted</a>, <a class="el" href="struct_x_intc___config.html#a6e2fc4f937193eb9e665a2e66af97db2">XIntc_Config::NumberofIntrs</a>, <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a>, <a class="el" href="group__intc__v3__4.html#gaf4bce8e2035f391b702686e49c66c839">XIN_SVC_SGL_ISR_OPTION</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga635187ed756cee70b4b4051560cbd7bc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_InterruptHandler </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Interrupt handler for the driver used when there can be no argument passed to the handler. </p>
+<p>This function is provided mostly for backward compatibility. The user should use <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818" title="This is the interrupt handler for the driver interface provided in this file when there can be no arg...">XIntc_DeviceInterruptHandler()</a>, defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a>, if possible.</p>
+<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in the driver compilation.</p>
+<p>The interrupt handler for the driver. This function is provided mostly for backward compatibility. The user should use <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818" title="This is the interrupt handler for the driver interface provided in this file when there can be no arg...">XIntc_DeviceInterruptHandler()</a>, defined in <a class="el" href="xintc__l_8c.html">xintc_l.c</a> when possible and pass the device ID of the interrupt controller device as its argument.</p>
+<p>The user must connect this function to the interrupt system such that it is called whenever the devices which are connected to it cause an interrupt.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#a1d58e4660c1f0727b1b29497b050cc2c">XIntc_Config::DeviceId</a>, and <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaac2cc8909b69948e755ea649998cd2e1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> * XIntc_LookupConfig </td>
+          <td>(</td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>DeviceId</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Looks up the device configuration based on the unique device ID. </p>
+<p>A table contains the configuration info for each device in the system.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DeviceId</td><td>is the unique identifier for a device.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>A pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> configuration structure for the specified device, or NULL if the device was not found.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="group__intc__v3__4.html#ga2187e69fdc39ef945a992d2602d0c1c1">XIntc_ConfigTable</a>.</p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga8604653ac3a24bbb49c5fecb6a9ebfc7">XIntc_Acknowledge()</a>, <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>, <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">XIntc_Disable()</a>, <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a>, <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#gaed2ddee41f0861539f959522ce2f44af">XIntc_RegisterFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#gad1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler()</a>, <a class="el" href="group__intc__v3__4.html#gab8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption()</a>, <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>, <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions()</a>, <a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr()</a>, and <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaed2ddee41f0861539f959522ce2f44af"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_RegisterFastHandler </td>
+          <td>(</td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>BaseAddress</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XFastInterruptHandler&#160;</td>
+          <td class="paramname"><em>FastHandler</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8c.html">xintc_l.c</a>&gt;</code></p>
+
+<p>Register a fast handler function for a specific interrupt ID. </p>
+<p>The handler function will be called when an interrupt occurs for the given interrupt ID. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the interrupt controller whose vector table will be modified. </td></tr>
+    <tr><td class="paramname">InterruptId</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
+    <tr><td class="paramname">FastHandler</td><td>is the function pointer that will be called when interrupt occurs</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Note that this function has no effect if the input base address is invalid. </p>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad1f8540fa2171b00a3af03329677f684"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_RegisterHandler </td>
+          <td>(</td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>BaseAddress</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>InterruptId</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XInterruptHandler&#160;</td>
+          <td class="paramname"><em>Handler</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>CallBackRef</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8c.html">xintc_l.c</a>&gt;</code></p>
+
+<p>Register a handler function for a specific interrupt ID. </p>
+<p>The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.</p>
+<p>This function can also be used to remove a handler from the vector table by passing in the XIntc_DefaultHandler() as the handler and NULL as the callback reference. In Cascade mode Interrupt Id is used to set Handler for corresponding Slave Controller</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the interrupt controller whose vector table will be modified. </td></tr>
+    <tr><td class="paramname">InterruptId</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
+    <tr><td class="paramname">Handler</td><td>is the function pointer that will be added to the vector table for the given interrupt ID. </td></tr>
+    <tr><td class="paramname">CallBackRef</td><td>is the argument that will be passed to the new handler function when it is called. This is user-specific.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Note that this function has no effect if the input base address is invalid. </p>
+
+<p>References <a class="el" href="struct_x_intc___config.html#af62197288a9019af6084a1675844e1ca">XIntc_Config::HandlerTable</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaf9a9a16180b363930d21bc94dfe71147"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_SelfTest </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Run a self-test on the driver/device. </p>
+<p>This is a destructive test.</p>
+<p>This involves forcing interrupts into the controller and verifying that they are recognized and can be acknowledged. This test will not succeed if the interrupt controller has been started in real mode such that interrupts cannot be forced.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if self-test is successful.</li>
+<li>XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the self-test. It will fail the self test if the device has previously been started in real mode.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, and <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab8e5767995d6318e6fc5cf114cda7b68"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_SetIntrSvcOption </td>
+          <td>(</td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>BaseAddress</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>Option</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__l_8c.html">xintc_l.c</a>&gt;</code></p>
+
+<p>Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs. </p>
+<p>The default behavior when using the driver interface given in <a class="el" href="xintc_8h.html">xintc.h</a> file is to service only a single interrupt, whereas the default behavior when using the driver interface given in this file is to service all outstanding interrupts when an interrupt occurs. In Cascade mode same Option is set to Slave controllers.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the unique identifier for a device. </td></tr>
+    <tr><td class="paramname">Option</td><td>is XIN_SVC_SGL_ISR_OPTION if you want only a single interrupt serviced when an interrupt occurs, or XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts serviced when an interrupt occurs.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>Note that this function has no effect if the input base address is invalid. </p>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a>, <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga881154092f4f8cd5e29a71b284f7b2ae"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_SetNormalIntrMode </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Sets the normal interrupt mode for the specified interrupt in the Interrupt Mode Register. </p>
+<p>In Cascade mode disconnects handler from corresponding Slave controller IVAR register depending on the Id and sets all interrupt sources of the Slave controller as normal interrupts.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the highest priority interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Slave controllers in Cascade Mode should have all as Fast interrupts or Normal interrupts, mixed interrupts are not supported </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#ac894d2be382d08d83821c1672615d4d4">XIntc_Config::FastIntr</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">XIntc_Disable()</a>, <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable()</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga1f0d32716f082a51a751df84312c7d56"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_SetOptions </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Options</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Set the options for the interrupt controller driver. </p>
+<p>In Cascade mode same Option is set to Slave controllers.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Options</td><td>to be set. The available options are described in <a class="el" href="xintc_8h.html">xintc.h</a>.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the options were set successfully</li>
+<li>XST_INVALID_PARAM if the specified option was not valid</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, <a class="el" href="struct_x_intc___config.html#ac3efdbf93e34b88aedead2e7ca44cee1">XIntc_Config::Options</a>, <a class="el" href="group__intc__v3__4.html#gaf4bce8e2035f391b702686e49c66c839">XIN_SVC_SGL_ISR_OPTION</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga17972363ab5a1a8f5f1d135c5b3c22c7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_SimulateIntr </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8h.html">xintc.h</a>&gt;</code></p>
+
+<p>Allows software to simulate an interrupt in the interrupt controller. </p>
+<p>This function will only be successful when the interrupt controller has been started in simulation mode. Once it has been started in real mode, interrupts cannot be simulated. A simulated interrupt allows the interrupt controller to be tested without any device to drive an interrupt input signal into it. In Cascade mode writes to ISR of appropraite Slave controller depending on Id.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Id</td><td>is the interrupt ID for which to simulate an interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if successful</li>
+</ul>
+</dd></dl>
+<ul>
+<li>XST_FAILURE if the interrupt could not be simulated because the interrupt controller is or has previously been in real mode.</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga863eb58a3ae9419c7ac5da7c9fa9cb50"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_Start </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>Mode</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Starts the interrupt controller by enabling the output from the controller to the processor. </p>
+<p>Interrupts may be generated by the interrupt controller after this function is called.</p>
+<p>It is necessary for the caller to connect the interrupt handler of this component to the proper interrupt source. This function also starts Slave controllers in Cascade mode.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on. </td></tr>
+    <tr><td class="paramname">Mode</td><td>determines if software is allowed to simulate interrupts or real interrupts are allowed to occur. Note that these modes are mutually exclusive. The interrupt controller hardware resets in a mode that allows software to simulate interrupts until this mode is exited. It cannot be reentered once it has been exited.</td></tr>
+  </table>
+  </dd>
+</dl>
+<p>One of the following values should be used for the mode.</p><ul>
+<li>XIN_SIMULATION_MODE enables simulation of interrupts only</li>
+<li>XIN_REAL_MODE enables hardware interrupts only</li>
+</ul>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if the device was started successfully</li>
+<li>XST_FAILURE if simulation mode was specified and it could not be set because real mode has already been entered.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Must be called after <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> initialization is completed. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc___config.html#ac0e28544f1ed2f06eda35ba9089e639f">XIntc_Config::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#ac76bb1d794c122fdb86f8e72a9ed22fd">XIntc::CfgPtr</a>, <a class="el" href="struct_x_intc___config.html#ae54682e47e6e506a52c7b6da6314a29a">XIntc_Config::IntcType</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc::IsStarted</a>, <a class="el" href="group__intc__v3__4.html#ga56b4aa3cb483ea5c882e2e36a4800af2">XIN_REAL_MODE</a>, <a class="el" href="group__intc__v3__4.html#gaefd5527cecdc1a6444b624d1e1a2514f">XIN_SIMULATION_MODE</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gafabb05cf2e5b62031524a33d1f88f405"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XIntc_Stop </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_intc.html">XIntc</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc_8c.html">xintc.c</a>&gt;</code></p>
+
+<p>Stops the interrupt controller by disabling the output from the controller so that no interrupts will be caused by the interrupt controller. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> instance to be worked on.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_intc.html#a9556236b7932be7fb353f47b8dc1dfcf">XIntc::BaseAddress</a>, <a class="el" href="struct_x_intc.html#a277e8f00e1f6eb05f8097c676e826b62">XIntc::IsReady</a>, and <a class="el" href="struct_x_intc.html#a3e45bbc3ed1e84a8d708c25c23fa252e">XIntc::IsStarted</a>.</p>
+
+</div>
+</div>
+<h2 class="groupheader">Variable Documentation</h2>
+<a class="anchor" id="ga6afbe6b28aa729c753744cba40ecf5b3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> XIntc_ConfigTable[]</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__i_8h.html">xintc_i.h</a>&gt;</code></p>
+
+<p>This table contains configuration information for each intc device in the system. </p>
+<p>The <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ack it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
+<p>Refer to the <a class="el" href="struct_x_intc___config.html" title="This typedef contains configuration information for the device. ">XIntc_Config</a> data structure in <a class="el" href="xintc_8h.html">xintc.h</a> for details on how this table should be initialized. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga2187e69fdc39ef945a992d2602d0c1c1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a> XIntc_ConfigTable[XPAR_XINTC_NUM_INSTANCES]</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xintc__g_8c.html">xintc_g.c</a>&gt;</code></p>
+<b>Initial value:</b><div class="fragment"><div class="line">= {</div>
+<div class="line">        {</div>
+<div class="line">         XPAR_INTC_0_DEVICE_ID, </div>
+<div class="line">         XPAR_INTC_0_BASEADDR,  </div>
+<div class="line">         XPAR_INTC_0_ACK_BEFORE,        </div>
+<div class="line">         0                      </div>
+<div class="line">         }</div>
+<div class="line">        ,</div>
+<div class="line">        {</div>
+<div class="line">         XPAR_INTC_1_DEVICE_ID, </div>
+<div class="line">         XPAR_INTC_1_BASEADDR,  </div>
+<div class="line">         XPAR_INTC_1_ACK_BEFORE,        </div>
+<div class="line">         0                      </div>
+<div class="line">         }</div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>This table contains configuration information for each intc device in the system. </p>
+<p>The <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ack it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
+<p>Refer to the <a class="el" href="struct_x_intc___config.html" title="This typedef contains configuration information for the device. ">XIntc_Config</a> data structure in <a class="el" href="xintc_8h.html">xintc.h</a> for details on how this table should be initialized. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, and <a class="el" href="group__intc__v3__4.html#gaac2cc8909b69948e755ea649998cd2e1">XIntc_LookupConfig()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+   <div id="projectname">intc_v3_4
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+<div class="title">intc_v3_4 Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>The Xilinx interrupt controller driver component. This component supports the Xilinx interrupt controller.</p>
+<p>The interrupt controller driver uses the idea of priority for the various handlers. Priority is an integer within the range of 0 and 31 inclusive with 0 being the highest priority interrupt source.</p>
+<p>The Xilinx interrupt controller supports the following features:</p>
+<ul>
+<li>specific individual interrupt enabling/disabling</li>
+<li>specific individual interrupt acknowledging</li>
+<li>attaching specific callback function to handle interrupt source</li>
+<li>master enable/disable</li>
+<li>single callback per interrupt or all pending interrupts handled for each interrupt of the processor</li>
+</ul>
+<p>The acknowledgement of the interrupt within the interrupt controller is selectable, either prior to the device's handler being called or after the handler is called. This is necessary to support interrupt signal inputs which are either edge or level signals. Edge driven interrupt signals require that the interrupt is acknowledged prior to the interrupt being serviced in order to prevent the loss of interrupts which are occurring extremely close together. A level driven interrupt input signal requires the interrupt to acknowledged after servicing the interrupt to ensure that the interrupt only generates a single interrupt condition.</p>
+<p>Details about connecting the interrupt handler of the driver are contained in the source file specific to interrupt processing, <a class="el" href="xintc__intr_8c.html">xintc_intr.c</a>.</p>
+<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
+<p><b>Interrupt Vector Tables</b></p>
+<p>The interrupt vector table for each interrupt controller device is declared statically in <a class="el" href="xintc__g_8c.html">xintc_g.c</a> within the configuration data for each instance. The device ID of the interrupt controller device is used by the driver as a direct index into the configuration data table - to retrieve the vector table for an instance of the interrupt controller. The user should populate the vector table with handlers and callbacks at run-time using the <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084" title="Makes the connection between the Id of the interrupt source and the associated handler that is to run...">XIntc_Connect()</a> and <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855" title="Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by th...">XIntc_Disconnect()</a> functions.</p>
+<p>Each vector table entry corresponds to a device that can generate an interrupt. Each entry contains an interrupt handler function and an argument to be passed to the handler when an interrupt occurs. The tools default this argument to the base address of the interrupting device. Note that the device driver interrupt handlers given in this file do not take a base address as an argument, but instead take a pointer to the driver instance. This means that although the table is created statically, the user must still use <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084" title="Makes the connection between the Id of the interrupt source and the associated handler that is to run...">XIntc_Connect()</a> when the interrupt handler takes an argument other than the base address. This is only to say that the existence of the static vector tables should not mislead the user into thinking they no longer need to register/connect interrupt handlers with this driver.</p>
+<pre>
+MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
+----- ---- -------- -------------------------------------------------------
+1.00a ecm  08/16/01 First release
+1.00a rpm  01/09/02 Removed the AckLocation argument from <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084" title="Makes the connection between the Id of the interrupt source and the associated handler that is to run...">XIntc_Connect()</a>.
+                    This information is now internal in <a class="el" href="xintc__g_8c.html">xintc_g.c</a>.
+1.00b jhl  02/13/02 Repartitioned the driver for smaller files
+1.00b jhl  04/24/02 Made LookupConfig function global and relocated config
+                    data type
+1.00c rpm  10/17/03 New release. Support the static vector table created
+                    in the <a class="el" href="xintc__g_8c.html">xintc_g.c</a> configuration table. Moved vector
+                    table and options out of instance structure and into
+                    the configuration table.
+1.10c mta  03/21/07 Updated to new coding style
+1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+2.00a ktn  10/20/09 Updated to use HAL Processor APIs and _m is removed from
+      	      all the macro names/definitions.
+2.01a sdm  04/27/10 Updated the tcl so that the defintions are generated in
+      	      the xparameters.h to know whether the optional registers
+      	      SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
+      	      This driver doesnot make use of these definitions and does
+      	      not use the optional registers.
+2.03a hvm  05/24/11 Updated the tcl to generate vector Ids for external
+      	      interrupts. CR565336
+2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
+      	      and XIntc_SetNormalIntrMode for setting to normal
+      	      interrupt mode.
+2.04a asa  03/19/12 Changed the <a class="el" href="struct_x_intc___config.html" title="This typedef contains configuration information for the device. ">XIntc_Config</a> struct. The order of entries
+      	      declared in the structure now matches with the
+      	      XIntc_ConfigTable generated by the driver tcl.
+2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
+      	      added IntVectorAddr to <a class="el" href="struct_x_intc___config.html" title="This typedef contains configuration information for the device. ">XIntc_Config</a> for this.
+      	      Added XIntc_RegisterFastHandler API to register fast
+      	      interrupt handlers using base address.
+2.06a bss  01/28/13 To support Cascade mode:
+		      Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
+      	      XIN_INTC_SECONDARY,XIN_INTC_LAST and
+      	      XIN_CONTROLLER_MAX_INTRS  macros
+      	      Added NumberofIntrs and IntcType fields in <a class="el" href="struct_x_intc___config.html" title="This typedef contains configuration information for the device. ">XIntc_Config</a>
+      	      structure.
+      	      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
+      	      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
+      	      XIntc_Acknowledge,XIntc_ConnectFastHandler and
+      	      XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
+      	      API in <a class="el" href="xintc_8c.html">xintc.c</a>
+ 		      Modified XIntc_DeviceInterruptHandler,
+ 		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
+      	      XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
+      	      API in <a class="el" href="xintc__l_8c.html">xintc_l.c</a>.
+      	      Modified XIntc_SetOptions API in <a class="el" href="xintc__options_8c.html">xintc_options.c</a>.
+      	      Modified XIntc_SimulateIntr API in <a class="el" href="xintc__selftest_8c.html">xintc_selftest.c</a>.
+      	      Modified driver tcl:
+      		to check for Cascade mode and generate XPAR_INTC_TYPE
+      		for each controller.
+      		Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
+      		interrupt sources of all Controllers in Cascade mode.
+2.07a bss  10/18/13 To support Nested interrupts:
+      	      Modified XIntc_DeviceInterruptHandler API.
+      	      Added XIN_ILR_OFFSET macro in <a class="el" href="xintc__l_8h.html">xintc_l.h</a>.
+      	      Modified driver tcl to generate HAS_ILR parameter in
+      	      xparameters.h
+3.0   bss  01/28/13 Modified <a class="el" href="xintc_8c.html">xintc.c</a> to initialize IVAR register with
+      	      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
+      	      CR#765931.
+      	      Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
+      	      correctly(CR#764865).</pre><pre><dl class="section note"><dt>Note</dt><dd>For Cascade mode, Interrupt IDs are generated in xparameters.h
+      	as shown below:</dd></dl>
+<p>Master/Primary INTC
+      	 ______
+      	|      |-0      Secondary INTC
+      	|      |-.         ______
+      	|      |-.        |      |-32        Last INTC
+      	|      |-.        |      |-.          ______
+      	|______|&lt;-31------|      |-.         |      |-64
+      		          |      |-.         |      |-.
+      		          |______|&lt;-63-------|      |-.
+                                                   |      |-.
+                                                   |______|-95</pre><pre>        All driver functions has to be called using DeviceId/
+      	InstancePtr/BaseAddress of Primary/Master Controller and
+      	Interrupts IDs generated in xparameters.h only.
+      	Driver functions takes care of Slave Controllers based on
+      	Interrupt ID passed. User must not use Interrupt source/ID
+      	31 of Primary and Secondary controllers to call driver
+      	functions.</pre><pre>        For nested interrupts, XIntc_DeviceInterruptHandler saves
+      	microblaze r14 register on entry and restores on exit. This is
+      	required since compiler does not support nesting. It enables
+      	Microblaze interrupts after blocking further interrupts from
+      	the current interrupt number and interrupts below current
+      	interrupt proirity by writing to Interrupt Level Register of
+      	INTC on entry. On exit, it disables microblaze interrupts and
+      	restores ILR register default value(0xFFFFFFFF)back. It is
+      	recommended to increase STACK_SIZE in linker script for nested
+      	interrupts.
+3.0     adk    12/10/13  Updated as per the New Tcl API's
+3.0 	  adk 	 17/02/14  Fixed the CR:771287 Changes are made in the intc
+		           driver tcl.
+3.1     adk    8/4/14    Fixed the CR:783248 Changes are made in
+      		   the test-app tcl
+3.2     bss    4/8/14    Fixed driver tcl to handle external interrupt pins
+      		   correctly (CR#799609).
+3.3     adk    11/3/14   added generation of C_HAS_ILR parameter to
+      		   xparameters.h.Changes are made in the driver tcl file
+      		   (CR#828046).</pre><pre></pre> </div></div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
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+ * Date: Mon Nov 21 21:11:03 2011 -0500
+ */
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+/*!
+ * Sizzle CSS Selector Engine
+ *  Copyright 2011, The Dojo Foundation
+ *  Released under the MIT, BSD, and GPL Licenses.
+ *  More information: http://sizzlejs.com/
+ */
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+ * jQuery UI 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI
+ */
+(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:"1.8.18",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e==="number"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css("overflow")==="hidden"){return false}var e=(f&&f==="left")?"scrollLeft":"scrollTop",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!
+ * jQuery UI Widget 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Widget
+ */
+(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!
+ * jQuery UI Mouse 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Mouse
+ *
+ * Depends:
+ *	jquery.ui.widget.js
+ */
+(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e=="sw"){h.left=j.left+(f.width-h.width);h.top=null}if(e=="nw"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css("borderTopWidth"),h.css("borderRightWidth"),h.css("borderBottomWidth"),h.css("borderLeftWidth")],j=[h.css("paddingTop"),h.css("paddingRight"),h.css("paddingBottom"),h.css("paddingLeft")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(":hidden")||c(g).parents(":hidden").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var 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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">APIs</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__intc__v3__4.html" target="_self">Intc_v3_4</a></td><td class="desc">Contains required functions for the <a class="el" href="struct_x_intc.html" title="The XIntc driver instance data. ">XIntc</a> driver for the Xilinx Interrupt Controller </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/struct_x_intc.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/struct_x_intc.html
new file mode 100644
index 000000000..8b559be52
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/struct_x_intc.html
@@ -0,0 +1,140 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: XIntc Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XIntc Struct Reference<div class="ingroups"><a class="el" href="group__intc__v3__4.html">Intc_v3_4</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>The user is required to allocate a variable of this type for every intc device in the system. A pointer to a variable of this type is then passed to the driver API functions. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a9556236b7932be7fb353f47b8dc1dfcf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc::BaseAddress</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Base address of registers. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga8604653ac3a24bbb49c5fecb6a9ebfc7">XIntc_Acknowledge()</a>, <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">XIntc_Disable()</a>, <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a>, <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#gaf9a9a16180b363930d21bc94dfe71147">XIntc_SelfTest()</a>, <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>, <a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr()</a>, <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>, and <a class="el" href="group__intc__v3__4.html#gafabb05cf2e5b62031524a33d1f88f405">XIntc_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac76bb1d794c122fdb86f8e72a9ed22fd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_intc___config.html">XIntc_Config</a>* XIntc::CfgPtr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Pointer to instance config entry. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>, <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a>, <a class="el" href="group__intc__v3__4.html#ga6fdbe96b1db87f0c78e68da8bc767a69">XIntc_GetOptions()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#ga635187ed756cee70b4b4051560cbd7bc">XIntc_InterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>, <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions()</a>, and <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a277e8f00e1f6eb05f8097c676e826b62"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc::IsReady</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Device is initialized and ready. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga8604653ac3a24bbb49c5fecb6a9ebfc7">XIntc_Acknowledge()</a>, <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>, <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">XIntc_Disable()</a>, <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a>, <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable()</a>, <a class="el" href="group__intc__v3__4.html#ga6fdbe96b1db87f0c78e68da8bc767a69">XIntc_GetOptions()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#gaf9a9a16180b363930d21bc94dfe71147">XIntc_SelfTest()</a>, <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>, <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions()</a>, <a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr()</a>, <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>, and <a class="el" href="group__intc__v3__4.html#gafabb05cf2e5b62031524a33d1f88f405">XIntc_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3e45bbc3ed1e84a8d708c25c23fa252e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc::IsStarted</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Device has been started. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>, and <a class="el" href="group__intc__v3__4.html#gafabb05cf2e5b62031524a33d1f88f405">XIntc_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="abf06c903e68a5569cdf238b185d83ff5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc::UnhandledInterrupts</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Intc Statistics. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/struct_x_intc___config.html b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/struct_x_intc___config.html
new file mode 100644
index 000000000..40d9d7d48
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/doc/html/api/struct_x_intc___config.html
@@ -0,0 +1,202 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>intc_v3_4: XIntc_Config Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">intc_v3_4
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XIntc_Config Struct Reference<div class="ingroups"><a class="el" href="group__intc__v3__4.html">Intc_v3_4</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a172cd1cd58904502d6f3cec734db1d6b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc_Config::AckBeforeService</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Ack location per interrupt. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac0e28544f1ed2f06eda35ba9089e639f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc_Config::BaseAddress</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Register base address. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga8604653ac3a24bbb49c5fecb6a9ebfc7">XIntc_Acknowledge()</a>, <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaea44ec361097925f2994558d402988ab">XIntc_Disable()</a>, <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a>, <a class="el" href="group__intc__v3__4.html#gac7f59192d3b3ba2e2283a264677577b8">XIntc_Enable()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#gaed2ddee41f0861539f959522ce2f44af">XIntc_RegisterFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>, <a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr()</a>, and <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a1d58e4660c1f0727b1b29497b050cc2c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u16 XIntc_Config::DeviceId</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Unique ID of device. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga635187ed756cee70b4b4051560cbd7bc">XIntc_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac894d2be382d08d83821c1672615d4d4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_Config::FastIntr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Fast Interrupt enabled. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler()</a>, <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, and <a class="el" href="group__intc__v3__4.html#ga881154092f4f8cd5e29a71b284f7b2ae">XIntc_SetNormalIntrMode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af62197288a9019af6084a1675844e1ca"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XIntc_VectorTableEntry XIntc_Config::HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS]</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Static vector table of interrupt handlers. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gaee9ec5873a764994d64b4da35a110084">XIntc_Connect()</a>, <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#ga8f7caaeb26b6b264fffefbd32f90f855">XIntc_Disconnect()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, and <a class="el" href="group__intc__v3__4.html#gad1f8540fa2171b00a3af03329677f684">XIntc_RegisterHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ae54682e47e6e506a52c7b6da6314a29a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_Config::IntcType</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Intc type 0 - No Cascade Mode 1 - primary instance 2 - secondary instance 3 - last instance. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#gab8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption()</a>, <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions()</a>, and <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3680484ddceab0bc26f7a4ac2e3b7852"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc_Config::IntVectorAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Interrupt Vector Address. </p>
+
+</div>
+</div>
+<a class="anchor" id="a6e2fc4f937193eb9e665a2e66af97db2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XIntc_Config::NumberofIntrs</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of Interrupt sources. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, and <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac3efdbf93e34b88aedead2e7ca44cee1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XIntc_Config::Options</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Device options. </p>
+
+<p>Referenced by <a class="el" href="group__intc__v3__4.html#gace91a1aeaf1a88e1b769decb4ac4a818">XIntc_DeviceInterruptHandler()</a>, <a class="el" href="group__intc__v3__4.html#ga6fdbe96b1db87f0c78e68da8bc767a69">XIntc_GetOptions()</a>, <a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize()</a>, <a class="el" href="group__intc__v3__4.html#gab8e5767995d6318e6fc5cf114cda7b68">XIntc_SetIntrSvcOption()</a>, and <a class="el" href="group__intc__v3__4.html#ga1f0d32716f082a51a751df84312c7d56">XIntc_SetOptions()</a>.</p>
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+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_b2d849fa2678e4b705013fb62deef518.html">intc_v3_4</a></li><li class="navelem"><a class="el" href="dir_1219a6aeeb4ccb0662ad676071b24e0b.html">src</a></li>  </ul>
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+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
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+<div class="title">xintc.c File Reference</div>  </div>
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+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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+<tr class="memitem:gaa7adc53d40c41e1a714ef8857329043d"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#gaa7adc53d40c41e1a714ef8857329043d">XIntc_Initialize</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u16 DeviceId)</td></tr>
+<tr class="separator:gaa7adc53d40c41e1a714ef8857329043d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga863eb58a3ae9419c7ac5da7c9fa9cb50"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50">XIntc_Start</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Mode)</td></tr>
+<tr class="separator:ga863eb58a3ae9419c7ac5da7c9fa9cb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gafabb05cf2e5b62031524a33d1f88f405"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#gafabb05cf2e5b62031524a33d1f88f405">XIntc_Stop</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
+<tr class="separator:gafabb05cf2e5b62031524a33d1f88f405"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaac2cc8909b69948e755ea649998cd2e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga24a344d15b12b8acd82cd4c49a020d74"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id, XFastInterruptHandler Handler)</td></tr>
+<tr class="separator:ga24a344d15b12b8acd82cd4c49a020d74"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+<a href="#nested-classes">Data Structures</a> &#124;
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+<div class="title">xintc.h File Reference</div>  </div>
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+<div class="contents">
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+<tr><td colspan="2"><div class="groupHeader">Configuration options</div></td></tr>
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+<tr><td colspan="2"><div class="groupText"><p>One of these values is passed to <a class="el" href="group__intc__v3__4.html#ga863eb58a3ae9419c7ac5da7c9fa9cb50" title="Starts the interrupt controller by enabling the output from the controller to the processor...">XIntc_Start()</a> to start the device. </p>
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+<tr><td colspan="2"><div class="groupHeader">Masks to specify Interrupt Controller Mode</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Mask to specify maximum number of interrupt sources per controller</div></td></tr>
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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+<tr class="separator:gaa7adc53d40c41e1a714ef8857329043d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaac2cc8909b69948e755ea649998cd2e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga24a344d15b12b8acd82cd4c49a020d74"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga24a344d15b12b8acd82cd4c49a020d74">XIntc_ConnectFastHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id, XFastInterruptHandler Handler)</td></tr>
+<tr class="separator:ga24a344d15b12b8acd82cd4c49a020d74"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga881154092f4f8cd5e29a71b284f7b2ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga635187ed756cee70b4b4051560cbd7bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga1f0d32716f082a51a751df84312c7d56"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6fdbe96b1db87f0c78e68da8bc767a69"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga6fdbe96b1db87f0c78e68da8bc767a69">XIntc_GetOptions</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
+<tr class="separator:ga6fdbe96b1db87f0c78e68da8bc767a69"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf9a9a16180b363930d21bc94dfe71147"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#gaf9a9a16180b363930d21bc94dfe71147">XIntc_SelfTest</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
+<tr class="separator:gaf9a9a16180b363930d21bc94dfe71147"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga17972363ab5a1a8f5f1d135c5b3c22c7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
+<tr class="separator:ga17972363ab5a1a8f5f1d135c5b3c22c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
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+<div class="contents">
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+<a href="#var-members">Variables</a>  </div>
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+</div><!--header-->
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+<div class="contents">
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+<tr class="memitem:ga635187ed756cee70b4b4051560cbd7bc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga635187ed756cee70b4b4051560cbd7bc">XIntc_InterruptHandler</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr)</td></tr>
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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+  <td id="projectalign" style="padding-left: 0.5em;">
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+<tr class="separator:gaf9a9a16180b363930d21bc94dfe71147"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga17972363ab5a1a8f5f1d135c5b3c22c7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intc__v3__4.html#ga17972363ab5a1a8f5f1d135c5b3c22c7">XIntc_SimulateIntr</a> (<a class="el" href="struct_x_intc.html">XIntc</a> *InstancePtr, u8 Id)</td></tr>
+<tr class="separator:ga17972363ab5a1a8f5f1d135c5b3c22c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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diff --git a/thirdparty/xilinx/orig/intc_v3_4/examples/index.html b/thirdparty/xilinx/orig/intc_v3_4/examples/index.html
new file mode 100644
index 000000000..6b5066175
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/examples/index.html
@@ -0,0 +1,19 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver intc_v3_2 </h1>
+<HR>
+<ul>
+  <li>xintc_low_level_example.c <a href="xintc_low_level_example.c">(source)</a> </li>
+  <li>xintc_example.c <a href="xintc_example.c">(source)</a> </li>
+  <li>xintc_tapp_example.c <a href="xintc_tapp_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright � 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_example.c b/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_example.c
new file mode 100644
index 000000000..db4069e5a
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_example.c
@@ -0,0 +1,348 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+*
+* @file xintc_example.c
+*
+* This file contains a design example using the Interrupt Controller driver
+* (XIntc) and hardware device. Please reference other device driver examples to
+* see more examples of how the intc and interrupts can be used by a software
+* application.
+*
+* This example shows the use of the Interrupt Controller both with a PowerPC
+* and MicroBlaze processor.
+*
+* @note
+*		This example can also be used for Cascade mode interrupt
+*		controllers by using the interrupt IDs generated in
+*		xparameters.h. For Cascade mode, Interrupt IDs are generated
+*		in xparameters.h as shown below:
+*
+*	    Master/Primary INTC
+*		 ______
+*		|      |-0      Secondary INTC
+*		|      |-.         ______
+*		|      |-.        |      |-32        Last INTC
+*		|      |-.        |      |-.          ______
+*		|______|<--31-----|      |-.         |      |-64
+*			          |      |-.         |      |-.
+*			          |______|<--63------|      |-.
+*                                                    |      |-.
+*                                                    |______|-95
+*
+*		All driver functions has to be called using
+*		DeviceId/InstancePtr of Primary/Master Controller only. Driver
+*		functions takes care of Slave Controllers based on Interrupt
+*		ID passed. User must not use Interrupt source/ID  31 of Primary
+*		and Secondary controllers to call driver functions.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+* Ver   Who  Date	 Changes
+* ----- ---- -------- ----------------------------------------------------
+* 1.00b jhl  02/13/02 First release
+* 1.00c rpm  11/13/03 Updated to show microblaze and PPC interrupt use and
+*		      to use the common L0/L1 interrupt handler with device ID.
+* 1.00c sv   06/29/05 Minor changes to comply to Doxygen and coding guidelines
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs amd minor modifications
+*		      as per coding guidelines.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xintc.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define INTC_DEVICE_ID		  XPAR_INTC_0_DEVICE_ID
+
+/*
+ *  This is the Interrupt Number of the Device whose Interrupt Output is
+ *  connected to the Input of the Interrupt Controller
+ */
+#define INTC_DEVICE_INT_ID	  XPAR_INTC_0_UARTLITE_0_VEC_ID
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int IntcExample(u16 DeviceId);
+
+int SetUpInterruptSystem(XIntc *XIntcInstancePtr);
+
+void DeviceDriverHandler(void *CallbackRef);
+
+
+/************************** Variable Definitions *****************************/
+
+static XIntc InterruptController; /* Instance of the Interrupt Controller */
+
+/*
+ * Create a shared variable to be used by the main thread of processing and
+ * the interrupt processing
+ */
+volatile static int InterruptProcessed = FALSE;
+
+/*****************************************************************************/
+/**
+*
+* This is the main function for the Interrupt Controller example.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the Intc example , specify the Device ID generated in
+	 * xparameters.h
+	 */
+	Status = IntcExample(INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function is an example of how to use the interrupt controller driver
+* component (XIntc) and the hardware device.  This function is designed to
+* work without any hardware devices to cause interrupts.  It may not return
+* if the interrupt controller is not properly connected to the processor in
+* either software or hardware.
+*
+* This function relies on the fact that the interrupt controller hardware
+* has come out of the reset state such that it will allow interrupts to be
+* simulated by the software.
+*
+* @param	DeviceId is Device ID of the Interrupt Controller Device,
+*		typically XPAR_<INTC_instance>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+int IntcExample(u16 DeviceId)
+{
+	int Status;
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	Status = XIntc_Initialize(&InterruptController, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly.
+	 */
+	Status = XIntc_SelfTest(&InterruptController);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Setup the Interrupt System.
+	 */
+	Status = SetUpInterruptSystem(&InterruptController);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 *  Simulate the Interrupt.
+	 */
+	Status = XIntc_SimulateIntr(&InterruptController, INTC_DEVICE_INT_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Wait for the interrupt to be processed, if the interrupt does not
+	 * occur this loop will wait forever.
+	 */
+	while (1)
+	{
+		/*
+		 * If the interrupt occurred which is indicated by the global
+		 * variable which is set in the device driver handler, then
+		 * stop waiting.
+		 */
+		if (InterruptProcessed) {
+			break;
+		}
+	}
+
+	return XST_SUCCESS;
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function connects the interrupt handler of the interrupt controller to
+* the processor.  This function is seperate to allow it to be customized for
+* each application.  Each processor or RTOS may require unique processing to
+* connect the interrupt handler.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+int SetUpInterruptSystem(XIntc *XIntcInstancePtr)
+{
+	int Status;
+
+
+	/*
+	 * Connect a device driver handler that will be called when an interrupt
+	 * for the device occurs, the device driver handler performs the
+	 * specific interrupt processing for the device.
+	 */
+	Status = XIntc_Connect(XIntcInstancePtr, INTC_DEVICE_INT_ID,
+				   (XInterruptHandler)DeviceDriverHandler,
+				   (void *)0);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Start the interrupt controller such that interrupts are enabled for
+	 * all devices that cause interrupts, specify simulation mode so that
+	 * an interrupt can be caused by software rather than a real hardware
+	 * interrupt.
+	 */
+	Status = XIntc_Start(XIntcInstancePtr, XIN_SIMULATION_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Enable the interrupt for the device and then cause (simulate) an
+	 * interrupt so the handlers will be called.
+	 */
+	XIntc_Enable(XIntcInstancePtr, INTC_DEVICE_INT_ID);
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				(Xil_ExceptionHandler)XIntc_InterruptHandler,
+				XIntcInstancePtr);
+
+	/*
+	 * Enable exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function is designed to look like an interrupt handler in a device
+* driver. This is typically a 2nd level handler that is called from the
+* interrupt controller interrupt handler.  This handler would typically
+* perform device specific processing such as reading and writing the registers
+* of the device to clear the interrupt condition and pass any data to an
+* application using the device driver.  Many drivers already provide this
+* handler and the user is not required to create it.
+*
+* @param	CallbackRef is passed back to the device driver's interrupt
+*		handler by the XIntc driver.  It was given to the XIntc driver
+*		in the XIntc_Connect() function call.  It is typically a pointer
+*		to the device driver instance variable if using the Xilinx
+*		Level 1 device drivers.  In this example, we do not care about
+*		the callback reference, so we passed it a 0 when connecting the
+*		handler to the XIntc driver and we make no use of it here.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void DeviceDriverHandler(void *CallbackRef)
+{
+	/*
+	 * Indicate the interrupt has been processed using a shared variable.
+	 */
+	InterruptProcessed = TRUE;
+
+}
diff --git a/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_low_level_example.c b/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_low_level_example.c
new file mode 100644
index 000000000..835b1b5a1
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_low_level_example.c
@@ -0,0 +1,302 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+*
+* @file xintc_low_level_example.c
+*
+* This file contains a design example using the low level-0 driver, interface
+* of the Interrupt Controller driver.
+*
+* This example shows the use of the Interrupt Controller both with a PowerPC
+* and a MicroBlaze processor.
+*
+* @note
+*		This example can also be used for Cascade mode interrupt
+*		controllers by using the interrupt IDs generated in
+*		xparameters.h. For Cascade mode, Interrupt IDs are generated
+*		in xparameters.h as shown below:
+*
+*	    Master/Primary INTC
+*		 ______
+*		|      |-0      Secondary INTC
+*		|      |-.         ______
+*		|      |-.        |      |-32        Last INTC
+*		|      |-.        |      |-.          ______
+*		|______|<--31-----|      |-.         |      |-64
+*			          |      |-.         |      |-.
+*			          |______|<--63------|      |-.
+*                                                    |      |-.
+*                                                    |______|-95
+*
+*		All driver functions has to be called using BaseAddress
+*		of Primary/Master Controller only. Driver functions takes
+*		care of Slave Controllers based on Interrupt ID passed.
+*		User must not use Interrupt source/ID  31 of Primary and
+*		Secondary controllers to call driver functions.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00c rpm  12/04/03 First release
+* 1.00c sv   06/29/05 Minor changes to comply to Doxygen and coding guidelines
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and _m is removed from
+*		      all the macro names/definitions. Minor changes done as per
+*		      coding guidelines.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xintc_l.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define INTC_BASEADDR		XPAR_INTC_0_BASEADDR
+#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_INTR_ID	XPAR_INTC_0_UARTLITE_0_VEC_ID
+#define INTC_DEVICE_INT_MASK	XPAR_RS232_UART_1_INTERRUPT_MASK
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int IntcLowLevelExample(u32 IntcBaseAddress);
+
+void SetupInterruptSystem();
+
+void DeviceDriverHandler(void *CallbackRef);
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create a shared variable to be used by the main thread of processing and
+ * the interrupt processing
+ */
+volatile static int InterruptProcessed = FALSE;
+
+/*****************************************************************************/
+/**
+*
+* This is the main function for the Interrupt Controller Low Level example.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the low level example of Interrupt Controller, specify the Base
+	 * Address generated in xparameters.h.
+	 */
+	Status = IntcLowLevelExample(INTC_BASEADDR);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is an example of how to use the interrupt controller driver
+* component (XIntc) and the hardware device.  This function is designed to
+* work without any hardware devices to cause interrupts. It may not return
+* if the interrupt controller is not properly connected to the processor in
+* either software or hardware.
+*
+* This function relies on the fact that the interrupt controller hardware
+* has come out of the reset state such that it will allow interrupts to be
+* simulated by the software.
+*
+* @param	IntcBaseAddress is Base Address of the the Interrupt Controller
+*		Device.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+int IntcLowLevelExample(u32 IntcBaseAddress)
+{
+
+	/*
+	 * Connect a device driver handler that will be called when an interrupt
+	 * for the device occurs, the device driver handler performs the
+	 * specific interrupt processing for the device.
+	 */
+	XIntc_RegisterHandler(IntcBaseAddress, INTC_DEVICE_INTR_ID,
+				(XInterruptHandler)DeviceDriverHandler,
+				(void *)0);
+
+	/*
+	 * Enable interrupts for all devices that cause interrupts, and enable
+	 * the INTC master enable bit.
+	 */
+	XIntc_EnableIntr(IntcBaseAddress, INTC_DEVICE_INT_MASK);
+
+
+	/*
+	 * Set the master enable bit. Note that we do not enable hardware
+	 * interrupts yet since we want to simulate an interrupt from software
+	 * down below.
+	 */
+	XIntc_Out32(IntcBaseAddress + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK);
+
+	/*
+	 * This step is processor specific, connect the handler for the
+	 * interrupt controller to the interrupt source for the processor.
+	 */
+	SetupInterruptSystem();
+
+	/*
+	 * Cause (simulate) an interrupt so the handler will be called. This is
+	 * done by writing a 1 to the interrupt status bit for the device
+	 * interrupt.
+	 */
+	XIntc_Out32(IntcBaseAddress + XIN_ISR_OFFSET, INTC_DEVICE_INT_MASK);
+
+	/*
+	 * Wait for the interrupt to be processed, if the interrupt does not
+	 * occur this loop will wait forever.
+	 */
+	while (1)
+	{
+		/*
+		 * If the interrupt occurred which is indicated by the global
+		 * variable which is set in the device driver handler, then
+		 * stop waiting.
+		 */
+		if (InterruptProcessed) {
+			break;
+		}
+	}
+
+
+	return XST_SUCCESS;
+
+}
+/*****************************************************************************/
+/**
+*
+* This function connects the interrupt handler of the interrupt controller to
+* the processor. This function is seperate to allow it to be customized for
+* each application. Each processor or RTOS may require unique processing to
+* connect the interrupt handler.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SetupInterruptSystem()
+{
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+			(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,
+			INTC_DEVICE_ID);
+
+	/*
+	 * Enable exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+}
+
+
+
+/*****************************************************************************/
+/**
+*
+* This function is designed to look like an interrupt handler in a device
+* driver. This is typically a 2nd level handler that is called from the
+* interrupt controller interrupt handler.  This handler would typically
+* perform device specific processing such as reading and writing the registers
+* of the device to clear the interrupt condition and pass any data to an
+* application using the device driver.
+*
+* @param	CallbackRef is passed back to the device driver's interrupt
+*		handler by the XIntc driver.  It was given to the XIntc driver
+*		in the XIntc_Connect() function call. It is typically a pointer
+*		to the device driver instance variable if using the Xilinx Level
+*		1 device drivers. In this example, we do not care about the
+*		callback reference, so we passed it a 0 when connecting the
+*		handler to the XIntc driver and we make no use of it here.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DeviceDriverHandler(void *CallbackRef)
+{
+	/*
+	 * Indicate the interrupt has been processed using a shared variable.
+	 */
+	InterruptProcessed = TRUE;
+
+}
diff --git a/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_tapp_example.c b/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_tapp_example.c
new file mode 100644
index 000000000..b3937439a
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/examples/xintc_tapp_example.c
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+*
+* @file xintc_tapp_example.c
+*
+* This file contains a self test example using the Interrupt Controller driver
+* (XIntc) and hardware device. Please reference other device driver examples to
+* see more examples of how the Intc and interrupts can be used by a software
+* application.
+*
+* This example shows the use of the Interrupt Controller both with a PowerPC405
+* and MicroBlaze processor.
+*
+* The TestApp Gen utility uses this file to perform the self test and setup
+* of Intc for interrupts.
+*
+* @note
+*
+* None
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a sv   06/29/05  Created for Test App Integration
+* 1.00c sn   05/09/06  Added Interrupt Setup Function
+* 2.00a ktn  10/20/09  Updated to use HAL Processor APIs and minor changes as
+*		       per coding guidelines.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xintc.h"
+#include "xil_exception.h"
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place. This definition is not
+ * included if the example is generated from the TestAppGen test tool.
+ */
+#ifndef TESTAPP_GEN
+#define INTC_DEVICE_ID		  XPAR_INTC_0_DEVICE_ID
+#endif
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int IntcSelfTestExample(u16 DeviceId);
+int IntcInterruptSetup(XIntc *IntcInstancePtr, u16 DeviceId);
+
+/************************** Variable Definitions *****************************/
+
+static XIntc InterruptController; /* Instance of the Interrupt Controller */
+
+
+/*****************************************************************************/
+/**
+*
+* This is the main function for the Interrupt Controller example. This
+* function is not included if the example is generated from the TestAppGen test
+* tool.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+#ifndef TESTAPP_GEN
+int main(void)
+{
+	int Status;
+
+	/*
+	 *  Run the Intc example , specify the Device ID generated in
+	 * xparameters.h.
+	 */
+	Status = IntcSelfTestExample(INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver/device. This is a destructive
+* test. This function is an example of how to use the interrupt controller
+* driver component (XIntc) and the hardware device.  This function is designed
+* to work without any hardware devices to cause interrupts.  It may not return
+* if the interrupt controller is not properly connected to the processor in
+* either software or hardware.
+*
+* This function relies on the fact that the interrupt controller hardware
+* has come out of the reset state such that it will allow interrupts to be
+* simulated by the software.
+*
+* @param	DeviceId is device ID of the Interrupt Controller Device,
+*		typically XPAR_<INTC_instance>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+int IntcSelfTestExample(u16 DeviceId)
+{
+	int Status;
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to use.
+	 */
+	Status = XIntc_Initialize(&InterruptController, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built correctly.
+	 */
+	Status = XIntc_SelfTest(&InterruptController);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function is used by the TestAppGen generated application to setup
+* the interrupt controller.
+*
+* @param	IntcInstancePtr is the reference to the Interrupt Controller
+*		instance.
+* @param	DeviceId is device ID of the Interrupt Controller Device,
+*		typically XPAR_<INTC_instance>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+int IntcInterruptSetup(XIntc *IntcInstancePtr, u16 DeviceId)
+{
+
+	int Status;
+
+	/*
+	 * Initialize the interrupt controller driver so that it is
+	 * ready to use.
+	 */
+	Status = XIntc_Initialize(IntcInstancePtr, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built  correctly.
+	 */
+	Status = XIntc_SelfTest(IntcInstancePtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+			(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,
+			(void*) 0);
+
+	/*
+	 * Enable exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+	/*
+	 * Start the interrupt controller such that interrupts are enabled for
+	 * all devices that cause interrupts.
+	 */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/Makefile b/thirdparty/xilinx/orig/intc_v3_4/src/Makefile
new file mode 100644
index 000000000..9dd1eeddc
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/Makefile
@@ -0,0 +1,28 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+LEVEL=0
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+
+OUTS = *.o
+
+libs:
+	echo "Compiling intc"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc.c b/thirdparty/xilinx/orig/intc_v3_4/src/xintc.c
new file mode 100644
index 000000000..916ebe0bc
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc.c
@@ -0,0 +1,1081 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc.c
+* @addtogroup intc_v3_4
+* @{
+*
+* Contains required functions for the XIntc driver for the Xilinx Interrupt
+* Controller. See xintc.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.00b jhl  04/24/02 Made LookupConfig global and compressed ack before table
+*                     in the configuration into a bit mask
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table.
+* 1.00c rpm  04/23/04 Removed check in XIntc_Connect for a previously connected
+*                     handler. Always overwrite the vector table handler with
+*                     the handler provided as an argument.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs.
+* 2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
+*		      and XIntc_SetNormalIntrMode for setting to normal
+*		      interrupt mode.
+* 2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
+*		      updated XIntc_SetNormalIntrMode to use IntVectorAddr
+*		      which is the interrupt vector address
+* 2.06a bss  01/28/13 To support Cascade mode:
+*		      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
+*		      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
+*		      XIntc_Acknowledge,XIntc_ConnectFastHandler and
+*		      XIntc_SetNormalIntrMode APIs.
+*		      Added XIntc_InitializeSlaves API.
+* 3.0   bss  01/28/13 Modified to initialize IVAR register with
+*		      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
+*		      CR#765931
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xintc.h"
+#include "xintc_l.h"
+#include "xintc_i.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Array of masks associated with the bit position, improves performance
+ * in the ISR and acknowledge functions, this table is shared between all
+ * instances of the driver. XIN_CONTROLLER_MAX_INTRS is the maximum number of
+ * sources of Interrupt controller
+ */
+u32 XIntc_BitPosMask[XIN_CONTROLLER_MAX_INTRS];
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+static void XIntc_InitializeSlaves(XIntc * InstancePtr);
+
+/*****************************************************************************/
+/**
+*
+* Initialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+*	- Initialize fields of the XIntc structure
+*	- Initial vector table with stub function calls
+*	- All interrupt sources are disabled
+*	- Interrupt output is disabled
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	DeviceId is the unique id of the device controlled by this XIntc
+*		instance.  Passing in a device id associates the generic XIntc
+*		instance to a specific device, as chosen by the caller or
+*		application developer.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*		- XST_DEVICE_IS_STARTED if the device has already been started
+*		- XST_DEVICE_NOT_FOUND if device configuration information was
+*		not found for a device with the supplied device ID.
+*
+* @note		In Cascade mode this function calls XIntc_InitializeSlaves to
+*	        initialiaze Slave Interrupt controllers.
+*
+******************************************************************************/
+int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId)
+{
+	u8 Id;
+	XIntc_Config *CfgPtr;
+	u32 NextBitMask = 1;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a status
+	 * indicating it is started.  This allows the user to stop the device
+	 * and reinitialize, but prevents a user from inadvertently initializing
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Lookup the device configuration in the CROM table. Use this
+	 * configuration info down below when initializing this component.
+	 */
+	CfgPtr = XIntc_LookupConfig(DeviceId);
+	if (CfgPtr == NULL) {
+		return XST_DEVICE_NOT_FOUND;
+	}
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->IsReady = 0;
+	InstancePtr->IsStarted = 0;	/* not started */
+	InstancePtr->CfgPtr = CfgPtr;
+
+	InstancePtr->CfgPtr->Options = XIN_SVC_SGL_ISR_OPTION;
+	InstancePtr->CfgPtr->IntcType = CfgPtr->IntcType;
+
+	/*
+	 * Save the base address pointer such that the registers of the
+	 * interrupt can be accessed
+	 */
+#if (XPAR_XINTC_USE_DCR_BRIDGE != 0)
+	InstancePtr->BaseAddress = ((CfgPtr->BaseAddress >> 2)) & 0xFFF;
+#else
+	InstancePtr->BaseAddress = CfgPtr->BaseAddress;
+#endif
+
+	/*
+	 * Initialize all the data needed to perform interrupt processing for
+	 * each interrupt ID up to the maximum used
+	 */
+	for (Id = 0; Id < CfgPtr->NumberofIntrs; Id++) {
+
+		/*
+		 * Initalize the handler to point to a stub to handle an
+		 * interrupt which has not been connected to a handler. Only
+		 * initialize it if the handler is 0 or XNullHandler, which
+		 * means it was not initialized statically by the tools/user.
+		 * Set the callback reference to this instance so that
+		 * unhandled interrupts can be tracked.
+		 */
+		if ((InstancePtr->CfgPtr->HandlerTable[Id].Handler == 0) ||
+		    (InstancePtr->CfgPtr->HandlerTable[Id].Handler ==
+		     XNullHandler)) {
+			InstancePtr->CfgPtr->HandlerTable[Id].Handler =
+				StubHandler;
+		}
+		InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
+
+		/*
+		 * Initialize the bit position mask table such that bit
+		 * positions are lookups only for each interrupt id, with 0
+		 * being a special case
+		 * (XIntc_BitPosMask[] = { 1, 2, 4, 8, ... })
+		 */
+		XIntc_BitPosMask[Id] = NextBitMask;
+		NextBitMask *= 2;
+	}
+
+	/*
+	 * Disable IRQ output signal
+	 * Disable all interrupt sources
+	 * Acknowledge all sources
+	 */
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0);
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, 0);
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, 0xFFFFFFFF);
+
+	/*
+	 * If the fast Interrupt mode is enabled then set all the
+	 * interrupts as normal mode.
+	 */
+	if(InstancePtr->CfgPtr->FastIntr == TRUE) {
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, 0);
+
+#ifdef XPAR_MICROBLAZE_BASE_VECTORS
+		for (Id = 0; Id < 32 ; Id++)
+		{
+			XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
+				+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
+				+ 0x10);
+		}
+#else
+		for (Id = 0; Id < 32 ; Id++)
+		{
+			XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
+							+ (Id * 4), 0x10);
+		}
+#endif
+	}
+
+	/* Initialize slaves in Cascade mode*/
+	if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
+		XIntc_InitializeSlaves(InstancePtr);
+	}
+
+	/*
+	 * Indicate the instance is now ready to use, successfully initialized
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Starts the interrupt controller by enabling the output from the controller
+* to the processor. Interrupts may be generated by the interrupt controller
+* after this function is called.
+*
+* It is necessary for the caller to connect the interrupt handler of this
+* component to the proper interrupt source. This function also starts Slave
+* controllers in Cascade mode.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Mode determines if software is allowed to simulate interrupts or
+*		real interrupts are allowed to occur. Note that these modes are
+*		mutually exclusive. The interrupt controller hardware resets in
+*		a mode that allows software to simulate interrupts until this
+*		mode is exited. It cannot be reentered once it has been exited.
+*
+*		One of the following values should be used for the mode.
+*		- XIN_SIMULATION_MODE enables simulation of interrupts only
+*		- XIN_REAL_MODE enables hardware interrupts only
+*
+* @return
+* 		- XST_SUCCESS if the device was started successfully
+* 		- XST_FAILURE if simulation mode was specified and it could not
+*		be set because real mode has already been entered.
+*
+* @note 	Must be called after XIntc initialization is completed.
+*
+******************************************************************************/
+int XIntc_Start(XIntc * InstancePtr, u8 Mode)
+{
+	u32 MasterEnable = XIN_INT_MASTER_ENABLE_MASK;
+	XIntc_Config *CfgPtr;
+	int Index;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Mode == XIN_SIMULATION_MODE) ||
+			(Mode == XIN_REAL_MODE));
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check for simulation mode
+	 */
+	if (Mode == XIN_SIMULATION_MODE) {
+		if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
+			return XST_FAILURE;
+		}
+	}
+	else {
+		MasterEnable |= XIN_INT_HARDWARE_ENABLE_MASK;
+	}
+
+	/*
+	 * Indicate the instance is ready to be used and is started before we
+	 * enable the device.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+	/* Start the Slaves for Cascade Mode */
+	if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
+		for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++)
+		{
+			CfgPtr = XIntc_LookupConfig(Index);
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET,
+					MasterEnable);
+		}
+	}
+
+	/* Start the master */
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, MasterEnable);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Stops the interrupt controller by disabling the output from the controller
+* so that no interrupts will be caused by the interrupt controller.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIntc_Stop(XIntc * InstancePtr)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Stop all interrupts from occurring thru the interrupt controller by
+	 * disabling all interrupts in the MER register
+	 */
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0);
+
+	InstancePtr->IsStarted = 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called. In Cascade mode, connects handler to
+* Slave controller handler table depending on the interrupt Id.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
+*   		the highest priority interrupt.
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+* 		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+int XIntc_Connect(XIntc * InstancePtr, u8 Id,
+		  XInterruptHandler Handler, void *CallBackRef)
+{
+	XIntc_Config *CfgPtr;
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Connect Handlers for Slave controllers in Cascade Mode */
+	if (Id > 31) {
+
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		CfgPtr->HandlerTable[Id%32].Handler = Handler;
+		CfgPtr->HandlerTable[Id%32].CallBackRef = CallBackRef;
+	}
+	/* Connect Handlers for Master/primary controller */
+	else {
+		/*
+		 * The Id is used as an index into the table to select the
+		 * proper handler
+		 */
+		InstancePtr->CfgPtr->HandlerTable[Id].Handler = Handler;
+		InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef =
+								CallBackRef;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also. In Cascade mode,
+* disconnects handler from Slave controller handler table depending on the
+* interrupt Id.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
+*		the highest priority interrupt.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIntc_Disconnect(XIntc * InstancePtr, u8 Id)
+{
+	u32 CurrentIER;
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without
+	 * modifying the other interrupt ids
+	 */
+
+	/* Disconnect Handlers for Slave controllers in Cascade Mode */
+	if (Id > 31) {
+
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
+					(CurrentIER & ~Mask));
+		/*
+		 * Disconnect the handler and connect a stub, the callback
+		 * reference must be set to this instance to allow unhandled
+		 * interrupts to be tracked
+		 */
+		CfgPtr->HandlerTable[Id%32].Handler = StubHandler;
+		CfgPtr->HandlerTable[Id%32].CallBackRef = InstancePtr;
+	}
+	/* Disconnect Handlers for Master/primary controller */
+	else {
+		CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
+							XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[Id];
+
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
+					(CurrentIER & ~Mask));
+		InstancePtr->CfgPtr->HandlerTable[Id%32].Handler =
+								StubHandler;
+		InstancePtr->CfgPtr->HandlerTable[Id%32].CallBackRef =
+								InstancePtr;
+	}
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Id. Any pending
+* interrupt condition for the specified Id will occur after this function is
+* called. In Cascade mode, enables corresponding interrupt of Slave controllers
+* depending on the Id.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
+*		the highest priority interrupt.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIntc_Enable(XIntc * InstancePtr, u8 Id)
+{
+	u32 CurrentIER;
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (Id > 31) {
+
+		/* Enable user required Id in Slave controller */
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
+						(CurrentIER | Mask));
+	}
+	else {
+		/*
+		 * The Id is used to create the appropriate mask for the
+		 * desired bit position.
+		 */
+		Mask = XIntc_BitPosMask[Id];
+
+		/*
+		 * Enable the selected interrupt source by reading the
+		 * interrupt enable register and then modifying only the
+		 * specified interrupt id enable
+		 */
+		CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
+							XIN_IER_OFFSET);
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
+		    (CurrentIER | Mask));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Id such that the
+* interrupt controller will not cause interrupts for the specified Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Id, but will not cause an interrupt.In Cascade mode, disables corresponding
+* interrupt of Slave controllers depending on the Id.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the
+*		highest priority interrupt.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIntc_Disable(XIntc * InstancePtr, u8 Id)
+{
+	u32 CurrentIER;
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (Id > 31) {
+		/* Enable user required Id in Slave controller */
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
+							(CurrentIER & ~Mask));
+	} else {
+		/*
+		 * The Id is used to create the appropriate mask for the
+		 * desired bit position. Id currently limited to 0 - 31
+		 */
+		Mask = XIntc_BitPosMask[Id];
+
+		/*
+		 * Disable the selected interrupt source by reading the
+		 * interrupt enable register and then modifying only the
+		 * specified interrupt id
+		 */
+		CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
+							XIN_IER_OFFSET);
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
+							(CurrentIER & ~Mask));
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Acknowledges the interrupt source provided as the argument Id. When the
+* interrupt is acknowledged, it causes the interrupt controller to clear its
+* interrupt condition.In Cascade mode, acknowledges corresponding interrupt
+* source of Slave controllers depending on the Id.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
+*    		the highest priority interrupt.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id)
+{
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (Id > 31) {
+		/* Enable user required Id in Slave controller */
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, Mask);
+	} else {
+		/*
+		 * The Id is used to create the appropriate mask for the
+		 * desired bit position.
+		 */
+		Mask = XIntc_BitPosMask[Id];
+
+		/*
+		 * Acknowledge the selected interrupt source, no read of the
+		 * acknowledge register is necessary since only the bits set
+		 * in the mask will be affected by the write
+		 */
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Mask);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef)
+{
+	/*
+	 * Verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XIntc *) CallBackRef)->UnhandledInterrupts++;
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XIntc configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XIntc_Config *XIntc_LookupConfig(u16 DeviceId)
+{
+	XIntc_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
+		if (XIntc_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIntc_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized.In Cascade
+* mode, connects handler to corresponding Slave controller IVAR register
+* depending on the Id and sets all interrupt sources of the Slave controller as
+* fast interrupts.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
+*		the highest priority interrupt.
+* @param	Handler to the handler for that interrupt.
+*
+* @return
+*		- XST_SUCCESS
+*
+* @note
+* 		Slave controllers in Cascade Mode should have all as Fast
+* 		interrupts or Normal interrupts, mixed interrupts are not
+*		supported
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
+				XFastInterruptHandler Handler)
+{
+	u32 Imr;
+	u32 CurrentIER;
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->CfgPtr->FastIntr == TRUE);
+
+
+	if (Id > 31) {
+		/* Enable user required Id in Slave controller */
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		if (CfgPtr->FastIntr != TRUE) {
+			/*Fast interrupts of slave controller are not enabled*/
+			return XST_FAILURE;
+		}
+
+		/* Get the Enabled Interrupts */
+		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		/* Disable the Interrupt if it was enabled before calling
+		 * this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Disable(InstancePtr, Id);
+		}
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
+				((Id%32) * 4), (u32) Handler);
+
+		/* Slave controllers in Cascade Mode should have all as Fast
+		 * interrupts or Normal interrupts, mixed interrupts are not
+		 * supported
+		 */
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
+
+		/* Enable the Interrupt if it was enabled before calling this
+		 * function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Enable(InstancePtr, Id);
+		}
+	}
+	else {
+		/* Get the Enabled Interrupts */
+		CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
+							 XIN_IER_OFFSET);
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[Id];
+
+		/* Disable the Interrupt if it was enabled before calling
+		 * this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Disable(InstancePtr, Id);
+		}
+
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET +
+					 (Id * 4), (u32) Handler);
+
+		Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
+							Imr | Mask);
+
+		/* Enable the Interrupt if it was enabled before
+		 * calling this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Enable(InstancePtr, Id);
+		}
+
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Sets the normal interrupt mode for the specified interrupt in the Interrupt
+* Mode Register. In Cascade mode disconnects handler from corresponding Slave
+* controller IVAR register depending on the Id and sets all interrupt sources
+* of the Slave controller as normal interrupts.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id contains the ID of the interrupt source and should be in the
+*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the
+*		highest priority interrupt.
+*
+* @return	None.
+*
+* @note
+*		Slave controllers in Cascade Mode should have all as Fast
+* 		interrupts or Normal interrupts, mixed interrupts are not
+*		supported
+*
+****************************************************************************/
+void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id)
+{
+	u32 Imr;
+	u32 CurrentIER;
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->CfgPtr->FastIntr == TRUE);
+
+	if (Id > 31) {
+		/* Enable user required Id in Slave controller */
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		/* Get the Enabled Interrupts */
+		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		/* Disable the Interrupt if it was enabled before calling
+		 * this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Disable(InstancePtr, Id);
+		}
+
+		/* Slave controllers in Cascade Mode should have all as Fast
+		 * interrupts or Normal interrupts, mixed interrupts are not
+		 * supported
+		 */
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0x0);
+
+#ifdef XPAR_MICROBLAZE_BASE_VECTORS
+		for (Id = 0; Id < 32 ; Id++)
+		{
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
+				+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
+				+ 0x10);
+		}
+#else
+		for (Id = 0; Id < 32 ; Id++)
+		{
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
+							+ (Id * 4), 0x10);
+		}
+#endif
+
+		/* Enable the Interrupt if it was enabled before calling this
+		 * function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Enable(InstancePtr, Id);
+		}
+
+	}
+	else {
+
+		/* Get the Enabled Interrupts */
+		CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET);
+		Mask = XIntc_BitPosMask[Id];/* Convert from integer id to bit mask */
+
+
+		/* Disable the Interrupt if it was enabled before
+		 * calling this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Disable(InstancePtr, Id);
+		}
+
+		/*
+		 * Disable the selected interrupt as Fast Interrupt by reading the
+		 * interrupt mode register and then modifying only the
+		 * specified interrupt id
+		 */
+		Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
+						    Imr & ~Mask);
+
+#ifdef XPAR_MICROBLAZE_BASE_VECTORS
+		for (Id = 0; Id < 32 ; Id++)
+		{
+			XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
+				+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
+				+ 0x10);
+		}
+#else
+		for (Id = 0; Id < 32 ; Id++)
+		{
+			XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
+							+ (Id * 4), 0x10);
+		}
+#endif
+		/* Enable the Interrupt if it was enabled before
+		 * calling this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Enable(InstancePtr, Id);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes Slave controllers in Cascade mode. The initialization entails:
+*	- Initial vector table with stub function calls
+*	- All interrupt sources are disabled for last controller.
+*	- All interrupt sources are disabled except sources to 31 pin of
+*	  primary and secondary controllers
+*	- Interrupt outputs are disabled
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XIntc_InitializeSlaves(XIntc * InstancePtr)
+{
+	int Index;
+	u32 Mask;
+	XIntc_Config *CfgPtr;
+	int Id;
+
+	Mask = XIntc_BitPosMask[31]; /* Convert from integer id to bit mask */
+
+	/* Enable interrupt id with 31 for Master
+	 * interrupt controller
+	 */
+	XIntc_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, Mask);
+
+	for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++) {
+		CfgPtr = XIntc_LookupConfig(Index);
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET,
+							0xFFFFFFFF);
+		if (CfgPtr->IntcType != XIN_INTC_LAST) {
+
+			/* Enable interrupt ids with 31 for secondary
+			 * interrupt controllers
+			 */
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
+									Mask);
+		} else {
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, 0x0);
+		}
+
+		/* Disable Interrupt output */
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET, 0);
+
+		/* Set all interrupts as normal mode if Fast Interrupts
+		 * are enabled
+		 */
+		if(CfgPtr->FastIntr == TRUE) {
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0);
+
+#ifdef XPAR_MICROBLAZE_BASE_VECTORS
+			for (Id = 0; Id < 32 ; Id++)
+			{
+				XIntc_Out32(CfgPtr->BaseAddress +
+					XIN_IVAR_OFFSET + (Id * 4),
+					XPAR_MICROBLAZE_BASE_VECTORS + 0x10);
+			}
+#else
+			for (Id = 0; Id < 32 ; Id++)
+			{
+				XIntc_Out32(CfgPtr->BaseAddress +
+					XIN_IVAR_OFFSET + (Id * 4), 0x10);
+			}
+#endif
+		}
+
+		/*
+		 * Initialize all the data needed to perform interrupt
+		 * processing for each interrupt ID up to the maximum used
+		 */
+		for (Id = 0; Id < CfgPtr->NumberofIntrs; Id++) {
+
+			/*
+			 * Initalize the handler to point to a stub to handle an
+			 * interrupt which has not been connected to a handler.
+			 * Only initialize it if the handler is 0 or
+			 * XNullHandler, which means it was not initialized
+			 * statically by the tools/user.Set the callback
+			 * reference to this instance so that unhandled
+			 * interrupts can be tracked.
+			 */
+			if ((CfgPtr->HandlerTable[Id].Handler == 0) ||
+				    (CfgPtr->HandlerTable[Id].Handler ==
+				     XNullHandler)) {
+				CfgPtr->HandlerTable[Id].Handler = StubHandler;
+			}
+			CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
+		}
+	}
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc.h b/thirdparty/xilinx/orig/intc_v3_4/src/xintc.h
new file mode 100644
index 000000000..080f01b51
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc.h
@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc.h
+* @addtogroup intc_v3_4
+* @{
+* @details
+*
+* The Xilinx interrupt controller driver component. This component supports the
+* Xilinx interrupt controller.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 0 and 31 inclusive with
+* 0 being the highest priority interrupt source.
+*
+* The Xilinx interrupt controller supports the following features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - master enable/disable
+*   - single callback per interrupt or all pending interrupts handled for
+*     each interrupt of the processor
+*
+* The acknowledgement of the interrupt within the interrupt controller is
+* selectable, either prior to the device's handler being called or after
+* the handler is called. This is necessary to support interrupt signal inputs
+* which are either edge or level signals.  Edge driven interrupt signals
+* require that the interrupt is acknowledged prior to the interrupt being
+* serviced in order to prevent the loss of interrupts which are occurring
+* extremely close together.  A level driven interrupt input signal requires
+* the interrupt to acknowledged after servicing the interrupt to ensure that
+* the interrupt only generates a single interrupt condition.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xintc_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The interrupt vector table for each interrupt controller device is declared
+* statically in xintc_g.c within the configuration data for each instance.
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table - to retrieve the vector table
+* for an instance of the interrupt controller. The user should populate the
+* vector table with handlers and callbacks at run-time using the XIntc_Connect()
+* and XIntc_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an argument
+* to be passed to the handler when an interrupt occurs.  The tools default this
+* argument to the base address of the interrupting device.  Note that the
+* device driver interrupt handlers given in this file do not take a base
+* address as an argument, but instead take a pointer to the driver instance.
+* This means that although the table is created statically, the user must still
+* use XIntc_Connect() when the interrupt handler takes an argument other than
+* the base address. This is only to say that the existence of the static vector
+* tables should not mislead the user into thinking they no longer need to
+* register/connect interrupt handlers with this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00a rpm  01/09/02 Removed the AckLocation argument from XIntc_Connect().
+*                     This information is now internal in xintc_g.c.
+* 1.00b jhl  02/13/02 Repartitioned the driver for smaller files
+* 1.00b jhl  04/24/02 Made LookupConfig function global and relocated config
+*                     data type
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table. Moved vector
+*                     table and options out of instance structure and into
+*                     the configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and _m is removed from
+*		      all the macro names/definitions.
+* 2.01a sdm  04/27/10 Updated the tcl so that the defintions are generated in
+*		      the xparameters.h to know whether the optional registers
+*		      SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
+*		      This driver doesnot make use of these definitions and does
+*		      not use the optional registers.
+* 2.03a hvm  05/24/11 Updated the tcl to generate vector Ids for external
+*		      interrupts. CR565336
+* 2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
+*		      and XIntc_SetNormalIntrMode for setting to normal
+*		      interrupt mode.
+* 2.04a asa  03/19/12 Changed the XIntc_Config struct. The order of entries
+*		      declared in the structure now matches with the
+*		      XIntc_ConfigTable generated by the driver tcl.
+* 2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
+*		      added IntVectorAddr to XIntc_Config for this.
+*		      Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.06a bss  01/28/13 To support Cascade mode:
+* 		      Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
+*		      XIN_INTC_SECONDARY,XIN_INTC_LAST and
+*		      XIN_CONTROLLER_MAX_INTRS  macros
+*		      Added NumberofIntrs and IntcType fields in XIntc_Config
+*		      structure.
+*		      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
+*		      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
+*		      XIntc_Acknowledge,XIntc_ConnectFastHandler and
+*		      XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
+*		      API in xintc.c
+*  		      Modified XIntc_DeviceInterruptHandler,
+*  		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
+*		      XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
+*		      API in xintc_l.c.
+*		      Modified XIntc_SetOptions API in xintc_options.c.
+*		      Modified XIntc_SimulateIntr API in xintc_selftest.c.
+*		      Modified driver tcl:
+*			to check for Cascade mode and generate XPAR_INTC_TYPE
+*			for each controller.
+*			Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
+*			interrupt sources of all Controllers in Cascade mode.
+* 2.07a bss  10/18/13 To support Nested interrupts:
+*		      Modified XIntc_DeviceInterruptHandler API.
+*		      Added XIN_ILR_OFFSET macro in xintc_l.h.
+*		      Modified driver tcl to generate HAS_ILR parameter in
+*		      xparameters.h
+* 3.0   bss  01/28/13 Modified xintc.c to initialize IVAR register with
+*		      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
+*		      CR#765931.
+*		      Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
+*		      correctly(CR#764865).
+*
+* @note
+*		For Cascade mode, Interrupt IDs are generated in xparameters.h
+*		as shown below:
+*
+*	    Master/Primary INTC
+*		 ______
+*		|      |-0      Secondary INTC
+*		|      |-.         ______
+*		|      |-.        |      |-32        Last INTC
+*		|      |-.        |      |-.          ______
+*		|______|<-31------|      |-.         |      |-64
+*			          |      |-.         |      |-.
+*			          |______|<-63-------|      |-.
+*                                                    |      |-.
+*                                                    |______|-95
+*
+*		All driver functions has to be called using DeviceId/
+*		InstancePtr/BaseAddress of Primary/Master Controller and
+*		Interrupts IDs generated in xparameters.h only.
+*		Driver functions takes care of Slave Controllers based on
+*		Interrupt ID passed. User must not use Interrupt source/ID
+*		31 of Primary and Secondary controllers to call driver
+*		functions.
+*
+*		For nested interrupts, XIntc_DeviceInterruptHandler saves
+*		microblaze r14 register on entry and restores on exit. This is
+*		required since compiler does not support nesting. It enables
+*		Microblaze interrupts after blocking further interrupts from
+*		the current interrupt number and interrupts below current
+*		interrupt proirity by writing to Interrupt Level Register of
+*		INTC on entry. On exit, it disables microblaze interrupts and
+*		restores ILR register default value(0xFFFFFFFF)back. It is
+*		recommended to increase STACK_SIZE in linker script for nested
+*		interrupts.
+* 3.0     adk    12/10/13  Updated as per the New Tcl API's
+* 3.0 	  adk 	 17/02/14  Fixed the CR:771287 Changes are made in the intc
+* 		           driver tcl.
+* 3.1     adk    8/4/14    Fixed the CR:783248 Changes are made in
+*			   the test-app tcl
+* 3.2     bss    4/8/14    Fixed driver tcl to handle external interrupt pins
+*			   correctly (CR#799609).
+* 3.3     adk    11/3/14   added generation of C_HAS_ILR parameter to
+*			   xparameters.h.Changes are made in the driver tcl file
+*			   (CR#828046).
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_H			/* prevent circular inclusions */
+#define XINTC_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xintc_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Configuration options
+ * These options are used in XIntc_SetOptions() to configure the device.
+ * @{
+ */
+/**
+ * <pre>
+ * XIN_SVC_SGL_ISR_OPTION	Service the highest priority pending interrupt
+ *				and then return.
+ * XIN_SVC_ALL_ISRS_OPTION	Service all of the pending interrupts and then
+ *				return.
+ * </pre>
+ */
+#define XIN_SVC_SGL_ISR_OPTION  1UL
+#define XIN_SVC_ALL_ISRS_OPTION 2UL
+/*@}*/
+
+/**
+ * @name Start modes
+ * One of these values is passed to XIntc_Start() to start the device.
+ * @{
+ */
+/** Simulation only mode, no hardware interrupts recognized */
+#define XIN_SIMULATION_MODE     0
+/** Real mode, no simulation allowed, hardware interrupts recognized */
+#define XIN_REAL_MODE           1
+/*@}*/
+
+/**
+ * @name Masks to specify Interrupt Controller Mode
+ * @{
+ */
+#define XIN_INTC_NOCASCADE     	0	/* Normal - No Cascade Mode */
+#define XIN_INTC_PRIMARY     	1	/* Master/Primary controller */
+#define XIN_INTC_SECONDARY     	2	/* Secondary Slave Controllers */
+#define XIN_INTC_LAST     	3	/* Last Slave Controller */
+
+/*@}*/
+
+/**
+ * @name Mask to specify maximum number of interrupt sources per controller
+ * @{
+ */
+#define XIN_CONTROLLER_MAX_INTRS	32  /* Each Controller has 32
+					       interrupt pins */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	u32 AckBeforeService;	/**< Ack location per interrupt */
+	int FastIntr;		/**< Fast Interrupt enabled */
+	u32 IntVectorAddr;	/**< Interrupt Vector Address */
+	int NumberofIntrs;      /**< Number of Interrupt sources */
+	u32 Options;		/**< Device options */
+	int IntcType;		/**< Intc type 0 - No Cascade Mode
+				               1 - primary instance
+				               2 - secondary instance
+				               3 - last instance */
+
+/** Static vector table of interrupt handlers */
+#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
+	XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
+#else
+	XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
+#endif
+
+} XIntc_Config;
+
+/**
+ * The XIntc driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	u32 BaseAddress;	 /**< Base address of registers */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 IsStarted;		 /**< Device has been started */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+	XIntc_Config *CfgPtr;	 /**< Pointer to instance config entry */
+
+} XIntc;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xintc.c
+ */
+int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
+
+int XIntc_Start(XIntc * InstancePtr, u8 Mode);
+void XIntc_Stop(XIntc * InstancePtr);
+
+int XIntc_Connect(XIntc * InstancePtr, u8 Id,
+		  XInterruptHandler Handler, void *CallBackRef);
+void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
+
+void XIntc_Enable(XIntc * InstancePtr, u8 Id);
+void XIntc_Disable(XIntc * InstancePtr, u8 Id);
+
+void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
+
+XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
+
+int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
+				XFastInterruptHandler Handler);
+void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
+
+/*
+ * Interrupt functions in xintr_intr.c
+ */
+void XIntc_VoidInterruptHandler(void);
+void XIntc_InterruptHandler(XIntc * InstancePtr);
+
+/*
+ * Options functions in xintc_options.c
+ */
+int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
+u32 XIntc_GetOptions(XIntc * InstancePtr);
+
+/*
+ * Self-test functions in xintc_selftest.c
+ */
+int XIntc_SelfTest(XIntc * InstancePtr);
+int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_g.c b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_g.c
new file mode 100644
index 000000000..46df40acb
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_g.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_g.c
+* @addtogroup intc_v3_4
+* @{
+*
+* This file contains a configuration table that specifies the configuration of
+* interrupt controller devices in the system.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  01/09/02 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.00b jhl  04/24/02 Compressed the ack table into a bit mask.
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* </pre>
+*
+* @internal
+*
+* This configuration table contains entries that are modified at runtime
+* by the driver. The EDK tools populate the table with default values for the
+* vector table and the options flag. These default values can be, and are,
+* overwritten at runtime by the driver.  This is a deviation from most drivers'
+* configuration tables in that most are created statically by the tools and
+* are never modified during runtime.  Most tables reflect only the hardware
+* configuration of the device. This Intc configuration table contains software
+* information in addition to hardware configuration.  The Intc configuration
+* table should be considered an exception to the usage of the configuration
+* table rather than the norm.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xintc.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Prototypes ******************************/
+
+/**
+ * This table contains configuration information for each intc device
+ * in the system. The XIntc driver must know when to acknowledge the interrupt.
+ * The entry which specifies this as a bit mask where each bit corresponds to
+ * a specific interrupt.  A bit set indicates to ack it before servicing it.
+ * Generally, acknowledge before service is used when the interrupt signal is
+ * edge-sensitive, and after when the signal is level-sensitive.
+ *
+ * Refer to the XIntc_Config data structure in xintc.h for details on how this
+ * table should be initialized.
+ */
+XIntc_Config XIntc_ConfigTable[] = {
+#if defined(XPAR_XINTC_NUM_INSTANCES) && XPAR_XINTC_NUM_INSTANCES > 0
+	{
+	 XPAR_INTC_0_DEVICE_ID,	/* Unique ID  of device */
+	 XPAR_INTC_0_BASEADDR,	/* Register base address */
+	 XPAR_INTC_0_ACK_BEFORE,	/* Ack before or after service */
+	 0			/* Device options */
+	 }
+#endif
+};
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_i.h b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_i.h
new file mode 100644
index 000000000..2c195dcde
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_i.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_i.h
+* @addtogroup intc_v3_4
+* @{
+*
+* This file contains data which is shared between files and internal to the
+* XIntc component. It is intended for internal use only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.00b jhl  04/24/02 Moved register definitions to xintc_l.h
+* 1.00c rpm  10/17/03 New release. Removed extern of global, single instance
+*                     pointer.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_I_H		/* prevent circular inclusions */
+#define XINTC_I_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xintc.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern u32 XIntc_BitPosMask[];
+
+extern XIntc_Config XIntc_ConfigTable[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_intr.c b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_intr.c
new file mode 100644
index 000000000..6eb210eb6
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_intr.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_intr.c
+* @addtogroup intc_v3_4
+* @{
+*
+* This file contains the interrupt processing for the XIntc component which
+* is the driver for the Xilinx Interrupt Controller.  The interrupt
+* processing is partitioned seperately such that users are not required to
+* use the provided interrupt processing.  This file requires other files of
+* the driver to be linked in also.
+*
+* Two different interrupt handlers are provided for this driver such that the
+* user must select the appropriate handler for the application.  The first
+* interrupt handler, XIntc_VoidInterruptHandler, is provided for systems
+* which use only a single interrupt controller or for systems that cannot
+* otherwise provide an argument to the XIntc interrupt handler (e.g., the RTOS
+* interrupt vector handler may not provide such a facility).  The constant
+* XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in
+* the driver.  The second interrupt handler, XIntc_InterruptHandler, uses an
+* input argument which is an instance pointer to an interrupt controller driver
+* such that multiple interrupt controllers can be supported.  This handler
+* requires the calling function to pass it the appropriate argument, so another
+* level of indirection may be required.
+*
+* Note that both of these handlers are now only provided for backward
+* compatibility. The handler defined in xintc_l.c is the recommended handler.
+*
+* The interrupt processing may be used by connecting one of the interrupt
+* handlers to the interrupt system.  These handlers do not save and restore
+* the processor context but only handle the processing of the Interrupt
+* Controller.  The two handlers are provided as working examples. The user is
+* encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00b jhl  02/13/02 First release
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table. Collapse handlers
+*                     to use the XIntc_DeviceInterruptHandler() in xintc_l.c.
+* 1.00c rpm  04/09/04 Added conditional compilation around the old handler
+*                     XIntc_VoidInterruptHandler(). This handler will only be
+*                     include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs.
+*
+* </pre>
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xintc.h"
+
+/************************** Constant Definitions *****************************/
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Interrupt handler for the driver used when there can be no argument passed
+* to the handler.  This function is provided mostly for backward compatibility.
+* The user should use XIntc_DeviceInterruptHandler(), defined in xintc_l.c,
+* if possible.
+*
+* The user must connect this function to the interrupt system such that it is
+* called whenever the devices which are connected to it cause an interrupt.
+*
+* @return	None.
+*
+* @note
+*
+* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
+* to be included in the driver compilation.
+*
+******************************************************************************/
+#ifdef XPAR_INTC_SINGLE_DEVICE_ID
+void XIntc_VoidInterruptHandler(void)
+{
+	/* Use the single instance to call the main interrupt handler */
+	XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for the driver. This function is provided mostly for
+* backward compatibility.  The user should use XIntc_DeviceInterruptHandler(),
+* defined in xintc_l.c when possible and pass the device ID of the interrupt
+* controller device as its argument.
+*
+* The user must connect this function to the interrupt system such that it is
+* called whenever the devices which are connected to it cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIntc_InterruptHandler(XIntc * InstancePtr)
+{
+	/* Assert that the pointer to the instance is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Use the instance's device ID to call the main interrupt handler.
+	 * (the casts are to avoid a compiler warning)
+	 */
+	XIntc_DeviceInterruptHandler((void *)
+				     ((u32) (InstancePtr->CfgPtr->DeviceId)));
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_l.c b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_l.c
new file mode 100644
index 000000000..375cf6b93
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_l.c
@@ -0,0 +1,665 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_l.c
+* @addtogroup intc_v3_4
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table.
+* 1.00c rpm  04/09/04 Added conditional compilation around the old handler
+*                     XIntc_LowLevelInterruptHandler(). This handler will only
+*                     be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
+*                     defined.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.10c ecm  07/09/07 Read the ISR after the Acknowledge in the interrupt
+*		      handler to support architectures with posted write bus
+*		      access issues.
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and  _m is removed
+*		      from all the macro definitions.
+* 2.04a bss  01/13/12 Removed the unused Register variable for warnings.
+* 2.05a bss  08/18/12 Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.06a bss  01/28/13 To support Cascade mode:
+*		      Modified XIntc_DeviceInterruptHandler,
+*		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
+*		      XIntc_RegisterFastHandler APIs.
+*		      Added XIntc_CascadeHandler API.
+* 2.07a bss  10/18/13 Modified XIntc_DeviceInterruptHandler to support
+*		      nested interrupts.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress);
+
+#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
+static void XIntc_CascadeHandler(void *DeviceId);
+#endif
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This is the interrupt handler for the driver interface provided in this file
+* when there can be no argument passed to the handler. In this case, we just
+* use the globally defined device ID for the interrupt controller. This function
+* is provided mostly for backward compatibility. The user should use
+* XIntc_DeviceInterruptHandler() if possible.
+*
+* This function does not support multiple interrupt controller instances to be
+* handled.
+*
+* The user must connect this function to the interrupt system such that it is
+* called whenever the devices which are connected to it cause an interrupt.
+*
+* @return	None.
+*
+* @note
+*
+* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
+* to be included in the driver compilation.
+*
+******************************************************************************/
+#ifdef XPAR_INTC_SINGLE_DEVICE_ID
+void XIntc_LowLevelInterruptHandler(void)
+{
+	/*
+	 * A level of indirection here because the interrupt handler used with
+	 * the driver interface given in this file needs to remain void - no
+	 * arguments.  So we need the globally defined device ID of THE
+	 * interrupt controller.
+	 */
+	XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the AckBeforeService flag in the configuration data to determine when to
+* acknowledge the interrupt. Highest priority interrupts are serviced first.
+* This function assumes that an interrupt vector table has been previously
+* initialized.It does not verify that entries in the table are valid before
+* calling an interrupt handler. In Cascade mode this function calls
+* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
+* This functions also handles interrupts nesting by  saving and restoring link
+* register of Microblaze and Interrupt Level register of interrupt controller
+* properly.
+
+* @param	DeviceId is the zero-based device ID defined in xparameters.h
+*		of the interrupting interrupt controller. It is used as a direct
+*		index into the configuration data, which contains the vector
+*		table for the interrupt controller. Note that even though the
+*		argument is a void pointer, the value is not a pointer but the
+*		actual device ID.  The void pointer type is necessary to meet
+*		the XInterruptHandler typedef for interrupt handlers.
+*
+* @return	None.
+*
+* @note		For nested interrupts, this function saves microblaze r14
+*		register on entry and restores on exit. This is required since
+*		compiler does not support nesting. This function enables
+*		Microblaze interrupts after blocking further interrupts
+*		from the current interrupt number and interrupts below current
+*		interrupt proirity by writing to Interrupt Level Register of
+*		INTC on entry. On exit, it disables microblaze interrupts and
+*		restores ILR register default value(0xFFFFFFFF)back. It is
+*		recommended to increase STACK_SIZE in linker script for nested
+*		interrupts.
+*
+******************************************************************************/
+void XIntc_DeviceInterruptHandler(void *DeviceId)
+{
+	u32 IntrStatus;
+	u32 IntrMask = 1;
+	int IntrNumber;
+	XIntc_Config *CfgPtr;
+	u32 Imr;
+
+	/* Get the configuration data using the device ID */
+	CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
+
+#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
+	if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
+		XIntc_CascadeHandler(DeviceId);
+	}
+	else
+#endif
+	{ /* This extra brace is required for compilation in Cascade Mode */
+
+#if XPAR_XINTC_HAS_ILR == TRUE
+#ifdef __MICROBLAZE__
+		volatile u32 R14_register;
+		/* Save r14 register */
+		R14_register = mfgpr(r14);
+#endif
+		volatile u32 ILR_reg;
+		/* Save ILR register */
+		ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
+#endif
+		/* Get the interrupts that are waiting to be serviced */
+		IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
+
+		/* Mask the Fast Interrupts */
+		if (CfgPtr->FastIntr == TRUE) {
+			Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
+			IntrStatus &=  ~Imr;
+		}
+
+		/* Service each interrupt that is active and enabled by
+		 * checking each bit in the register from LSB to MSB which
+		 * corresponds to an interrupt input signal
+		 */
+		for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
+								IntrNumber++) {
+			if (IntrStatus & 1) {
+				XIntc_VectorTableEntry *TablePtr;
+#if XPAR_XINTC_HAS_ILR == TRUE
+				/* Write to ILR the current interrupt
+				* number
+				*/
+				Xil_Out32(CfgPtr->BaseAddress +
+						XIN_ILR_OFFSET, IntrNumber);
+
+				/* Read back ILR to ensure the value
+				* has been updated and it is safe to
+				* enable interrupts
+				*/
+
+				Xil_In32(CfgPtr->BaseAddress +
+						XIN_ILR_OFFSET);
+
+				/* Enable interrupts */
+				Xil_ExceptionEnable();
+#endif
+				/* If the interrupt has been setup to
+				 * acknowledge it before servicing the
+				 * interrupt, then ack it */
+				if (CfgPtr->AckBeforeService & IntrMask) {
+					XIntc_AckIntr(CfgPtr->BaseAddress,
+								IntrMask);
+				}
+
+				/* The interrupt is active and enabled, call
+				 * the interrupt handler that was setup with
+				 * the specified parameter
+				 */
+				TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
+				TablePtr->Handler(TablePtr->CallBackRef);
+
+				/* If the interrupt has been setup to
+				 * acknowledge it after it has been serviced
+				 * then ack it
+				 */
+				if ((CfgPtr->AckBeforeService &
+							IntrMask) == 0) {
+					XIntc_AckIntr(CfgPtr->BaseAddress,
+								IntrMask);
+				}
+
+#if XPAR_XINTC_HAS_ILR == TRUE
+				/* Disable interrupts */
+				Xil_ExceptionDisable();
+				/* Restore ILR */
+				Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
+								ILR_reg);
+#endif
+				/*
+				 * Read the ISR again to handle architectures
+				 * with posted write bus access issues.
+				 */
+				 XIntc_GetIntrStatus(CfgPtr->BaseAddress);
+
+				/*
+				 * If only the highest priority interrupt is to
+				 * be serviced, exit loop and return after
+				 * servicing
+				 * the interrupt
+				 */
+				if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
+
+#if XPAR_XINTC_HAS_ILR == TRUE
+#ifdef __MICROBLAZE__
+					/* Restore r14 */
+					mtgpr(r14, R14_register);
+#endif
+#endif
+					return;
+				}
+			}
+
+			/* Move	 to the next interrupt to check */
+			IntrMask <<= 1;
+			IntrStatus >>= 1;
+
+			/* If there are no other bits set indicating that all
+			 * interrupts have been serviced, then exit the loop
+			 */
+			if (IntrStatus == 0) {
+				break;
+			}
+		}
+#if XPAR_XINTC_HAS_ILR == TRUE
+#ifdef __MICROBLAZE__
+		/* Restore r14 */
+		mtgpr(r14, R14_register);
+#endif
+#endif
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the interrupt service option, which can configure the driver so that it
+* services only a single interrupt at a time when an interrupt occurs, or
+* services all pending interrupts when an interrupt occurs. The default
+* behavior when using the driver interface given in xintc.h file is to service
+* only a single interrupt, whereas the default behavior when using the driver
+* interface given in this file is to service all outstanding interrupts when an
+* interrupt occurs. In Cascade mode same Option is set to Slave controllers.
+*
+* @param	BaseAddress is the unique identifier for a device.
+* @param 	Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
+*		interrupt serviced when an interrupt occurs, or
+*		XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
+*		serviced when an interrupt occurs.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option)
+{
+	XIntc_Config *CfgPtr;
+
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+	if (CfgPtr != NULL) {
+		CfgPtr->Options = Option;
+		/* If Cascade mode set the option for all Slaves */
+		if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
+			int Index;
+			for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
+					Index++) {
+				CfgPtr = XIntc_LookupConfig(Index);
+				CfgPtr->Options = Option;
+			}
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* This function can also be used to remove a handler from the vector table
+* by passing in the XIntc_DefaultHandler() as the handler and NULL as the
+* callback reference.
+* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
+* Controller
+*
+* @param 	BaseAddress is the base address of the interrupt controller
+*		whose vector table will be modified.
+* @param 	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param 	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
+			   XInterruptHandler Handler, void *CallBackRef)
+{
+	XIntc_Config *CfgPtr;
+
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if (CfgPtr != NULL) {
+
+		if (InterruptId > 31) {
+			CfgPtr = XIntc_LookupConfig(InterruptId/32);
+			CfgPtr->HandlerTable[InterruptId%32].Handler = Handler;
+			CfgPtr->HandlerTable[InterruptId%32].CallBackRef =
+								CallBackRef;
+		}
+		else {
+			CfgPtr->HandlerTable[InterruptId].Handler = Handler;
+			CfgPtr->HandlerTable[InterruptId].CallBackRef =
+								CallBackRef;
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the base address of the device.
+* A table contains the configuration info for each device in the system.
+*
+* @param	BaseAddress is the unique identifier for a device.
+*
+* @return
+*
+* A pointer to the configuration structure for the specified device, or
+* NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress)
+{
+	XIntc_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
+		if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) {
+			CfgPtr = &XIntc_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a fast handler function for a specific interrupt ID. The handler
+* function will be called when an interrupt occurs for the given interrupt ID.
+* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
+* Controller
+*
+* @param 	BaseAddress is the base address of the interrupt controller
+*		whose vector table will be modified.
+* @param 	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param 	FastHandler is the function pointer that will be called when
+*   		interrupt occurs
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
+					XFastInterruptHandler FastHandler)
+{
+	u32 CurrentIER;
+	u32 Mask;
+	u32 Imr;
+	XIntc_Config *CfgPtr;
+
+
+	if (Id > 31) {
+		/* Enable user required Id in Slave controller */
+		CfgPtr = XIntc_LookupConfig(Id/32);
+
+		/* Get the Enabled Interrupts */
+		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[(Id%32)];
+
+		/* Disable the Interrupt if it was enabled before calling
+		 * this function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
+							(CurrentIER & ~Mask));
+		}
+
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
+					((Id%32) * 4), (u32) FastHandler);
+
+		/* Slave controllers in Cascade Mode should have all as Fast
+		 * interrupts or Normal interrupts, mixed interrupts are not
+		 * supported
+		 */
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
+
+		/* Enable the Interrupt if it was enabled before calling this
+		 * function
+		 */
+		if (CurrentIER & Mask) {
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
+						(CurrentIER | Mask));
+		}
+	}
+	else {
+
+		CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
+
+		/* Convert from integer id to bit mask */
+		Mask = XIntc_BitPosMask[Id];
+
+		if (CurrentIER & Mask) {
+			/* Disable Interrupt if it was enabled */
+			CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
+			XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
+							(CurrentIER & ~Mask));
+		}
+
+		XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4),
+						(u32) FastHandler);
+
+		Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET);
+		XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask);
+
+
+		/* Enable Interrupt if it was enabled before calling
+		 * this function
+		 */
+		if (CurrentIER & Mask) {
+			CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
+			XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
+							(CurrentIER | Mask));
+		}
+	}
+}
+
+#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
+/*****************************************************************************/
+/**
+*
+* This function is called by primary interrupt handler for the driver to handle
+* all Controllers in Cascade mode.It will resolve which interrupts are active
+* and enabled and call the appropriate interrupt handler. It uses the
+* AckBeforeService flag in the configuration data to determine when to
+* acknowledge the interrupt. Highest priority interrupts are serviced first.
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.This function calls itself recursively to handle
+* all interrupt controllers.
+*
+* @param	DeviceId is the zero-based device ID defined in xparameters.h
+*		of the interrupting interrupt controller. It is used as a direct
+*		index into the configuration data, which contains the vector
+*		table for the interrupt controller.
+*
+* @return	None.
+*
+* @note
+*
+******************************************************************************/
+static void XIntc_CascadeHandler(void *DeviceId)
+{
+	u32 IntrStatus;
+	u32 IntrMask = 1;
+	int IntrNumber;
+	u32 Imr;
+	XIntc_Config *CfgPtr;
+	static int Id = 0;
+
+	/* Get the configuration data using the device ID */
+	CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
+
+	/* Get the interrupts that are waiting to be serviced */
+	IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
+
+	/* Mask the Fast Interrupts */
+	if (CfgPtr->FastIntr == TRUE) {
+		Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
+		IntrStatus &=  ~Imr;
+	}
+
+	/* Service each interrupt that is active and enabled by
+	 * checking each bit in the register from LSB to MSB which
+	 * corresponds to an interrupt input signal
+	 */
+	for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) {
+		if (IntrStatus & 1) {
+			XIntc_VectorTableEntry *TablePtr;
+
+			/* In Cascade mode call this function recursively
+			 * for interrupt id 31 and until interrupts of last
+			 * instance/controller are handled
+			 */
+			if ((IntrNumber == 31) &&
+			  (CfgPtr->IntcType != XIN_INTC_LAST) &&
+			  (CfgPtr->IntcType != XIN_INTC_NOCASCADE)) {
+				XIntc_CascadeHandler((void *)++Id);
+				Id--;
+			}
+
+			/* If the interrupt has been setup to
+			 * acknowledge it before servicing the
+			 * interrupt, then ack it */
+			if (CfgPtr->AckBeforeService & IntrMask) {
+				XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
+			}
+
+			/* Handler of 31 interrupt Id has to be called only
+			 * for Last controller in cascade Mode
+			 */
+			if (!((IntrNumber == 31) &&
+			  (CfgPtr->IntcType != XIN_INTC_LAST) &&
+			  (CfgPtr->IntcType != XIN_INTC_NOCASCADE))) {
+
+				/* The interrupt is active and enabled, call
+				 * the interrupt handler that was setup with
+				 * the specified parameter
+				 */
+				TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
+				TablePtr->Handler(TablePtr->CallBackRef);
+			}
+			/* If the interrupt has been setup to acknowledge it
+			 * after it has been serviced then ack it
+			 */
+			if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
+				XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
+			}
+
+			/*
+			 * Read the ISR again to handle architectures with
+			 * posted write bus access issues.
+			 */
+			 XIntc_GetIntrStatus(CfgPtr->BaseAddress);
+
+			/*
+			 * If only the highest priority interrupt is to be
+			 * serviced, exit loop and return after servicing
+			 * the interrupt
+			 */
+			if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
+				return;
+			}
+		}
+
+		/* Move	 to the next interrupt to check */
+		IntrMask <<= 1;
+		IntrStatus >>= 1;
+
+		/* If there are no other bits set indicating that all interrupts
+		 * have been serviced, then exit the loop
+		 */
+		if (IntrStatus == 0) {
+			break;
+		}
+	}
+}
+#endif
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_l.h b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_l.h
new file mode 100644
index 000000000..9d9c9eaff
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_l.h
@@ -0,0 +1,330 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_l.h
+* @addtogroup intc_v3_4
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+*
+* Note that users of the driver interface given in this file can register
+* an interrupt handler dynamically (at run-time) using the
+* XIntc_RegisterHandler() function.
+* User of the driver interface given in xintc.h should still use
+* XIntc_Connect(), as always.
+* Also see the discussion of the interrupt vector tables in xintc.h.
+*
+* There are currently two interrupt handlers specified in this interface.
+*
+* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
+*   is used in cases where there is a single interrupt controller device in
+*   the system and the handler cannot be passed an argument. This function is
+*   provided mostly for backward compatibility.
+*
+* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
+*   argument, indicating which interrupt controller device in the system is
+*   causing the interrupt - thereby supporting multiple interrupt controllers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs. _m is removed from all
+*		      the macro definitions.
+* 2.04a bss  01/13/12 Updated for adding defines for IMR and IVAR for
+*                     the FAST Interrupt
+* 2.05a bss  08/18/12 Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.07a bss  10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_L_H		/* prevent circular inclusions */
+#define XINTC_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xil_io.h"
+
+/*
+ * XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
+ * accessed through a DCR bus connected to a bridge.
+ */
+#define XPAR_XINTC_USE_DCR_BRIDGE 0
+
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+#include "xio_dcr.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* define the offsets from the base address for all the registers of the
+ * interrupt controller, some registers may be optional in the hardware device
+ */
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+
+#define XIN_ISR_OFFSET      0	/* Interrupt Status Register */
+#define XIN_IPR_OFFSET      1	/* Interrupt Pending Register */
+#define XIN_IER_OFFSET      2	/* Interrupt Enable Register */
+#define XIN_IAR_OFFSET      3	/* Interrupt Acknowledge Register */
+#define XIN_SIE_OFFSET      4	/* Set Interrupt Enable Register */
+#define XIN_CIE_OFFSET      5	/* Clear Interrupt Enable Register */
+#define XIN_IVR_OFFSET      6	/* Interrupt Vector Register */
+#define XIN_MER_OFFSET      7	/* Master Enable Register */
+#define XIN_IMR_OFFSET      8	/* Interrupt Mode Register , this is present
+				 *  only for Fast Interrupt */
+#define XIN_IVAR_OFFSET     64  /* Interrupt Vector Address Register
+				 * Interrupt 0 Offest, this is present
+				 * only for Fast Interrupt */
+
+#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
+
+#define XIN_ISR_OFFSET      0	/* Interrupt Status Register */
+#define XIN_IPR_OFFSET      4	/* Interrupt Pending Register */
+#define XIN_IER_OFFSET      8	/* Interrupt Enable Register */
+#define XIN_IAR_OFFSET      12	/* Interrupt Acknowledge Register */
+#define XIN_SIE_OFFSET      16	/* Set Interrupt Enable Register */
+#define XIN_CIE_OFFSET      20	/* Clear Interrupt Enable Register */
+#define XIN_IVR_OFFSET      24	/* Interrupt Vector Register */
+#define XIN_MER_OFFSET      28	/* Master Enable Register */
+#define XIN_IMR_OFFSET      32	/* Interrupt Mode Register , this is present
+				 *  only for Fast Interrupt */
+#define XIN_ILR_OFFSET      36  /* Interrupt level register */
+#define XIN_IVAR_OFFSET     0x100 /* Interrupt Vector Address Register
+				   * Interrupt 0 Offest, this is present
+				   * only for Fast Interrupt */
+
+
+
+#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
+
+/* Bit definitions for the bits of the MER register */
+
+#define XIN_INT_MASTER_ENABLE_MASK      0x1UL
+#define XIN_INT_HARDWARE_ENABLE_MASK    0x2UL	/* once set cannot be cleared */
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the driver interface given in this file and an instance pointer for the
+ * driver interface given in xintc.h file.
+ */
+typedef struct {
+	XInterruptHandler Handler;
+	void *CallBackRef;
+} XIntc_VectorTableEntry;
+
+typedef void (*XFastInterruptHandler) (void);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Define the appropriate I/O access method to memory mapped I/O or DCR.
+ */
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+
+#define XIntc_In32  XIo_DcrIn
+#define XIntc_Out32 XIo_DcrOut
+
+#else
+
+#define XIntc_In32  Xil_In32
+#define XIntc_Out32 Xil_Out32
+
+#endif
+
+/****************************************************************************/
+/**
+*
+* Enable all interrupts in the Master Enable register of the interrupt
+* controller.  The interrupt controller defaults to all interrupts disabled
+* from reset such that this macro must be used to enable interrupts.
+*
+* @param	BaseAddress is the base address of the device.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_MasterEnable(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_MasterEnable(BaseAddress) \
+	XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
+	XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable all interrupts in the Master Enable register of the interrupt
+* controller.
+*
+* @param	BaseAddress is the base address of the device.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_MasterDisable(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_MasterDisable(BaseAddress) \
+	XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	EnableMask is the 32-bit value to write to the enable register.
+*		Each bit of the mask corresponds to an interrupt input signal
+*		that is connected to the interrupt controller (INT0 = LSB).
+*		Only the bits which are set in the mask will enable interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
+*
+*****************************************************************************/
+#define XIntc_EnableIntr(BaseAddress, EnableMask) \
+	XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	DisableMask is the 32-bit value to write to the enable register.
+*		Each bit of the mask corresponds to an interrupt input signal
+*		that is connected to the interrupt controller (INT0 = LSB).
+*		Only the bits which are set in the mask will disable interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
+*
+*****************************************************************************/
+#define XIntc_DisableIntr(BaseAddress, DisableMask) \
+	XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
+
+/****************************************************************************/
+/**
+*
+* Acknowledge specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	AckMask is the 32-bit value to write to the acknowledge
+*		register. Each bit of the mask corresponds to an interrupt input
+*		signal that is connected to the interrupt controller (INT0 =
+*		LSB).  Only the bits which are set in the mask will acknowledge
+*		interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
+*
+*****************************************************************************/
+#define XIntc_AckIntr(BaseAddress, AckMask) \
+	XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
+
+/****************************************************************************/
+/**
+*
+* Get the interrupt status from the interrupt controller which indicates
+* which interrupts are active and enabled.
+*
+* @param	BaseAddress is the base address of the device
+*
+* @return	The 32-bit contents of the interrupt status register. Each bit
+*		corresponds to an interrupt input signal that is connected to
+*		the interrupt controller (INT0 = LSB). Bits which are set
+*		indicate an active interrupt which is also enabled.
+*
+* @note		C-style signature:
+*		u32 XIntc_GetIntrStatus(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_GetIntrStatus(BaseAddress) \
+	(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
+	XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Interrupt controller handlers, to be connected to processor exception
+ * handling code.
+ */
+void XIntc_LowLevelInterruptHandler(void);
+void XIntc_DeviceInterruptHandler(void *DeviceId);
+
+/* Various configuration functions */
+void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option);
+
+void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
+			   XInterruptHandler Handler, void *CallBackRef);
+
+void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
+					XFastInterruptHandler FastHandler);
+
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_options.c b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_options.c
new file mode 100644
index 000000000..0a6668bb0
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_options.c
@@ -0,0 +1,149 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_options.c
+* @addtogroup intc_v3_4
+* @{
+*
+* Contains option functions for the XIntc driver. These functions allow the
+* user to configure an instance of the XIntc driver.  This file requires other
+* files of the component to be linked in also.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00b jhl  02/21/02 First release
+* 1.00c rpm  10/17/03 New release. Support the relocation of the options flag
+*                     from the instance structure to the xintc_g.c
+*                     configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs
+* 2.06a bss  01/28/13 To support Cascade mode:
+*		      Modified XIntc_SetOptions API.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xintc.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Set the options for the interrupt controller driver. In Cascade mode same
+* Option is set to Slave controllers.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Options to be set. The available options are described in
+*		xintc.h.
+*
+* @return
+* 		- XST_SUCCESS if the options were set successfully
+* 		- XST_INVALID_PARAM if the specified option was not valid
+*
+* @note		None.
+*
+****************************************************************************/
+int XIntc_SetOptions(XIntc * InstancePtr, u32 Options)
+{
+	XIntc_Config *CfgPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Make sure option request is valid
+	 */
+	if ((Options == XIN_SVC_SGL_ISR_OPTION) ||
+	    (Options == XIN_SVC_ALL_ISRS_OPTION)) {
+		InstancePtr->CfgPtr->Options = Options;
+		/* If Cascade mode set the option for all Slaves */
+		if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
+			int Index;
+			for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
+								Index++) {
+				CfgPtr = XIntc_LookupConfig(Index);
+				CfgPtr->Options = Options;
+			}
+		}
+		return XST_SUCCESS;
+	}
+	else {
+		return XST_INVALID_PARAM;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Return the currently set options.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+*
+* @return	The currently set options. The options are described in xintc.h.
+*
+* @note		None.
+*
+****************************************************************************/
+u32 XIntc_GetOptions(XIntc * InstancePtr)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return InstancePtr->CfgPtr->Options;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/intc_v3_4/src/xintc_selftest.c b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_selftest.c
new file mode 100644
index 000000000..78558c188
--- /dev/null
+++ b/thirdparty/xilinx/orig/intc_v3_4/src/xintc_selftest.c
@@ -0,0 +1,255 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_selftest.c
+* @addtogroup intc_v3_4
+* @{
+*
+* Contains diagnostic self-test functions for the XIntc component. This file
+* requires other files of the component to be linked in also.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/21/02 First release
+* 1.10c mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs
+* 2.04a bss  01/16/12 Removed CurrentMIE variable and reading of the
+*                     MER register to remove warnings
+* 2.06a bss  01/28/13 To support Cascade mode:
+*		      Modified XIntc_SimulateIntr API.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XIN_TEST_MASK 1
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This is a destructive test.
+*
+* This involves forcing interrupts into the controller and verifying that they
+* are recognized and can be acknowledged. This test will not succeed if the
+* interrupt controller has been started in real mode such that interrupts
+* cannot be forced.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the
+*		self-test. It will fail the self test if the device has
+*		previously been started in real mode.
+*
+* @note		None.
+*
+******************************************************************************/
+int XIntc_SelfTest(XIntc * InstancePtr)
+{
+	u32 CurrentISR;
+	u32 Temp;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Acknowledge all pending interrupts by reading the interrupt status
+	 * register and writing the value to the acknowledge register
+	 */
+	Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
+
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
+
+	/*
+	 * Verify that there are no interrupts by reading the interrupt status
+	 */
+	CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
+
+	/*
+	 * ISR should be zero after all interrupts are acknowledged
+	 */
+	if (CurrentISR != 0) {
+		return XST_INTC_FAIL_SELFTEST;
+	}
+
+	/*
+	 * Set a bit in the ISR which simulates an interrupt
+	 */
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK);
+
+	/*
+	 * Verify that it was set
+	 */
+	CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
+
+	if (CurrentISR != XIN_TEST_MASK) {
+		return XST_INTC_FAIL_SELFTEST;
+	}
+
+	/*
+	 * Acknowledge the interrupt
+	 */
+	XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK);
+
+	/*
+	 * Read back the ISR to verify that the interrupt is gone
+	 */
+	CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
+
+	if (CurrentISR != 0) {
+		return XST_INTC_FAIL_SELFTEST;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller. This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode. Once it has been started in real mode,
+* interrupts cannot be simulated. A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it. In Cascade mode writes to ISR of appropraite Slave
+* controller depending on Id.
+*
+* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
+* @param	Id is the interrupt ID for which to simulate an interrupt.
+*
+* @return
+* 		- XST_SUCCESS if successful
+*		- XST_FAILURE if the interrupt could not be
+* 		simulated because the interrupt controller is or
+*		has previously been in real mode.
+*
+* @note		None.
+*
+******************************************************************************/
+int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id)
+{
+	u32 Mask;
+	u32 MasterEnable;
+	XIntc_Config *CfgPtr;
+	int Index;
+	int DeviceId;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
+
+
+	/* Get the contents of the master enable register and determine if
+	 * hardware interrupts have already been enabled, if so, this is a write
+	 * once bit such that simulation can't be done at this point because
+	 * the ISR register is no longer writable by software
+	 */
+	MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET);
+	if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
+		return XST_FAILURE;
+	}
+
+
+	if (Id > 31) {
+
+		DeviceId = Id/32;
+
+		CfgPtr = XIntc_LookupConfig(Id/32);
+		Mask = XIntc_BitPosMask[Id%32];
+		XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask);
+
+		/* Generate interrupt for 31 by writing to Interrupt Status
+		 * register of parent controllers. Primary controller ISR
+		 * will be written last in the loop
+		 */
+		Mask = XIntc_BitPosMask[31];
+		for (Index = DeviceId - 1; Index >= 0; Index--)
+		{
+			CfgPtr = XIntc_LookupConfig(Index);
+
+			XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET,
+									Mask);
+		}
+	}
+	else {
+		/*
+		 * The Id is used to create the appropriate mask for the
+		 * desired bit position.
+		 */
+		Mask = XIntc_BitPosMask[Id];
+
+		/*
+		 * Enable the selected interrupt source by reading the interrupt
+		 * enable register and then modifying only the specified
+		 * interrupt id enable
+		 */
+		XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask);
+
+	}
+	/* indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/data/llfifo.mdd b/thirdparty/xilinx/orig/llfifo_v5_0/data/llfifo.mdd
new file mode 100644
index 000000000..63585bbbf
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/data/llfifo.mdd
@@ -0,0 +1,47 @@
+###############################################################################
+#
+# Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# Ver      Who    Date     Changes
+# -------- ------ -------- --------------------------------------------------
+# 4.0     adk    10/12/13  Removed support for xps_ll_fifo
+##############################################################################
+OPTION psf_version = 2.1;
+
+BEGIN driver llfifo
+
+  OPTION supported_peripherals = (axi_fifo_mm_s_v[4-9]_[1-9]);
+  OPTION driver_state = ACTIVE;
+  OPTION copyfiles = all;
+  OPTION VERSION = 5.0;
+  OPTION NAME = llfifo;
+
+END driver
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/data/llfifo.tcl b/thirdparty/xilinx/orig/llfifo_v5_0/data/llfifo.tcl
new file mode 100644
index 000000000..0f4d79291
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/data/llfifo.tcl
@@ -0,0 +1,53 @@
+###############################################################################
+#
+# Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# Modification History
+#
+# Ver   Who  Date     Changes
+# ----- ---- -------- -----------------------------------------------
+# 2.00a sdm  07/26/10 Updated to use the string "Axi_Fifo" in canonical
+#                     definitions for AxiFifo
+# 3.00a adk  08/10/13 Added parameters C_AXI4_BASEADDR and C_AXI4_HIGHADDR
+#		      and C_DATA_INTERFACE_TYPE inorder to support AXI4
+#		      Datainterface.
+# 4.0      adk    12/10/13 Updated as per the New Tcl API's
+#
+##############################################################################
+
+
+proc generate {drv_handle} {
+    ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XLlFifo"  "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR"  "C_AXI4_BASEADDR" "C_AXI4_HIGHADDR" "C_DATA_INTERFACE_TYPE"
+
+    ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "Axi_Fifo" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_AXI4_BASEADDR" "C_AXI4_HIGHADDR" "C_DATA_INTERFACE_TYPE"
+
+   ::hsi::utils::define_config_file $drv_handle "xllfifo_g.c" "XLlFifo"  "DEVICE_ID" "C_BASEADDR" "C_AXI4_BASEADDR" "C_DATA_INTERFACE_TYPE"
+}
\ No newline at end of file
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/HTML_custom.css b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/HTML_custom.css
new file mode 100644
index 000000000..26defe1a8
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/HTML_custom.css
@@ -0,0 +1,1430 @@
+/* The standard CSS for doxygen 1.8.5 */
+
+body{
+	background: none repeat scroll 0 0 #FFFFFF;
+	color: #51626F;
+	font-family: arial,sans-serif !important;
+    	font-size: 75% !important;
+    	font-weight: normal !important;
+    	margin-left: 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+.contents, .textblock {
+font: 400 12px/15px arial,sans-serif;
+}
+.textblock ul, .contents ul{ 
+	margin: 5px 0;
+	padding: 0;
+}
+.textblockol {
+	margin:5px 15px; 
+	padding:0;
+	list-style-image: none; 
+}
+.textblock li, .contents li {
+	margin: 0 0 2px 15px;
+    	padding: 0 0 2px 2px;
+}
+
+/* For hiding RHS TOC 
+.toc{
+display:none;
+}*/
+/* For hiding RHS TOC*/ 
+
+For hiding Nav Bar
+.navpath, #nav-path{
+display:none;
+}
+/* For hiding Nav Bar*/
+/* For hiding extra navrows */
+#navrow2, #navrow3, #navrow4, #navrow5 {
+display:none;
+}
+/* @group Heading Levels */
+
+.title {
+	font: 400 14px/28px arial,sans-serif;
+	font-size: 150%;
+	font-weight: bold;
+	margin: 9px 2px;
+	text-align: left;
+}
+
+h2, h3 {
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+    text-indent: 0 !important;
+}
+h4, h5{
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+}
+h5{
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+h6{
+    color: #E66A08 !important;
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+p {
+    padding-bottom: 0px !important;
+	font: 400 12px/15px arial,sans-serif;
+}
+li p {
+    padding-bottom: 0px !important;
+	margin: 0px;
+}
+
+h1, h2.groupheader {
+    clear: both !important;
+    color: #627178 !important;
+    font-size: 1.4em !important;
+    font-weight: bold !important;
+    line-height: 28px !important;
+    margin-top: 0.6em !important;
+}
+
+h1, h2, h3, h4, h5, h6 {
+	-webkit-transition: text-shadow 0.5s linear;
+	-moz-transition: text-shadow 0.5s linear;
+	-ms-transition: text-shadow 0.5s linear;
+	-o-transition: text-shadow 0.5s linear;
+	transition: text-shadow 0.5s linear;
+	margin-right: 15px;
+}
+
+h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {
+	text-shadow: 0 0 15px cyan;
+}
+
+dt {
+	font-weight: bold;
+}
+
+
+/*Hiding Tabs - Tushar
+div.tabs 
+{ 
+    visibility: hidden; 
+} */
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #017bba;
+	font-weight: normal;
+	text-decoration: none;
+	/*font: 400 12px/15px;*/
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code, a.code:visited, a.line, a.line:visited {
+	color: #4665A2;
+}
+
+a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {
+	color: #4665A2; 
+	/*font: 400 12px/15px;*/
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+pre.fragment {
+        border: 0px solid #C4CFE5;
+        background-color: #FFFFFF;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        font-size:  9pt;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 105%;
+}
+
+div.fragment {
+        padding: 0px;
+        margin: 0px;
+	background-color: #FFFFFF;
+	border: 0px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 13px;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+div.line.glow {
+	background-color: cyan;
+	box-shadow: 0 0 10px cyan;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #51626F
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: cyan;
+	box-shadow: 0 0 15px cyan;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
+        border-bottom: 1px solid #DEE4F0;
+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+	font-size: 80%;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+        -webkit-transition: box-shadow 0.5s linear;
+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
+        display: table !important;
+        width: 100%;
+}
+
+.memitem.glow {
+         box-shadow: 0 0 15px cyan;
+}
+
+.memname {
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memname td {
+	vertical-align: bottom;
+}
+
+.memproto, dl.reflist dt {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #E66A08 !important;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+.memdoc, dl.reflist dd {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 6px 10px 2px 10px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        background-image:url('nav_g.png');
+        background-repeat:repeat-x;
+        background-color: #FFFFFF;
+        /* opera specific markup */
+        border-bottom-left-radius: 4px;
+        border-bottom-right-radius: 4px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 4px;
+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 4px;
+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
+        margin: 0px 0px 10px 0px;
+        padding: 5px;
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+.paramname code {
+        line-height: 14px;
+}
+
+.params, .retval, .exception, .tparams {
+        margin-left: 0px;
+        padding-left: 0px;
+		font: 400 12px/15px arial,sans-serif;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+table.mlabels {
+	border-spacing: 0px;
+}
+
+td.mlabels-left {
+	width: 100%;
+	padding: 0px;
+}
+
+td.mlabels-right {
+	vertical-align: bottom;
+	padding: 0px;
+	white-space: nowrap;
+}
+
+span.mlabels {
+        margin-left: 8px;
+}
+
+span.mlabel {
+        background-color: #728DC1;
+        border-top:1px solid #5373B4;
+        border-left:1px solid #5373B4;
+        border-right:1px solid #C4CFE5;
+        border-bottom:1px solid #C4CFE5;
+	text-shadow: none;
+	color: white;
+	margin-right: 4px;
+	padding: 2px 3px;
+	border-radius: 3px;
+	font-size: 7pt;
+	white-space: nowrap;
+	vertical-align: middle;
+}
+
+
+
+/* @end */
+
+/* these are for tree view when not used as main index */
+
+div.directory {
+        margin: 10px 0px;
+        border-top: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        width: 100%;
+}
+
+.directory table {
+        border-collapse:collapse;
+}
+
+.directory td {
+        margin: 0px;
+        padding: 0px;
+	vertical-align: top;
+}
+
+.directory td.entry {
+        white-space: nowrap;
+        padding-right: 6px;
+	padding-top: 3px;
+}
+
+.directory td.entry a {
+        outline:none;
+}
+
+.directory td.entry a img {
+        border: none;
+}
+
+.directory td.desc {
+        width: 100%;
+        padding-left: 6px;
+	padding-right: 6px;
+	padding-top: 3px;
+	border-left: 1px solid rgba(0,0,0,0.05);
+}
+
+.directory tr.even {
+	padding-left: 6px;
+	background-color: #F7F8FB;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+.directory .levels {
+        white-space: nowrap;
+        width: 100%;
+        text-align: right;
+        font-size: 9pt;
+}
+
+.directory .levels span {
+        cursor: pointer;
+        padding-left: 2px;
+        padding-right: 2px;
+	color: #3D578C;
+}
+
+div.dynheader {
+        margin-top: 8px;
+	-webkit-touch-callout: none;
+	-webkit-user-select: none;
+	-khtml-user-select: none;
+	-moz-user-select: none;
+	-ms-user-select: none;
+	user-select: none;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+        margin-top: 4px;
+        margin-bottom: 4px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #CCCCCC;
+	color: #51626F;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+}
+table.fieldtable {
+        /*width: 100%;*/
+        margin-bottom: 10px;
+        border: 1px solid #A8B8D9;
+        border-spacing: 0px;
+        -moz-border-radius: 4px;
+        -webkit-border-radius: 4px;
+        border-radius: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);
+}
+
+.fieldtable td, .fieldtable th {
+        padding: 3px 7px 2px;
+}
+
+.fieldtable td.fieldtype, .fieldtable td.fieldname {
+        white-space: nowrap;
+        border-right: 1px solid #A8B8D9;
+        border-bottom: 1px solid #A8B8D9;
+        vertical-align: top;
+}
+
+.fieldtable td.fieldname {
+        padding-top: 3px;
+}
+
+.fieldtable td.fielddoc {
+        border-bottom: 1px solid #A8B8D9;
+        /*width: 100%;*/
+}
+
+.fieldtable td.fielddoc p:first-child {
+        margin-top: 0px;
+}       
+        
+.fieldtable td.fielddoc p:last-child {
+        margin-bottom: 2px;
+}
+
+.fieldtable tr:last-child td {
+        border-bottom: none;
+}
+
+.fieldtable th {
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        font-size: 90%;
+        color: #253555;
+        padding-bottom: 4px;
+        padding-top: 5px;
+        text-align:left;
+        -moz-border-radius-topleft: 4px;
+        -moz-border-radius-topright: 4px;
+        -webkit-border-top-left-radius: 4px;
+        -webkit-border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        border-top-right-radius: 4px;
+        border-bottom: 1px solid #A8B8D9;
+}
+
+
+.tabsearch {
+	top: 5px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	background-position: 0 -5px;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+	color: #283A5D;
+	font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;
+	text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+	text-decoration: none;        
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('');
+        background-repeat:repeat-x;
+	background-color: #FFFFFF;
+	margin:  0px;
+	border-bottom: 0px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+
+/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */
+dl.section
+{
+	margin-left: 0px;
+	padding-left: 0px;
+}
+
+dl.note
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
+        border-color: #505050;
+}
+
+dl.todo
+{
+        margin-left:-7px;
+        padding-left: 12px;
+        border-left:4px solid;
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        margin-left:-7px;
+        padding-left: 3px;
+        border-left:4px solid;
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+    currentRowSpans.filter(".iconfclosed").removeClass("iconfclosed").addClass("iconfopen");
+    currentRowSpans.filter(".arrow").html('&#9660;');
+    // replace down arrows by right arrows for child rows
+    var childRowsSpans = childRows.find("span");
+    childRowsSpans.filter(".iconfopen").removeClass("iconfopen").addClass("iconfclosed");
+    childRowsSpans.filter(".arrow").html('&#9658;');
+    childRows.show(); //show all children
+  }
+  updateStripes();
+}
+
+
+function toggleInherit(id)
+{
+  var rows = $('tr.inherit.'+id);
+  var img = $('tr.inherit_header.'+id+' img');
+  var src = $(img).attr('src');
+  if (rows.filter(':first').is(':visible')===true) {
+    rows.css('display','none');
+    $(img).attr('src',src.substring(0,src.length-8)+'closed.png');
+  } else {
+    rows.css('display','table-row'); // using show() causes jump in firefox
+    $(img).attr('src',src.substring(0,src.length-10)+'open.png');
+  }
+}
+
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/files.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/files.html
new file mode 100644
index 000000000..b12a50573
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/files.html
@@ -0,0 +1,60 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: File List</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li class="current"><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">File List</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xllfifo_8c.html" target="_self">xllfifo.c</a></td><td class="desc"></td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xllfifo_8h.html" target="_self">xllfifo.h</a></td><td class="desc"></td></tr>
+<tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xllfifo__hw_8h.html" target="_self">xllfifo_hw.h</a></td><td class="desc"></td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/functions.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/functions.html
new file mode 100644
index 000000000..0cbbbe8bb
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/functions.html
@@ -0,0 +1,116 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="functions.html"><span>All</span></a></li>
+      <li><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div><ul>
+<li>Axi4BaseAddress
+: <a class="el" href="struct_x_ll_fifo.html#a455c634fb80553cecfcba0845eb99937">XLlFifo</a>
+</li>
+<li>BaseAddress
+: <a class="el" href="struct_x_ll_fifo.html#ab1d14782860778f2546bee03cb27f192">XLlFifo</a>
+</li>
+<li>Datainterface
+: <a class="el" href="struct_x_ll_fifo.html#a9e2342496ea8183c012567d7c89851b3">XLlFifo</a>
+</li>
+<li>FifoInstance
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#ab278ceaef035943f8a3a8b85a8cab99d">XStrm_RxFifoStreamer</a>
+, <a class="el" href="struct_x_strm___tx_fifo_streamer.html#ac20fde8a3090fddfc01f8b2900fd9051">XStrm_TxFifoStreamer</a>
+</li>
+<li>FifoWidth
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a3ad4cdd1ad14dcecfaf5f923850289fb">XStrm_RxFifoStreamer</a>
+, <a class="el" href="struct_x_strm___tx_fifo_streamer.html#a474cf91d66d43f716a34299d4ab9b9b2">XStrm_TxFifoStreamer</a>
+</li>
+<li>FrmByteCnt
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a9fa74d02f4fa2607e78b11de059be837">XStrm_RxFifoStreamer</a>
+</li>
+<li>GetLenFn
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a01fa1cc2098388ac9371beb090c0c212">XStrm_RxFifoStreamer</a>
+</li>
+<li>GetOccupancyFn
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a8d552e42f58c3230de010178832b41b1">XStrm_RxFifoStreamer</a>
+</li>
+<li>GetVacancyFn
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#ab33212eea0a6327f2c6b1173510170a9">XStrm_TxFifoStreamer</a>
+</li>
+<li>HeadIndex
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a6321ab6bf1a1f3979c0771618a4aba7c">XStrm_RxFifoStreamer</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_ll_fifo.html#abe388bb422699248b26a9d76652474b1">XLlFifo</a>
+</li>
+<li>ReadFn
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#af3bfc974fd88c7b707edf680b3c9aed2">XStrm_RxFifoStreamer</a>
+</li>
+<li>RxStreamer
+: <a class="el" href="struct_x_ll_fifo.html#a456fbf87ce23b1334c67b386722b1434">XLlFifo</a>
+</li>
+<li>SetLenFn
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#aa315e740022ccc81ef9cccfe7c82022d">XStrm_TxFifoStreamer</a>
+</li>
+<li>TailIndex
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#a265500391a387c5354a14fea79a1b446">XStrm_TxFifoStreamer</a>
+</li>
+<li>TxStreamer
+: <a class="el" href="struct_x_ll_fifo.html#a13363fb4d5d45a5725b7427b36c44817">XLlFifo</a>
+</li>
+<li>WriteFn
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#abaed83d1259485a6deadbf4644b0be1b">XStrm_TxFifoStreamer</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/functions_vars.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/functions_vars.html
new file mode 100644
index 000000000..024deec1b
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/functions_vars.html
@@ -0,0 +1,116 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: Data Fields - Variables</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>Axi4BaseAddress
+: <a class="el" href="struct_x_ll_fifo.html#a455c634fb80553cecfcba0845eb99937">XLlFifo</a>
+</li>
+<li>BaseAddress
+: <a class="el" href="struct_x_ll_fifo.html#ab1d14782860778f2546bee03cb27f192">XLlFifo</a>
+</li>
+<li>Datainterface
+: <a class="el" href="struct_x_ll_fifo.html#a9e2342496ea8183c012567d7c89851b3">XLlFifo</a>
+</li>
+<li>FifoInstance
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#ab278ceaef035943f8a3a8b85a8cab99d">XStrm_RxFifoStreamer</a>
+, <a class="el" href="struct_x_strm___tx_fifo_streamer.html#ac20fde8a3090fddfc01f8b2900fd9051">XStrm_TxFifoStreamer</a>
+</li>
+<li>FifoWidth
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a3ad4cdd1ad14dcecfaf5f923850289fb">XStrm_RxFifoStreamer</a>
+, <a class="el" href="struct_x_strm___tx_fifo_streamer.html#a474cf91d66d43f716a34299d4ab9b9b2">XStrm_TxFifoStreamer</a>
+</li>
+<li>FrmByteCnt
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a9fa74d02f4fa2607e78b11de059be837">XStrm_RxFifoStreamer</a>
+</li>
+<li>GetLenFn
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a01fa1cc2098388ac9371beb090c0c212">XStrm_RxFifoStreamer</a>
+</li>
+<li>GetOccupancyFn
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a8d552e42f58c3230de010178832b41b1">XStrm_RxFifoStreamer</a>
+</li>
+<li>GetVacancyFn
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#ab33212eea0a6327f2c6b1173510170a9">XStrm_TxFifoStreamer</a>
+</li>
+<li>HeadIndex
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#a6321ab6bf1a1f3979c0771618a4aba7c">XStrm_RxFifoStreamer</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_ll_fifo.html#abe388bb422699248b26a9d76652474b1">XLlFifo</a>
+</li>
+<li>ReadFn
+: <a class="el" href="struct_x_strm___rx_fifo_streamer.html#af3bfc974fd88c7b707edf680b3c9aed2">XStrm_RxFifoStreamer</a>
+</li>
+<li>RxStreamer
+: <a class="el" href="struct_x_ll_fifo.html#a456fbf87ce23b1334c67b386722b1434">XLlFifo</a>
+</li>
+<li>SetLenFn
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#aa315e740022ccc81ef9cccfe7c82022d">XStrm_TxFifoStreamer</a>
+</li>
+<li>TailIndex
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#a265500391a387c5354a14fea79a1b446">XStrm_TxFifoStreamer</a>
+</li>
+<li>TxStreamer
+: <a class="el" href="struct_x_ll_fifo.html#a13363fb4d5d45a5725b7427b36c44817">XLlFifo</a>
+</li>
+<li>WriteFn
+: <a class="el" href="struct_x_strm___tx_fifo_streamer.html#abaed83d1259485a6deadbf4644b0be1b">XStrm_TxFifoStreamer</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals.html
new file mode 100644
index 000000000..46fb4a7a1
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals.html
@@ -0,0 +1,246 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XLLF_AXI4_RDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga256c51f97ca57cc89c9b51449f3601e1">xllfifo_hw.h</a>
+</li>
+<li>XLLF_AXI4_TDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga7a72ef43b9e2ca7e28a9e939012f1044">xllfifo_hw.h</a>
+</li>
+<li>XLLF_IER_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_ALL_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_ERROR_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga97d0964de7c5721e6856a9d7ccb22ebd">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga838f0b2d56bffea01160c141b0c1de67">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RFPE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gabeef1be2532662b2b6aa865057e30b48">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RFPF_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gacb37ede3ec3b10522a8bf3c597747331">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RPORE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga98ccef60e66cffea379deead95c3084e">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RPUE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga2c30251a44596328ec255b652e20f15a">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RPURE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gab34174dc4dc0d42aa610f51bcf2cb492">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RRC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gaaa9d308d7b3224c47b619467c2384754">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RXERROR_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga2e6b02f445993c00ec77914e3696fd9a">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gabca5de4c7fc02bcad56912a2919319ae">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TFPE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga7e06f24d66d729c445ebb72dde652aad">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TFPF_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga8b6dae752508cc137eb13b88561f88a5">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TPOE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga44becb1eedec6a7d02293d1f088d30c7">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TRC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga08cda800d1468726a65844d40100b9cb">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TSE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga77c2faac5f93834b0a6f7b9da529c5ad">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TXERROR_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga417b7cfe9d44e8154311f8d7c5cef577">xllfifo_hw.h</a>
+</li>
+<li>XLLF_ISR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">xllfifo_hw.h</a>
+</li>
+<li>XLLF_LLR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga5331d2736e9b1b516b4262d8e3f11690">xllfifo_hw.h</a>
+</li>
+<li>XLLF_LLR_RESET_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gad8b59856939038963e68acf4e2e2c47c">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga93e049a21e43548bf03161b4a4394440">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFO_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga9c4bbf51bc4b0410b61ef3933776a63c">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gae1533e466df30729597a1b44ed1059ed">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFR_RESET_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga11c4da53ae9b166832186f9a817fba6d">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gaf0240fc89cce2e27e1943d2e23a5af25">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RLF_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga267285e6015808291ef6671038cba888">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gaeca8c86badc0df67426442f9bb6a5195">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gaa55be9e9452783cde92cd70a33e31e56">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFR_RESET_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gaf7b4bcf41280c1fb01684b6706603420">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFV_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gab77ae26c2fe9b0ac15ebdbf0c6c30960">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga5c691ac1237fb77b8e356a7d2b0b8b54">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TLF_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gac14e6d7e1116f9a43c0adfbe93422fa7">xllfifo_hw.h</a>
+</li>
+<li>XLlFfio_LookupConfig()
+: <a class="el" href="group__llfifo__v5__0.html#ga549da0fb83b3bb11ea6401b8001f9c4e">xllfifo.h</a>
+</li>
+<li>XLlFifo
+: <a class="el" href="group__llfifo__v5__0.html#ga89057d90d6eacdbe8adc766f53f60ed7">xllfifo.h</a>
+</li>
+<li>XLlFifo_CfgInitialize()
+: <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">xllfifo.c</a>
+</li>
+<li>XLlFifo_Initialize()
+: <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">xllfifo.c</a>
+</li>
+<li>XLlFifo_IntClear
+: <a class="el" href="group__llfifo__v5__0.html#gac712eea89e9d7fa37d095003c927c61e">xllfifo.h</a>
+</li>
+<li>XLlFifo_IntDisable
+: <a class="el" href="group__llfifo__v5__0.html#gabff8f5ef31f09865808da90055e29d42">xllfifo.h</a>
+</li>
+<li>XLlFifo_IntEnable
+: <a class="el" href="group__llfifo__v5__0.html#gae65ece5c6c9cce1ccdcf9d404fd8f463">xllfifo.h</a>
+</li>
+<li>XLlFifo_IntPending
+: <a class="el" href="group__llfifo__v5__0.html#gac356d3e8d55aa6e82753400f0bd026a1">xllfifo.h</a>
+</li>
+<li>XLlFifo_IsRxDone
+: <a class="el" href="group__llfifo__v5__0.html#ga556524c17aee71ae8407540a5e2cd65f">xllfifo.h</a>
+</li>
+<li>XLlFifo_IsRxEmpty
+: <a class="el" href="group__llfifo__v5__0.html#gaba876eb888126638848fb2f89a9b4436">xllfifo.h</a>
+</li>
+<li>XLlFifo_IsTxDone
+: <a class="el" href="group__llfifo__v5__0.html#ga869bc4c1072da021e747a0a179bfe2da">xllfifo.h</a>
+</li>
+<li>XLlFifo_Read
+: <a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03">xllfifo.h</a>
+</li>
+<li>XLlFifo_ReadRdr
+: <a class="el" href="group__llfifo__v5__0.html#ga59307ef23e5b4b71d0d01cef8e06e247">xllfifo.h</a>
+</li>
+<li>XLlFifo_ReadReg
+: <a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">xllfifo_hw.h</a>
+</li>
+<li>XLlFifo_Reset
+: <a class="el" href="group__llfifo__v5__0.html#gace8f47c03f1818797c152cb27296df7c">xllfifo.h</a>
+</li>
+<li>XLlFifo_RxGetLen
+: <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e">xllfifo.h</a>
+</li>
+<li>XLlFifo_RxOccupancy
+: <a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5">xllfifo.h</a>
+</li>
+<li>XLlFifo_RxReset
+: <a class="el" href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134">xllfifo.h</a>
+</li>
+<li>XLlFifo_Status
+: <a class="el" href="group__llfifo__v5__0.html#ga095f3e0f8571dc02959852e38237f23e">xllfifo.h</a>
+</li>
+<li>XLlFifo_TxReset
+: <a class="el" href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577">xllfifo.h</a>
+</li>
+<li>XLlFifo_TxSetLen
+: <a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7">xllfifo.h</a>
+</li>
+<li>XLlFifo_TxVacancy
+: <a class="el" href="group__llfifo__v5__0.html#gaf2884c49ae41dc5c5317c2ef6df45a28">xllfifo.h</a>
+</li>
+<li>XLlFifo_Write
+: <a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295">xllfifo.h</a>
+</li>
+<li>XLlFifo_WriteReg
+: <a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">xllfifo_hw.h</a>
+</li>
+<li>XLlFifo_WriteTdr
+: <a class="el" href="group__llfifo__v5__0.html#ga105828f79f13c07d571db218c5837fae">xllfifo.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_defs.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_defs.html
new file mode 100644
index 000000000..1b0c75186
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_defs.html
@@ -0,0 +1,234 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XLLF_AXI4_RDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga256c51f97ca57cc89c9b51449f3601e1">xllfifo_hw.h</a>
+</li>
+<li>XLLF_AXI4_TDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga7a72ef43b9e2ca7e28a9e939012f1044">xllfifo_hw.h</a>
+</li>
+<li>XLLF_IER_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_ALL_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_ERROR_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga97d0964de7c5721e6856a9d7ccb22ebd">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga838f0b2d56bffea01160c141b0c1de67">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RFPE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gabeef1be2532662b2b6aa865057e30b48">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RFPF_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gacb37ede3ec3b10522a8bf3c597747331">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RPORE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga98ccef60e66cffea379deead95c3084e">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RPUE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga2c30251a44596328ec255b652e20f15a">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RPURE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gab34174dc4dc0d42aa610f51bcf2cb492">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RRC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gaaa9d308d7b3224c47b619467c2384754">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_RXERROR_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga2e6b02f445993c00ec77914e3696fd9a">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gabca5de4c7fc02bcad56912a2919319ae">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TFPE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga7e06f24d66d729c445ebb72dde652aad">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TFPF_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga8b6dae752508cc137eb13b88561f88a5">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TPOE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga44becb1eedec6a7d02293d1f088d30c7">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TRC_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga08cda800d1468726a65844d40100b9cb">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TSE_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga77c2faac5f93834b0a6f7b9da529c5ad">xllfifo_hw.h</a>
+</li>
+<li>XLLF_INT_TXERROR_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga417b7cfe9d44e8154311f8d7c5cef577">xllfifo_hw.h</a>
+</li>
+<li>XLLF_ISR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">xllfifo_hw.h</a>
+</li>
+<li>XLLF_LLR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga5331d2736e9b1b516b4262d8e3f11690">xllfifo_hw.h</a>
+</li>
+<li>XLLF_LLR_RESET_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gad8b59856939038963e68acf4e2e2c47c">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga93e049a21e43548bf03161b4a4394440">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFO_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga9c4bbf51bc4b0410b61ef3933776a63c">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gae1533e466df30729597a1b44ed1059ed">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDFR_RESET_MASK
+: <a class="el" href="group__llfifo__v5__0.html#ga11c4da53ae9b166832186f9a817fba6d">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RDR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gaf0240fc89cce2e27e1943d2e23a5af25">xllfifo_hw.h</a>
+</li>
+<li>XLLF_RLF_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga267285e6015808291ef6671038cba888">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFD_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gaeca8c86badc0df67426442f9bb6a5195">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gaa55be9e9452783cde92cd70a33e31e56">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFR_RESET_MASK
+: <a class="el" href="group__llfifo__v5__0.html#gaf7b4bcf41280c1fb01684b6706603420">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDFV_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gab77ae26c2fe9b0ac15ebdbf0c6c30960">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TDR_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#ga5c691ac1237fb77b8e356a7d2b0b8b54">xllfifo_hw.h</a>
+</li>
+<li>XLLF_TLF_OFFSET
+: <a class="el" href="group__llfifo__v5__0.html#gac14e6d7e1116f9a43c0adfbe93422fa7">xllfifo_hw.h</a>
+</li>
+<li>XLlFifo_IntClear
+: <a class="el" href="group__llfifo__v5__0.html#gac712eea89e9d7fa37d095003c927c61e">xllfifo.h</a>
+</li>
+<li>XLlFifo_IntDisable
+: <a class="el" href="group__llfifo__v5__0.html#gabff8f5ef31f09865808da90055e29d42">xllfifo.h</a>
+</li>
+<li>XLlFifo_IntEnable
+: <a class="el" href="group__llfifo__v5__0.html#gae65ece5c6c9cce1ccdcf9d404fd8f463">xllfifo.h</a>
+</li>
+<li>XLlFifo_IntPending
+: <a class="el" href="group__llfifo__v5__0.html#gac356d3e8d55aa6e82753400f0bd026a1">xllfifo.h</a>
+</li>
+<li>XLlFifo_IsRxDone
+: <a class="el" href="group__llfifo__v5__0.html#ga556524c17aee71ae8407540a5e2cd65f">xllfifo.h</a>
+</li>
+<li>XLlFifo_IsRxEmpty
+: <a class="el" href="group__llfifo__v5__0.html#gaba876eb888126638848fb2f89a9b4436">xllfifo.h</a>
+</li>
+<li>XLlFifo_IsTxDone
+: <a class="el" href="group__llfifo__v5__0.html#ga869bc4c1072da021e747a0a179bfe2da">xllfifo.h</a>
+</li>
+<li>XLlFifo_Read
+: <a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03">xllfifo.h</a>
+</li>
+<li>XLlFifo_ReadRdr
+: <a class="el" href="group__llfifo__v5__0.html#ga59307ef23e5b4b71d0d01cef8e06e247">xllfifo.h</a>
+</li>
+<li>XLlFifo_ReadReg
+: <a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">xllfifo_hw.h</a>
+</li>
+<li>XLlFifo_Reset
+: <a class="el" href="group__llfifo__v5__0.html#gace8f47c03f1818797c152cb27296df7c">xllfifo.h</a>
+</li>
+<li>XLlFifo_RxGetLen
+: <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e">xllfifo.h</a>
+</li>
+<li>XLlFifo_RxOccupancy
+: <a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5">xllfifo.h</a>
+</li>
+<li>XLlFifo_RxReset
+: <a class="el" href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134">xllfifo.h</a>
+</li>
+<li>XLlFifo_Status
+: <a class="el" href="group__llfifo__v5__0.html#ga095f3e0f8571dc02959852e38237f23e">xllfifo.h</a>
+</li>
+<li>XLlFifo_TxReset
+: <a class="el" href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577">xllfifo.h</a>
+</li>
+<li>XLlFifo_TxSetLen
+: <a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7">xllfifo.h</a>
+</li>
+<li>XLlFifo_TxVacancy
+: <a class="el" href="group__llfifo__v5__0.html#gaf2884c49ae41dc5c5317c2ef6df45a28">xllfifo.h</a>
+</li>
+<li>XLlFifo_Write
+: <a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295">xllfifo.h</a>
+</li>
+<li>XLlFifo_WriteReg
+: <a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">xllfifo_hw.h</a>
+</li>
+<li>XLlFifo_WriteTdr
+: <a class="el" href="group__llfifo__v5__0.html#ga105828f79f13c07d571db218c5837fae">xllfifo.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_func.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_func.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+<title>llfifo_v5_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XLlFfio_LookupConfig()
+: <a class="el" href="group__llfifo__v5__0.html#ga549da0fb83b3bb11ea6401b8001f9c4e">xllfifo.h</a>
+</li>
+<li>XLlFifo_CfgInitialize()
+: <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">xllfifo.c</a>
+</li>
+<li>XLlFifo_Initialize()
+: <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">xllfifo.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_type.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/globals_type.html
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@@ -0,0 +1,62 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: APIs</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XLlFifo
+: <a class="el" href="group__llfifo__v5__0.html#ga89057d90d6eacdbe8adc766f53f60ed7">xllfifo.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/group__llfifo__v5__0.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/group__llfifo__v5__0.html
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+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/group__llfifo__v5__0.html
@@ -0,0 +1,1623 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: Llfifo_v5_0</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
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+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#nested-classes">Data Structures</a> &#124;
+<a href="#define-members">Macros</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Llfifo_v5_0</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_ll_fifo.html">XLlFifo</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+<tr class="separator:gace8f47c03f1818797c152cb27296df7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga095f3e0f8571dc02959852e38237f23e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memitem:gaf2884c49ae41dc5c5317c2ef6df45a28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gaf2884c49ae41dc5c5317c2ef6df45a28">XLlFifo_TxVacancy</a>(InstancePtr)&#160;&#160;&#160;XStrm_TxVacancy(&amp;((InstancePtr)-&gt;TxStreamer))</td></tr>
+<tr class="separator:gaf2884c49ae41dc5c5317c2ef6df45a28"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gacd09ed5189e0b85994901102655964f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7">XLlFifo_TxSetLen</a>(InstancePtr,  Bytes)&#160;&#160;&#160;XStrm_TxSetLen(&amp;((InstancePtr)-&gt;TxStreamer), (Bytes))</td></tr>
+<tr class="separator:gacd09ed5189e0b85994901102655964f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga1fa93f486abaaf35c7d599a8cd91b295"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295">XLlFifo_Write</a>(InstancePtr,  BufPtr,  Bytes)&#160;&#160;&#160;XStrm_Write(&amp;((InstancePtr)-&gt;TxStreamer), (BufPtr), (Bytes))</td></tr>
+<tr class="separator:ga1fa93f486abaaf35c7d599a8cd91b295"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga105828f79f13c07d571db218c5837fae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga105828f79f13c07d571db218c5837fae">XLlFifo_WriteTdr</a>(InstancePtr,  Tdest)</td></tr>
+<tr class="separator:ga105828f79f13c07d571db218c5837fae"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga59307ef23e5b4b71d0d01cef8e06e247"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga59307ef23e5b4b71d0d01cef8e06e247">XLlFifo_ReadRdr</a>(InstancePtr)&#160;&#160;&#160;<a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="el" href="group__llfifo__v5__0.html#gaf0240fc89cce2e27e1943d2e23a5af25">XLLF_RDR_OFFSET</a>)</td></tr>
+<tr class="separator:ga59307ef23e5b4b71d0d01cef8e06e247"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga7526eab563fa4e0fe8b60474e96afe55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32((BaseAddress) + (RegOffset)))</td></tr>
+<tr class="separator:ga7526eab563fa4e0fe8b60474e96afe55"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gacd283ce73981f7f9eab94f8bb421bc78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>(BaseAddress,  RegOffset,  Value)&#160;&#160;&#160;((Xil_Out32((BaseAddress) + (RegOffset), (Value))))</td></tr>
+<tr class="separator:gacd283ce73981f7f9eab94f8bb421bc78"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:gadc1db2785627a0d8da46dc60990889a0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, XLlFifo_Config *Config, u32 EffectiveAddress)</td></tr>
+<tr class="separator:gadc1db2785627a0d8da46dc60990889a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga1fdf07ca198f5cfe2dc14ced21e5631d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, u32 BaseAddress)</td></tr>
+<tr class="separator:ga1fdf07ca198f5cfe2dc14ced21e5631d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga549da0fb83b3bb11ea6401b8001f9c4e"><td class="memItemLeft" align="right" valign="top">XLlFifo_Config *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga549da0fb83b3bb11ea6401b8001f9c4e">XLlFfio_LookupConfig</a> (u32 DeviceId)</td></tr>
+<tr class="separator:ga549da0fb83b3bb11ea6401b8001f9c4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga256c51f97ca57cc89c9b51449f3601e1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_AXI4_RDFD_OFFSET&#160;&#160;&#160;0x00001000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Axi4 Receive Data. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7a72ef43b9e2ca7e28a9e939012f1044"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_AXI4_TDFD_OFFSET&#160;&#160;&#160;0x00000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Axi4 Transmit Data. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac34e090e52a9ef5cdf4337cae6ca717c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_IER_OFFSET&#160;&#160;&#160;0x00000004</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Interrupt Enable. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae3bfcad24428233d9e2a8a861e2d9eed"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_ALL_MASK&#160;&#160;&#160;0xfff80000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>All the ints. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga97d0964de7c5721e6856a9d7ccb22ebd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_ERROR_MASK&#160;&#160;&#160;0xf2000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Error status ints. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga838f0b2d56bffea01160c141b0c1de67"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RC_MASK&#160;&#160;&#160;0x04000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive complete. </p>
+
+</div>
+</div>
+<a class="anchor" id="gabeef1be2532662b2b6aa865057e30b48"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RFPE_MASK&#160;&#160;&#160;0x00080000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Rx FIFO Programmable Empty AXI FIFO MM2S Only. </p>
+
+</div>
+</div>
+<a class="anchor" id="gacb37ede3ec3b10522a8bf3c597747331"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RFPF_MASK&#160;&#160;&#160;0x00100000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Rx FIFO Programmable Full AXI FIFO MM2S Only. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga98ccef60e66cffea379deead95c3084e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RPORE_MASK&#160;&#160;&#160;0x40000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive over-read. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2c30251a44596328ec255b652e20f15a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RPUE_MASK&#160;&#160;&#160;0x20000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive underrun (empty) </p>
+
+</div>
+</div>
+<a class="anchor" id="gab34174dc4dc0d42aa610f51bcf2cb492"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RPURE_MASK&#160;&#160;&#160;0x80000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive under-read. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaaa9d308d7b3224c47b619467c2384754"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RRC_MASK&#160;&#160;&#160;0x00800000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive reset complete. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2e6b02f445993c00ec77914e3696fd9a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_RXERROR_MASK&#160;&#160;&#160;0xe0000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive Error status ints. </p>
+
+</div>
+</div>
+<a class="anchor" id="gabca5de4c7fc02bcad56912a2919319ae"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TC_MASK&#160;&#160;&#160;0x08000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit complete. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7e06f24d66d729c445ebb72dde652aad"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TFPE_MASK&#160;&#160;&#160;0x00200000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Tx FIFO Programmable Empty AXI FIFO MM2S Only. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8b6dae752508cc137eb13b88561f88a5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TFPF_MASK&#160;&#160;&#160;0x00400000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Tx FIFO Programmable Full, AXI FIFO MM2S Only. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga44becb1eedec6a7d02293d1f088d30c7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TPOE_MASK&#160;&#160;&#160;0x10000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit overrun. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga08cda800d1468726a65844d40100b9cb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TRC_MASK&#160;&#160;&#160;0x01000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit reset complete. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga77c2faac5f93834b0a6f7b9da529c5ad"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TSE_MASK&#160;&#160;&#160;0x02000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit length mismatch. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga417b7cfe9d44e8154311f8d7c5cef577"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_INT_TXERROR_MASK&#160;&#160;&#160;0x12000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit Error status ints. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga90a5fafb06870a7ff8043d3a34bf54cc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_ISR_OFFSET&#160;&#160;&#160;0x00000000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Interrupt Status. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5331d2736e9b1b516b4262d8e3f11690"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_LLR_OFFSET&#160;&#160;&#160;0x00000028</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Local Link Reset. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad8b59856939038963e68acf4e2e2c47c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_LLR_RESET_MASK&#160;&#160;&#160;0x000000a5</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Local Link reset value. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga93e049a21e43548bf03161b4a4394440"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_RDFD_OFFSET&#160;&#160;&#160;0x00000020</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive Data. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9c4bbf51bc4b0410b61ef3933776a63c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_RDFO_OFFSET&#160;&#160;&#160;0x0000001c</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive Occupancy. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae1533e466df30729597a1b44ed1059ed"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_RDFR_OFFSET&#160;&#160;&#160;0x00000018</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive Reset. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga11c4da53ae9b166832186f9a817fba6d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_RDFR_RESET_MASK&#160;&#160;&#160;0x000000a5</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>receive reset value </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaf0240fc89cce2e27e1943d2e23a5af25"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_RDR_OFFSET&#160;&#160;&#160;0x00000030</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive Destination. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga267285e6015808291ef6671038cba888"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_RLF_OFFSET&#160;&#160;&#160;0x00000024</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Receive Length. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaeca8c86badc0df67426442f9bb6a5195"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_TDFD_OFFSET&#160;&#160;&#160;0x00000010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit Data. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa55be9e9452783cde92cd70a33e31e56"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_TDFR_OFFSET&#160;&#160;&#160;0x00000008</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit Reset. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf7b4bcf41280c1fb01684b6706603420"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_TDFR_RESET_MASK&#160;&#160;&#160;0x000000a5</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit reset value. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab77ae26c2fe9b0ac15ebdbf0c6c30960"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_TDFV_OFFSET&#160;&#160;&#160;0x0000000c</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit Vacancy. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5c691ac1237fb77b8e356a7d2b0b8b54"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_TDR_OFFSET&#160;&#160;&#160;0x0000002C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit Destination. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac14e6d7e1116f9a43c0adfbe93422fa7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLLF_TLF_OFFSET&#160;&#160;&#160;0x00000014</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>Transmit Length. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac712eea89e9d7fa37d095003c927c61e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IntClear</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a>, \</div>
+<div class="line">                        ((Mask) &amp; <a class="code" href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">XLLF_INT_ALL_MASK</a>))</div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gae3bfcad24428233d9e2a8a861e2d9eed"><div class="ttname"><a href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">XLLF_INT_ALL_MASK</a></div><div class="ttdeci">#define XLLF_INT_ALL_MASK</div><div class="ttdoc">All the ints. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:134</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga90a5fafb06870a7ff8043d3a34bf54cc"><div class="ttname"><a href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a></div><div class="ttdeci">#define XLLF_ISR_OFFSET</div><div class="ttdoc">Interrupt Status. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:82</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IntClear clears pending interrupts specified in <em>Mask</em> for the FIFO specified by <em>InstancePtr</em>. </p>
+<p>The corresponding pending interrupt for each bit set to 1 in <em>Mask</em>, will be cleared. In other words, XLlFifo_IntClear uses the "set a bit to clear it" scheme.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+    <tr><td class="paramname">Mask</td><td>contains a bit mask of the pending interrupts to clear. The mask can be formed using a set of bitwise or'd values from the <code>XLLF_INT_*_MASK</code> preprocessor symbols.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#gac712eea89e9d7fa37d095003c927c61e" title="XLlFifo_IntClear clears pending interrupts specified in Mask for the FIFO specified by InstancePtr...">XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gabff8f5ef31f09865808da90055e29d42"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IntDisable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 Reg = <a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, \</div>
+<div class="line">                        <a class="code" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a>); \</div>
+<div class="line">        Reg &amp;= ~((Mask) &amp; <a class="code" href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">XLLF_INT_ALL_MASK</a>);  <a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">\</a></div>
+<div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">	XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a>, \</div>
+<div class="line">                        Reg); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gae3bfcad24428233d9e2a8a861e2d9eed"><div class="ttname"><a href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">XLLF_INT_ALL_MASK</a></div><div class="ttdeci">#define XLLF_INT_ALL_MASK</div><div class="ttdoc">All the ints. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:134</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga7526eab563fa4e0fe8b60474e96afe55"><div class="ttname"><a href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a></div><div class="ttdeci">#define XLlFifo_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...</div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:206</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gac34e090e52a9ef5cdf4337cae6ca717c"><div class="ttname"><a href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a></div><div class="ttdeci">#define XLLF_IER_OFFSET</div><div class="ttdoc">Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:83</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IntDisable disables the interrupts specified in <em>Mask</em> for the FIFO specified by <em>InstancePtr</em>. </p>
+<p>The corresponding interrupt for each bit set to 1 in <em>Mask</em>, will be disabled. In other words, XLlFifo_IntDisable uses the "set a bit to clear it" scheme.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+    <tr><td class="paramname">Mask</td><td>contains a bit mask of the interrupts to disable. The mask can be formed using a set of bitwise or'd values from the <code>XLLF_INT_*_MASK</code> preprocessor symbols.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#gabff8f5ef31f09865808da90055e29d42" title="XLlFifo_IntDisable disables the interrupts specified in Mask for the FIFO specified by InstancePtr...">XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae65ece5c6c9cce1ccdcf9d404fd8f463"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IntEnable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Mask&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">{ \</div>
+<div class="line">        u32 Reg = <a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, \</div>
+<div class="line">                        <a class="code" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a>); \</div>
+<div class="line">        Reg |= ((Mask) &amp; <a class="code" href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">XLLF_INT_ALL_MASK</a>);                    <a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">\</a></div>
+<div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">	XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a>, \</div>
+<div class="line">                        Reg); \</div>
+<div class="line">}</div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gae3bfcad24428233d9e2a8a861e2d9eed"><div class="ttname"><a href="group__llfifo__v5__0.html#gae3bfcad24428233d9e2a8a861e2d9eed">XLLF_INT_ALL_MASK</a></div><div class="ttdeci">#define XLLF_INT_ALL_MASK</div><div class="ttdoc">All the ints. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:134</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga7526eab563fa4e0fe8b60474e96afe55"><div class="ttname"><a href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a></div><div class="ttdeci">#define XLlFifo_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...</div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:206</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gac34e090e52a9ef5cdf4337cae6ca717c"><div class="ttname"><a href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a></div><div class="ttdeci">#define XLLF_IER_OFFSET</div><div class="ttdoc">Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:83</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IntEnable enables the interrupts specified in <em>Mask</em> for the FIFO specified by <em>InstancePtr</em>. </p>
+<p>The corresponding interrupt for each bit set to 1 in <em>Mask</em>, will be enabled.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+    <tr><td class="paramname">Mask</td><td>contains a bit mask of the interrupts to enable. The mask can be formed using a set of bitwise or'd values from the <code>XLLF_INT_*_MASK</code> preprocessor symbols.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#gae65ece5c6c9cce1ccdcf9d404fd8f463" title="XLlFifo_IntEnable enables the interrupts specified in Mask for the FIFO specified by InstancePtr...">XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac356d3e8d55aa6e82753400f0bd026a1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IntPending</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a>) &amp;  <a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">\</a></div>
+<div class="line"><a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">	 XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a>))</div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga7526eab563fa4e0fe8b60474e96afe55"><div class="ttname"><a href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a></div><div class="ttdeci">#define XLlFifo_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...</div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:206</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga90a5fafb06870a7ff8043d3a34bf54cc"><div class="ttname"><a href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a></div><div class="ttdeci">#define XLLF_ISR_OFFSET</div><div class="ttdoc">Interrupt Status. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:82</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gac34e090e52a9ef5cdf4337cae6ca717c"><div class="ttname"><a href="group__llfifo__v5__0.html#gac34e090e52a9ef5cdf4337cae6ca717c">XLLF_IER_OFFSET</a></div><div class="ttdeci">#define XLLF_IER_OFFSET</div><div class="ttdoc">Interrupt Enable. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:83</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IntPending returns a bit mask of the pending interrupts for the FIFO specified by <em>InstancePtr</em>. </p>
+<p>Each bit set to 1 in the return value represents a pending interrupt.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_IntPending returns a bit mask of the interrupts that are pending. The mask will be a set of bitwise or'd values from the <code>XLLF_INT_*_MASK</code> preprocessor symbols.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__llfifo__v5__0.html#gac356d3e8d55aa6e82753400f0bd026a1" title="XLlFifo_IntPending returns a bit mask of the pending interrupts for the FIFO specified by InstancePtr...">XLlFifo_IntPending(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga556524c17aee71ae8407540a5e2cd65f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IsRxDone</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a>) &amp; <a class="code" href="group__llfifo__v5__0.html#ga838f0b2d56bffea01160c141b0c1de67">\</a></div>
+<div class="line"><a class="code" href="group__llfifo__v5__0.html#ga838f0b2d56bffea01160c141b0c1de67">		XLLF_INT_RC_MASK</a>) \</div>
+<div class="line">                ? TRUE : FALSE)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga7526eab563fa4e0fe8b60474e96afe55"><div class="ttname"><a href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a></div><div class="ttdeci">#define XLlFifo_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...</div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:206</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga838f0b2d56bffea01160c141b0c1de67"><div class="ttname"><a href="group__llfifo__v5__0.html#ga838f0b2d56bffea01160c141b0c1de67">XLLF_INT_RC_MASK</a></div><div class="ttdeci">#define XLLF_INT_RC_MASK</div><div class="ttdoc">Receive complete. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:118</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga90a5fafb06870a7ff8043d3a34bf54cc"><div class="ttname"><a href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a></div><div class="ttdeci">#define XLLF_ISR_OFFSET</div><div class="ttdoc">Interrupt Status. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:82</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IsRxDone returns true if the reception in the receive channel of the FIFO, specified by <em>InstancePtr</em>, is complete. </p>
+<p>XLlFifo_IsRxDone works only if the RC bit in the ISR register is cleared before receiving a frame.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_IsRxDone returns TRUE when the receive channel of the FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__llfifo__v5__0.html#ga556524c17aee71ae8407540a5e2cd65f" title="XLlFifo_IsRxDone returns true if the reception in the receive channel of the FIFO, specified by InstancePtr, is complete. ">XLlFifo_IsRxDone(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaba876eb888126638848fb2f89a9b4436"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IsRxEmpty</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga9c4bbf51bc4b0410b61ef3933776a63c">XLLF_RDFO_OFFSET</a>) == 0) \</div>
+<div class="line">                                                        ? TRUE : FALSE)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga7526eab563fa4e0fe8b60474e96afe55"><div class="ttname"><a href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a></div><div class="ttdeci">#define XLlFifo_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...</div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:206</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga9c4bbf51bc4b0410b61ef3933776a63c"><div class="ttname"><a href="group__llfifo__v5__0.html#ga9c4bbf51bc4b0410b61ef3933776a63c">XLLF_RDFO_OFFSET</a></div><div class="ttdeci">#define XLLF_RDFO_OFFSET</div><div class="ttdoc">Receive Occupancy. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:92</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified by <em>InstancePtr</em>, is empty. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_IsRxEmpty returns TRUE when the receive channel of the FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__llfifo__v5__0.html#gaba876eb888126638848fb2f89a9b4436" title="XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified by InstancePtr, is empty. ">XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga869bc4c1072da021e747a0a179bfe2da"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_IsTxDone</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a>) &amp; <a class="code" href="group__llfifo__v5__0.html#gabca5de4c7fc02bcad56912a2919319ae">\</a></div>
+<div class="line"><a class="code" href="group__llfifo__v5__0.html#gabca5de4c7fc02bcad56912a2919319ae">		XLLF_INT_TC_MASK</a>) \</div>
+<div class="line">                ? TRUE : FALSE)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga7526eab563fa4e0fe8b60474e96afe55"><div class="ttname"><a href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a></div><div class="ttdeci">#define XLlFifo_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...</div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:206</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gabca5de4c7fc02bcad56912a2919319ae"><div class="ttname"><a href="group__llfifo__v5__0.html#gabca5de4c7fc02bcad56912a2919319ae">XLLF_INT_TC_MASK</a></div><div class="ttdeci">#define XLLF_INT_TC_MASK</div><div class="ttdoc">Transmit complete. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:117</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga90a5fafb06870a7ff8043d3a34bf54cc"><div class="ttname"><a href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a></div><div class="ttdeci">#define XLLF_ISR_OFFSET</div><div class="ttdoc">Interrupt Status. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:82</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_IsTxDone returns true if the transmission in the transmit channel of the FIFO, specified by <em>InstancePtr</em>, is complete. </p>
+<p>XLlFifo_IsTxDone works only if the TC bit in the IS register is cleared before sending a frame.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_IsTxDone returns TRUE when the transmit channel of the FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__llfifo__v5__0.html#ga869bc4c1072da021e747a0a179bfe2da" title="XLlFifo_IsTxDone returns true if the transmission in the transmit channel of the FIFO, specified by InstancePtr, is complete. ">XLlFifo_IsTxDone(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaadc3685592b060c0d864850e86be5c03"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_Read</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BufPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XStrm_Read(&amp;((InstancePtr)-&gt;RxStreamer), (BufPtr), (Bytes))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_Read reads <em>Bytes</em> bytes from the receive channel of the FIFO referenced by <em>InstancePtr</em> to the block of memory, referenced by <em>BufPtr</em>. </p>
+<p>Care must be taken to ensure that the number of bytes read with one or more calls to <a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03" title="XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the ...">XLlFifo_Read()</a> does not exceed the number of bytes available given from the last call to <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen()</a>.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+    <tr><td class="paramname">BufPtr</td><td>specifies the memory address to place the data read.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>specifies the number of bytes to read.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Error handling is handled through hardware exceptions and interrupts.</dd></dl>
+<p>C Signature: void <a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03" title="XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the ...">XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ga59307ef23e5b4b71d0d01cef8e06e247"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_ReadRdr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;<a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="el" href="group__llfifo__v5__0.html#gaf0240fc89cce2e27e1943d2e23a5af25">XLLF_RDR_OFFSET</a>)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR). </p>
+<p>The RDR contains destination address corresponding to the valid packet that is received. The RDR should only be read when a receive packet is available for processing (the receive occupancy is not zero). Once the RDR is read, the receive packet data should be read from the receive data FIFO before the RDR is read again. The RDR values are stored in the receive data FIFO by the AXI4-Stream FIFO core with the data of each packet. The RDR value for the subsequent packet to be processed is moved to the RDR when the previous RDR value has been read.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The Receive Destination address read from the RDR.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C Signature: u32 <a class="el" href="group__llfifo__v5__0.html#ga59307ef23e5b4b71d0d01cef8e06e247" title="XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR). ">XLlFifo_ReadRdr(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7526eab563fa4e0fe8b60474e96afe55"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_ReadReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;(Xil_In32((BaseAddress) + (RegOffset)))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>XLlFifo_ReadReg returns the value of the register at the offet, <em>RegOffset</em>, from the memory mapped base address, <em>BaseAddress</em>. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>specifies the base address of the device.</td></tr>
+    <tr><td class="paramname">RegOffset</td><td>specifies the offset from BaseAddress.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_ReadReg returns the value of the specified register.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55" title="XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped bas...">XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gace8f47c03f1818797c152cb27296df7c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_Reset</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga5331d2736e9b1b516b4262d8e3f11690">XLLF_LLR_OFFSET</a>, \</div>
+<div class="line">                        <a class="code" href="group__llfifo__v5__0.html#gad8b59856939038963e68acf4e2e2c47c">XLLF_LLR_RESET_MASK</a>)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga5331d2736e9b1b516b4262d8e3f11690"><div class="ttname"><a href="group__llfifo__v5__0.html#ga5331d2736e9b1b516b4262d8e3f11690">XLLF_LLR_OFFSET</a></div><div class="ttdeci">#define XLLF_LLR_OFFSET</div><div class="ttdoc">Local Link Reset. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:96</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gad8b59856939038963e68acf4e2e2c47c"><div class="ttname"><a href="group__llfifo__v5__0.html#gad8b59856939038963e68acf4e2e2c47c">XLLF_LLR_RESET_MASK</a></div><div class="ttdeci">#define XLLF_LLR_RESET_MASK</div><div class="ttdoc">Local Link reset value. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:147</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_Reset resets both the Tx and Rx channels and the local link interface the FIFO specified by <em>InstancePtr</em>. </p>
+<p>XLlFifo_TxReset resets also sends a reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO not yet transmitted.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#gace8f47c03f1818797c152cb27296df7c" title="XLlFifo_Reset resets both the Tx and Rx channels and the local link interface the FIFO specified by I...">XLlFifo_Reset(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga53af32ae6901462cc8d6fb9adc04655e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_RxGetLen</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;XStrm_RxGetLen(&amp;((InstancePtr)-&gt;RxStreamer))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the receive channel of the FIFO, specified by <em>InstancePtr</em>. </p>
+<p>Note that the program must first call XLlFifo_RxGetLen before pulling data out of the receive channel of the FIFO with XLlFifo_Read.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_RxGetLen returns the number of bytes available in the next frame.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>C Signature: u32 <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen(XLlFifo *InstancePtr)</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ga12da547aa1c9a85e2b0b151f438ff9d5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_RxOccupancy</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;XStrm_RxOccupancy(&amp;((InstancePtr)-&gt;RxStreamer))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the receive channel of the FIFO, specified by <em>InstancePtr</em>. </p>
+<p>The xps_ll_fifo core uses the same fifo to store data values and frame length values. Upon initialization, the XLlFifo_RxOccupancy will give the value of 1, which means one length value (a reserved fifo location) and no data values.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_RxOccupancy returns the occupancy count for the specified packet FIFO.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>C Signature: u32 <a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5" title="XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the rece...">XLlFifo_RxOccupancy(XLlFifo *InstancePtr)</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf3739a78b92f17cead0d831757b3a134"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_RxReset</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#gae1533e466df30729597a1b44ed1059ed">XLLF_RDFR_OFFSET</a>, \</div>
+<div class="line">                        <a class="code" href="group__llfifo__v5__0.html#ga11c4da53ae9b166832186f9a817fba6d">XLLF_RDFR_RESET_MASK</a>)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga11c4da53ae9b166832186f9a817fba6d"><div class="ttname"><a href="group__llfifo__v5__0.html#ga11c4da53ae9b166832186f9a817fba6d">XLLF_RDFR_RESET_MASK</a></div><div class="ttdeci">#define XLLF_RDFR_RESET_MASK</div><div class="ttdoc">receive reset value </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:145</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gae1533e466df30729597a1b44ed1059ed"><div class="ttname"><a href="group__llfifo__v5__0.html#gae1533e466df30729597a1b44ed1059ed">XLLF_RDFR_OFFSET</a></div><div class="ttdeci">#define XLLF_RDFR_OFFSET</div><div class="ttdoc">Receive Reset. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:91</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_RxReset resets the receive channel of the FIFO specified by <em>InstancePtr</em>. </p>
+<p>XLlFifo_RxReset drops any bytes in the FIFO not yet retrieved.</p>
+<p>The calling software may want to test for the completion of the reset by reading the interrupt status (IS) register and testing for the Rx Reset complete (RRC) bit.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134" title="XLlFifo_RxReset resets the receive channel of the FIFO specified by InstancePtr. ">XLlFifo_RxReset(XLlFifo *InstancePtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga095f3e0f8571dc02959852e38237f23e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_Status</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;<a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="el" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a>)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_Status returns a bit mask of the interrupt status register (ISR) for the FIFO specified by <em>InstancePtr</em>. </p>
+<p>XLlFifo_Status can be used to query the status of the FIFO without having to have interrupts enabled.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_IntStatus returns a bit mask of the status conditions. The mask will be a set of bitwise or'd values from the <code>XLLF_INT_*_MASK</code> preprocessor symbols.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 XLlFifo_IntStatus(XLlFifo *InstancePtr) </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga922419fdcd342fa709fb07ec1a9e5577"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_TxReset</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#gaa55be9e9452783cde92cd70a33e31e56">XLLF_TDFR_OFFSET</a>, \</div>
+<div class="line">                        <a class="code" href="group__llfifo__v5__0.html#gaf7b4bcf41280c1fb01684b6706603420">XLLF_TDFR_RESET_MASK</a>)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gaf7b4bcf41280c1fb01684b6706603420"><div class="ttname"><a href="group__llfifo__v5__0.html#gaf7b4bcf41280c1fb01684b6706603420">XLLF_TDFR_RESET_MASK</a></div><div class="ttdeci">#define XLLF_TDFR_RESET_MASK</div><div class="ttdoc">Transmit reset value. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:146</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_gaa55be9e9452783cde92cd70a33e31e56"><div class="ttname"><a href="group__llfifo__v5__0.html#gaa55be9e9452783cde92cd70a33e31e56">XLLF_TDFR_OFFSET</a></div><div class="ttdeci">#define XLLF_TDFR_OFFSET</div><div class="ttdoc">Transmit Reset. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:85</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_TxReset resets the transmit channel of the FIFO specified by <em>InstancePtr</em>. </p>
+<p>XLlFifo_TxReset drops any bytes in the FIFO not yet transmitted.</p>
+<p>The calling software may want to test for the completion of the reset by reading the interrupt status (IS) register and testing for the Tx Reset complete (TRC) bit.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577" title="XLlFifo_TxReset resets the transmit channel of the FIFO specified by InstancePtr. ...">XLlFifo_TxReset(XLlFifo *InstancePtr)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gacd09ed5189e0b85994901102655964f7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_TxSetLen</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XStrm_TxSetLen(&amp;((InstancePtr)-&gt;TxStreamer), (Bytes))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_TxSetLen begins a hardware transfer of <em>Bytes</em> bytes out of the transmit channel of the FIFO specified by <em>InstancePtr</em>. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>specifies the frame length in bytes.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>C Signature: void <a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7" title="XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO sp...">XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf2884c49ae41dc5c5317c2ef6df45a28"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_TxVacancy</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr</td><td>)</td>
+          <td>&#160;&#160;&#160;XStrm_TxVacancy(&amp;((InstancePtr)-&gt;TxStreamer))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_TxVacancy returns the number of unused 32 bit words available (vacancy) in the send channel of the FIFO specified by <em>InstancePtr</em>. </p>
+<p>The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length values. Upon initialization, the XLlFifo_TxVacancy will give the value of FIFO_WIDTH - 1, which means one length value used (a reserved fifo location) and no data values yet present.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>XLlFifo_TxVacancy returns the vacancy count in 32-bit words for the specified FIFO.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__llfifo__v5__0.html#gaf2884c49ae41dc5c5317c2ef6df45a28" title="XLlFifo_TxVacancy returns the number of unused 32 bit words available (vacancy) in the send channel o...">XLlFifo_TxVacancy(XLlFifo *InstancePtr)</a> </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1fa93f486abaaf35c7d599a8cd91b295"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_Write</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BufPtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Bytes&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;XStrm_Write(&amp;((InstancePtr)-&gt;TxStreamer), (BufPtr), (Bytes))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>XLlFifo_Write writes <em>Bytes</em> bytes of the block of memory, referenced by <em>BufPtr</em>, to the transmit channel of the FIFO referenced by <em>InstancePtr</em>. </p>
+<p>Care must be taken to ensure that the number of bytes written with one or more calls to <a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295" title="XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channe...">XLlFifo_Write()</a> matches the number of bytes given in the next call to <a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7" title="XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO sp...">XLlFifo_TxSetLen()</a>.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate.</td></tr>
+    <tr><td class="paramname">BufPtr</td><td>specifies the memory address of data to write.</td></tr>
+    <tr><td class="paramname">Bytes</td><td>specifies the number of bytes to write.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Error handling is handled through hardware exceptions and interrupts.</dd></dl>
+<p>C Signature: void <a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295" title="XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channe...">XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="gacd283ce73981f7f9eab94f8bb421bc78"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_WriteReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Value&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;((Xil_Out32((BaseAddress) + (RegOffset), (Value))))</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo__hw_8h.html">xllfifo_hw.h</a>&gt;</code></p>
+
+<p>XLlFifo_WriteReg writes the value, <em>Value</em>, to the register at the offet, <em>RegOffset</em>, from the memory mapped base address, <em>BaseAddress</em>. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>specifies the base address of the device.</td></tr>
+    <tr><td class="paramname">RegOffset</td><td>specifies the offset from BaseAddress.</td></tr>
+    <tr><td class="paramname">Value</td><td>is value to write to the register.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78" title="XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. ">XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)</a> </dd></dl>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga105828f79f13c07d571db218c5837fae"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XLlFifo_WriteTdr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">InstancePtr, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">Tdest&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>((InstancePtr)-&gt;BaseAddress, <a class="code" href="group__llfifo__v5__0.html#ga5c691ac1237fb77b8e356a7d2b0b8b54">XLLF_TDR_OFFSET</a>, \</div>
+<div class="line">                          Tdest &amp; 0xF)</div>
+<div class="ttc" id="group__llfifo__v5__0_html_gacd283ce73981f7f9eab94f8bb421bc78"><div class="ttname"><a href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a></div><div class="ttdeci">#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)</div><div class="ttdoc">XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:238</div></div>
+<div class="ttc" id="group__llfifo__v5__0_html_ga5c691ac1237fb77b8e356a7d2b0b8b54"><div class="ttname"><a href="group__llfifo__v5__0.html#ga5c691ac1237fb77b8e356a7d2b0b8b54">XLLF_TDR_OFFSET</a></div><div class="ttdeci">#define XLLF_TDR_OFFSET</div><div class="ttdoc">Transmit Destination. </div><div class="ttdef"><b>Definition:</b> xllfifo_hw.h:97</div></div>
+</div><!-- fragment -->
+<p>XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR) </p>
+<p>The TDR stores the destination address corresponding to the packet to be transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core the following sequence should be followed</p><ul>
+<li>Write the destination address into TDR first,</li>
+<li>Write the packet data to the Transmit Data FIFO next</li>
+<li>Write the length of the packet into the Transmit Length Register.</li>
+</ul>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the FIFO on which to operate. </td></tr>
+    <tr><td class="paramname">Tdest</td><td>is the Transmit Destination address to be written to TDR.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C Signature: void <a class="el" href="group__llfifo__v5__0.html#ga105828f79f13c07d571db218c5837fae" title="XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR) ">XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest)</a>; </dd></dl>
+
+</div>
+</div>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="ga89057d90d6eacdbe8adc766f53f60ed7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="struct_x_ll_fifo.html">XLlFifo</a>  <a class="el" href="struct_x_ll_fifo.html">XLlFifo</a></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>This typedef defines a run-time instance of an <a class="el" href="struct_x_ll_fifo.html" title="This typedef defines a run-time instance of an XLlFifo device. ">XLlFifo</a> device. </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga549da0fb83b3bb11ea6401b8001f9c4e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XLlFifo_Config * XLlFfio_LookupConfig </td>
+          <td>(</td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>DeviceId</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8h.html">xllfifo.h</a>&gt;</code></p>
+
+<p>Look up the hardware configuration for a device instance. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device to lookup for</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadc1db2785627a0d8da46dc60990889a0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XLlFifo_CfgInitialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">XLlFifo_Config *&#160;</td>
+          <td class="paramname"><em>Config</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>EffectiveAddress</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8c.html">xllfifo.c</a>&gt;</code></p>
+
+<p>XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the <em>InstancePtr</em> that references it. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the Axi Streaming FIFO instance to be worked on. </td></tr>
+    <tr><td class="paramname">CfgPtr</td><td>references the structure holding the hardware configuration for the Axi Streaming FIFO core to initialize. </td></tr>
+    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config-&gt;BaseAddress for this parameters, passing the physical address instead.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A </dd></dl>
+
+<p>References <a class="el" href="struct_x_ll_fifo.html#a455c634fb80553cecfcba0845eb99937">XLlFifo::Axi4BaseAddress</a>, <a class="el" href="struct_x_ll_fifo.html#ab1d14782860778f2546bee03cb27f192">XLlFifo::BaseAddress</a>, <a class="el" href="struct_x_ll_fifo.html#a9e2342496ea8183c012567d7c89851b3">XLlFifo::Datainterface</a>, <a class="el" href="struct_x_ll_fifo.html#abe388bb422699248b26a9d76652474b1">XLlFifo::IsReady</a>, <a class="el" href="struct_x_ll_fifo.html#a456fbf87ce23b1334c67b386722b1434">XLlFifo::RxStreamer</a>, <a class="el" href="struct_x_ll_fifo.html#a13363fb4d5d45a5725b7427b36c44817">XLlFifo::TxStreamer</a>, <a class="el" href="group__llfifo__v5__0.html#ga5331d2736e9b1b516b4262d8e3f11690">XLLF_LLR_OFFSET</a>, <a class="el" href="group__llfifo__v5__0.html#ga11c4da53ae9b166832186f9a817fba6d">XLLF_RDFR_RESET_MASK</a>, <a class="el" href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134">XLlFifo_RxReset</a>, <a class="el" href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577">XLlFifo_TxReset</a>, and <a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga1fdf07ca198f5cfe2dc14ced21e5631d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XLlFifo_Initialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>BaseAddress</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xllfifo_8c.html">xllfifo.c</a>&gt;</code></p>
+
+<p>XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the <em>InstancePtr</em> that references it. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>references the memory instance to be associated with the FIFO device upon initialization.</td></tr>
+    <tr><td class="paramname">BaseAddress</td><td>is the processor address used to access the base address of the Fifo device.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>N/A </dd></dl>
+
+<p>References <a class="el" href="struct_x_ll_fifo.html#a455c634fb80553cecfcba0845eb99937">XLlFifo::Axi4BaseAddress</a>, <a class="el" href="struct_x_ll_fifo.html#ab1d14782860778f2546bee03cb27f192">XLlFifo::BaseAddress</a>, <a class="el" href="struct_x_ll_fifo.html#abe388bb422699248b26a9d76652474b1">XLlFifo::IsReady</a>, <a class="el" href="struct_x_ll_fifo.html#a456fbf87ce23b1334c67b386722b1434">XLlFifo::RxStreamer</a>, <a class="el" href="struct_x_ll_fifo.html#a13363fb4d5d45a5725b7427b36c44817">XLlFifo::TxStreamer</a>, <a class="el" href="group__llfifo__v5__0.html#ga5331d2736e9b1b516b4262d8e3f11690">XLLF_LLR_OFFSET</a>, <a class="el" href="group__llfifo__v5__0.html#ga11c4da53ae9b166832186f9a817fba6d">XLLF_RDFR_RESET_MASK</a>, <a class="el" href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134">XLlFifo_RxReset</a>, <a class="el" href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577">XLlFifo_TxReset</a>, and <a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
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+ </tbody>
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+<!-- Generated by Doxygen 1.8.10 -->
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
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+<div class="header">
+  <div class="headertitle">
+<div class="title">llfifo_v5_0 Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>The Xilinx Dual Channel Fifo driver component. This driver supports the Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.</p>
+<p>For a full description of the bridge features, please see the HW spec. This driver supports the following features:</p><ul>
+<li>Memory mapped access to host interface registers</li>
+<li>API for polled frame transfers</li>
+<li>API for interrupt driven frame transfers</li>
+<li>Virtual memory support</li>
+<li>Full duplex operation</li>
+</ul>
+<h2>Driver Description</h2>
+<p>This driver enables higher layer software to access the XPS_llFifo core using any alignment in the data buffers.</p>
+<p>This driver supports send and receive channels in the same instance structure in the same fashion as the hardware core.</p>
+<h2>Initialization</h2>
+<p>An instance of this driver is initialized using a call to Initialize().</p>
+<h2>Usage</h2>
+<p>It is fairly simple to use the API provided by this FIFO driver. The only somewhat tricky part is that the calling code must correctly call a couple routines in the right sequence for receive and transmit.</p>
+<p>This sequence is described here. Check the routine functional descriptions for information on how to use a specific API routine.</p>
+<h3>Receive</h3>
+<p>A frame is received by using the following sequence:<br />
+ 1) call <a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5" title="XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the rece...">XLlFifo_RxOccupancy()</a> to check the occupancy count<br />
+ 2) call <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen()</a> to get the length of the next incoming frame<br />
+ 3) call <a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03" title="XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the ...">XLlFifo_Read()</a> one or more times to read the number of bytes reported by <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen()</a>.<br />
+</p>
+<p>For example: </p><pre>
+ 	while (<a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5" title="XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the rece...">XLlFifo_RxOccupancy(&amp;RxInstance)</a>) {
+ 		frame_len = <a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e" title="XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the r...">XLlFifo_RxGetLen(&amp;RxInstance)</a>;
+		while (frame_len) {
+ 			unsigned bytes = min(sizeof(buffer), frame_len);
+ 			<a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03" title="XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the ...">XLlFifo_Read(&amp;RxInstance, buffer, bytes)</a>;
+ 			// ********
+ 			// do something with buffer here
+ 			// ********
+ 			frame_len -= bytes;
+		}
+ 	}
+ </pre><p>This FIFO hardware core does <b>not</b> support a sequence where the calling code calls RxGetLen() twice in a row and then receive the data for two frames. Each frame must be read in by calling RxGetLen() just prior to reading the data.</p>
+<h3>Transmit</h3>
+<p>A frame is transmittted by using the following sequence:<br />
+ 1) call <a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295" title="XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channe...">XLlFifo_Write()</a> one or more times to write all the of bytes in the next frame.<br />
+ 2) call <a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7" title="XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO sp...">XLlFifo_TxSetLen()</a> to begin the transmission of frame just written.<br />
+</p>
+<p>For example: </p><pre>
+ 	frame_left = frame_len;
+ 	while (frame_left) {
+ 		unsigned bytes = min(sizeof(buffer), frame_left);
+ 		<a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295" title="XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channe...">XLlFifo_Write(&amp;TxInstance, buffer, bytes)</a>;
+ 		// ********
+ 		// do something here to refill buffer
+ 		// ********
+ 		frame_left -= bytes;
+ 	}
+ 	<a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7" title="XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO sp...">XLlFifo_TxSetLen(&amp;RxInstance, frame_len)</a>;
+ </pre><p>This FIFO hardware core does <b>not</b> support a sequence where the calling code writes the data for two frames and then calls TxSetLen() twice in a row. Each frame must be written by writting the data for one frame and then calling TxSetLen().</p>
+<h2>Interrupts</h2>
+<p>This driver does not handle interrupts from the FIFO hardware. The software layer above may make use of the interrupts by setting up its own handlers for the interrupts.</p>
+<pre>
+ MODIFICATION HISTORY:</pre><pre> Ver   Who  Date     Changes
+ ----- ---- -------- -------------------------------------------------------
+ 1.00a jvb  10/12/06 First release
+ 1.01a sdm  08/22/08 Removed support for static interrupt handlers from the
+		       MDD file
+ 1.02a jz   12/04/09 Hal phase 1 support
+ 2.01a asa  09/17/10 Added code for resetting Local Link/AXI Streaming
+		       interface for CR574868
+ 2.02a asa  12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
+		       HeadIndex to zero when all bytes have been read.
+		       Changed the macro XStrm_IsRxInternalEmpty in file
+		       xtreamer.h to use FrmByteCnt instead of HeadIndex.
+		       When FrmByteCnt is zero, this means all internal buffers
+		       in streamer are empty. Earlier implementation using
+		       HeadIndex was not very clear and could give improper
+		       results for some cases.
+		       Changed the macro XLlFifo_IsRxEmpty in file <a class="el" href="xllfifo_8h.html">xllfifo.h</a>
+		       These changes are done to fix the CR 604650.
+  2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+		         defines for the new registers, and XLLF_INT_TFPF_MASK,
+		         XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+		         XLLF_INT_RFPE_MASK for the new version of the
+		         AXI4-Stream FIFO core (v2.01a and later)</pre><pre> 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
+ 		      In <a class="el" href="xllfifo_8c.html">Xllfifo.c</a> file XLlFifo_RxGetWord,XLlFifo_TxPutword.
+ 		      In <a class="el" href="xllfifo_8h.html">XLlfifo.h</a> file updated XLlfifo structure for
+ 		      Axi4BaseAddress and for Datainterface type provided
+		      polling and interrupt examples. XLlfifo_IsRxDone Macro
+		      Is added in the <a class="el" href="xllfifo_8h.html">XLlfifo.h</a> file for polledmode exmaple.
+		      Added Static initialzation for the driver.
+		      XLlFifo_Initialize is still used to make the driver
+		      backward compatible.
+ 4.0   adk  19/12/13 Updated as per the New Tcl API's
+ 5.0   adk  15/05/15 Updated the register offsets in the AXI4 data path
+		       as per latest IP version(v4.1)(CR:860254).</pre><pre> </pre> </div></div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/jquery.js b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/jquery.js
new file mode 100644
index 000000000..1f4d0b47c
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/jquery.js
@@ -0,0 +1,68 @@
+/*!
+ * jQuery JavaScript Library v1.7.1
+ * http://jquery.com/
+ *
+ * Copyright 2011, John Resig
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * Includes Sizzle.js
+ * http://sizzlejs.com/
+ * Copyright 2011, The Dojo Foundation
+ * Released under the MIT, BSD, and GPL Licenses.
+ *
+ * Date: Mon Nov 21 21:11:03 2011 -0500
+ */
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+/*!
+ * Sizzle CSS Selector Engine
+ *  Copyright 2011, The Dojo Foundation
+ *  Released under the MIT, BSD, and GPL Licenses.
+ *  More information: http://sizzlejs.com/
+ */
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+ * jQuery UI 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI
+ */
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+ * jQuery UI Widget 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Widget
+ */
+(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!
+ * jQuery UI Mouse 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Mouse
+ *
+ * Depends:
+ *	jquery.ui.widget.js
+ */
+(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e=="sw"){h.left=j.left+(f.width-h.width);h.top=null}if(e=="nw"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css("borderTopWidth"),h.css("borderRightWidth"),h.css("borderBottomWidth"),h.css("borderLeftWidth")],j=[h.css("paddingTop"),h.css("paddingRight"),h.css("paddingBottom"),h.css("paddingLeft")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(":hidden")||c(g).parents(":hidden").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var 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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+<title>llfifo_v5_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">APIs</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__llfifo__v5__0.html" target="_self">Llfifo_v5_0</a></td><td class="desc">The Xilinx local link FIFO driver component </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_ll_fifo.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_ll_fifo.html
new file mode 100644
index 000000000..e80cea6a0
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_ll_fifo.html
@@ -0,0 +1,165 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: XLlFifo Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
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+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">XLlFifo Struct Reference<div class="ingroups"><a class="el" href="group__llfifo__v5__0.html">Llfifo_v5_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a9e2342496ea8183c012567d7c89851b3"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_ll_fifo.html#a9e2342496ea8183c012567d7c89851b3">Datainterface</a></td></tr>
+<tr class="separator:a9e2342496ea8183c012567d7c89851b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a455c634fb80553cecfcba0845eb99937"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XLlFifo::Axi4BaseAddress</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>BaseAddress if the FIFO Data interface is AXI4 this address should use for FIFO access. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ab1d14782860778f2546bee03cb27f192"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XLlFifo::BaseAddress</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>BaseAddress is the physical base address of the device's registers. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a9e2342496ea8183c012567d7c89851b3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XLlFifo::Datainterface</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Data interface of the FIFO. </p>
+<p>This value is zero if the Datainterface is AXI4-lite. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="abe388bb422699248b26a9d76652474b1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XLlFifo::IsReady</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>IsReady is non-zero if the driver instance has been initialized. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a456fbf87ce23b1334c67b386722b1434"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_strm___rx_fifo_streamer.html">XStrm_RxFifoStreamer</a> XLlFifo::RxStreamer</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>RxStreamer is the byte streamer instance for the receive channel. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a13363fb4d5d45a5725b7427b36c44817"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_strm___tx_fifo_streamer.html">XStrm_TxFifoStreamer</a> XLlFifo::TxStreamer</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>TxStreamer is the byte streamer instance for the transmit channel. </p>
+
+<p>Referenced by <a class="el" href="group__llfifo__v5__0.html#gadc1db2785627a0d8da46dc60990889a0">XLlFifo_CfgInitialize()</a>, and <a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_strm___rx_fifo_streamer.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_strm___rx_fifo_streamer.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+<title>llfifo_v5_0: XStrm_RxFifoStreamer Struct Reference</title>
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+<script type="text/javascript" src="dynsections.js"></script>
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+<div id="titlearea">
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+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
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+</table>
+</div>
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+<!-- Generated by Doxygen 1.8.10 -->
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+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
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+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XStrm_RxFifoStreamer Struct Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ab278ceaef035943f8a3a8b85a8cab99d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* XStrm_RxFifoStreamer::FifoInstance</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>FifoInstance is the FIFO driver instance to pass to ReadFn, GetLenFn, and GetOccupancyFn routines. </p>
+
+</div>
+</div>
+<a class="anchor" id="a3ad4cdd1ad14dcecfaf5f923850289fb"></a>
+<div class="memitem">
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+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned XStrm_RxFifoStreamer::FifoWidth</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>FifoWidth is the FIFO key hole width in bytes. </p>
+
+</div>
+</div>
+<a class="anchor" id="a9fa74d02f4fa2607e78b11de059be837"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned XStrm_RxFifoStreamer::FrmByteCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>FrmByteCnt is the number of bytes in the next Frame. </p>
+
+</div>
+</div>
+<a class="anchor" id="a01fa1cc2098388ac9371beb090c0c212"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XStrm_GetLenFnType XStrm_RxFifoStreamer::GetLenFn</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>GetLenFn is the routine the streamer uses to initiate receive operations on the FIFO. </p>
+
+</div>
+</div>
+<a class="anchor" id="a8d552e42f58c3230de010178832b41b1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XStrm_GetOccupancyFnType XStrm_RxFifoStreamer::GetOccupancyFn</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>GetOccupancyFn is the routine the streamer uses to get the occupancy from the FIFO. </p>
+
+</div>
+</div>
+<a class="anchor" id="a6321ab6bf1a1f3979c0771618a4aba7c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned XStrm_RxFifoStreamer::HeadIndex</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>HeadIndex is the index to the AlignedBuffer as bytes. </p>
+
+</div>
+</div>
+<a class="anchor" id="af3bfc974fd88c7b707edf680b3c9aed2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XStrm_XferFnType XStrm_RxFifoStreamer::ReadFn</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>ReadFn is the routine the streamer uses to receive bytes from the Fifo. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_strm___tx_fifo_streamer.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_strm___tx_fifo_streamer.html
new file mode 100644
index 000000000..225c58309
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/struct_x_strm___tx_fifo_streamer.html
@@ -0,0 +1,144 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: XStrm_TxFifoStreamer Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XStrm_TxFifoStreamer Struct Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ac20fde8a3090fddfc01f8b2900fd9051"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">void* XStrm_TxFifoStreamer::FifoInstance</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>FifoInstance is the FIFO driver instance to pass to WriteFn, SetLenFn, and GetVacancyFn routines. </p>
+
+</div>
+</div>
+<a class="anchor" id="a474cf91d66d43f716a34299d4ab9b9b2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned XStrm_TxFifoStreamer::FifoWidth</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>FifoWidth is the FIFO key hole width in bytes. </p>
+
+</div>
+</div>
+<a class="anchor" id="ab33212eea0a6327f2c6b1173510170a9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XStrm_GetVacancyFnType XStrm_TxFifoStreamer::GetVacancyFn</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>GetVaccancyFn is the routine the streamer uses to get the vacancy from the FIFO. </p>
+
+</div>
+</div>
+<a class="anchor" id="aa315e740022ccc81ef9cccfe7c82022d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">XStrm_SetLenFnType XStrm_TxFifoStreamer::SetLenFn</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>SetLenFn is the routine the streamer uses to initiate transmit operations on the FIFO. </p>
+
+</div>
+</div>
+<a class="anchor" id="a265500391a387c5354a14fea79a1b446"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned XStrm_TxFifoStreamer::TailIndex</td>
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+
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+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
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+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
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+<div class="title">xllfifo.c File Reference</div>  </div>
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+  </ul>
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+<tr class="separator:ga105828f79f13c07d571db218c5837fae"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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+<tr class="memitem:ga1fdf07ca198f5cfe2dc14ced21e5631d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga1fdf07ca198f5cfe2dc14ced21e5631d">XLlFifo_Initialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, u32 BaseAddress)</td></tr>
+<tr class="separator:ga1fdf07ca198f5cfe2dc14ced21e5631d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga549da0fb83b3bb11ea6401b8001f9c4e"><td class="memItemLeft" align="right" valign="top">XLlFifo_Config *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga549da0fb83b3bb11ea6401b8001f9c4e">XLlFfio_LookupConfig</a> (u32 DeviceId)</td></tr>
+<tr class="separator:ga549da0fb83b3bb11ea6401b8001f9c4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/xllfifo__hw_8h.html b/thirdparty/xilinx/orig/llfifo_v5_0/doc/html/api/xllfifo__hw_8h.html
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+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>llfifo_v5_0: xllfifo_hw.h File Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">llfifo_v5_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_a52b273757869cfc1920fae4a1b566e2.html">llfifo_v5_0</a></li><li class="navelem"><a class="el" href="dir_4468dcb9415154bf287f63611f80e391.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">xllfifo_hw.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga7526eab563fa4e0fe8b60474e96afe55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32((BaseAddress) + (RegOffset)))</td></tr>
+<tr class="separator:ga7526eab563fa4e0fe8b60474e96afe55"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gacd283ce73981f7f9eab94f8bb421bc78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gacd283ce73981f7f9eab94f8bb421bc78">XLlFifo_WriteReg</a>(BaseAddress,  RegOffset,  Value)&#160;&#160;&#160;((Xil_Out32((BaseAddress) + (RegOffset), (Value))))</td></tr>
+<tr class="separator:gacd283ce73981f7f9eab94f8bb421bc78"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr><td colspan="2"><div class="groupHeader">Registers</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Interrupt bits</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET registers. </p>
+</div></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Reset register values</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET reset registers. </p>
+</div></td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/examples/index.html b/thirdparty/xilinx/orig/llfifo_v5_0/examples/index.html
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index 000000000..c3fc8110c
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/examples/index.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver llfifo_v5_0 </h1>
+<HR>
+<ul>
+  <li>xllfifo_interrupt_example.c <a href="xllfifo_interrupt_example.c">(source)</a> </li>
+    <li>xllfifo_polling_example.c <a href="xllfifo_polling_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright � 1995-2015 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/examples/xllfifo_interrupt_example.c b/thirdparty/xilinx/orig/llfifo_v5_0/examples/xllfifo_interrupt_example.c
new file mode 100644
index 000000000..85f00caad
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/examples/xllfifo_interrupt_example.c
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+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xllfifo_interrupt_example.c
+ * This file demonstrates how to use the Streaming fifo driver on the xilinx AXI
+ * Streaming FIFO IP.The AXI4-Stream FIFO core allows memory mapped access to a
+ * AXI-Stream interface. The core can be used to interface to AXI Streaming IPs
+ * similar to the LogiCORE IP AXI Ethernet core, without having to use full DMA
+ * solution.
+ *
+ * This is the interrupt example for the FIFO it assumes that at the
+ * h/w level FIFO is connected in loopback.In these we write known amount of
+ * data to the FIFO and wait for interrupts and after compltely receiving the
+ * data compares it with the data transmitted.
+ *
+ * Note: The TDEST Must be enabled in the H/W design inorder to get
+ * correct RDR value.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 3.00a adk 08/10/2013 initial release CR:727787
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xstreamer.h"
+#include "xil_cache.h"
+#include "xllfifo.h"
+#include "xstatus.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #include "xintc.h"
+#else
+ #include "xscugic.h"
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define FIFO_DEV_ID	   	XPAR_AXI_FIFO_0_DEVICE_ID
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
+#define FIFO_INTR_ID		XPAR_INTC_0_LLFIFO_0_VEC_ID
+#else
+#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define FIFO_INTR_ID            XPAR_FABRIC_LLFIFO_0_VEC_ID
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #define INTC           XIntc
+ #define INTC_HANDLER   XIntc_InterruptHandler
+#else
+ #define INTC           XScuGic
+ #define INTC_HANDLER   XScuGic_InterruptHandler
+#endif
+
+
+#define WORD_SIZE 4			/* Size of words in bytes */
+
+#define MAX_PACKET_LEN 4
+
+#define NO_OF_PACKETS 64
+
+#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN
+
+#undef DEBUG
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId);
+int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr);
+static void FifoHandler(XLlFifo *Fifo);
+static void FifoRecvHandler(XLlFifo *Fifo);
+static void FifoSendHandler(XLlFifo *Fifo);
+static void FifoErrorHandler(XLlFifo *InstancePtr, u32 Pending);
+int SetupInterruptSystem(INTC *IntcInstancePtr, XLlFifo *InstancePtr,
+				u16 FifoIntrId);
+static void DisableIntrSystem(INTC *IntcInstancePtr, u16 FifoIntrId);
+
+/*
+ * Flags interrupt handlers use to notify the application context the events.
+ */
+volatile int Done;
+volatile int Error;
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Device instance definitions
+ */
+XLlFifo FifoInstance;
+
+/*
+ * Instance of the Interrupt Controller
+ */
+static INTC Intc;
+
+u32 SourceBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
+u32 DestinationBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the AXI FIFO interrupt test.
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if tests pass
+* 		- XST_FAILURE if fails.
+*
+* @note		None
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("--- Entering main() ---\n\r");
+
+	Status = XLlFifoInterruptExample(&FifoInstance, FIFO_DEV_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Axi Streaming FIFO Interrupt Example Test Failed");
+		xil_printf("--- Exiting main() ---\n\r");
+		return XST_FAILURE;
+	}
+
+	xil_printf("Axi Streaming FIFO Interrupt Example Test passed\n\r");
+	xil_printf("--- Exiting main() ---\n\r");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the usage of AXI FIFO
+* It does the following:
+*       - Set up the output terminal if UART16550 is in the hardware build
+*       - Initialize the Axi FIFO Device.
+*	- Set up the interrupt handler for fifo
+*	- Transmit the data
+*	- Compare the data
+*	- Return the result
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XLlFifo instance.
+* @param	DeviceId is Device ID of the Axi Fifo Deive instance,
+*		typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId)
+{
+	XLlFifo_Config *Config;
+	int Status;
+	int i;
+	int err;
+	Status = XST_SUCCESS;
+
+	/* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	/* Initialize the Device Configuration Interface driver */
+	Config = XLlFfio_LookupConfig(DeviceId);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * This is where the virtual address would be used, this example
+	 * uses physical address.
+	 */
+	Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed\n\r");
+		return Status;
+	}
+
+	/* Check for the Reset value */
+	Status = XLlFifo_Status(InstancePtr);
+	XLlFifo_IntClear(InstancePtr,0xffffffff);
+	Status = XLlFifo_Status(InstancePtr);
+	if(Status != 0x0) {
+		xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
+			    "Expected : 0x0\n\r",
+			    XLlFifo_Status(InstancePtr));
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the Axi Streaming FIFO to the interrupt subsystem such
+	 * that interrupts can occur. This function is application specific.
+	 */
+	Status = SetupInterruptSystem(&Intc, InstancePtr, FIFO_INTR_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed intr setup\r\n");
+		return XST_FAILURE;
+	}
+
+	XLlFifo_IntEnable(InstancePtr, XLLF_INT_ALL_MASK);
+
+	Done = 0;
+	/* Transmit the Data Stream */
+	Status = TxSend(InstancePtr, SourceBuffer);
+	if (Status != XST_SUCCESS){
+		xil_printf("Transmission of Data failed\n\r");
+		return XST_FAILURE;
+	}
+	while(!Done);
+
+	/* Check for errors */
+	if(Error) {
+		xil_printf("Errors in the FIFO\n\r");
+		return XST_FAILURE;
+	}
+
+	err = 0;
+
+	/* Compare the data sent with the data received */
+	xil_printf("Comparing data...\n\r");
+	for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
+		if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
+			err = 1;
+			break;
+		}
+
+	}
+
+	if (err != 0){
+		return XST_FAILURE;
+	}
+
+	DisableIntrSystem(&Intc, FIFO_INTR_ID);
+	return Status;
+}
+
+/*****************************************************************************/
+/*
+*
+* TxSend routine, It will send the requested amount of data at the
+* specified addr.
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XLlFifo component.
+*
+* @param	SourceAddr is the address of the memory
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+* @note		None
+*
+******************************************************************************/
+int TxSend(XLlFifo *InstancePtr, u32  *SourceAddr)
+{
+	int i;
+	int j;
+	xil_printf("Transmitting Data ... \r\n");
+
+	/* Filling the buffer with the */
+	for (i=0; i < MAX_DATA_BUFFER_SIZE; i++)
+		*(SourceAddr + i) = 0;
+
+	for(i=0; i < NO_OF_PACKETS; i++){
+		/* Writing into the FIFO Transmit Port Buffer */
+		for (j=0; j < MAX_PACKET_LEN; j++){
+			if( XLlFifo_iTxVacancy(InstancePtr) ){
+				XLlFifo_TxPutWord(InstancePtr,
+					*(SourceAddr+(i*MAX_PACKET_LEN)+j));
+			}
+		}
+
+	}
+
+	/* Start Transmission by writing transmission length into the TLR */
+	XLlFifo_iTxSetLen(InstancePtr, (MAX_DATA_BUFFER_SIZE * WORD_SIZE));
+
+
+	/* Transmission Complete */
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the interrupt handler for the fifo it checks for the type of interrupt
+* and proceeds according to it.
+*
+* @param	InstancePtr is a reference to the Fifo device instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void FifoHandler(XLlFifo *InstancePtr)
+{
+	u32 Pending;
+
+	Pending = XLlFifo_IntPending(InstancePtr);
+	while (Pending) {
+		if (Pending & XLLF_INT_RC_MASK) {
+			FifoRecvHandler(InstancePtr);
+			XLlFifo_IntClear(InstancePtr, XLLF_INT_RC_MASK);
+		}
+		else if (Pending & XLLF_INT_TC_MASK) {
+			FifoSendHandler(InstancePtr);
+		}
+		else if (Pending & XLLF_INT_ERROR_MASK){
+			FifoErrorHandler(InstancePtr, Pending);
+			XLlFifo_IntClear(InstancePtr, XLLF_INT_ERROR_MASK);
+		} else {
+			XLlFifo_IntClear(InstancePtr, Pending);
+		}
+		Pending = XLlFifo_IntPending(InstancePtr);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the Receive handler callback function.
+*
+* @param	InstancePtr is a reference to the Fifo device instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void FifoRecvHandler(XLlFifo *InstancePtr)
+{
+	int i;
+	u32 RxWord;
+	static u32 ReceiveLength;
+
+	xil_printf("Receiving Data... \n\r");
+
+	/* Read Recieve Length */
+	ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE;
+
+	while(XLlFifo_iRxOccupancy(InstancePtr)) {
+		for (i=0; i < ReceiveLength; i++) {
+				RxWord = XLlFifo_RxGetWord(InstancePtr);
+				*(DestinationBuffer+i) = RxWord;
+		}
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the transfer Complete Interrupt handler function.
+*
+* This clears the trasmit complete interrupt and set the done flag.
+*
+* @param	InstancePtr is a pointer to Instance of AXI FIFO device.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void FifoSendHandler(XLlFifo *InstancePtr)
+{
+	XLlFifo_IntClear(InstancePtr, XLLF_INT_TC_MASK);
+
+	Done = 1;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the Error handler callback function and this function increments the
+* the error counter so that the main thread knows the number of errors.
+*
+* @param	InstancePtr is a pointer to Instance of AXI FIFO device.
+*
+* @param	Pending is a bitmask of the pending interrupts.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void FifoErrorHandler(XLlFifo *InstancePtr, u32 Pending)
+{
+	if (Pending & XLLF_INT_RPURE_MASK) {
+		XLlFifo_RxReset(InstancePtr);
+	} else if (Pending & XLLF_INT_RPORE_MASK) {
+		XLlFifo_RxReset(InstancePtr);
+	} else if(Pending & XLLF_INT_RPUE_MASK) {
+		XLlFifo_RxReset(InstancePtr);
+	} else if (Pending & XLLF_INT_TPOE_MASK) {
+		XLlFifo_TxReset(InstancePtr);
+	} else if (Pending & XLLF_INT_TSE_MASK) {
+	}
+	Error++;
+}
+
+/****************************************************************************/
+/**
+*
+* This function setups the interrupt system such that interrupts can occur
+* for the FIFO device. This function is application specific since the
+* actual system may or may not have an interrupt controller. The FIFO
+* could be directly connected to a processor without an interrupt controller.
+* The user should modify this function to fit the application.
+*
+* @param    InstancePtr contains a pointer to the instance of the FIFO
+*           component which is going to be connected to the interrupt
+*           controller.
+*
+* @return   XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note     None.
+*
+****************************************************************************/
+int SetupInterruptSystem(INTC *IntcInstancePtr, XLlFifo *InstancePtr,
+				u16 FifoIntrId)
+{
+
+	int Status;
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Connect a device driver handler that will be called when an interrupt
+	 * for the device occurs, the device driver handler performs the
+	 * specific interrupt processing for the device.
+	 */
+	Status = XIntc_Connect(IntcInstancePtr, FifoIntrId,
+			   (XInterruptHandler)FifoHandler,
+			   (void *)InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Start the interrupt controller such that interrupts are enabled for
+	 * all devices that cause interrupts, specific real mode so that
+	 * the FIFO can cause interrupts through the interrupt controller.
+	 */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the interrupt for the AXI FIFO device.
+	 */
+	XIntc_Enable(IntcInstancePtr, FifoIntrId);
+#else
+	XScuGic_Config *IntcConfig;
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+				IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, FifoIntrId, 0xA0, 0x3);
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, FifoIntrId,
+				(Xil_InterruptHandler)FifoHandler,
+				InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XScuGic_Enable(IntcInstancePtr, FifoIntrId);
+#endif
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+		(Xil_ExceptionHandler)INTC_HANDLER,
+		(void *)IntcInstancePtr);;
+
+	/*
+	 * Enable exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts for the AXI FIFO device.
+*
+* @param	IntcInstancePtr is the pointer to the INTC component instance
+* @param	FifoIntrId is interrupt ID associated for the FIFO component
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void DisableIntrSystem(INTC *IntcInstancePtr, u16 FifoIntrId)
+{
+#ifdef XPAR_INTC_0_DEVICE_ID
+	/* Disconnect the interrupts */
+	XIntc_Disconnect(IntcInstancePtr, FifoIntrId);
+#else
+	XScuGic_Disconnect(IntcInstancePtr, FifoIntrId);
+#endif
+}
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/examples/xllfifo_polling_example.c b/thirdparty/xilinx/orig/llfifo_v5_0/examples/xllfifo_polling_example.c
new file mode 100644
index 000000000..6b018ba5a
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/examples/xllfifo_polling_example.c
@@ -0,0 +1,361 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file XLlFifo_polling_example.c
+ * This file demonstrates how to use the Streaming fifo driver on the xilinx AXI
+ * Streaming FIFO IP.The AXI4-Stream FIFO core allows memory mapped access to a
+ * AXI-Stream interface. The core can be used to interface to AXI Streaming IPs
+ * similar to the LogiCORE IP AXI Ethernet core, without having to use full DMA
+ * solution.
+ *
+ * This is the polling example for the FIFO it assumes that at the
+ * h/w level FIFO is connected in loopback.In these we write known amount of
+ * data to the FIFO and Receive the data and compare with the data transmitted.
+ *
+ * Note: The TDEST Must be enabled in the H/W design inorder to
+ * get correct RDR value.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 3.00a adk 08/10/2013 initial release CR:727787
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xstreamer.h"
+#include "xil_cache.h"
+#include "xllfifo.h"
+#include "xstatus.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define FIFO_DEV_ID	   	XPAR_AXI_FIFO_0_DEVICE_ID
+
+#define WORD_SIZE 4			/* Size of words in bytes */
+
+#define MAX_PACKET_LEN 4
+
+#define NO_OF_PACKETS 64
+
+#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN
+
+#undef DEBUG
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId);
+int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr);
+int RxReceive(XLlFifo *InstancePtr, u32 *DestinationAddr);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XLlFifo FifoInstance;
+
+u32 SourceBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
+u32 DestinationBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the Axi FIFO Polling test.
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if tests pass
+* 		- XST_FAILURE if fails.
+*
+* @note		None
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("--- Entering main() ---\n\r");
+
+	Status = XLlFifoPollingExample(&FifoInstance, FIFO_DEV_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Axi Streaming FIFO Polling Example TestFailed\n\r");
+		xil_printf("--- Exiting main() ---\n\r");
+		return XST_FAILURE;
+	}
+
+	xil_printf("Axi Streaming FIFO Polling Example Test passed\n\r");
+	xil_printf("--- Exiting main() ---\n\r");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the usage AXI FIFO
+* It does the following:
+*       - Set up the output terminal if UART16550 is in the hardware build
+*       - Initialize the Axi FIFO Device.
+*	- Transmit the data
+*	- Receive the data from fifo
+*	- Compare the data
+*	- Return the result
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XLlFifo component.
+* @param	DeviceId is Device ID of the Axi Fifo Deive instance,
+*		typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId)
+{
+	XLlFifo_Config *Config;
+	int Status;
+	int i;
+	int Error;
+	Status = XST_SUCCESS;
+
+	/* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	/* Initialize the Device Configuration Interface driver */
+	Config = XLlFfio_LookupConfig(DeviceId);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * This is where the virtual address would be used, this example
+	 * uses physical address.
+	 */
+	Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed\n\r");
+		return Status;
+	}
+
+	/* Check for the Reset value */
+	Status = XLlFifo_Status(InstancePtr);
+	XLlFifo_IntClear(InstancePtr,0xffffffff);
+	Status = XLlFifo_Status(InstancePtr);
+	if(Status != 0x0) {
+		xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
+			    "Expected : 0x0\n\r",
+			    XLlFifo_Status(InstancePtr));
+		return XST_FAILURE;
+	}
+
+	/* Transmit the Data Stream */
+	Status = TxSend(InstancePtr, SourceBuffer);
+	if (Status != XST_SUCCESS){
+		xil_printf("Transmisson of Data failed\n\r");
+		return XST_FAILURE;
+	}
+
+	/* Revceive the Data Stream */
+	Status = RxReceive(InstancePtr, DestinationBuffer);
+	if (Status != XST_SUCCESS){
+		xil_printf("Receiving data failed");
+		return XST_FAILURE;
+	}
+
+	Error = 0;
+
+	/* Compare the data send with the data received */
+	xil_printf(" Comparing data ...\n\r");
+	for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
+		if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
+			Error = 1;
+			break;
+		}
+
+	}
+
+	if (Error != 0){
+		return XST_FAILURE;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/*
+*
+* TxSend routine, It will send the requested amount of data at the
+* specified addr.
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XLlFifo component.
+*
+* @param	SourceAddr is the address where the FIFO stars writing
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+* @note		None
+*
+******************************************************************************/
+int TxSend(XLlFifo *InstancePtr, u32  *SourceAddr)
+{
+
+	int i;
+	int j;
+	xil_printf(" Transmitting Data ... \r\n");
+
+	/* Filling the buffer with data */
+	for (i=0;i<MAX_DATA_BUFFER_SIZE;i++)
+		*(SourceAddr + i) = 0;
+
+	for(i=0 ; i < NO_OF_PACKETS ; i++){
+
+		/* Writing into the FIFO Transmit Port Buffer */
+		for (j=0 ; j < MAX_PACKET_LEN ; j++){
+			if( XLlFifo_iTxVacancy(InstancePtr) ){
+				XLlFifo_TxPutWord(InstancePtr,
+					*(SourceAddr+(i*MAX_PACKET_LEN)+j));
+			}
+		}
+
+	}
+
+	/* Start Transmission by writing transmission length into the TLR */
+	XLlFifo_iTxSetLen(InstancePtr, (MAX_DATA_BUFFER_SIZE * WORD_SIZE));
+
+	/* Check for Transmission completion */
+	while( !(XLlFifo_IsTxDone(InstancePtr)) ){
+
+	}
+
+	/* Transmission Complete */
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* RxReceive routine.It will receive the data from the FIFO.
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XLlFifo instance.
+*
+* @param	DestinationAddr is the address where to copy the received data.
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+* @note		None
+*
+******************************************************************************/
+int RxReceive (XLlFifo *InstancePtr, u32* DestinationAddr)
+{
+
+	int i;
+	int Status;
+	u32 RxWord;
+	static u32 ReceiveLength;
+
+	xil_printf(" Receiving data ....\n\r");
+	/* Read Recieve Length */
+	ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE;
+
+	/* Start Receiving */
+	for ( i=0; i < ReceiveLength; i++){
+		RxWord = 0;
+		RxWord = XLlFifo_RxGetWord(InstancePtr);
+
+		if(XLlFifo_iRxOccupancy(InstancePtr)){
+			RxWord = XLlFifo_RxGetWord(InstancePtr);
+		}
+		*(DestinationAddr+i) = RxWord;
+	}
+
+	Status = XLlFifo_IsRxDone(InstancePtr);
+	if(Status != TRUE){
+		xil_printf("Failing in receive complete ... \r\n");
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/Makefile b/thirdparty/xilinx/orig/llfifo_v5_0/src/Makefile
new file mode 100644
index 000000000..100e478ad
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/Makefile
@@ -0,0 +1,27 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES:=xllfifo.h xllfifo_hw.h xstreamer.h
+LIBSOURCES:=*.c
+OUTS := *.o
+
+
+libs:
+	echo "Compiling llfifo"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	 ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OUTS}
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo.c b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo.c
new file mode 100644
index 000000000..7997dc66e
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo.c
@@ -0,0 +1,498 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xllfifo.c
+* @addtogroup llfifo_v5_0
+* @{
+ *
+ * The Xilinx local link FIFO driver component. This driver supports the
+ * Xilinx xps_ll_fifo core.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/13/06 First release
+ * 1.00a xd   12/17/07 Added type casting to fix CR #456850
+ * 1.02a jz   12/04/09  Hal phase 1 support
+ * 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+ * 2.01a asa  09/17/10  Added code for resetting Streaming interface
+ *		        for CR574868
+ * 3.00a adk  08/10/13  Added support for AXI4 Datainterface.Updated
+ * 		        XLlFifo_RxGetWord, XLlFifo_TxPutword inorder to
+ * 		        handle AXI4 Datainterface. Added Config
+ * 		        initialization for the driver.
+ * </pre>
+ ******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xllfifo.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+#define FIFO_WIDTH_BYTES 4
+
+/*
+ * Implementation Notes:
+ *
+ * This Fifo driver makes use of a byte streamer driver (xstreamer.h). The code
+ * is structured like so:
+ *
+ * +--------------------+
+ * |     llfifo        |
+ * |   +----------------+
+ * |   | +--------------+
+ * |   | |  xstreamer   |
+ * |   | +--------------+
+ * |   +----------------+
+ * |                    |
+ * +--------------------+
+ *
+ * Initialization
+ * At initialization time this driver (llfifo) sets up the streamer objects to
+ * use routines in this driver (llfifo) to perform the actual I/O to the H/W
+ * FIFO core.
+ *
+ * Operation
+ * Once the streamer objects are set up, the API routines in this driver, just
+ * call through to the streamer driver to perform the read/write operations.
+ * The streamer driver will eventually make calls back into the routines (which
+ * reside in this driver) given at initialization to peform the actual I/O.
+ *
+ * Interrupts
+ * Interrupts are handled in the OS/Application layer above this driver.
+ */
+
+xdbg_stmnt(u32 _xllfifo_rr_value;)
+xdbg_stmnt(u32 _xllfifo_ipie_value;)
+xdbg_stmnt(u32 _xllfifo_ipis_value;)
+
+/*****************************************************************************/
+/*
+*
+* XLlFifo_iRxOccupancy returns the number of 32-bit words available (occupancy)
+* to be read from the receive channel of the FIFO, specified by
+* <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_iRxOccupancy returns the occupancy count in 32-bit words for
+*           the specified FIFO.
+*
+******************************************************************************/
+u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr);
+
+	return XLlFifo_ReadReg(InstancePtr->BaseAddress,
+			XLLF_RDFO_OFFSET);
+}
+
+/*****************************************************************************/
+/*
+*
+* XLlFifo_iRxGetLen notifies the hardware that the program is ready to receive the
+* next frame from the receive channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* Note that the program must first call XLlFifo_iRxGetLen before pulling data
+* out of the receive channel of the FIFO with XLlFifo_Read.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_iRxGetLen returns the number of bytes available in the next
+*           frame.
+*
+******************************************************************************/
+u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr);
+
+	return XLlFifo_ReadReg(InstancePtr->BaseAddress,
+		XLLF_RLF_OFFSET);
+}
+
+/*****************************************************************************/
+/*
+*
+* XLlFifo_iRead_Aligned reads, <i>WordCount</i>, words from the FIFO referenced by
+* <i>InstancePtr</i> to the block of memory, referenced by <i>BufPtr</i>.
+*
+* XLlFifo_iRead_Aligned assumes that <i>BufPtr</i> is already aligned according
+* to the following hardware limitations:
+*    ppc        - aligned on 32 bit boundaries to avoid performance penalties
+*                 from unaligned exception handling.
+*    microblaze - aligned on 32 bit boundaries as microblaze does not handle
+*                 unaligned transfers.
+*
+* Care must be taken to ensure that the number of words read with one or more
+* calls to XLlFifo_Read() does not exceed the number of bytes (rounded up to
+* the nearest whole 32 bit word) available given from the last call to
+* XLlFifo_RxGetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address to place the data read.
+*
+* @param    WordCount specifies the number of 32 bit words to read.
+*
+* @return   XLlFifo_iRead_Aligned always returns XST_SUCCESS. Error handling is
+*           otherwise handled through hardware exceptions and interrupts.
+*
+* @note
+*
+* C Signature: int XLlFifo_iRead_Aligned(XLlFifo *InstancePtr,
+*                      void *BufPtr, unsigned WordCount);
+*
+******************************************************************************/
+/* static */ int XLlFifo_iRead_Aligned(XLlFifo *InstancePtr, void *BufPtr,
+			     unsigned WordCount)
+{
+	unsigned WordsRemaining = WordCount;
+	u32 *BufPtrIdx = (u32 *)BufPtr;
+
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "XLlFifo_iRead_Aligned: start\n");
+	Xil_AssertNonvoid(InstancePtr);
+	Xil_AssertNonvoid(BufPtr);
+	/* assert bufer is 32 bit aligned */
+	Xil_AssertNonvoid(((unsigned)BufPtr & 0x3) == 0x0);
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "XLlFifo_iRead_Aligned: after asserts\n");
+
+	while (WordsRemaining) {
+/*		xdbg_printf(XDBG_DEBUG_FIFO_RX,
+			    "XLlFifo_iRead_Aligned: WordsRemaining: %d\n",
+			    WordsRemaining);
+*/
+		*BufPtrIdx = XLlFifo_RxGetWord(InstancePtr);
+		BufPtrIdx++;
+		WordsRemaining--;
+	}
+	xdbg_printf(XDBG_DEBUG_FIFO_RX,
+		    "XLlFifo_iRead_Aligned: returning SUCCESS\n");
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/*
+*
+* XLlFifo_iTxVacancy returns the number of unused 32 bit words available
+* (vacancy) in the send channel of the FIFO, specified by <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_iTxVacancy returns the vacancy count in 32-bit words for
+*           the specified FIFO.
+*
+*****************************************************************************/
+u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr);
+
+	return XLlFifo_ReadReg(InstancePtr->BaseAddress,
+			XLLF_TDFV_OFFSET);
+}
+
+/*****************************************************************************/
+/*
+*
+* XLlFifo_iTxSetLen begins a hardware transfer of data out of the transmit
+* channel of the FIFO, specified by <i>InstancePtr</i>. <i>Bytes</i> specifies the number
+* of bytes in the frame to transmit.
+*
+* Note that <i>Bytes</i> (rounded up to the nearest whole 32 bit word) must be same
+* number of words just written using one or more calls to
+* XLlFifo_iWrite_Aligned()
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Bytes specifies the number of bytes to transmit.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes)
+{
+	Xil_AssertVoid(InstancePtr);
+
+	XLlFifo_WriteReg(InstancePtr->BaseAddress, XLLF_TLF_OFFSET,
+			Bytes);
+}
+
+/*****************************************************************************/
+/*
+*
+* XLlFifo_iWrite_Aligned writes, <i>WordCount</i>, words to the FIFO referenced by
+* <i>InstancePtr</i> from the block of memory, referenced by <i>BufPtr</i>.
+*
+* XLlFifo_iWrite_Aligned assumes that <i>BufPtr</i> is already aligned according
+* to the following hardware limitations:
+*    ppc        - aligned on 32 bit boundaries to avoid performance penalties
+*                 from unaligned exception handling.
+*    microblaze - aligned on 32 bit boundaries as microblaze does not handle
+*                 unaligned transfers.
+*
+* Care must be taken to ensure that the number of words written with one or
+* more calls to XLlFifo_iWrite_Aligned() matches the number of bytes (rounded up
+* to the nearest whole 32 bit word) given in the next call to
+* XLlFifo_iTxSetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address to place the data read.
+*
+* @param    WordCount specifies the number of 32 bit words to read.
+*
+* @return   XLlFifo_iWrite_Aligned always returns XST_SUCCESS. Error handling is
+*           otherwise handled through hardware exceptions and interrupts.
+*
+* @note
+*
+* C Signature: int XLlFifo_iWrite_Aligned(XLlFifo *InstancePtr,
+*                      void *BufPtr, unsigned WordCount);
+*
+******************************************************************************/
+/* static */ int XLlFifo_iWrite_Aligned(XLlFifo *InstancePtr, void *BufPtr,
+			      unsigned WordCount)
+{
+	unsigned WordsRemaining = WordCount;
+	u32 *BufPtrIdx = (u32 *)BufPtr;
+
+	xdbg_printf(XDBG_DEBUG_FIFO_TX,
+		    "XLlFifo_iWrite_Aligned: Inst: %p; Buff: %p; Count: %d\n",
+		    InstancePtr, BufPtr, WordCount);
+	Xil_AssertNonvoid(InstancePtr);
+	Xil_AssertNonvoid(BufPtr);
+	/* assert bufer is 32 bit aligned */
+	Xil_AssertNonvoid(((unsigned)BufPtr & 0x3) == 0x0);
+
+	xdbg_printf(XDBG_DEBUG_FIFO_TX,
+		    "XLlFifo_iWrite_Aligned: WordsRemaining: %d\n",
+		    WordsRemaining);
+	while (WordsRemaining) {
+		XLlFifo_TxPutWord(InstancePtr, *BufPtrIdx);
+		BufPtrIdx++;
+		WordsRemaining--;
+	}
+
+	xdbg_printf(XDBG_DEBUG_FIFO_TX,
+		    "XLlFifo_iWrite_Aligned: returning SUCCESS\n");
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the
+* <i>InstancePtr</i> that references it.
+*
+* @param       InstancePtr is a pointer to the Axi Streaming FIFO instance
+*              to be worked on.
+* @param	CfgPtr references the structure holding the hardware
+*		configuration for the Axi Streaming FIFO core to initialize.
+* @param 	EffectiveAddr is the device base address in the virtual memory
+*		address	space. The caller is responsible for keeping the
+*		address mapping from EffectiveAddr to the device physical base
+*		address unchanged once this function is invoked. Unexpected
+*		errors may occur if the address mapping changes after this
+*		function is called. If address translation is not used,
+*		use Config->BaseAddress for this parameters, passing the
+*		physical address instead.
+*
+* @return   N/A
+*
+******************************************************************************/
+int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
+			XLlFifo_Config *Config, u32 EffectiveAddress)
+{
+	Xil_AssertNonvoid(InstancePtr);
+
+	if(!Config) {
+		return XST_INVALID_PARAM;
+	}
+
+
+	/* Clear instance memory */
+	memset(InstancePtr, 0, sizeof(XLlFifo));
+
+	/*
+	 * We don't care about the physical base address, just copy the
+	 * processor address over it.
+	 */
+	InstancePtr->BaseAddress = EffectiveAddress;
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	InstancePtr->Datainterface = Config->Datainterface;
+	InstancePtr->Axi4BaseAddress = Config->Axi4BaseAddress;
+	if (InstancePtr->Datainterface == 0)
+		InstancePtr->Axi4BaseAddress = EffectiveAddress;
+
+	XLlFifo_TxReset(InstancePtr);
+	XLlFifo_RxReset(InstancePtr);
+
+	/*
+	 * Reset the core and generate the external reset by writing to
+	 * the Local Link/AXI Streaming Reset Register.
+	 */
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET,
+				XLLF_RDFR_RESET_MASK);
+
+	XStrm_RxInitialize(&(InstancePtr->RxStreamer), FIFO_WIDTH_BYTES,
+			(void *)InstancePtr,
+			(XStrm_XferFnType)XLlFifo_iRead_Aligned,
+			(XStrm_GetLenFnType)XLlFifo_iRxGetLen,
+			(XStrm_GetOccupancyFnType)XLlFifo_iRxOccupancy);
+
+	XStrm_TxInitialize(&(InstancePtr->TxStreamer), FIFO_WIDTH_BYTES,
+			(void *)InstancePtr,
+			(XStrm_XferFnType)XLlFifo_iWrite_Aligned,
+			(XStrm_SetLenFnType)XLlFifo_iTxSetLen,
+			(XStrm_GetVacancyFnType)XLlFifo_iTxVacancy);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/*
+*
+* XLlFifo_RxGetWord reads one 32 bit word from the FIFO specified by
+* <i>InstancePtr</i>.
+*
+* XLlFifo_RxGetLen or XLlFifo_iRxGetLen must be called before calling
+* XLlFifo_RxGetWord. Otherwise, the hardware will raise an <i>Over Read
+* Exception</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxGetWord returns the 32 bit word read from the FIFO.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr)
+{
+	if (InstancePtr->Datainterface)
+		return XLlFifo_ReadReg((InstancePtr)->Axi4BaseAddress,
+				XLLF_AXI4_RDFD_OFFSET);
+	else
+		return XLlFifo_ReadReg((InstancePtr)->Axi4BaseAddress,
+				XLLF_RDFD_OFFSET);
+}
+
+/****************************************************************************/
+/*
+*
+* XLlFifo_TxPutWord writes the 32 bit word, <i>Word</i> to the FIFO specified by
+* <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word)
+*
+*****************************************************************************/
+void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word)
+{
+	if (InstancePtr->Datainterface)
+		XLlFifo_WriteReg((InstancePtr)->Axi4BaseAddress,
+					XLLF_AXI4_TDFD_OFFSET, (Word));
+	else
+		XLlFifo_WriteReg((InstancePtr)->Axi4BaseAddress,
+					XLLF_TDFD_OFFSET, (Word));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the
+* <i>InstancePtr</i> that references it.
+*
+* @param    InstancePtr references the memory instance to be associated with
+*           the FIFO device upon initialization.
+*
+* @param    BaseAddress is the processor address used to access the
+*           base address of the Fifo device.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress)
+{
+	Xil_AssertVoid(InstancePtr);
+	Xil_AssertVoid(BaseAddress);
+
+	/* Clear instance memory */
+	memset(InstancePtr, 0, sizeof(XLlFifo));
+
+	/*
+	 * We don't care about the physical base address, just copy the
+	 * processor address over it.
+	 */
+	InstancePtr->BaseAddress = BaseAddress;
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Axi4BaseAddress = BaseAddress;
+
+	XLlFifo_TxReset(InstancePtr);
+	XLlFifo_RxReset(InstancePtr);
+
+	/*
+	 * Reset the core and generate the external reset by writing to
+	 * the Local Link/AXI Streaming Reset Register.
+	 */
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET,
+				XLLF_RDFR_RESET_MASK);
+
+	XStrm_RxInitialize(&(InstancePtr->RxStreamer), FIFO_WIDTH_BYTES,
+			(void *)InstancePtr,
+			(XStrm_XferFnType)XLlFifo_iRead_Aligned,
+			(XStrm_GetLenFnType)XLlFifo_iRxGetLen,
+			(XStrm_GetOccupancyFnType)XLlFifo_iRxOccupancy);
+
+	XStrm_TxInitialize(&(InstancePtr->TxStreamer), FIFO_WIDTH_BYTES,
+			(void *)InstancePtr,
+			(XStrm_XferFnType)XLlFifo_iWrite_Aligned,
+			(XStrm_SetLenFnType)XLlFifo_iTxSetLen,
+			(XStrm_GetVacancyFnType)XLlFifo_iTxVacancy);
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo.h b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo.h
new file mode 100644
index 000000000..0afb38281
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo.h
@@ -0,0 +1,715 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xllfifo.h
+* @addtogroup llfifo_v5_0
+* @{
+* @details
+ *
+ * The Xilinx Dual Channel Fifo driver component. This driver supports the
+ * Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.
+ *
+ * For a full description of the bridge features, please see the HW spec. This
+ * driver supports the following features:
+ *   - Memory mapped access to host interface registers
+ *   - API for polled frame transfers
+ *   - API for interrupt driven frame transfers
+ *   - Virtual memory support
+ *   - Full duplex operation
+ *
+ * <h2>Driver Description</h2>
+ *
+ * This driver enables higher layer software to access the XPS_llFifo core
+ * using any alignment in the data buffers.
+ *
+ * This driver supports send and receive channels in the same instance
+ * structure in the same fashion as the hardware core.
+ *
+ * <h2>Initialization</h2>
+ *
+ * An instance of this driver is initialized using a call to Initialize().
+ *
+ * <h2>Usage</h2>
+ *
+ * It is fairly simple to use the API provided by this FIFO driver. The
+ * only somewhat tricky part is that the calling code must correctly call
+ * a couple routines in the right sequence for receive and transmit.
+ *
+ * This sequence is described here. Check the routine functional
+ * descriptions for information on how to use a specific API routine.
+ *
+ * <h3>Receive</h3>
+ *
+ * A frame is received by using the following sequence:<br>
+ * 1) call XLlFifo_RxOccupancy() to check the occupancy count<br>
+ * 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame<br>
+ * 3) call XLlFifo_Read() one or more times to read the number of bytes
+ *    reported by XLlFifo_RxGetLen().<br>
+ *
+ * For example:
+ * <pre>
+ * 	while (XLlFifo_RxOccupancy(&RxInstance)) {
+ * 		frame_len = XLlFifo_RxGetLen(&RxInstance);
+ *		while (frame_len) {
+ * 			unsigned bytes = min(sizeof(buffer), frame_len);
+ * 			XLlFifo_Read(&RxInstance, buffer, bytes);
+ * 			// ********
+ * 			// do something with buffer here
+ * 			// ********
+ * 			frame_len -= bytes;
+ *		}
+ * 	}
+ * </pre>
+ *
+ * This FIFO hardware core does <b>not</b> support a sequence where the
+ * calling code calls RxGetLen() twice in a row and then receive the data
+ * for two frames. Each frame must be read in by calling RxGetLen() just
+ * prior to reading the data.
+ *
+ * <h3>Transmit</h3>
+ * A frame is transmittted by using the following sequence:<br>
+ * 1) call XLlFifo_Write() one or more times to write all the of bytes in
+ *    the next frame.<br>
+ * 2) call XLlFifo_TxSetLen() to begin the transmission of frame just
+ *    written.<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_left = frame_len;
+ * 	while (frame_left) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_left);
+ * 		XLlFifo_Write(&TxInstance, buffer, bytes);
+ * 		// ********
+ * 		// do something here to refill buffer
+ * 		// ********
+ * 		frame_left -= bytes;
+ * 	}
+ * 	XLlFifo_TxSetLen(&RxInstance, frame_len);
+ * </pre>
+ *
+ * This FIFO hardware core does <b>not</b> support a sequence where the
+ * calling code writes the data for two frames and then calls TxSetLen()
+ * twice in a row. Each frame must be written by writting the data for one
+ * frame and then calling TxSetLen().
+ *
+ * <h2>Interrupts</h2>
+ * This driver does not handle interrupts from the FIFO hardware. The
+ * software layer above may make use of the interrupts by setting up its
+ * own handlers for the interrupts.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/12/06 First release
+ * 1.01a sdm  08/22/08 Removed support for static interrupt handlers from the
+ *		       MDD file
+ * 1.02a jz   12/04/09 Hal phase 1 support
+ * 2.01a asa  09/17/10 Added code for resetting Local Link/AXI Streaming
+ *		       interface for CR574868
+ * 2.02a asa  12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
+ *		       HeadIndex to zero when all bytes have been read.
+ *		       Changed the macro XStrm_IsRxInternalEmpty in file
+ *		       xtreamer.h to use FrmByteCnt instead of HeadIndex.
+ *		       When FrmByteCnt is zero, this means all internal buffers
+ *		       in streamer are empty. Earlier implementation using
+ *		       HeadIndex was not very clear and could give improper
+ *		       results for some cases.
+ *		       Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
+ *		       These changes are done to fix the CR 604650.
+  * 2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+ *		         defines for the new registers, and XLLF_INT_TFPF_MASK,
+ *		         XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+ *		         XLLF_INT_RFPE_MASK for the new version of the
+ *		         AXI4-Stream FIFO core (v2.01a and later)
+ *
+ * 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
+ * 		      In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
+ * 		      In XLlfifo.h file updated XLlfifo structure for
+ * 		      Axi4BaseAddress and for Datainterface type provided
+ *		      polling and interrupt examples. XLlfifo_IsRxDone Macro
+ *		      Is added in the XLlfifo.h file for polledmode exmaple.
+ *		      Added Static initialzation for the driver.
+ *		      XLlFifo_Initialize is still used to make the driver
+ *		      backward compatible.
+ * 4.0   adk  19/12/13 Updated as per the New Tcl API's
+ * 5.0   adk  15/05/15 Updated the register offsets in the AXI4 data path
+ *		       as per latest IP version(v4.1)(CR:860254).
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+#ifndef XLLFIFO_H		/* prevent circular inclusions */
+#define XLLFIFO_H		/* by using preprocessor symbols */
+
+/* force C linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+/* This order needs to be kept this way to avoid xstatus/xil_types conflict */
+#include "xstreamer.h"
+#include "xllfifo_hw.h"
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines a run-time instance of an XLlFifo device.
+ */
+typedef struct XLlFifo {
+	u32 BaseAddress;  /**< BaseAddress is the physical base address of the
+	                   *   device's registers
+	                   */
+
+	u32 IsReady;           /**< IsReady is non-zero if the driver instance
+	                        *   has been initialized.
+	                        */
+
+	u32 Axi4BaseAddress;	/**< BaseAddress if the FIFO Data interface is
+				 *	AXI4 this address should use for FIFO
+				 *	access
+				 */
+	u32 Datainterface;	/**< Data interface of the FIFO. This value is zero
+				 *	if the Datainterface is AXI4-lite.
+				 */
+	XStrm_RxFifoStreamer RxStreamer; /**< RxStreamer is the byte streamer
+	                                  *   instance for the receive channel.
+	                                  */
+	XStrm_TxFifoStreamer TxStreamer; /**< TxStreamer is the byte streamer
+	                                  *   instance for the transmit channel.
+	                                  */
+} XLlFifo;
+
+typedef struct XLlFifo_Config {
+	u32 DeviceId;		/**< Deviceid of the AXI FIFO */
+	u32 BaseAddress;	/**< Base Address of the AXI FIFO */
+	u32 Axi4BaseAddress;    /**< Axi4 interface Base address */
+	u32 Datainterface;	/**< Type of Datainterface */
+}XLlFifo_Config;
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_Reset resets both the Tx and Rx channels and the local link interface
+* the FIFO specified by <i>InstancePtr</i>. XLlFifo_TxReset resets also sends a
+* reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any
+* bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO
+* not yet transmitted.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_Reset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Reset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \
+			XLLF_LLR_RESET_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_Status returns a bit mask of the interrupt status register (ISR)
+* for the FIFO specified by <i>InstancePtr</i>. XLlFifo_Status can be used
+* to query the status of the FIFO without having to have interrupts enabled.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IntStatus returns a bit mask of the status conditions.
+*           The mask will be a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Status(InstancePtr) \
+	 XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntEnable enables the interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
+* set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the interrupts to enable. The mask
+*           can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntEnable(InstancePtr, Mask) \
+{ \
+	u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+			XLLF_IER_OFFSET); \
+	Reg |= ((Mask) & XLLF_INT_ALL_MASK);                    \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+			Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntDisable disables the interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
+* set to 1 in <i>Mask</i>, will be disabled. In other words, XLlFifo_IntDisable
+* uses the "set a bit to clear it" scheme.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the interrupts to disable. The mask
+*           can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntDisable(InstancePtr, Mask) \
+{ \
+	u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+			XLLF_IER_OFFSET); \
+	Reg &= ~((Mask) & XLLF_INT_ALL_MASK);  \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+			Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntPending returns a bit mask of the pending interrupts for the
+* FIFO specified by <i>InstancePtr</i>. Each bit set to 1 in the return value
+* represents a pending interrupt.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IntPending returns a bit mask of the interrupts that are
+*           pending. The mask will be a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_ipie_value;
+extern u32 _xllfifo_ipis_value;
+#define XLlFifo_IntPending(InstancePtr) \
+	(_xllfifo_ipie_value = XLlFifo_ReadReg( \
+		(InstancePtr)->BaseAddress, XLLF_IER_OFFSET),  \
+	_xllfifo_ipis_value = XLlFifo_ReadReg( \
+		(InstancePtr)->BaseAddress, XLLF_ISR_OFFSET),  \
+	(_xllfifo_ipie_value & _xllfifo_ipis_value))
+#else
+#define XLlFifo_IntPending(InstancePtr) \
+	(XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) &  \
+	 XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntClear clears pending interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding pending interrupt for
+* each bit set to 1 in <i>Mask</i>, will be cleared. In other words,
+* XLlFifo_IntClear uses the "set a bit to clear it" scheme.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the pending interrupts to clear. The
+*           mask can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntClear(InstancePtr, Mask) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
+			((Mask) & XLLF_INT_ALL_MASK))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_RxReset resets the receive channel of the FIFO specified by
+* <i>InstancePtr</i>. XLlFifo_RxReset drops any bytes in the FIFO not yet
+* retrieved.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Rx Reset
+* complete (RRC) bit.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_RxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_RxReset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
+			XLLF_RDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified
+* by <i>InstancePtr</i>, is empty.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsRxEmpty returns TRUE when the receive channel of the
+*           FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxEmpty(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
+							? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the receive channel of the FIFO, specified by <i>InstancePtr</i>.
+*
+* The xps_ll_fifo core uses the same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_RxOccupancy will give the value of
+* 1, which means one length value (a reserved fifo location) and no data
+* values.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxOccupancy returns the occupancy count for the specified
+*           packet FIFO.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxOccupancy(InstancePtr) \
+	XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxGetLen notifies the hardware that the program is ready to receive
+* the next frame from the receive channel of the FIFO, specified by
+* <i>InstancePtr</i>.
+*
+* Note that the program must first call XLlFifo_RxGetLen before pulling data
+* out of the receive channel of the FIFO with XLlFifo_Read.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxGetLen returns the number of bytes available in the next
+*           frame.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxGetLen(InstancePtr) \
+	XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Read reads <i>Bytes</i> bytes from the receive channel of the FIFO
+* referenced by <i>InstancePtr</i> to the block of memory, referenced by
+* <i>BufPtr</i>.
+*
+* Care must be taken to ensure that the number of bytes read with one or more
+* calls to XLlFifo_Read() does not exceed the number of bytes available given
+* from the last call to XLlFifo_RxGetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address to place the data read.
+*
+* @param    Bytes specifies the number of bytes to read.
+*
+* @return   N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Read(InstancePtr, BufPtr, Bytes) \
+	XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxReset resets the transmit channel of the FIFO specified by
+* <i>InstancePtr</i>. XLlFifo_TxReset drops any bytes in the FIFO not yet
+* transmitted.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Tx Reset
+* complete (TRC) bit.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_TxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxReset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
+			XLLF_TDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsTxDone returns true if the transmission in the transmit channel
+* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsTxDone
+* works only if the TC bit in the IS register is cleared before sending a
+* frame.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsTxDone returns TRUE when the transmit channel of the
+*           FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsTxDone(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+		XLLF_INT_TC_MASK) \
+		? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxDone returns true if the reception in the receive channel
+* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsRxDone
+* works only if the RC bit in the ISR register is cleared before receiving a
+* frame.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsRxDone returns TRUE when the receive channel of the
+*           FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxDone(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+		XLLF_INT_RC_MASK) \
+		? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxVacancy returns the number of unused 32 bit words available
+* (vacancy) in the send channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_TxVacancy will give the value of
+* FIFO_WIDTH - 1, which means one length value used (a reserved fifo location)
+* and no data values yet present.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_TxVacancy returns the vacancy count in 32-bit words for
+*           the specified FIFO.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxVacancy(InstancePtr) \
+	XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_TxSetLen begins a hardware transfer of <i>Bytes</i> bytes out of the
+* transmit channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Bytes specifies the frame length in bytes.
+*
+* @return   N/A
+*
+* @note
+*
+* C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)
+*
+******************************************************************************/
+#define XLlFifo_TxSetLen(InstancePtr, Bytes) \
+	XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
+* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
+* <i>InstancePtr</i>.
+*
+* Care must be taken to ensure that the number of bytes written with one or
+* more calls to XLlFifo_Write() matches the number of bytes given in the next
+* call to XLlFifo_TxSetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address of data to write.
+*
+* @param    Bytes specifies the number of bytes to write.
+*
+* @return   N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Write(InstancePtr, BufPtr, Bytes) \
+	XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)
+*
+* The TDR stores the destination address corresponding to the packet to  be
+* transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core
+* the following sequence should be followed
+*  - Write the destination address into TDR first,
+*  - Write the packet data to the Transmit Data FIFO next
+*  - Write the length of the packet into the Transmit Length Register.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+* @param    Tdest is the Transmit Destination address to be written to TDR.
+*
+* @return   N/A
+*
+* @note		C Signature:
+*		void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
+*
+******************************************************************************/
+#define XLlFifo_WriteTdr(InstancePtr, Tdest) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
+			  Tdest & 0xF)
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).
+*
+* The RDR contains destination address corresponding to the valid packet that
+* is received. The RDR should only be read when a receive packet is available
+* for processing (the receive occupancy is not zero).
+* Once the RDR is read, the receive packet data should be read from the receive
+* data FIFO before the RDR is read again. The RDR values are stored in the
+* receive data FIFO by the AXI4-Stream FIFO core with the data of each packet.
+* The RDR value for the subsequent packet to be processed is moved to the RDR
+* when the previous RDR value has been read.
+*
+* @param    	InstancePtr references the FIFO on which to operate.
+*
+* @return   	The Receive Destination address  read from the RDR.
+*
+* @note		C Signature:
+*		u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_ReadRdr(InstancePtr) 				\
+	XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+/*
+ * Initialization functions xllfifo.c
+ */
+int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
+			XLlFifo_Config *Config, u32 EffectiveAddress);
+void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress);
+XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId);
+u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr);
+u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr);
+u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr);
+void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes);
+u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr);
+void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XLLFIFO_H  end of preprocessor protection symbols */
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_g.c b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_g.c
new file mode 100644
index 000000000..2b9ffffa8
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_g.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen_g.c
+* @addtogroup llfifo_v5_0
+* @{
+*
+* Provide a template for user to define their own hardware settings.
+*
+* If using XPS, this file will be automatically generated.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a adk 9/10/2013 initial release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xllfifo.h"
+
+/************************** Constant Definitions *****************************/
+
+XLlFifo_Config XLlFifo_ConfigTable[] =
+{
+#if defined(XPAR_XLLFIFO_NUM_INSTANCES) && (XPAR_XLLFIFO_NUM_INSTANCES > 0)
+	{
+		XPAR_AXI_FIFO_MM_S_1_DEVICE_ID,
+		XPAR_AXI_FIFO_MM_S_1_BASEADDR,
+		XPAR_AXI_FIFO_MM_S_1_AXI4_BASEADDR,
+		XPAR_AXI_FIFO_MM_S_1_DATA_INTERFACE_TYPE
+	}
+#endif
+};
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_hw.h b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_hw.h
new file mode 100644
index 000000000..694dd358e
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_hw.h
@@ -0,0 +1,242 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xllfifo_hw.h
+* @addtogroup llfifo_v5_0
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the xps_ll_fifo core.
+* High-level driver functions are defined in xpfifo.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jvb  10/16/06 First release.
+* 1.02a jz   12/04/09  Hal phase 1 support
+* 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+* 2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+*		       defines for the new registers, and XLLF_INT_TFPF_MASK,
+*		       XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+*		       XLLF_INT_RFPE_MASK for the new version of the
+*		       AXI4-Stream FIFO core (v2.01a and later)
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XLLFIFO_HW_H		/* prevent circular inclusions */
+#define XLLFIFO_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xdebug.h"
+#include "xil_io.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit.
+ */
+
+/** @name Registers
+ *  @{
+ */
+#define XLLF_ISR_OFFSET  0x00000000  /**< Interrupt Status */
+#define XLLF_IER_OFFSET  0x00000004  /**< Interrupt Enable */
+
+#define XLLF_TDFR_OFFSET 0x00000008  /**< Transmit Reset */
+#define XLLF_TDFV_OFFSET 0x0000000c  /**< Transmit Vacancy */
+#define XLLF_TDFD_OFFSET 0x00000010  /**< Transmit Data */
+#define XLLF_AXI4_TDFD_OFFSET   0x00000000  /**< Axi4 Transmit Data */
+#define XLLF_TLF_OFFSET  0x00000014  /**< Transmit Length */
+
+#define XLLF_RDFR_OFFSET 0x00000018  /**< Receive Reset */
+#define XLLF_RDFO_OFFSET 0x0000001c  /**< Receive Occupancy */
+#define XLLF_RDFD_OFFSET 0x00000020  /**< Receive Data */
+#define XLLF_AXI4_RDFD_OFFSET 	0x00001000  /**< Axi4 Receive Data */
+#define XLLF_RLF_OFFSET  0x00000024  /**< Receive Length */
+#define XLLF_LLR_OFFSET  0x00000028  /**< Local Link Reset */
+#define XLLF_TDR_OFFSET  0x0000002C  /**< Transmit Destination  */
+#define XLLF_RDR_OFFSET  0x00000030  /**< Receive Destination  */
+
+/*@}*/
+
+/* Register masks. The following constants define bit locations of various
+ * control bits in the registers. Constants are not defined for those registers
+ * that have a single bit field representing all 32 bits. For further
+ * information on the meaning of the various bit masks, refer to the HW spec.
+ */
+
+/** @name Interrupt bits
+ *  These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET
+ *  registers.
+ * @{
+ */
+#define XLLF_INT_RPURE_MASK       0x80000000 /**< Receive under-read */
+#define XLLF_INT_RPORE_MASK       0x40000000 /**< Receive over-read */
+#define XLLF_INT_RPUE_MASK        0x20000000 /**< Receive underrun (empty) */
+#define XLLF_INT_TPOE_MASK        0x10000000 /**< Transmit overrun */
+#define XLLF_INT_TC_MASK          0x08000000 /**< Transmit complete */
+#define XLLF_INT_RC_MASK          0x04000000 /**< Receive complete */
+#define XLLF_INT_TSE_MASK         0x02000000 /**< Transmit length mismatch */
+#define XLLF_INT_TRC_MASK         0x01000000 /**< Transmit reset complete */
+#define XLLF_INT_RRC_MASK         0x00800000 /**< Receive reset complete */
+#define XLLF_INT_TFPF_MASK        0x00400000 /**< Tx FIFO Programmable Full,
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_TFPE_MASK        0x00200000 /**< Tx FIFO Programmable Empty
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_RFPF_MASK        0x00100000 /**< Rx FIFO Programmable Full
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_RFPE_MASK        0x00080000 /**< Rx FIFO Programmable Empty
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_ALL_MASK         0xfff80000 /**< All the ints */
+#define XLLF_INT_ERROR_MASK       0xf2000000 /**< Error status ints */
+#define XLLF_INT_RXERROR_MASK     0xe0000000 /**< Receive Error status ints */
+#define XLLF_INT_TXERROR_MASK     0x12000000 /**< Transmit Error status ints */
+/*@}*/
+
+/** @name Reset register values
+ *  These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET
+ *  reset registers.
+ * @{
+ */
+#define XLLF_RDFR_RESET_MASK        0x000000a5 /**< receive reset value */
+#define XLLF_TDFR_RESET_MASK        0x000000a5 /**< Transmit reset value */
+#define XLLF_LLR_RESET_MASK         0x000000a5 /**< Local Link reset value */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**** debug macros ****/
+#define XLlFifo_reg_name(RegOffset) \
+	(((RegOffset) == XLLF_ISR_OFFSET) ? "ISR": \
+	((RegOffset) == XLLF_IER_OFFSET) ? "IER": \
+	((RegOffset) == XLLF_TDFR_OFFSET) ? "TDFR {tx reset}": \
+	((RegOffset) == XLLF_TDFV_OFFSET) ? "TDFV {tx vacancy}": \
+	((RegOffset) == XLLF_TDFD_OFFSET) ? "TDFD {tx data}": \
+	((RegOffset) == XLLF_TLF_OFFSET) ? "TLF {tx length}": \
+	((RegOffset) == XLLF_RDFR_OFFSET) ? "RDFR {rx reset}": \
+	((RegOffset) == XLLF_RDFO_OFFSET) ? "RDFO {rx occupancy}": \
+	((RegOffset) == XLLF_RDFD_OFFSET) ? "RDFD {rx data}": \
+	((RegOffset) == XLLF_RLF_OFFSET) ? "RLF {rx length}": \
+	"unknown")
+
+#define XLlFifo_print_reg_o(BaseAddress, RegOffset, Value) \
+	 xdbg_printf(XDBG_DEBUG_FIFO_REG, "0x%08x -> %s(0x%08x)\n", (Value), \
+			  XLlFifo_reg_name(RegOffset), \
+			 (RegOffset) + (BaseAddress))
+
+#define XLlFifo_print_reg_i(BaseAddress, RegOffset, Value) \
+	xdbg_printf(XDBG_DEBUG_FIFO_REG, "%s(0x%08x) -> 0x%08x\n", \
+			 XLlFifo_reg_name(RegOffset), \
+			(RegOffset) + (BaseAddress), (Value))
+/**** end debug macros ****/
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_ReadReg returns the value of the register at the offet,
+* <i>RegOffset</i>, from the memory mapped base address, <i>BaseAddress</i>.
+*
+* @param    BaseAddress specifies the base address of the device.
+*
+* @param    RegOffset specifies the offset from BaseAddress.
+*
+* @return   XLlFifo_ReadReg returns the value of the specified register.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_rr_value;
+#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
+	((((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
+		"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
+		(RegOffset)) : 0), \
+	_xllfifo_rr_value = Xil_In32((BaseAddress) + (RegOffset)), \
+	XLlFifo_print_reg_i((BaseAddress), (RegOffset), _xllfifo_rr_value), \
+	_xllfifo_rr_value)
+#else
+#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_WriteReg writes the value, <i>Value</i>, to the register at the
+* offet, <i>RegOffset</i>, from the memory mapped base address,
+* <i>BaseAddress</i>.
+*
+* @param    BaseAddress specifies the base address of the device.
+*
+* @param    RegOffset specifies the offset from BaseAddress.
+*
+* @param    Value is value to write to the register.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)
+*
+*****************************************************************************/
+#ifdef DEBUG
+#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
+	(((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
+		"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
+		(RegOffset)) : 0), \
+	XLlFifo_print_reg_o((BaseAddress), (RegOffset), (Value)), \
+	(Xil_Out32((BaseAddress) + (RegOffset), (Value)))
+#else
+#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
+	((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XLLFIFO_HW_H  end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_sinit.c b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_sinit.c
new file mode 100644
index 000000000..a1f6b0535
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xllfifo_sinit.c
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen_sinit.c
+* @addtogroup llfifo_v5_0
+* @{
+*
+* This file contains static initialzation functionality for Axi Streaming FIFO
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a adk 9/10/2013 initial release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xllfifo.h"
+
+/*****************************************************************************/
+/**
+ * Look up the hardware configuration for a device instance
+ *
+ * @param	DeviceId is the unique device ID of the device to lookup for
+ *
+ * @return
+ *		The configuration structure for the device. If the device ID is
+ *		not found,a NULL pointer is returned.
+ *
+ * @note	None
+ *
+ ******************************************************************************/
+XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId)
+{
+	extern XLlFifo_Config XLlFifo_ConfigTable[];
+	XLlFifo_Config *CfgPtr;
+	u32 Index;
+
+	CfgPtr = NULL;
+
+	for (Index = 0; Index < XPAR_XLLFIFO_NUM_INSTANCES; Index++) {
+		if (XLlFifo_ConfigTable[Index].DeviceId == DeviceId) {
+
+			CfgPtr = &XLlFifo_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xstreamer.c b/thirdparty/xilinx/orig/llfifo_v5_0/src/xstreamer.c
new file mode 100644
index 000000000..ce2e17660
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xstreamer.c
@@ -0,0 +1,516 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*
+* @file xstreamer.c
+* @addtogroup llfifo_v5_0
+* @{
+*
+* See xtreamer.h for a description on how to use this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jvb  10/13/06 First release - based on Robert McGee's streaming packet
+*                     fifo driver.
+* 1.02a jz   12/04/09  Hal phase 1 support
+* 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+* 2.02a asa  12/28/11  The function XStrm_Read is changed to reset HeadIndex
+*		       to zero when all the bytes are read.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstreamer.h"
+#include "xil_assert.h"
+
+/*
+ * Implementation Notes
+ *
+ * --- Receive ---
+ *
+ * The basic algorithm for receiving bytes through this byte streamer copies a
+ * fifo key-hole width chunk from the fifo into a holding buffer and then doles
+ * out the bytes from the holding buffer. In some cases, when the buffer given
+ * happens to already be aligned in memory, this algorithm will bypass the
+ * holding buffer.
+ *
+ * Here is a picture to depict this process:
+ *
+ * Initial state:                 holding buffer
+ *                                +--------------+
+ *                                |   <empty>    |
+ *                                +--------------+
+ *                                               ^
+ *                                               |
+ *                                             index
+ *
+ * during XStrm_Read():
+ * first holding buffer fill:     holding buffer
+ *                                +--------------+
+ *                                |////<full>////|
+ *                                +--------------+
+ *                                ^
+ *                                |
+ *                              index
+ *
+ * first holding buffer read:     holding buffer
+ *                                 read   unread
+ *                                +--------------+
+ *                                |      |///////|
+ *                                +--------------+
+ *                                       ^
+ *                                       |
+ *                                     index
+ *
+ * ...
+ *
+ * last holding buffer read:     holding buffer
+ *                                +--------------+
+ *                                |   <empty>    |
+ *                                +--------------+
+ *                                               ^
+ *                                               |
+ *                                             index
+ *
+ * repeat this process ^^^
+ *
+ *
+ * --- Transmit ---
+ *
+ * The basic algorithm for transmitting bytes through this byte streamer copies
+ * bytes into a holding buffer and then writes the holding buffer into the fifo
+ * when it is full.  In some cases, when the buffer given happens to already be
+ * aligned in memory, this algorithm will bypass the holding buffer.
+ *
+ * Here is a picture to depict this process:
+ *
+ * Initial state:                 holding buffer
+ *                                +--------------+
+ *                                |   <empty>    |
+ *                                +--------------+
+ *                                ^
+ *                                |
+ *                              index
+ *
+ * during XStrm_Write():
+ * first holding buffer write:    holding buffer
+ *                                 writen  empty
+ *                                +--------------+
+ *                                |//////|       |
+ *                                +--------------+
+ *                                       ^
+ *                                       |
+ *                                     index
+ *
+ * ...
+ * last holding buffer write:     holding buffer
+ *                                +--------------+
+ *                                |////<full>////|
+ *                                +--------------+
+ *                                               ^
+ *                                               |
+ *                                             index
+ *
+ * holding buffer flush:          holding buffer
+ *                                +--------------+
+ *                                |   <empty>    |
+ *                                +--------------+
+ *                                ^
+ *                                |
+ *                              index
+ *
+ * repeat this process ^^^
+ */
+
+#ifndef min
+#define min(x, y) (((x) < (y)) ? (x) : (y))
+#endif
+
+xdbg_stmnt(u32 _xstrm_ro_value;)
+xdbg_stmnt(u32 _xstrm_buffered;)
+
+/*****************************************************************************/
+/*
+*
+* XStrm_RxInitialize initializes the XStrm_RxFifoStreamer object referenced by
+* <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the tx streamer on which to operate.
+*
+* @param    FifoWidth specifies the FIFO keyhole size in bytes.
+*
+* @param    FifoInstance references the FIFO driver instance that this streamer
+*           object should use to transfer data into the the actual fifo.
+*
+* @param    ReadFn specifies a routine to use to read data from the actual
+*           FIFO. It is assumed that this read routine will handle only reads
+*           from an aligned buffer. (Otherwise, why are we using this streamer
+*           driver?)
+*
+* @param    GetLenFn specifies a routine to use to initiate a receive on the
+*           actual FIFO.
+*
+* @param    GetOccupancyFn specifies a routine to use to retrieve the occupancy
+*           in the actual FIFO. The true occupancy value needs to come through
+*           this streamer driver becuase it holds some of the bytes.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr, unsigned FifoWidth,
+			void *FifoInstance, XStrm_XferFnType ReadFn,
+			XStrm_GetLenFnType GetLenFn,
+			XStrm_GetOccupancyFnType GetOccupancyFn)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	InstancePtr->HeadIndex = FifoWidth;
+	InstancePtr->FifoWidth = FifoWidth;
+	InstancePtr->FifoInstance = FifoInstance;
+	InstancePtr->ReadFn = ReadFn;
+	InstancePtr->GetLenFn = GetLenFn;
+	InstancePtr->GetOccupancyFn = GetOccupancyFn;
+}
+
+/*****************************************************************************/
+/*
+*
+* XStrm_TxInitialize initializes the XStrm_TxFifoStreamer object referenced by
+* <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the tx streamer on which to operate.
+*
+* @param    FifoWidth specifies the FIFO keyhole size in bytes.
+*
+* @param    FifoInstance references the FIFO driver instance that this streamer
+*           object should use to transfer data into the the actual fifo.
+*
+* @param    WriteFn specifies a routine to use to write data into the actual
+*           FIFO. It is assumed that this write routine will handle only writes
+*           from an aligned buffer. (Otherwise, why are we using this streamer
+*           driver?)
+*
+* @param    SetLenFn specifies a routine to use to initiate a transmit on the
+*           actual FIFO.
+*
+* @param    GetVacancyFn specifies a routine to use to retrieve the vacancy in
+*           the actual FIFO. The true vacancy value needs to come through this
+*           streamer driver becuase it holds some of the bytes.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr, unsigned FifoWidth,
+			void *FifoInstance, XStrm_XferFnType WriteFn,
+			XStrm_SetLenFnType SetLenFn,
+			XStrm_GetVacancyFnType GetVacancyFn)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	InstancePtr->TailIndex = 0;
+	InstancePtr->FifoWidth = FifoWidth;
+	InstancePtr->FifoInstance = FifoInstance;
+	InstancePtr->WriteFn = WriteFn;
+	InstancePtr->SetLenFn = SetLenFn;
+	InstancePtr->GetVacancyFn = GetVacancyFn;
+}
+
+/*****************************************************************************/
+/*
+*
+* XStrm_RxGetLen notifies the hardware that the program is ready to receive the
+* next frame from the receive channel of the FIFO, specified by
+* <i>InstancePtr</i>.
+*
+* Note that the program must first call XStrm_RxGetLen before pulling data
+* out of the receive channel of the FIFO with XStrm_Read.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XStrm_RxGetLen returns the number of bytes available in the next
+*           frame.
+*
+******************************************************************************/
+u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr)
+{
+	u32 len;
+
+	InstancePtr->HeadIndex = InstancePtr->FifoWidth;
+	len = (*InstancePtr->GetLenFn)(InstancePtr->FifoInstance);
+	InstancePtr->FrmByteCnt = len;
+	return len;
+}
+
+/*****************************************************************************/
+/*
+*
+* XStrm_Read reads <i>Bytes</i> bytes from the FIFO specified by
+* <i>InstancePtr</i> to the block of memory, referenced by <i>BufPtr</i>.
+*
+* Care must be taken to ensure that the number of bytes read with one or more
+* calls to XStrm_Read() does not exceed the number of bytes available given
+* from the last call to XStrm_RxGetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address to place the data read.
+*
+* @param    Bytes specifies the number of bytes to read.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr,
+		   unsigned Bytes)
+{
+	u8 *DestPtr = (u8 *) BufPtr;
+	unsigned BytesRemaining = Bytes;
+	unsigned FifoWordsToXfer;
+	unsigned PartialBytes;
+	unsigned i;
+
+	while (BytesRemaining) {
+		xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: BytesRemaining: %d\n", BytesRemaining);
+		/* Case 1: There are bytes in the holding buffer
+		 *
+		 *   1) Read the bytes from the holding buffer to the target buffer.
+		 *   2) Loop back around and handle the rest of the transfer.
+		 */
+		if (InstancePtr->HeadIndex != InstancePtr->FifoWidth) {
+			xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: Case 1: InstancePtr->HeadIndex [%d] != InstancePtr->FifoWidth [%d]\n",
+				    InstancePtr->HeadIndex, InstancePtr->FifoWidth);
+			i = InstancePtr->HeadIndex;
+
+			PartialBytes = min(BytesRemaining,
+				InstancePtr->FifoWidth -
+				InstancePtr->HeadIndex);
+			InstancePtr->HeadIndex += PartialBytes;
+			BytesRemaining -= PartialBytes;
+			InstancePtr->FrmByteCnt -= PartialBytes;
+			while (PartialBytes--) {
+				*DestPtr = InstancePtr->AlignedBuffer.bytes[i];
+				i++;
+				DestPtr++;
+			}
+		}
+		/* Case 2: There are no more bytes in the holding buffer and
+		 *         the target buffer is 32 bit aligned and
+		 *         the number of bytes remaining to transfer is greater
+		 *         than or equal to the fifo width.
+		 *
+		 *   1) We can go fast by reading a long string of fifo words right out
+		 *      of the fifo into the target buffer.
+		 *   2) Loop back around to transfer the last few bytes.
+		 */
+		else if ((((unsigned)DestPtr & 3) == 0) &&
+			 (BytesRemaining >= InstancePtr->FifoWidth)) {
+			xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: Case 2: DestPtr: %p, BytesRemaining: %d, InstancePtr->FifoWidth: %d\n",
+				    DestPtr, BytesRemaining, InstancePtr->FifoWidth);
+			FifoWordsToXfer =
+			    BytesRemaining / InstancePtr->FifoWidth;
+
+			(*(InstancePtr->ReadFn)) (InstancePtr->FifoInstance,
+						DestPtr, FifoWordsToXfer);
+			DestPtr += FifoWordsToXfer * InstancePtr->FifoWidth;
+			BytesRemaining -=
+				FifoWordsToXfer * InstancePtr->FifoWidth;
+			InstancePtr->FrmByteCnt -=
+				FifoWordsToXfer * InstancePtr->FifoWidth;
+		}
+		/* Case 3: There are no more bytes in the holding buffer and
+		 *         the number of bytes remaining to transfer is less than
+		 *         the fifo width or
+		 *         things just don't line up.
+		 *
+		 *   1) Fill the holding buffer.
+		 *   2) Loop back around and handle the rest of the transfer.
+		 */
+		else {
+			xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: Case 3\n");
+			/*
+			 * At the tail end, read one fifo word into the local holding
+			 * buffer and loop back around to take care of the transfer.
+			 */
+			(*InstancePtr->ReadFn) (InstancePtr->FifoInstance,
+						&(InstancePtr->AlignedBuffer.
+						  bytes[0]), 1);
+			InstancePtr->HeadIndex = 0;
+		}
+	}
+	if ((InstancePtr->FrmByteCnt) == 0) {
+		InstancePtr->HeadIndex = 0;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* XStrm_TxSetLen flushes to the FIFO, specified by <i>InstancePtr</i>, any
+* bytes remaining in internal buffers and begins a hardware transfer of data
+* out of the transmit channel of the FIFO. <i>Bytes</i> specifies the number
+* of bytes in the frame to transmit.
+*
+* @param    InstancePtr references the FIFO Streamer on which to operate.
+*
+* @param    Bytes specifies the frame length in bytes.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes)
+{
+	/*
+	 * First flush what's in the holding buffer
+	 */
+	if (InstancePtr->TailIndex != 0) {
+		(*InstancePtr->WriteFn) (InstancePtr->FifoInstance,
+					 &(InstancePtr->AlignedBuffer.bytes[0]),
+					 1);
+		InstancePtr->TailIndex = 0;
+	}
+
+	/*
+	 * Kick off the hw write
+	 */
+	(*(InstancePtr)->SetLenFn) (InstancePtr->FifoInstance, Bytes);
+}
+
+/*****************************************************************************/
+/*
+*
+* XStrm_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
+* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
+* <i>InstancePtr</i>.
+*
+* Care must be taken to ensure that the number of bytes written with one or
+* more calls to XStrm_Write() matches the number of bytes given in the next
+* call to XStrm_TxSetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address of data to write.
+*
+* @param    Bytes specifies the number of bytes to write.
+*
+* @return   N/A
+*
+******************************************************************************/
+void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr,
+		    unsigned Bytes)
+{
+	u8 *SrcPtr = (u8 *) BufPtr;
+	unsigned BytesRemaining = Bytes;
+	unsigned FifoWordsToXfer;
+	unsigned PartialBytes;
+	unsigned i;
+
+	while (BytesRemaining) {
+		xdbg_printf(XDBG_DEBUG_FIFO_TX,
+			    "XStrm_Write: BytesRemaining: %d\n",
+			    BytesRemaining);
+		/* Case 1: The holding buffer is full
+		 *
+		 *   1) Write it to the fifo.
+		 *   2) Fall through to transfer more bytes in this iteration.
+		 */
+		if (InstancePtr->TailIndex == InstancePtr->FifoWidth) {
+			xdbg_printf(XDBG_DEBUG_FIFO_TX,
+				    "XStrm_Write: (case 1) TailIndex: %d; FifoWidth: %d; WriteFn: %p\n",
+				    InstancePtr->TailIndex, InstancePtr->FifoWidth,
+				    InstancePtr->WriteFn);
+			(*InstancePtr->WriteFn) (InstancePtr->FifoInstance,
+						 &(InstancePtr->AlignedBuffer.
+						   bytes[0]), 1);
+			InstancePtr->TailIndex = 0;
+		}
+		/* Case 2: There are no bytes in the holding buffer and
+		 *         the target buffer is 32 bit aligned and
+		 *         the number of bytes remaining to transfer is greater
+		 *         than or equal to the fifo width.
+		 *
+		 *   1) We can go fast by writing a long string of fifo words right out
+		 *      of the source buffer into the fifo.
+		 *   2) Loop back around to transfer the last few bytes.
+		 */
+		if ((InstancePtr->TailIndex == 0) &&
+		    (BytesRemaining >= InstancePtr->FifoWidth) &&
+		    (((unsigned)SrcPtr & 3) == 0)) {
+			FifoWordsToXfer =
+				BytesRemaining / InstancePtr->FifoWidth;
+
+			xdbg_printf(XDBG_DEBUG_FIFO_TX, "XStrm_Write: (case 2) TailIndex: %d; BytesRemaining: %d; FifoWidth: %d; SrcPtr: %p;\n InstancePtr: %p; WriteFn: %p ,\nFifoWordsToXfer: %d (BytesRemaining: %d)\n",
+				    InstancePtr->TailIndex, BytesRemaining,
+				    InstancePtr->FifoWidth, SrcPtr,
+				    InstancePtr, InstancePtr->WriteFn,
+				    FifoWordsToXfer,
+				    BytesRemaining);
+
+			(*InstancePtr->WriteFn) (InstancePtr->FifoInstance,
+						 SrcPtr, FifoWordsToXfer);
+			SrcPtr += FifoWordsToXfer * InstancePtr->FifoWidth;
+			BytesRemaining -=
+				FifoWordsToXfer * InstancePtr->FifoWidth;
+			xdbg_printf(XDBG_DEBUG_FIFO_TX, "XStrm_Write: (end case 2) TailIndex: %d; BytesRemaining: %d; SrcPtr: %p\n",
+				    InstancePtr->TailIndex, BytesRemaining, SrcPtr);
+		}
+		/* Case 3: The alignment of the "galaxies" didn't occur in
+		 *         Case 2 above, so we must pump the bytes through the
+		 *         holding buffer.
+		 *
+		 *   1) Write bytes from the source buffer to the holding buffer
+		 *   2) Loop back around and handle the rest of the transfer.
+		 */
+		else {
+			i = InstancePtr->TailIndex;
+
+			PartialBytes =
+			    min(BytesRemaining,
+				InstancePtr->FifoWidth -
+				InstancePtr->TailIndex);
+			BytesRemaining -= PartialBytes;
+			InstancePtr->TailIndex += PartialBytes;
+			while (PartialBytes--) {
+				xdbg_printf(XDBG_DEBUG_FIFO_TX, "XStrm_Write: (case 3) PartialBytes: %d\n",
+					    PartialBytes);
+				InstancePtr->AlignedBuffer.bytes[i] = *SrcPtr;
+				i++;
+				SrcPtr++;
+			}
+		}
+	}
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/llfifo_v5_0/src/xstreamer.h b/thirdparty/xilinx/orig/llfifo_v5_0/src/xstreamer.h
new file mode 100644
index 000000000..bbb65f0e9
--- /dev/null
+++ b/thirdparty/xilinx/orig/llfifo_v5_0/src/xstreamer.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*
+ *
+ * @file xstreamer.h
+* @addtogroup llfifo_v5_0
+* @{
+ *
+ * The Xilinx byte streamer for packet FIFOs.
+ *
+ * <h2>Driver Description</h2>
+ *
+ * This driver enables higher layer software to access a hardware FIFO using
+ * any alignment in the data buffers while preserving alignment for the hardware
+ * FIFO access.
+ *
+ * This driver treats send and receive channels separately, using different
+ * types of instance objects for each.
+ *
+ * This driver makes use of another FIFO driver to access the specific FIFO
+ * hardware through use of the routines passed into the Tx/RxInitialize
+ * routines.
+ *
+ * <h2>Initialization</h2>
+ *
+ * Send and receive channels are intialized separately. The receive channel is
+ * initiailzed using XStrm_RxInitialize(). The send channel is initialized
+ * using XStrm_TxInitialize().
+ *
+ *
+ * <h2>Usage</h2>
+ * It is fairly simple to use the API provided by this byte streamer
+ * driver. The only somewhat tricky part is that the calling code must
+ * correctly call a couple routines in the right sequence for receive and
+ * transmit.
+ *
+ * 	This sequence is described here. Check the routine functional
+ * descriptions for information on how to use a specific API routine.
+ *
+ * <h3>Receive</h3>
+ * A frame is received by using the following sequence:<br>
+ * 1) call XStrm_RxGetLen() to get the length of the next incoming frame.<br>
+ * 2) call XStrm_Read() one or more times to read the number of bytes
+ * 	   reported by XStrm_RxGetLen().<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_len = XStrm_RxGetLen(&RxInstance);
+ * 	while (frame_len) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_len);
+ * 		XStrm_Read(&RxInstance, buffer, bytes);
+ * 		// do something with buffer here
+ * 		frame_len -= bytes;
+ * 	}
+ * </pre>
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * <h3>Transmit</h3>
+ * A frame is transmittted by using the following sequence:<br>
+ * 1) call XStrm_Write() one or more times to write all the of bytes in
+ *    the next frame.<br>
+ * 2) call XStrm_TxSetLen() to begin the transmission of frame just
+ *    written.<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_left = frame_len;
+ * 	while (frame_left) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_left);
+ * 		XStrm_Write(&TxInstance, buffer, bytes);
+ * 		// do something here to refill buffer
+ * 	}
+ * 	XStrm_TxSetLen(&RxInstance, frame_len);
+ * </pre>
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/12/06 First release
+ * 1.02a jz   12/04/09  Hal phase 1 support
+ * 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+ * 2.02a asa  12/28/11  The macro XStrm_IsRxInternalEmpty is changed to use
+ *			FrmByteCnt instead of HeadIndex.
+ * </pre>
+ *
+ *****************************************************************************/
+#ifndef XSTREAMER_H		/* prevent circular inclusions */
+#define XSTREAMER_H		/* by using preprocessor symbols */
+
+/* force C linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xenv.h"
+#include "xdebug.h"
+#include "xil_types.h"
+
+/*
+ * key hole size in 32 bit words
+ */
+#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS 4
+
+/*
+ * This union is used simply to force a 32bit alignment on the
+ * buffer. Only the 'bytes' member is really used.
+ */
+union XStrm_AlignedBufferType {
+	u32 _words[LARGEST_FIFO_KEYHOLE_SIZE_WORDS];
+	char bytes[LARGEST_FIFO_KEYHOLE_SIZE_WORDS * 4];
+};
+
+typedef int(*XStrm_XferFnType) (void *FifoInstance, void *BufPtr,
+                                    unsigned WordCount);
+typedef u32 (*XStrm_GetLenFnType) (void *FifoInstance);
+typedef void (*XStrm_SetLenFnType) (void *FifoInstance,
+                                    u32 ByteCount);
+typedef u32 (*XStrm_GetOccupancyFnType) (void *FifoInstance);
+typedef u32 (*XStrm_GetVacancyFnType) (void *FifoInstance);
+
+/**
+ * This typedef defines a run-time instance of a receive byte-streamer.
+ */
+typedef struct XStrm_RxFifoStreamer {
+	union XStrm_AlignedBufferType AlignedBuffer;
+	unsigned HeadIndex;  /**< HeadIndex is the index to the AlignedBuffer
+	                      *   as bytes.
+                              */
+	unsigned FifoWidth;  /**< FifoWidth is the FIFO key hole width in bytes.
+	                      */
+	unsigned FrmByteCnt; /**< FrmByteCnt is the number of bytes in the next
+			      *   Frame.
+			      */
+	void *FifoInstance;  /**< FifoInstance is the FIFO driver instance to
+	                      *   pass to ReadFn, GetLenFn, and GetOccupancyFn
+	                      *   routines.
+	                      */
+	XStrm_XferFnType ReadFn;     /**< ReadFn is the routine the streamer
+	                              *   uses to receive bytes from the Fifo.
+	                              */
+	XStrm_GetLenFnType GetLenFn; /**< GetLenFn is the routine the streamer
+	                              *   uses to initiate receive operations
+	                              *   on the FIFO.
+                                      */
+	XStrm_GetOccupancyFnType GetOccupancyFn; /**< GetOccupancyFn is the
+	                                          *   routine the streamer uses
+	                                          *   to get the occupancy from
+	                                          *   the FIFO.
+	                                          */
+} XStrm_RxFifoStreamer;
+
+/**
+ * This typedef defines a run-time instance of a transmit byte-streamer.
+ */
+typedef struct XStrm_TxFifoStreamer {
+	union XStrm_AlignedBufferType AlignedBuffer;
+	unsigned TailIndex; /**< TailIndex is the index to the AlignedBuffer
+	                     *   as bytes
+                             */
+	unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes.
+	                     */
+
+	void *FifoInstance; /**< FifoInstance is the FIFO driver instance to
+	                     *   pass to WriteFn, SetLenFn, and GetVacancyFn
+	                     *   routines.
+	                     */
+	XStrm_XferFnType WriteFn; /**< WriteFn is the routine the streamer
+	                           *   uses to transmit bytes to the Fifo.
+	                           */
+	XStrm_SetLenFnType SetLenFn; /**< SetLenFn is the routine the streamer
+	                              *   uses to initiate transmit operations
+	                              *   on the FIFO.
+                                      */
+	XStrm_GetVacancyFnType GetVacancyFn; /**< GetVaccancyFn is the routine
+	                                      *   the streamer uses to get the
+	                                      *   vacancy from the FIFO.
+	                                      */
+} XStrm_TxFifoStreamer;
+
+/*****************************************************************************/
+/*
+*
+* XStrm_TxVacancy returns the number of unused 32-bit words available (vacancy)
+* between the streamer, specified by <i>InstancePtr</i>, and the FIFO this
+* streamer is using.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_TxVacancy returns the vacancy count in number of 32 bit words.
+*
+* @note
+*
+* C Signature: u32 XStrm_TxVacancy(XStrm_TxFifoStreamer *InstancePtr)
+*
+* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
+* is subtracted from the vacancy value of FIFO this streamer is using. This is
+* to ensure the caller can write the number words given in the return value and
+* not overflow the FIFO.
+*
+******************************************************************************/
+#define XStrm_TxVacancy(InstancePtr) \
+	(((*(InstancePtr)->GetVacancyFn)((InstancePtr)->FifoInstance)) - \
+			(((InstancePtr)->TailIndex + 3) / 4))
+
+/*****************************************************************************/
+/*
+*
+* XStrm_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the streamer, specified by <i>InstancePtr</i>, and FIFO this
+* steamer is using.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_RxOccupancy returns the occupancy count in number of 32 bit
+*           words.
+*
+* @note
+*
+* C Signature: u32 XStrm_RxOccupancy(XStrm_RxFifoStreamer *InstancePtr)
+*
+* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
+* is added to the occupancy value of FIFO this streamer is using. This is to
+* ensure the caller will get a little more accurate occupancy value.
+*
+******************************************************************************/
+#ifdef DEBUG
+extern u32 _xstrm_ro_value;
+extern u32 _xstrm_buffered;
+#define XStrm_RxOccupancy(InstancePtr) \
+        (_xstrm_ro_value = ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "reg: %d; frmbytecnt: %d\n", \
+		_xstrm_ro_value, (InstancePtr)->FrmByteCnt), \
+	(((InstancePtr)->FrmByteCnt) ? \
+		_xstrm_buffered = ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+		0), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered_bytes: %d\n", _xstrm_buffered), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered (rounded): %d\n", _xstrm_buffered), \
+	(_xstrm_ro_value + _xstrm_buffered))
+#else
+#define XStrm_RxOccupancy(InstancePtr) \
+	( \
+	  ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)) + \
+	  ( \
+	    ((InstancePtr)->FrmByteCnt) ? \
+	      ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+	      0 \
+	  ) \
+	)
+#endif
+
+/****************************************************************************/
+/*
+*
+* XStrm_IsRxInternalEmpty returns true if the streamer, specified by
+* <i>InstancePtr</i>, is not holding any bytes in it's  internal buffers. Note
+* that this routine does not reflect information about the state of the
+* FIFO used by this streamer.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_IsRxInternalEmpty returns TRUE when the streamer is not
+*           holding any bytes in it's internal buffers. Otherwise,
+*           XStrm_IsRxInternalEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XStrm_IsRxInternalEmpty(XStrm_RxFifoStreamer *InstancePtr)
+*
+*****************************************************************************/
+#define XStrm_IsRxInternalEmpty(InstancePtr) \
+	(((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE)
+
+void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr,
+                        unsigned FifoWidth, void *FifoInstance,
+                        XStrm_XferFnType ReadFn,
+                        XStrm_GetLenFnType GetLenFn,
+                        XStrm_GetOccupancyFnType GetOccupancyFn);
+
+void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr,
+                        unsigned FifoWidth, void *FifoInstance,
+                        XStrm_XferFnType WriteFn,
+                        XStrm_SetLenFnType SetLenFn,
+                        XStrm_GetVacancyFnType GetVacancyFn);
+
+void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes);
+void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr,
+                    unsigned bytes);
+
+u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr);
+void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr,
+                   unsigned bytes);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XSTREAMER_H  end of preprocessor protection symbols */
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr.mdd b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr.mdd
new file mode 100644
index 000000000..3ab53ff4f
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr.mdd
@@ -0,0 +1,61 @@
+###############################################################################
+#
+# Copyright (C) 2004 - 2015 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- --------------------------------------------------
+# 3.0      adk    10/12/13 Removed support for xps_timer
+# 4.0      als    09/30/15 Updated initialization API.
+##############################################################################
+## @BEGIN_CHANGELOG EDK_M
+##
+##  11/18/2009 ktn Removed support for opb_timer
+##    
+## @END_CHANGELOG
+
+## @BEGIN_CHANGELOG EDK_MS3
+##
+## 06/16/10 sv Added support for axi_timer
+##    
+## @END_CHANGELOG
+
+OPTION psf_version = 2.1;
+
+BEGIN driver tmrctr
+
+  OPTION supported_peripherals = (axi_timer);
+  OPTION driver_state = ACTIVE;
+  OPTION copyfiles = all;
+  OPTION VERSION = 4.0;
+  OPTION NAME = tmrctr;
+
+END driver
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr.tcl b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr.tcl
new file mode 100644
index 000000000..da1afd118
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr.tcl
@@ -0,0 +1,173 @@
+###############################################################################
+#
+# Copyright (C) 2004 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ------------------------------------
+# 3.0      adk    12/10/13 Updated as per the New Tcl API's
+##############################################################################
+
+
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XTmrCtr" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "CLOCK_FREQ_HZ"
+    ::hsi::utils::define_config_file $drv_handle "xtmrctr_g.c" "XTmrCtr"  "DEVICE_ID" "C_BASEADDR" "CLOCK_FREQ_HZ"
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "TmrCtr" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "CLOCK_FREQ_HZ"
+}
+
+#
+# Given a list of arguments, define them all in an include file.
+# Handles mpd and mld parameters, as well as the special parameters NUM_INSTANCES,
+# DEVICE_ID
+#
+proc xdefine_include_file {drv_handle file_name drv_string args} {
+    # Open include file
+    set file_handle [::hsi::utils::open_include_file $file_name]
+
+    # Get all peripherals connected to this driver
+    set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
+
+    # Handle special cases
+    set arg "NUM_INSTANCES"
+    set posn [lsearch -exact $args $arg]
+    if {$posn > -1} {
+        puts $file_handle "/* Definitions for driver [string toupper [common::get_property NAME $drv_handle]] */"
+        # Define NUM_INSTANCES
+        puts $file_handle "#define [::hsi::utils::get_driver_param_name $drv_string $arg] [llength $periphs]"
+        set args [lreplace $args $posn $posn]
+    }
+
+    # Print all parameters for all peripherals
+    set device_id 0
+    foreach periph $periphs {
+        set periph_name [string toupper [common::get_property NAME $periph]]
+        #set freq [xget_freq $periph]
+	set freq [::hsi::utils::get_clk_pin_freq  $periph "S_AXI_ACLK"]
+
+        puts $file_handle ""
+        puts $file_handle "/* Definitions for peripheral $periph_name */"
+        foreach arg $args {
+
+            if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
+                set value $device_id
+                incr device_id
+            } elseif {[string compare -nocase "CLOCK_FREQ_HZ" $arg] == 0} {
+                if {[llength $freq] == 0} {
+                    set freq "100000000"
+                    puts "WARNING: Clock frequency information is not available in the design, \
+                          for peripheral $periph_name. Assuming a default frequency of 100MHz. \
+                          If this is incorrect, the peripheral $periph_name will be non-functional"
+                }
+                set value $freq
+            } else {
+                set value [common::get_property CONFIG.$arg $periph]
+            }
+            if {[llength $value] == 0} {
+                set value 0
+            }
+            set value [::hsi::utils::format_addr_string $value $arg]
+            puts $file_handle "#define [::hsi::utils::get_ip_param_name $periph $arg] $value"
+        }
+        puts $file_handle ""
+    }
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+
+#
+# Given a list of arguments, define each as a canonical constant name, using
+# the driver name, in an include file.
+#
+proc xdefine_canonical_xpars {drv_handle file_name drv_string args} {
+    # Open include file
+    set file_handle [::hsi::utils::open_include_file $file_name]
+
+    # Get all the peripherals connected to this driver
+    set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
+
+    # Get the names of all the peripherals connected to this driver
+    foreach periph $periphs {
+        set peripheral_name [string toupper [common::get_property NAME $periph]]
+        lappend peripherals $peripheral_name
+    }
+
+    # Get possible canonical names for all the peripherals connected to this driver
+    set device_id 0
+    foreach periph $periphs {
+        set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]]
+        lappend canonicals $canonical_name
+        
+        # Create a list of IDs of the peripherals whose hardware instance name
+        # doesn't match the canonical name. These IDs can be used later to
+        # generate canonical definitions
+        if { [lsearch $peripherals $canonical_name] < 0 } {
+            lappend indices $device_id
+        }
+        incr device_id
+    }
+
+    set i 0
+    foreach periph $periphs {
+        set periph_name [string toupper [common::get_property NAME $periph]]
+
+        # Generate canonical definitions only for the peripherals whose
+        # canonical name is not the same as hardware instance name
+        if { [lsearch $canonicals $periph_name] < 0 } {
+            puts $file_handle "/* Canonical definitions for peripheral $periph_name */"
+            set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]]
+
+            foreach arg $args {
+                set lvalue [::hsi::utils::get_driver_param_name $canonical_name $arg]
+
+                #handle CLOCK_FREQ_HZ as a special case
+                if {[string compare -nocase "CLOCK_FREQ_HZ" $arg] == 0} {
+                    set rvalue [::hsi::utils::get_ip_param_name $periph $arg]
+                } else {
+                    set rvalue [common::get_property CONFIG.$arg $periph]
+                    if {[llength $rvalue] == 0} {
+                        set rvalue 0
+                    }
+                    set rvalue [::hsi::utils::format_addr_string $rvalue $arg]
+                }
+
+                puts $file_handle "#define $lvalue $rvalue"
+            }
+
+            incr i
+        }
+    }
+
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_header.h b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_header.h
new file mode 100644
index 000000000..19ca74e1d
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_header.h
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef TMRCTR_HEADER_H		/* prevent circular inclusions */
+#define TMRCTR_HEADER_H		/* by using protection macros */
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+int TmrCtrSelfTestExample(u16 DeviceId, u8 TmrCtrNumber);
+
+#endif
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_intr_header.h b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_intr_header.h
new file mode 100644
index 000000000..b18a5666c
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_intr_header.h
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef TMRCTR_INTR_HEADER_H		/* prevent circular inclusions */
+#define TMRCTR_INTR_HEADER_H		/* by using protection macros */
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+int TmrCtrIntrExample(XIntc* IntcInstancePtr,
+                          XTmrCtr* InstancePtr,
+                          u16 DeviceId,
+                          u16 IntrId,
+                          u8 TmrCtrNumber);
+#else
+int TmrCtrIntrExample(XScuGic* IntcInstancePtr,
+                          XTmrCtr* InstancePtr,
+                          u16 DeviceId,
+                          u16 IntrId,
+                          u8 TmrCtrNumber);
+#endif
+#endif
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_tapp.tcl b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_tapp.tcl
new file mode 100644
index 000000000..0b8008a07
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/data/tmrctr_tapp.tcl
@@ -0,0 +1,236 @@
+###############################################################################
+#
+# Copyright (C) 2004 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ------------------------------------
+# 3.0      adk    12/10/13 Updated as per the New Tcl API's
+##############################################################################
+## @BEGIN_CHANGELOG EDK_I
+##
+##  - include header files
+##
+## @END_CHANGELOG
+
+## @BEGIN_CHANGELOG EDK_H
+##
+##  - Added support for generation of multiple applications.
+##    All TCL procedures are now required to have a software
+##    project type as its first argument
+##    
+## @END_CHANGELOG
+
+# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
+
+# -----------------------------------------------------------------
+# Software Project Types (swproj):
+#   0 : MemoryTest - Calls basic  memorytest routines from common driver dir
+#   1 : PeripheralTest - Calls any existing polled_example and/or selftest
+# -----------------------------------------------------------------
+
+# -----------------------------------------------------------------
+# TCL Procedures:
+# -----------------------------------------------------------------
+
+proc gen_include_files {swproj mhsinst} {
+    if {$swproj == 0} {
+        return ""
+    }
+    if {$swproj == 1} {
+        set iftmrintr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
+        if {$iftmrintr == 1} {
+            set inc_file_lines {xtmrctr.h tmrctr_header.h tmrctr_intr_header.h}
+        } else {
+            set inc_file_lines {xtmrctr.h tmrctr_header.h}
+        }    
+        return $inc_file_lines
+    }
+}
+    
+proc gen_src_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+      set iftmrintr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
+      
+      if {$iftmrintr == 1} {
+          set inc_file_lines {examples/xtmrctr_selftest_example.c examples/xtmrctr_intr_example.c data/tmrctr_header.h data/tmrctr_intr_header.h}
+      } else {
+          set inc_file_lines {examples/xtmrctr_selftest_example.c data/tmrctr_header.h}
+      }
+      return $inc_file_lines
+  }
+}
+
+proc gen_testfunc_def {swproj mhsinst} {
+  return ""
+}
+
+proc gen_init_code {swproj mhsinst} {
+    
+    if {$swproj == 0} {
+        return ""
+    }
+    if {$swproj == 1} {
+        
+      set ipname [common::get_property NAME $mhsinst]
+      set iftmrintr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
+      if {$iftmrintr == 1} {
+          set decl "   static XTmrCtr ${ipname}_Timer;"
+          set inc_file_lines $decl
+          return $inc_file_lines
+      } else {
+          return ""
+      }
+  }
+    
+}
+
+proc gen_testfunc_call {swproj mhsinst} {
+    
+    if {$swproj == 0} {
+        return ""
+    }
+
+    set iftmrintr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
+    set ipname [common::get_property NAME  $mhsinst]
+    set deviceid [::hsi::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
+    set stdout [common::get_property CONFIG.STDOUT [hsi::get_os]]
+    if { $stdout == "" || $stdout == "none" } {
+	set hasStdout 0
+    } else {
+       set hasStdout 1
+    }
+    
+    if {$iftmrintr == 1} {
+       set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname]  -filter "TYPE==INTERRUPT"]
+       set intcname [::hsi::utils::get_connected_intr_cntrl $ipname  $intr_pin_name]
+       set intcvar intc
+       set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
+    }
+    
+    set testfunc_call ""
+
+  if {${hasStdout} == 0} {
+
+      append testfunc_call "
+
+   {
+      int status;
+                        
+      status = TmrCtrSelfTestExample(${deviceid}, 0x0);
+
+   }"
+  
+
+  if {$iftmrintr == 1} {
+	if {
+           $proc == "microblaze"
+	} then {
+		set intr_id "XPAR_${intcname}_${ipname}_${intr_pin_name}_INTR"
+	} else {
+		set intr_id "XPAR_FABRIC_${ipname}_${intr_pin_name}_INTR"
+	}
+	set intr_id [string toupper $intr_id]
+	
+      append testfunc_call "
+        
+   {
+      int Status;
+      Status = TmrCtrIntrExample(&${intcvar}, &${ipname}_Timer, \\
+                                 ${deviceid}, \\
+                                 ${intr_id}, 0);
+   }"
+
+	}
+
+
+  } else {
+
+      append testfunc_call "
+
+   {
+      int status;
+      
+      print(\"\\r\\n Running TmrCtrSelfTestExample() for ${ipname}...\\r\\n\");
+      
+      status = TmrCtrSelfTestExample(${deviceid}, 0x0);
+      
+      if (status == 0) {
+         print(\"TmrCtrSelfTestExample PASSED\\r\\n\");
+      }
+      else {
+         print(\"TmrCtrSelfTestExample FAILED\\r\\n\");
+      }
+   }"
+
+
+  if {$iftmrintr == 1} {
+	if {
+           $proc == "microblaze"
+	} then {
+		set intr_id "XPAR_${intcname}_${ipname}_${intr_pin_name}_INTR"
+	} else {
+		set intr_id "XPAR_FABRIC_${ipname}_${intr_pin_name}_INTR"
+	}
+	set intr_id [string toupper $intr_id]
+	
+      append testfunc_call "
+   {
+      int Status;
+
+      print(\"\\r\\n Running Interrupt Test  for ${ipname}...\\r\\n\");
+      
+      Status = TmrCtrIntrExample(&${intcvar}, &${ipname}_Timer, \\
+                                 ${deviceid}, \\
+                                 ${intr_id}, 0);
+	
+      if (Status == 0) {
+         print(\"Timer Interrupt Test PASSED\\r\\n\");
+      } 
+      else {
+         print(\"Timer Interrupt Test FAILED\\r\\n\");
+      }
+
+   }"
+
+    }
+
+
+  }
+
+  return $testfunc_call
+}
+
+
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/HTML_custom.css b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/HTML_custom.css
new file mode 100644
index 000000000..26defe1a8
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/HTML_custom.css
@@ -0,0 +1,1430 @@
+/* The standard CSS for doxygen 1.8.5 */
+
+body{
+	background: none repeat scroll 0 0 #FFFFFF;
+	color: #51626F;
+	font-family: arial,sans-serif !important;
+    	font-size: 75% !important;
+    	font-weight: normal !important;
+    	margin-left: 10px;
+		font: 400 12px/15px arial,sans-serif;
+}
+.contents, .textblock {
+font: 400 12px/15px arial,sans-serif;
+}
+.textblock ul, .contents ul{ 
+	margin: 5px 0;
+	padding: 0;
+}
+.textblockol {
+	margin:5px 15px; 
+	padding:0;
+	list-style-image: none; 
+}
+.textblock li, .contents li {
+	margin: 0 0 2px 15px;
+    	padding: 0 0 2px 2px;
+}
+
+/* For hiding RHS TOC 
+.toc{
+display:none;
+}*/
+/* For hiding RHS TOC*/ 
+
+For hiding Nav Bar
+.navpath, #nav-path{
+display:none;
+}
+/* For hiding Nav Bar*/
+/* For hiding extra navrows */
+#navrow2, #navrow3, #navrow4, #navrow5 {
+display:none;
+}
+/* @group Heading Levels */
+
+.title {
+	font: 400 14px/28px arial,sans-serif;
+	font-size: 150%;
+	font-weight: bold;
+	margin: 9px 2px;
+	text-align: left;
+}
+
+h2, h3 {
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+    text-indent: 0 !important;
+}
+h4, h5{
+    color: #E66A08 !important;
+    font-size: 1.2em !important;
+    line-height: 1.2em !important;
+}
+h5{
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+h6{
+    color: #E66A08 !important;
+    font-size: 1.0em !important;
+    line-height: 1.0em !important;
+}
+p {
+    padding-bottom: 0px !important;
+	font: 400 12px/15px arial,sans-serif;
+}
+li p {
+    padding-bottom: 0px !important;
+	margin: 0px;
+}
+
+h1, h2.groupheader {
+    clear: both !important;
+    color: #627178 !important;
+    font-size: 1.4em !important;
+    font-weight: bold !important;
+    line-height: 28px !important;
+    margin-top: 0.6em !important;
+}
+
+h1, h2, h3, h4, h5, h6 {
+	-webkit-transition: text-shadow 0.5s linear;
+	-moz-transition: text-shadow 0.5s linear;
+	-ms-transition: text-shadow 0.5s linear;
+	-o-transition: text-shadow 0.5s linear;
+	transition: text-shadow 0.5s linear;
+	margin-right: 15px;
+}
+
+h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {
+	text-shadow: 0 0 15px cyan;
+}
+
+dt {
+	font-weight: bold;
+}
+
+
+/*Hiding Tabs - Tushar
+div.tabs 
+{ 
+    visibility: hidden; 
+} */
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #017bba;
+	font-weight: normal;
+	text-decoration: none;
+	/*font: 400 12px/15px;*/
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code, a.code:visited, a.line, a.line:visited {
+	color: #4665A2;
+}
+
+a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {
+	color: #4665A2; 
+	/*font: 400 12px/15px;*/
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+pre.fragment {
+        border: 0px solid #C4CFE5;
+        background-color: #FFFFFF;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        font-size:  9pt;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 105%;
+}
+
+div.fragment {
+        padding: 0px;
+        margin: 0px;
+	background-color: #FFFFFF;
+	border: 0px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 13px;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+div.line.glow {
+	background-color: cyan;
+	box-shadow: 0 0 10px cyan;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #51626F
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: cyan;
+	box-shadow: 0 0 15px cyan;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
+        border-bottom: 1px solid #DEE4F0;
+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+	font-size: 80%;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+        -webkit-transition: box-shadow 0.5s linear;
+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
+        display: table !important;
+        width: 100%;
+}
+
+.memitem.glow {
+         box-shadow: 0 0 15px cyan;
+}
+
+.memname {
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memname td {
+	vertical-align: bottom;
+}
+
+.memproto, dl.reflist dt {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #E66A08 !important;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 4px;
+        border-top-left-radius: 4px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+.memdoc, dl.reflist dd {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 6px 10px 2px 10px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        background-image:url('nav_g.png');
+        background-repeat:repeat-x;
+        background-color: #FFFFFF;
+        /* opera specific markup */
+        border-bottom-left-radius: 4px;
+        border-bottom-right-radius: 4px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 4px;
+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 4px;
+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
+        margin: 0px 0px 10px 0px;
+        padding: 5px;
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+.paramname code {
+        line-height: 14px;
+}
+
+.params, .retval, .exception, .tparams {
+        margin-left: 0px;
+        padding-left: 0px;
+		font: 400 12px/15px arial,sans-serif;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+table.mlabels {
+	border-spacing: 0px;
+}
+
+td.mlabels-left {
+	width: 100%;
+	padding: 0px;
+}
+
+td.mlabels-right {
+	vertical-align: bottom;
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+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+<div class="title">Data Structures</div>  </div>
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+<div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icona"><span class="icon">C</span></span><a class="el" href="struct_x_tmr_ctr.html" target="_self">XTmrCtr</a></td><td class="desc">The <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> driver instance data </td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icona"><span class="icon">C</span></span><a class="el" href="struct_x_tmr_ctr___config.html" target="_self">XTmrCtr_Config</a></td><td class="desc">This typedef contains configuration information for the device </td></tr>
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+<title>tmrctr_v4_0: Data Structure Index</title>
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+<script type="text/javascript" src="dynsections.js"></script>
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+      <li><a href="globals.html"><span>APIs</span></a></li>
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+  <div id="navrow2" class="tabs2">
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">Data Structure Index</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="qindex"><a class="qindex" href="#letter_X">X</a></div>
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+<tr><td></td><td></td><td></td></tr>
+<tr><td valign="top"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a>&#160;&#160;&#160;</td><td></td><td></td><td></td></tr>
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+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+<title>tmrctr_v4_0: File List</title>
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+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
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+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
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+      <li><a href="globals.html"><span>APIs</span></a></li>
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+    </ul>
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+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">File List</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xtmrctr_8c.html" target="_self">xtmrctr.c</a></td><td class="desc"></td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xtmrctr_8h.html" target="_self">xtmrctr.h</a></td><td class="desc"></td></tr>
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+<tr id="row_8_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xtmrctr__selftest_8c.html" target="_self">xtmrctr_selftest.c</a></td><td class="desc"></td></tr>
+<tr id="row_9_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xtmrctr__sinit_8c.html" target="_self">xtmrctr_sinit.c</a></td><td class="desc"></td></tr>
+<tr id="row_10_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xtmrctr__stats_8c.html" target="_self">xtmrctr_stats.c</a></td><td class="desc"></td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/functions.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/functions.html
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--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/functions.html
@@ -0,0 +1,97 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="functions.html"><span>All</span></a></li>
+      <li><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div><ul>
+<li>BaseAddress
+: <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr</a>
+, <a class="el" href="struct_x_tmr_ctr___config.html#a3dfdf86126f37e26d966dda7c8317dcd">XTmrCtr_Config</a>
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+<li>CallBackRef
+: <a class="el" href="struct_x_tmr_ctr.html#a19b7b38862e322c61d95f0f71f325f13">XTmrCtr</a>
+</li>
+<li>Config
+: <a class="el" href="struct_x_tmr_ctr.html#a1fc51ca5db0c37e2b9b8db794f8a7496">XTmrCtr</a>
+</li>
+<li>DeviceId
+: <a class="el" href="struct_x_tmr_ctr___config.html#a2720753d361a041bea550a352730cec6">XTmrCtr_Config</a>
+</li>
+<li>Handler
+: <a class="el" href="struct_x_tmr_ctr.html#a5cc0b10723d9bad1b654dab33ae56c23">XTmrCtr</a>
+</li>
+<li>Interrupts
+: <a class="el" href="struct_x_tmr_ctr_stats.html#a3e3996ef053ba44bc8720616f3f4c397">XTmrCtrStats</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr</a>
+</li>
+<li>IsStartedTmrCtr0
+: <a class="el" href="struct_x_tmr_ctr.html#aa273d27a5f60d8b003eb83247aca3341">XTmrCtr</a>
+</li>
+<li>IsStartedTmrCtr1
+: <a class="el" href="struct_x_tmr_ctr.html#adcc945170ebc1ae68a01ba548ad60b0d">XTmrCtr</a>
+</li>
+<li>Stats
+: <a class="el" href="struct_x_tmr_ctr.html#ad5cd023157ffa3ef8881bc88ae6ea26b">XTmrCtr</a>
+</li>
+<li>SysClockFreqHz
+: <a class="el" href="struct_x_tmr_ctr___config.html#a8841b74af7282d4328dafd915b277b10">XTmrCtr_Config</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/functions_vars.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/functions_vars.html
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+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: Data Fields - Variables</title>
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+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>BaseAddress
+: <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr</a>
+, <a class="el" href="struct_x_tmr_ctr___config.html#a3dfdf86126f37e26d966dda7c8317dcd">XTmrCtr_Config</a>
+</li>
+<li>CallBackRef
+: <a class="el" href="struct_x_tmr_ctr.html#a19b7b38862e322c61d95f0f71f325f13">XTmrCtr</a>
+</li>
+<li>Config
+: <a class="el" href="struct_x_tmr_ctr.html#a1fc51ca5db0c37e2b9b8db794f8a7496">XTmrCtr</a>
+</li>
+<li>DeviceId
+: <a class="el" href="struct_x_tmr_ctr___config.html#a2720753d361a041bea550a352730cec6">XTmrCtr_Config</a>
+</li>
+<li>Handler
+: <a class="el" href="struct_x_tmr_ctr.html#a5cc0b10723d9bad1b654dab33ae56c23">XTmrCtr</a>
+</li>
+<li>Interrupts
+: <a class="el" href="struct_x_tmr_ctr_stats.html#a3e3996ef053ba44bc8720616f3f4c397">XTmrCtrStats</a>
+</li>
+<li>IsReady
+: <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr</a>
+</li>
+<li>IsStartedTmrCtr0
+: <a class="el" href="struct_x_tmr_ctr.html#aa273d27a5f60d8b003eb83247aca3341">XTmrCtr</a>
+</li>
+<li>IsStartedTmrCtr1
+: <a class="el" href="struct_x_tmr_ctr.html#adcc945170ebc1ae68a01ba548ad60b0d">XTmrCtr</a>
+</li>
+<li>Stats
+: <a class="el" href="struct_x_tmr_ctr.html#ad5cd023157ffa3ef8881bc88ae6ea26b">XTmrCtr</a>
+</li>
+<li>SysClockFreqHz
+: <a class="el" href="struct_x_tmr_ctr___config.html#a8841b74af7282d4328dafd915b277b10">XTmrCtr_Config</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals.html
new file mode 100644
index 000000000..df2e9254e
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals.html
@@ -0,0 +1,218 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XTC_CASCADE_MODE_OPTION
+: <a class="el" href="group__tmrctr__v4__0.html#ga4fb085742ee50628791c81ff9a14bc2c">xtmrctr.h</a>
+</li>
+<li>XTC_CSR_AUTO_RELOAD_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gab06d844c7a245c7be88a63f3559bbd46">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_CAPTURE_MODE_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa0563f5483d9fef6126df6b2e447da08">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_CASC_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaaf3300005339d29c2ee9a79e6bb81959">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_DOWN_COUNT_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga6b40b30b1d1d5b07f4101a5b657dddba">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_ALL_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gabfaa1357c7843a1a72c740b017061a38">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_INT_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_PWM_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa6304f96140472ea199517984b5a18d5">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_TMR_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_EXT_CAPTURE_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gadcf0bfbbe0244d0fc208c783858a9c5c">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_EXT_GENERATE_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga2345d81184385344ae236b8aa99f2423">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_INT_OCCURED_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_LOAD_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">xtmrctr_l.h</a>
+</li>
+<li>XTC_DEVICE_TIMER_COUNT
+: <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">xtmrctr_l.h</a>
+</li>
+<li>XTC_TCR_OFFSET
+: <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">xtmrctr_l.h</a>
+</li>
+<li>XTC_TCSR_OFFSET
+: <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">xtmrctr_l.h</a>
+</li>
+<li>XTC_TLR_OFFSET
+: <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_CfgInitialize()
+: <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_ClearStats()
+: <a class="el" href="group__tmrctr__v4__0.html#ga6f51d8030e9d1a4edc588b0846e22e49">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_ConfigTable
+: <a class="el" href="group__tmrctr__v4__0.html#gab696b83980f59544e04b19249734883d">xtmrctr_g.c</a>
+, <a class="el" href="group__tmrctr__v4__0.html#ga5ce980ccbed0b805d08e295f71dbade7">xtmrctr_sinit.c</a>
+</li>
+<li>XTmrCtr_Disable
+: <a class="el" href="group__tmrctr__v4__0.html#gae5874bbf23d48004ab15acd250a34688">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_DisableIntr
+: <a class="el" href="group__tmrctr__v4__0.html#ga5c712d9f0122fd56355fec99a9c8c1c3">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_Enable
+: <a class="el" href="group__tmrctr__v4__0.html#gaf312964acd6f01aeed63981877c63e8e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_EnableIntr
+: <a class="el" href="group__tmrctr__v4__0.html#gaee205a5d80c200eb12b99b2d99837891">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetCaptureValue()
+: <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_GetControlStatusReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga45ca70c55615831432d0a2b32e0e77af">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetLoadReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga248be00d1ff730871bf8201143dc1480">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetOptions()
+: <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_GetStats()
+: <a class="el" href="group__tmrctr__v4__0.html#ga3c99744f99aef2a019616e712206f1b0">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_GetTimerCounterReg
+: <a class="el" href="group__tmrctr__v4__0.html#gaa6ab051d2011676e6cc3ea8fbc4ec6da">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetValue()
+: <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Handler
+: <a class="el" href="group__tmrctr__v4__0.html#ga60d20c9562b95591c9d6000b21747135">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_HasEventOccurred
+: <a class="el" href="group__tmrctr__v4__0.html#gac6bbcadfe43a528d4d895650bee25a4e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_InitHw()
+: <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Initialize()
+: <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_InterruptHandler()
+: <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_IsExpired()
+: <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_LoadTimerCounterReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga433680f98acc79f69d227a041f20ecb9">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_LookupConfig()
+: <a class="el" href="group__tmrctr__v4__0.html#ga59bced86622b77630d18e731fbcec7f5">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_ReadReg
+: <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_Reset()
+: <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_SelfTest()
+: <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_SetControlStatusReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga74c246c9f5ac5fb8793f0f792bc8fa0e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_SetHandler()
+: <a class="el" href="group__tmrctr__v4__0.html#ga9eb7b372c13b5e3493fec7370858309f">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_SetLoadReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga66eee1751bc9d207eef8143492669c96">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_SetOptions()
+: <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_SetResetValue()
+: <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Start()
+: <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Stop()
+: <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_WriteReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">xtmrctr_l.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_defs.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_defs.html
new file mode 100644
index 000000000..979510007
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_defs.html
@@ -0,0 +1,150 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XTC_CASCADE_MODE_OPTION
+: <a class="el" href="group__tmrctr__v4__0.html#ga4fb085742ee50628791c81ff9a14bc2c">xtmrctr.h</a>
+</li>
+<li>XTC_CSR_AUTO_RELOAD_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gab06d844c7a245c7be88a63f3559bbd46">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_CAPTURE_MODE_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa0563f5483d9fef6126df6b2e447da08">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_CASC_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaaf3300005339d29c2ee9a79e6bb81959">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_DOWN_COUNT_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga6b40b30b1d1d5b07f4101a5b657dddba">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_ALL_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gabfaa1357c7843a1a72c740b017061a38">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_INT_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_PWM_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa6304f96140472ea199517984b5a18d5">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_ENABLE_TMR_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_EXT_CAPTURE_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gadcf0bfbbe0244d0fc208c783858a9c5c">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_EXT_GENERATE_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga2345d81184385344ae236b8aa99f2423">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_INT_OCCURED_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">xtmrctr_l.h</a>
+</li>
+<li>XTC_CSR_LOAD_MASK
+: <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">xtmrctr_l.h</a>
+</li>
+<li>XTC_DEVICE_TIMER_COUNT
+: <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">xtmrctr_l.h</a>
+</li>
+<li>XTC_TCR_OFFSET
+: <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">xtmrctr_l.h</a>
+</li>
+<li>XTC_TCSR_OFFSET
+: <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">xtmrctr_l.h</a>
+</li>
+<li>XTC_TLR_OFFSET
+: <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_Disable
+: <a class="el" href="group__tmrctr__v4__0.html#gae5874bbf23d48004ab15acd250a34688">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_DisableIntr
+: <a class="el" href="group__tmrctr__v4__0.html#ga5c712d9f0122fd56355fec99a9c8c1c3">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_Enable
+: <a class="el" href="group__tmrctr__v4__0.html#gaf312964acd6f01aeed63981877c63e8e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_EnableIntr
+: <a class="el" href="group__tmrctr__v4__0.html#gaee205a5d80c200eb12b99b2d99837891">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetControlStatusReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga45ca70c55615831432d0a2b32e0e77af">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetLoadReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga248be00d1ff730871bf8201143dc1480">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_GetTimerCounterReg
+: <a class="el" href="group__tmrctr__v4__0.html#gaa6ab051d2011676e6cc3ea8fbc4ec6da">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_HasEventOccurred
+: <a class="el" href="group__tmrctr__v4__0.html#gac6bbcadfe43a528d4d895650bee25a4e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_LoadTimerCounterReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga433680f98acc79f69d227a041f20ecb9">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_ReadReg
+: <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_SetControlStatusReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga74c246c9f5ac5fb8793f0f792bc8fa0e">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_SetLoadReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga66eee1751bc9d207eef8143492669c96">xtmrctr_l.h</a>
+</li>
+<li>XTmrCtr_WriteReg
+: <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">xtmrctr_l.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_func.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_func.html
new file mode 100644
index 000000000..ff98b72ea
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_func.html
@@ -0,0 +1,114 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XTmrCtr_CfgInitialize()
+: <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_ClearStats()
+: <a class="el" href="group__tmrctr__v4__0.html#ga6f51d8030e9d1a4edc588b0846e22e49">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_GetCaptureValue()
+: <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_GetOptions()
+: <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_GetStats()
+: <a class="el" href="group__tmrctr__v4__0.html#ga3c99744f99aef2a019616e712206f1b0">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_GetValue()
+: <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_InitHw()
+: <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Initialize()
+: <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_InterruptHandler()
+: <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_IsExpired()
+: <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_LookupConfig()
+: <a class="el" href="group__tmrctr__v4__0.html#ga59bced86622b77630d18e731fbcec7f5">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_Reset()
+: <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_SelfTest()
+: <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_SetHandler()
+: <a class="el" href="group__tmrctr__v4__0.html#ga9eb7b372c13b5e3493fec7370858309f">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_SetOptions()
+: <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">xtmrctr.h</a>
+</li>
+<li>XTmrCtr_SetResetValue()
+: <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Start()
+: <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">xtmrctr.c</a>
+</li>
+<li>XTmrCtr_Stop()
+: <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">xtmrctr.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_type.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_type.html
new file mode 100644
index 000000000..39a2bda56
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_type.html
@@ -0,0 +1,63 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XTmrCtr_Handler
+: <a class="el" href="group__tmrctr__v4__0.html#ga60d20c9562b95591c9d6000b21747135">xtmrctr.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_vars.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_vars.html
new file mode 100644
index 000000000..572e85aee
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/globals_vars.html
@@ -0,0 +1,64 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li class="current"><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XTmrCtr_ConfigTable
+: <a class="el" href="group__tmrctr__v4__0.html#gab696b83980f59544e04b19249734883d">xtmrctr_g.c</a>
+, <a class="el" href="group__tmrctr__v4__0.html#ga5ce980ccbed0b805d08e295f71dbade7">xtmrctr_sinit.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/group__tmrctr__v3__0.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/group__tmrctr__v3__0.html
new file mode 100644
index 000000000..d67fab1bf
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/group__tmrctr__v3__0.html
@@ -0,0 +1,53 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: Tmrctr_v3_0</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">Tmrctr_v3_0</div>  </div>
+</div><!--header-->
+<div class="contents">
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/group__tmrctr__v4__0.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/group__tmrctr__v4__0.html
new file mode 100644
index 000000000..7509b00cc
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/group__tmrctr__v4__0.html
@@ -0,0 +1,1909 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: Tmrctr_v4_0</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
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+ </tbody>
+</table>
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
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+    </ul>
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+<div class="header">
+  <div class="summary">
+<a href="#nested-classes">Data Structures</a> &#124;
+<a href="#define-members">Macros</a> &#124;
+<a href="#typedef-members">Typedefs</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Tmrctr_v4_0</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr_stats.html">XTmrCtrStats</a></td></tr>
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+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>&#160;&#160;&#160;2</td></tr>
+<tr class="separator:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaea427162ce7e92fd08afb7ee1cc1c12e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>(BaseAddress,  TmrCtrNumber,  RegOffset)</td></tr>
+<tr class="separator:gaea427162ce7e92fd08afb7ee1cc1c12e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga56d9c2d54afce39c3693356e3892547f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>(BaseAddress,  TmrCtrNumber,  RegOffset,  ValueToWrite)</td></tr>
+<tr class="separator:ga56d9c2d54afce39c3693356e3892547f"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga74c246c9f5ac5fb8793f0f792bc8fa0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga74c246c9f5ac5fb8793f0f792bc8fa0e">XTmrCtr_SetControlStatusReg</a>(BaseAddress,  TmrCtrNumber,  RegisterValue)</td></tr>
+<tr class="separator:ga74c246c9f5ac5fb8793f0f792bc8fa0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga45ca70c55615831432d0a2b32e0e77af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga45ca70c55615831432d0a2b32e0e77af">XTmrCtr_GetControlStatusReg</a>(BaseAddress,  TmrCtrNumber)&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>)</td></tr>
+<tr class="separator:ga45ca70c55615831432d0a2b32e0e77af"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa6ab051d2011676e6cc3ea8fbc4ec6da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa6ab051d2011676e6cc3ea8fbc4ec6da">XTmrCtr_GetTimerCounterReg</a>(BaseAddress,  TmrCtrNumber)&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>) \</td></tr>
+<tr class="separator:gaa6ab051d2011676e6cc3ea8fbc4ec6da"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gae5874bbf23d48004ab15acd250a34688"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga433680f98acc79f69d227a041f20ecb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gac6bbcadfe43a528d4d895650bee25a4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:ga60d20c9562b95591c9d6000b21747135"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga60d20c9562b95591c9d6000b21747135">XTmrCtr_Handler</a>) (void *CallBackRef, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga60d20c9562b95591c9d6000b21747135"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga5186828a046cd32bbf69874524e983d2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, <a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
+<tr class="separator:ga5186828a046cd32bbf69874524e983d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac3ffcfef4ba4507d5f2b9e17a08c7bf0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr)</td></tr>
+<tr class="separator:gac3ffcfef4ba4507d5f2b9e17a08c7bf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gad5f9b6172f448d2dd13d1c200ca37928"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga009c17ab4fcedf73279638dd97b6edd4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga009c17ab4fcedf73279638dd97b6edd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gab8156ff2a16b8efc0fcd3ed2b7ecf91a"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga325269055bb6f9f7a0c7f703bd2f2174"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga74b790866611a3ab1e96700feb48f6ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gad8f339bdf71ed11fa92f08720c9ce663"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaa7b4ca5a0ac2199ee5341fddd8056500"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga44d19561a31682753e4996c7b57d6982"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga59bced86622b77630d18e731fbcec7f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga2c00e99b19f58b5821c5541069ffb20b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Configuration options</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp50f33d14f129e4548c1c270fd6725a78"></a>These options are used in <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76" title="Enables the specified options for the specified timer counter. ">XTmrCtr_SetOptions()</a> and <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b" title="Get the options for the specified timer counter. ">XTmrCtr_GetOptions()</a> </p>
+</td></tr>
+<tr class="memitem:ga4fb085742ee50628791c81ff9a14bc2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga4fb085742ee50628791c81ff9a14bc2c">XTC_CASCADE_MODE_OPTION</a>&#160;&#160;&#160;0x00000080UL</td></tr>
+<tr class="separator:ga4fb085742ee50628791c81ff9a14bc2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Control Status Register Bit Definitions</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp77718337863d9bf57fe00a0d3574ed3d"></a>Control Status Register bit masks Used to configure the timer counter device. </p>
+</td></tr>
+<tr class="memitem:ga2744df54b0fc4bc5df1dba14a6afc840"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
+<tr class="separator:ga2744df54b0fc4bc5df1dba14a6afc840"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga0e56ed788d0a3f4b6d89319e03797002"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
+<tr class="separator:ga0e56ed788d0a3f4b6d89319e03797002"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa10a23e3e387b53bac89f97cc5adf455"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
+<tr class="separator:gaa10a23e3e387b53bac89f97cc5adf455"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab06d844c7a245c7be88a63f3559bbd46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gab06d844c7a245c7be88a63f3559bbd46">XTC_CSR_AUTO_RELOAD_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
+<tr class="separator:gab06d844c7a245c7be88a63f3559bbd46"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gadcf0bfbbe0244d0fc208c783858a9c5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gadcf0bfbbe0244d0fc208c783858a9c5c">XTC_CSR_EXT_CAPTURE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
+<tr class="separator:gadcf0bfbbe0244d0fc208c783858a9c5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2345d81184385344ae236b8aa99f2423"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga2345d81184385344ae236b8aa99f2423">XTC_CSR_EXT_GENERATE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
+<tr class="separator:ga2345d81184385344ae236b8aa99f2423"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6b40b30b1d1d5b07f4101a5b657dddba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga6b40b30b1d1d5b07f4101a5b657dddba">XTC_CSR_DOWN_COUNT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
+<tr class="separator:ga6b40b30b1d1d5b07f4101a5b657dddba"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa0563f5483d9fef6126df6b2e447da08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa0563f5483d9fef6126df6b2e447da08">XTC_CSR_CAPTURE_MODE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
+<tr class="separator:gaa0563f5483d9fef6126df6b2e447da08"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga4fb085742ee50628791c81ff9a14bc2c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CASCADE_MODE_OPTION&#160;&#160;&#160;0x00000080UL</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Used to configure the timer counter device. </p>
+<pre>
+XTC_CASCADE_MODE_OPTION	Enables the Cascade Mode only valid for TCSRO.
+XTC_ENABLE_ALL_OPTION	Enables all timer counters at once.
+XTC_DOWN_COUNT_OPTION	Configures the timer counter to count down from
+     			start value, the default is to count up.
+XTC_CAPTURE_MODE_OPTION	Configures the timer to capture the timer
+     			counter value when the external capture line is
+     			asserted. The default mode is compare mode.
+XTC_INT_MODE_OPTION		Enables the timer counter interrupt output.
+XTC_AUTO_RELOAD_OPTION	In compare mode, configures the timer counter to
+     			reload from the compare value. The default mode
+     			causes the timer counter to hold when the
+     			compare value is hit.
+     			In capture mode, configures the timer counter to
+     			not hold the previous capture value if a new
+     			event occurs. The default mode cause the timer
+     			counter to hold the capture value until
+     			recognized.
+XTC_EXT_COMPARE_OPTION	Enables the external compare output signal.
+</pre> 
+</div>
+</div>
+<a class="anchor" id="gab06d844c7a245c7be88a63f3559bbd46"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_AUTO_RELOAD_MASK&#160;&#160;&#160;0x00000010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>In compare mode, configures the timer counter to reload from the Load Register. </p>
+<p>The default mode causes the timer counter to hold when the compare value is hit. In capture mode, configures the timer counter to not hold the previous capture value if a new event occurs. The default mode cause the timer counter to hold the capture value until recognized. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa0563f5483d9fef6126df6b2e447da08"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_CAPTURE_MODE_MASK&#160;&#160;&#160;0x00000001</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables the timer to capture the timer counter value when the external capture line is asserted. </p>
+<p>The default mode is compare mode. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaaf3300005339d29c2ee9a79e6bb81959"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_CASC_MASK&#160;&#160;&#160;0x00000800</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Cascade Mode. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6b40b30b1d1d5b07f4101a5b657dddba"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_DOWN_COUNT_MASK&#160;&#160;&#160;0x00000002</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Configures the timer counter to count down from start value, the default is to count up. </p>
+
+</div>
+</div>
+<a class="anchor" id="gabfaa1357c7843a1a72c740b017061a38"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_ENABLE_ALL_MASK&#160;&#160;&#160;0x00000400</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables all timer counters. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga0e56ed788d0a3f4b6d89319e03797002"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_ENABLE_INT_MASK&#160;&#160;&#160;0x00000040</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables the interrupt output. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa6304f96140472ea199517984b5a18d5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_ENABLE_PWM_MASK&#160;&#160;&#160;0x00000200</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables the Pulse Width Modulation. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa7cbbacf96f3f51bcd12d5826b03e620"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_ENABLE_TMR_MASK&#160;&#160;&#160;0x00000080</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables only the specific timer. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gadcf0bfbbe0244d0fc208c783858a9c5c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_EXT_CAPTURE_MASK&#160;&#160;&#160;0x00000008</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables the external input to the timer counter. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2345d81184385344ae236b8aa99f2423"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_EXT_GENERATE_MASK&#160;&#160;&#160;0x00000004</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Enables the external generate output for the timer. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2744df54b0fc4bc5df1dba14a6afc840"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_INT_OCCURED_MASK&#160;&#160;&#160;0x00000100</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>If bit is set, an interrupt has occured. </p>
+<p>If set and '1' is written to this bit position, bit is cleared. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa10a23e3e387b53bac89f97cc5adf455"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_CSR_LOAD_MASK&#160;&#160;&#160;0x00000020</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Loads the timer using the load value provided earlier in the Load Register, XTC_TLR_OFFSET. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaba99b973ef1f13bf0a2716cf52ca5319"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_DEVICE_TIMER_COUNT&#160;&#160;&#160;2</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Defines the number of timer counters within a single hardware device. </p>
+<p>This number is not currently parameterized in the hardware but may be in the future. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">XTmrCtr_GetCaptureValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">XTmrCtr_GetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">XTmrCtr_GetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">XTmrCtr_SetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">XTmrCtr_SetResetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad054cd3c12bc686f9be366e093c2f97a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_TCR_OFFSET&#160;&#160;&#160;8</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Timer counter register. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">XTmrCtr_GetValue()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga81c9a818cb57cf5f106cf5a3b7c3c59f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_TCSR_OFFSET&#160;&#160;&#160;0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Control/Status register. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">XTmrCtr_GetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">XTmrCtr_SetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga38a380fdcb3114c3db51524a8182c4ad"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTC_TLR_OFFSET&#160;&#160;&#160;4</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Load register. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">XTmrCtr_GetCaptureValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">XTmrCtr_SetResetValue()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gae5874bbf23d48004ab15acd250a34688"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_Disable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, \</div>
+<div class="line">                        (<a class="code" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber),\</div>
+<div class="line">                        <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>) &amp; ~ <a class="code" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaea427162ce7e92fd08afb7ee1cc1c12e"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a></div><div class="ttdeci">#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)</div><div class="ttdoc">Read one of the timer counter registers. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:231</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaa7cbbacf96f3f51bcd12d5826b03e620"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a></div><div class="ttdeci">#define XTC_CSR_ENABLE_TMR_MASK</div><div class="ttdoc">Enables only the specific timer. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:126</div></div>
+</div><!-- fragment -->
+<p>Disable a timer counter such that it stops running. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group__tmrctr__v4__0.html#gae5874bbf23d48004ab15acd250a34688" title="Disable a timer counter such that it stops running. ">XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga5c712d9f0122fd56355fec99a9c8c1c3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_DisableIntr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>,  \</div>
+<div class="line">        (<a class="code" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber),            \</div>
+<div class="line">                <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>) &amp; ~ <a class="code" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a>))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaea427162ce7e92fd08afb7ee1cc1c12e"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a></div><div class="ttdeci">#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)</div><div class="ttdoc">Read one of the timer counter registers. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:231</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga0e56ed788d0a3f4b6d89319e03797002"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a></div><div class="ttdeci">#define XTC_CSR_ENABLE_INT_MASK</div><div class="ttdoc">Enables the interrupt output. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:129</div></div>
+</div><!-- fragment -->
+<p>Disable the interrupt for a timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group__tmrctr__v4__0.html#ga5c712d9f0122fd56355fec99a9c8c1c3" title="Disable the interrupt for a timer counter. ">XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf312964acd6f01aeed63981877c63e8e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_Enable</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>,   \</div>
+<div class="line">                        (<a class="code" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), ( TmrCtrNumber), \</div>
+<div class="line">                        <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>) | <a class="code" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaea427162ce7e92fd08afb7ee1cc1c12e"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a></div><div class="ttdeci">#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)</div><div class="ttdoc">Read one of the timer counter registers. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:231</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaa7cbbacf96f3f51bcd12d5826b03e620"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a></div><div class="ttdeci">#define XTC_CSR_ENABLE_TMR_MASK</div><div class="ttdoc">Enables only the specific timer. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:126</div></div>
+</div><!-- fragment -->
+<p>Enable a timer counter such that it starts running. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group__tmrctr__v4__0.html#gaf312964acd6f01aeed63981877c63e8e" title="Enable a timer counter such that it starts running. ">XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaee205a5d80c200eb12b99b2d99837891"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_EnableIntr</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>,   \</div>
+<div class="line">                        (<a class="code" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber),  \</div>
+<div class="line">                        <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>) | <a class="code" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a>))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaea427162ce7e92fd08afb7ee1cc1c12e"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a></div><div class="ttdeci">#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)</div><div class="ttdoc">Read one of the timer counter registers. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:231</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga0e56ed788d0a3f4b6d89319e03797002"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a></div><div class="ttdeci">#define XTC_CSR_ENABLE_INT_MASK</div><div class="ttdoc">Enables the interrupt output. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:129</div></div>
+</div><!-- fragment -->
+<p>Enable the interrupt for a timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group__tmrctr__v4__0.html#gaee205a5d80c200eb12b99b2d99837891" title="Enable the interrupt for a timer counter. ">XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga45ca70c55615831432d0a2b32e0e77af"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_GetControlStatusReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Get the Control Status Register of a timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The value read from the register, a 32 bit value.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress, u8 TmrCtrNumber); </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga248be00d1ff730871bf8201143dc1480"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_GetLoadReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Get the Load Register of a timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The value read from the register, a 32 bit value.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 <a class="el" href="group__tmrctr__v4__0.html#ga248be00d1ff730871bf8201143dc1480" title="Get the Load Register of a timer counter. ">XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa6ab051d2011676e6cc3ea8fbc4ec6da"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_GetTimerCounterReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>) \</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+
+<p>Get the Timer Counter Register of a timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The value read from the register, a 32 bit value.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress, u8 TmrCtrNumber); </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac6bbcadfe43a528d4d895650bee25a4e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_HasEventOccurred</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber),        \</div>
+<div class="line">                <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>) &amp; <a class="code" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>) ==         \</div>
+<div class="line">                <a class="code" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>)</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaea427162ce7e92fd08afb7ee1cc1c12e"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a></div><div class="ttdeci">#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)</div><div class="ttdoc">Read one of the timer counter registers. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:231</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga2744df54b0fc4bc5df1dba14a6afc840"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a></div><div class="ttdeci">#define XTC_CSR_INT_OCCURED_MASK</div><div class="ttdoc">If bit is set, an interrupt has occured. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:115</div></div>
+</div><!-- fragment -->
+<p>Determine if a timer counter event has occurred. </p>
+<p>Events are defined to be when a capture has occurred or the counter has roller over.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: int <a class="el" href="group__tmrctr__v4__0.html#gac6bbcadfe43a528d4d895650bee25a4e" title="Determine if a timer counter event has occurred. ">XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber)</a>; </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga433680f98acc79f69d227a041f20ecb9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_LoadTimerCounterReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, \</div>
+<div class="line">                        (<a class="code" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber),\</div>
+<div class="line">                        <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>) | <a class="code" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaea427162ce7e92fd08afb7ee1cc1c12e"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a></div><div class="ttdeci">#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)</div><div class="ttdoc">Read one of the timer counter registers. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:231</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_gaa10a23e3e387b53bac89f97cc5adf455"><div class="ttname"><a href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a></div><div class="ttdeci">#define XTC_CSR_LOAD_MASK</div><div class="ttdoc">Loads the timer using the load value provided earlier in the Load Register, XTC_TLR_OFFSET. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:132</div></div>
+</div><!-- fragment -->
+<p>Cause the timer counter to load it's Timer Counter Register with the value in the Load Register. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress, u8 TmrCtrNumber); </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaea427162ce7e92fd08afb7ee1cc1c12e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_ReadReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \</div>
+<div class="line">                        (RegOffset))</div>
+</div><!-- fragment -->
+<p>Read one of the timer counter registers. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the timer counter device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>contains the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+    <tr><td class="paramname">RegOffset</td><td>contains the offset from the 1st register of the timer counter to select the specific register of the timer counter.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The value read from the register, a 32 bit value.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber, unsigned RegOffset); </dd></dl>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">XTmrCtr_GetCaptureValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">XTmrCtr_GetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">XTmrCtr_GetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga74c246c9f5ac5fb8793f0f792bc8fa0e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_SetControlStatusReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegisterValue&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>,     \</div>
+<div class="line">                                           (RegisterValue))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga81c9a818cb57cf5f106cf5a3b7c3c59f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a></div><div class="ttdeci">#define XTC_TCSR_OFFSET</div><div class="ttdoc">Control/Status register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:96</div></div>
+</div><!-- fragment -->
+<p>Set the Control Status Register of a timer counter to the specified value. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+    <tr><td class="paramname">RegisterValue</td><td>is the 32 bit value to be written to the register.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XTmrCtr_SetControlStatusReg(u32 BaseAddress, u8 TmrCtrNumber,u32 RegisterValue); </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga66eee1751bc9d207eef8143492669c96"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_SetLoadReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegisterValue&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>((BaseAddress), (TmrCtrNumber), <a class="code" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>, \</div>
+<div class="line">                                           (RegisterValue))</div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga56d9c2d54afce39c3693356e3892547f"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a></div><div class="ttdeci">#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)</div><div class="ttdoc">Write a specified value to a register of a timer counter. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:254</div></div>
+<div class="ttc" id="group__tmrctr__v4__0_html_ga38a380fdcb3114c3db51524a8182c4ad"><div class="ttname"><a href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a></div><div class="ttdeci">#define XTC_TLR_OFFSET</div><div class="ttdoc">Load register. </div><div class="ttdef"><b>Definition:</b> xtmrctr_l.h:97</div></div>
+</div><!-- fragment -->
+<p>Set the Load Register of a timer counter to the specified value. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+    <tr><td class="paramname">RegisterValue</td><td>is the 32 bit value to be written to the register.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber, u32 RegisterValue); </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga56d9c2d54afce39c3693356e3892547f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define XTmrCtr_WriteReg</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">BaseAddress, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">TmrCtrNumber, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">RegOffset, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">ValueToWrite&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__l_8h.html">xtmrctr_l.h</a>&gt;</code></p>
+<b>Value:</b><div class="fragment"><div class="line">Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +    \</div>
+<div class="line">                           (RegOffset)), (ValueToWrite))</div>
+</div><!-- fragment -->
+<p>Write a specified value to a register of a timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">BaseAddress</td><td>is the base address of the timer counter device. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the specific timer counter within the device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+    <tr><td class="paramname">RegOffset</td><td>contain the offset from the 1st register of the timer counter to select the specific register of the timer counter. </td></tr>
+    <tr><td class="paramname">ValueToWrite</td><td>is the 32 bit value to be written to the register.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>C-Style signature: void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber, unsigned RegOffset, u32 ValueToWrite); </dd></dl>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">XTmrCtr_SetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">XTmrCtr_SetResetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="ga60d20c9562b95591c9d6000b21747135"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef void(* XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber)</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Signature for the callback function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">CallBackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is unimportant to the driver, so it is a void pointer. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the number of the timer/counter within the device. The device typically contains at least two timer/counters. The timer number is a zero based number with a range of 0 to (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+  </table>
+  </dd>
+</dl>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga5186828a046cd32bbf69874524e983d2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_CfgInitialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> *&#160;</td>
+          <td class="paramname"><em>ConfigPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>This function populates the timer counter's configuration structure and sets some configurations defaults. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">ConfigPtr</td><td>is a pointer to the configuration structure that will be used to copy the settings from. </td></tr>
+    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>Unexpected errors may occur if the address mapping is changed after this function is invoked. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr___config.html#a3dfdf86126f37e26d966dda7c8317dcd">XTmrCtr_Config::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a19b7b38862e322c61d95f0f71f325f13">XTmrCtr::CallBackRef</a>, <a class="el" href="struct_x_tmr_ctr.html#a1fc51ca5db0c37e2b9b8db794f8a7496">XTmrCtr::Config</a>, <a class="el" href="struct_x_tmr_ctr.html#a5cc0b10723d9bad1b654dab33ae56c23">XTmrCtr::Handler</a>, <a class="el" href="struct_x_tmr_ctr_stats.html#a3e3996ef053ba44bc8720616f3f4c397">XTmrCtrStats::Interrupts</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, and <a class="el" href="struct_x_tmr_ctr.html#ad5cd023157ffa3ef8881bc88ae6ea26b">XTmrCtr::Stats</a>.</p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">XTmrCtr_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga6f51d8030e9d1a4edc588b0846e22e49"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_ClearStats </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Clear the <a class="el" href="struct_x_tmr_ctr_stats.html" title="Timer/Counter statistics. ">XTmrCtrStats</a> structure for this driver. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr_stats.html#a3e3996ef053ba44bc8720616f3f4c397">XTmrCtrStats::Interrupts</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, and <a class="el" href="struct_x_tmr_ctr.html#ad5cd023157ffa3ef8881bc88ae6ea26b">XTmrCtr::Stats</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad8f339bdf71ed11fa92f08720c9ce663"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr_GetCaptureValue </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Returns the timer counter value that was captured the last time the external capture input was asserted. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The current capture value for the indicated timer counter.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaaff209dc01c2946c239c6e5c1bdc1a5b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr_GetOptions </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Get the options for the specified timer counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd></dd></dl>
+<p>The currently set options. An option which is set to a '1' is enabled and set to a '0' is disabled. The options are bit masks such that multiple options may be set or cleared. The options are described in <a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>.</p>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga3c99744f99aef2a019616e712206f1b0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_GetStats </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr_stats.html">XTmrCtrStats</a> *&#160;</td>
+          <td class="paramname"><em>StatsPtr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Get a copy of the <a class="el" href="struct_x_tmr_ctr_stats.html" title="Timer/Counter statistics. ">XTmrCtrStats</a> structure, which contains the current statistics for this driver. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">StatsPtr</td><td>is a pointer to a <a class="el" href="struct_x_tmr_ctr_stats.html" title="Timer/Counter statistics. ">XTmrCtrStats</a> structure which will get a copy of current statistics.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr_stats.html#a3e3996ef053ba44bc8720616f3f4c397">XTmrCtrStats::Interrupts</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, and <a class="el" href="struct_x_tmr_ctr.html#ad5cd023157ffa3ef8881bc88ae6ea26b">XTmrCtr::Stats</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga325269055bb6f9f7a0c7f703bd2f2174"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr_GetValue </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Get the current value of the specified timer counter. </p>
+<p>The timer counter may be either incrementing or decrementing based upon the current mode of operation.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The current value for the timer counter.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gac3ffcfef4ba4507d5f2b9e17a08c7bf0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XTmrCtr_InitHw </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>(Re-)initialzes all timer counters which aren't started already. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if at least one timer counter is stopped.</li>
+<li>XST_DEVICE_IS_STARTED otherwise.</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="struct_x_tmr_ctr.html#aa273d27a5f60d8b003eb83247aca3341">XTmrCtr::IsStartedTmrCtr0</a>, <a class="el" href="struct_x_tmr_ctr.html#adcc945170ebc1ae68a01ba548ad60b0d">XTmrCtr::IsStartedTmrCtr1</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">XTmrCtr_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gad5f9b6172f448d2dd13d1c200ca37928"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XTmrCtr_Initialize </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>DeviceId</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Initializes a specific timer/counter instance/driver. </p>
+<p>Initialize fields of the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> structure, then reset the timer/counter.If a timer is already running then it is not initialized.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">DeviceId</td><td>is the unique id of the device controlled by this <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> component. Passing in a device id associates the generic <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> component to a specific device, as chosen by the caller or application developer.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if initialization was successful</li>
+<li>XST_DEVICE_IS_STARTED if the device has already been started</li>
+<li>XST_DEVICE_NOT_FOUND if the device doesn't exist</li>
+</ul>
+</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr___config.html#a3dfdf86126f37e26d966dda7c8317dcd">XTmrCtr_Config::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#aa273d27a5f60d8b003eb83247aca3341">XTmrCtr::IsStartedTmrCtr0</a>, <a class="el" href="struct_x_tmr_ctr.html#adcc945170ebc1ae68a01ba548ad60b0d">XTmrCtr::IsStartedTmrCtr1</a>, <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga59bced86622b77630d18e731fbcec7f5">XTmrCtr_LookupConfig()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga2c00e99b19f58b5821c5541069ffb20b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_InterruptHandler </td>
+          <td>(</td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Interrupt Service Routine (ISR) for the driver. </p>
+<p>This function only performs processing for the device and does not save and restore the interrupt context.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>contains a pointer to the timer/counter instance for the interrupt.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a19b7b38862e322c61d95f0f71f325f13">XTmrCtr::CallBackRef</a>, <a class="el" href="struct_x_tmr_ctr.html#a5cc0b10723d9bad1b654dab33ae56c23">XTmrCtr::Handler</a>, <a class="el" href="struct_x_tmr_ctr_stats.html#a3e3996ef053ba44bc8720616f3f4c397">XTmrCtrStats::Interrupts</a>, <a class="el" href="struct_x_tmr_ctr.html#ad5cd023157ffa3ef8881bc88ae6ea26b">XTmrCtr::Stats</a>, <a class="el" href="group__tmrctr__v4__0.html#gab06d844c7a245c7be88a63f3559bbd46">XTC_CSR_AUTO_RELOAD_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa0563f5483d9fef6126df6b2e447da08">XTC_CSR_CAPTURE_MODE_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga44d19561a31682753e4996c7b57d6982"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XTmrCtr_IsExpired </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Checks if the specified timer counter of the device has expired. </p>
+<p>In capture mode, expired is defined as a capture occurred. In compare mode, expired is defined as the timer counter rolled over/under for up/down counting.</p>
+<p>When interrupts are enabled, the expiration causes an interrupt. This function is typically used to poll a timer counter to determine when it has expired.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>TRUE if the timer has expired, and FALSE otherwise.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga59bced86622b77630d18e731fbcec7f5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> * XTmrCtr_LookupConfig </td>
+          <td>(</td>
+          <td class="paramtype">u16&#160;</td>
+          <td class="paramname"><em>DeviceId</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Looks up the device configuration based on the unique device ID. </p>
+<p>The table TmrCtr_ConfigTable contains the configuration info for each device in the system.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">DeviceId</td><td>is the unique device ID to search for in the config table.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>A pointer to the configuration that matches the given device ID, or NULL if no match is found.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">XTmrCtr_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gaa7b4ca5a0ac2199ee5341fddd8056500"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_Reset </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Resets the specified timer counter of the device. </p>
+<p>A reset causes the timer counter to set it's value to the reset value.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga42b972b6d7ae5d18a9bb2ca99446b1e7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XTmrCtr_SelfTest </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Runs a self-test on the driver/device. </p>
+<p>This test verifies that the specified timer counter of the device can be enabled and increments.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li>XST_SUCCESS if self-test was successful</li>
+</ul>
+</dd></dl>
+<ul>
+<li>XST_FAILURE if the timer is not incrementing.</li>
+</ul>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>This is a destructive test using the provided timer. The current settings of the timer are returned to the initialized values and all settings at the time this function is called are overwritten. </p>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga9eb7b372c13b5e3493fec7370858309f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_SetHandler </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group__tmrctr__v4__0.html#ga60d20c9562b95591c9d6000b21747135">XTmrCtr_Handler</a>&#160;</td>
+          <td class="paramname"><em>FuncPtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>CallBackRef</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Sets the timer callback function, which the driver calls when the specified timer times out. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance . </td></tr>
+    <tr><td class="paramname">CallBackRef</td><td>is the upper layer callback reference passed back when the callback function is invoked. </td></tr>
+    <tr><td class="paramname">FuncPtr</td><td>is the pointer to the callback function.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd></dd></dl>
+<p>The handler is called within interrupt context so the function that is called should either be short or pass the more extensive processing off to another task to allow the interrupt to return and normal processing to continue. </p>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#a19b7b38862e322c61d95f0f71f325f13">XTmrCtr::CallBackRef</a>, <a class="el" href="struct_x_tmr_ctr.html#a5cc0b10723d9bad1b654dab33ae56c23">XTmrCtr::Handler</a>, and <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga93d796cf55144d6adb3c51fedf6c3b76"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_SetOptions </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>Options</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>&gt;</code></p>
+
+<p>Enables the specified options for the specified timer counter. </p>
+<p>This function sets the options without regard to the current options of the driver. To prevent a loss of the current options, the user should call <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b" title="Get the options for the specified timer counter. ">XTmrCtr_GetOptions()</a> prior to this function and modify the retrieved options to pass into this function to prevent loss of the current options.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+    <tr><td class="paramname">Options</td><td>contains the desired options to be set or cleared. Setting the option to '1' enables the option, clearing the to '0' disables the option. The options are bit masks such that multiple options may be set or cleared. The options are described in <a class="el" href="xtmrctr_8h.html">xtmrctr.h</a>.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga74b790866611a3ab1e96700feb48f6ea"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_SetResetValue </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u32&#160;</td>
+          <td class="paramname"><em>ResetValue</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Set the reset value for the specified timer counter. </p>
+<p>This is the value that is loaded into the timer counter when it is reset. This value is also loaded when the timer counter is started.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1). </td></tr>
+    <tr><td class="paramname">ResetValue</td><td>contains the value to be used to reset the timer counter.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ga009c17ab4fcedf73279638dd97b6edd4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_Start </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Starts the specified timer counter of the device such that it starts running. </p>
+<p>The timer counter is reset before it is started and the reset value is loaded into the timer counter.</p>
+<p>If interrupt mode is specified in the options, it is necessary for the caller to connect the interrupt handler of the timer/counter to the interrupt source, typically an interrupt controller, and enable the interrupt within the interrupt controller.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="struct_x_tmr_ctr.html#aa273d27a5f60d8b003eb83247aca3341">XTmrCtr::IsStartedTmrCtr0</a>, <a class="el" href="struct_x_tmr_ctr.html#adcc945170ebc1ae68a01ba548ad60b0d">XTmrCtr::IsStartedTmrCtr1</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="gab8156ff2a16b8efc0fcd3ed2b7ecf91a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void XTmrCtr_Stop </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *&#160;</td>
+          <td class="paramname"><em>InstancePtr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8&#160;</td>
+          <td class="paramname"><em>TmrCtrNumber</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr_8c.html">xtmrctr.c</a>&gt;</code></p>
+
+<p>Stops the timer counter by disabling it. </p>
+<p>It is the callers' responsibility to disconnect the interrupt handler of the timer_counter from the interrupt source, typically an interrupt controller, and disable the interrupt within the interrupt controller.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance. </td></tr>
+    <tr><td class="paramname">TmrCtrNumber</td><td>is the timer counter of the device to operate on. Each device may contain multiple timer counters. The timer number is a zero based number with a range of 0 - (XTC_DEVICE_TIMER_COUNT - 1).</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
+<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
+
+<p>References <a class="el" href="struct_x_tmr_ctr.html#ae65c2b8939adb3aa2c5ab4aec2a018af">XTmrCtr::BaseAddress</a>, <a class="el" href="struct_x_tmr_ctr.html#a6e340e798d785abfe551a776fd6f7bb9">XTmrCtr::IsReady</a>, <a class="el" href="struct_x_tmr_ctr.html#aa273d27a5f60d8b003eb83247aca3341">XTmrCtr::IsStartedTmrCtr0</a>, <a class="el" href="struct_x_tmr_ctr.html#adcc945170ebc1ae68a01ba548ad60b0d">XTmrCtr::IsStartedTmrCtr1</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>, <a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>, <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>, <a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>.</p>
+
+</div>
+</div>
+<h2 class="groupheader">Variable Documentation</h2>
+<a class="anchor" id="ga5ce980ccbed0b805d08e295f71dbade7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> XTmrCtr_ConfigTable[XPAR_XTMRCTR_NUM_INSTANCES]</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__sinit_8c.html">xtmrctr_sinit.c</a>&gt;</code></p>
+
+<p>The timer/counter configuration table, sized by the number of instances defined in xparameters.h. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab696b83980f59544e04b19249734883d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> XTmrCtr_ConfigTable[]</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p><code>#include &lt;<a class="el" href="xtmrctr__g_8c.html">xtmrctr_g.c</a>&gt;</code></p>
+<b>Initial value:</b><div class="fragment"><div class="line">= {</div>
+<div class="line"></div>
+<div class="line"></div>
+<div class="line"></div>
+<div class="line"></div>
+<div class="line"></div>
+<div class="line"></div>
+<div class="line"></div>
+<div class="line">}</div>
+</div><!-- fragment -->
+<p>The timer/counter configuration table, sized by the number of instances defined in xparameters.h. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
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+<!-- Generated by Doxygen 1.8.10 -->
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+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
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+<div class="title">tmrctr_v4_0 Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>The Xilinx timer/counter component. This component supports the Xilinx timer/counter. More detailed description of the driver operation can be found in the <a class="el" href="xtmrctr_8c.html">xtmrctr.c</a> file.</p>
+<p>The Xilinx timer/counter supports the following features:</p><ul>
+<li>Polled mode.</li>
+<li>Interrupt driven mode</li>
+<li>enabling and disabling specific timers</li>
+<li>PWM operation</li>
+<li>Cascade Operation (This is to be used for getting a 64 bit timer and this feature is present in the latest versions of the axi_timer IP)</li>
+</ul>
+<p>The driver does not currently support the PWM operation of the device.</p>
+<p>The timer counter operates in 2 primary modes, compare and capture. In either mode, the timer counter may count up or down, with up being the default.</p>
+<p>Compare mode is typically used for creating a single time period or multiple repeating time periods in the auto reload mode, such as a periodic interrupt. When started, the timer counter loads an initial value, referred to as the compare value, into the timer counter and starts counting down or up. The timer counter expires when it rolls over/under depending upon the mode of counting. An external compare output signal may be configured such that a pulse is generated with this signal when it hits the compare value.</p>
+<p>Capture mode is typically used for measuring the time period between external events. This mode uses an external capture input signal to cause the value of the timer counter to be captured. When started, the timer counter loads an initial value, referred to as the compare value,</p>
+<p>The timer can be configured to either cause an interrupt when the count reaches the compare value in compare mode or latch the current count value in the capture register when an external input is asserted in capture mode. The external capture input can be enabled/disabled using the XTmrCtr_SetOptions function. While in compare mode, it is also possible to drive an external output when the compare value is reached in the count register The external compare output can be enabled/disabled using the XTmrCtr_SetOptions function.</p>
+<p><b>Interrupts</b></p>
+<p>It is the responsibility of the application to connect the interrupt handler of the timer/counter to the interrupt source. The interrupt handler function, XTmrCtr_InterruptHandler, is visible such that the user can connect it to the interrupt source. Note that this interrupt handler does not provide interrupt context save and restore processing, the user must perform this processing.</p>
+<p>The driver services interrupts and passes timeouts to the upper layer software through callback functions. The upper layer software must register its callback functions during initialization. The driver requires callback functions for timers.</p>
+<dl class="section note"><dt>Note</dt><dd>The default settings for the timers are:<ul>
+<li>Interrupt generation disabled</li>
+<li>Count up mode</li>
+<li>Compare mode</li>
+<li>Hold counter (will not reload the timer)</li>
+<li>External compare output disabled</li>
+<li>External capture input disabled</li>
+<li>Pulse width modulation disabled</li>
+<li>Timer disabled, waits for Start function to be called <br />
+<br />
+ A timer counter device may contain multiple timer counters. The symbol XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device. The device currently contains 2 timer counters. <br />
+<br />
+ This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</li>
+</ul>
+</dd></dl>
+<pre>
+MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
+----- ---- -------- -----------------------------------------------
+1.00a ecm  08/16/01 First release
+1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+1.10b mta  03/21/07 Updated to new coding style.
+1.11a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+      	      file
+2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+      	      definitions.
+2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+      	      for naming consistency (CR 559142).
+2.02a sdm  09/28/10 Updated the driver tcl to generate the xparameters
+      	      for the timer clock frequency (CR 572679).
+2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
+      	      processing for CR 584557.
+2.04a sdm  07/12/11 Added support for cascade mode operation.
+		      The cascade mode of operation is present in the latest
+      	      versions of the axi_timer IP. Please check the HW
+      	      Datasheet to see whether this feature is present in the
+      	      version of the IP that you are using.
+2.05a adk  15/05/13 Fixed the CR:693066
+      	      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
+      	      <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> instance structure.
+      	      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
+      	      the XTmrCtr_Start function.
+      	      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
+      	      There will be no Initialization done in the
+      	      XTmrCtr_Initialize if both the timers have already started and
+      	      the XST_DEVICE_IS_STARTED Status is returned.
+      	      Removed the logic in the XTmrCtr_Initialize function
+      	      which was checking the Register Value to know whether
+      	      a timer has started or not.
+3.0   adk  19/12/13 Updated as per the New Tcl API's
+4.0   als  09/30/15 Updated initialization API.
+</pre> </div></div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/jquery.js b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/jquery.js
new file mode 100644
index 000000000..1f4d0b47c
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/jquery.js
@@ -0,0 +1,68 @@
+/*!
+ * jQuery JavaScript Library v1.7.1
+ * http://jquery.com/
+ *
+ * Copyright 2011, John Resig
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * Includes Sizzle.js
+ * http://sizzlejs.com/
+ * Copyright 2011, The Dojo Foundation
+ * Released under the MIT, BSD, and GPL Licenses.
+ *
+ * Date: Mon Nov 21 21:11:03 2011 -0500
+ */
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+/*!
+ * Sizzle CSS Selector Engine
+ *  Copyright 2011, The Dojo Foundation
+ *  Released under the MIT, BSD, and GPL Licenses.
+ *  More information: http://sizzlejs.com/
+ */
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+ * jQuery UI 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI
+ */
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+ * jQuery UI Widget 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Widget
+ */
+(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!
+ * jQuery UI Mouse 1.8.18
+ *
+ * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT or GPL Version 2 licenses.
+ * http://jquery.org/license
+ *
+ * http://docs.jquery.com/UI/Mouse
+ *
+ * Depends:
+ *	jquery.ui.widget.js
+ */
+(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e=="sw"){h.left=j.left+(f.width-h.width);h.top=null}if(e=="nw"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css("borderTopWidth"),h.css("borderRightWidth"),h.css("borderBottomWidth"),h.css("borderLeftWidth")],j=[h.css("paddingTop"),h.css("paddingRight"),h.css("paddingBottom"),h.css("paddingLeft")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(":hidden")||c(g).parents(":hidden").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null;p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var 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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
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+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">APIs</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__tmrctr__v3__0.html" target="_self">Tmrctr_v3_0</a></td><td class="desc">This file contains data which is shared between files internal to the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> component </td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__tmrctr__v4__0.html" target="_self">Tmrctr_v4_0</a></td><td class="desc">Contains required functions for the <a class="el" href="struct_x_tmr_ctr.html" title="The XTmrCtr driver instance data. ">XTmrCtr</a> driver </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr.html
new file mode 100644
index 000000000..f4b1a76b0
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr.html
@@ -0,0 +1,198 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: XTmrCtr Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">XTmrCtr Struct Reference<div class="ingroups"><a class="el" href="group__tmrctr__v4__0.html">Tmrctr_v4_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a1fc51ca5db0c37e2b9b8db794f8a7496"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr.html#a1fc51ca5db0c37e2b9b8db794f8a7496">Config</a></td></tr>
+<tr class="separator:a1fc51ca5db0c37e2b9b8db794f8a7496"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>The user is required to allocate a variable of this type for every timer/counter device in the system. A pointer to a variable of this type is then passed to the driver API functions. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ae65c2b8939adb3aa2c5ab4aec2a018af"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr::BaseAddress</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Base address of registers. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">XTmrCtr_GetCaptureValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">XTmrCtr_GetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">XTmrCtr_GetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">XTmrCtr_SetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">XTmrCtr_SetResetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a19b7b38862e322c61d95f0f71f325f13"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* XTmrCtr::CallBackRef</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Callback reference for handler. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga9eb7b372c13b5e3493fec7370858309f">XTmrCtr_SetHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a1fc51ca5db0c37e2b9b8db794f8a7496"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> XTmrCtr::Config</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Core configuration. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a5cc0b10723d9bad1b654dab33ae56c23"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__tmrctr__v4__0.html#ga60d20c9562b95591c9d6000b21747135">XTmrCtr_Handler</a> XTmrCtr::Handler</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Callback function. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga9eb7b372c13b5e3493fec7370858309f">XTmrCtr_SetHandler()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a6e340e798d785abfe551a776fd6f7bb9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr::IsReady</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Device is initialized and ready. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga6f51d8030e9d1a4edc588b0846e22e49">XTmrCtr_ClearStats()</a>, <a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">XTmrCtr_GetCaptureValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">XTmrCtr_GetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga3c99744f99aef2a019616e712206f1b0">XTmrCtr_GetStats()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">XTmrCtr_GetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired()</a>, <a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga9eb7b372c13b5e3493fec7370858309f">XTmrCtr_SetHandler()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76">XTmrCtr_SetOptions()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">XTmrCtr_SetResetValue()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aa273d27a5f60d8b003eb83247aca3341"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr::IsStartedTmrCtr0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Is Timer Counter 0 started. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">XTmrCtr_Initialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="adcc945170ebc1ae68a01ba548ad60b0d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr::IsStartedTmrCtr1</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Is Timer Counter 1 started. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw()</a>, <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">XTmrCtr_Initialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ad5cd023157ffa3ef8881bc88ae6ea26b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="struct_x_tmr_ctr_stats.html">XTmrCtrStats</a> XTmrCtr::Stats</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Component Statistics. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga6f51d8030e9d1a4edc588b0846e22e49">XTmrCtr_ClearStats()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga3c99744f99aef2a019616e712206f1b0">XTmrCtr_GetStats()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr___config.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr___config.html
new file mode 100644
index 000000000..ca4a397b9
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr___config.html
@@ -0,0 +1,104 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: XTmrCtr_Config Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XTmrCtr_Config Struct Reference<div class="ingroups"><a class="el" href="group__tmrctr__v4__0.html">Tmrctr_v4_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3dfdf86126f37e26d966dda7c8317dcd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr_Config::BaseAddress</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Register base address. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, and <a class="el" href="group__tmrctr__v4__0.html#gad5f9b6172f448d2dd13d1c200ca37928">XTmrCtr_Initialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a2720753d361a041bea550a352730cec6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u16 XTmrCtr_Config::DeviceId</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Unique ID of device. </p>
+
+</div>
+</div>
+<a class="anchor" id="a8841b74af7282d4328dafd915b277b10"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XTmrCtr_Config::SysClockFreqHz</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>The AXI bus clock frequency. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr_stats.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/struct_x_tmr_ctr_stats.html
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+<title>tmrctr_v4_0: XTmrCtrStats Struct Reference</title>
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+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
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+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XTmrCtrStats Struct Reference<div class="ingroups"><a class="el" href="group__tmrctr__v4__0.html">Tmrctr_v4_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3e3996ef053ba44bc8720616f3f4c397"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">u32 XTmrCtrStats::Interrupts</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>The number of interrupts that have occurred. </p>
+
+<p>Referenced by <a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga6f51d8030e9d1a4edc588b0846e22e49">XTmrCtr_ClearStats()</a>, <a class="el" href="group__tmrctr__v4__0.html#ga3c99744f99aef2a019616e712206f1b0">XTmrCtr_GetStats()</a>, and <a class="el" href="group__tmrctr__v4__0.html#ga2c00e99b19f58b5821c5541069ffb20b">XTmrCtr_InterruptHandler()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
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+</div>
+</body>
+</html>
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+<div class="title">xtmrctr.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga5186828a046cd32bbf69874524e983d2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, <a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
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+<tr class="memitem:gac3ffcfef4ba4507d5f2b9e17a08c7bf0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr)</td></tr>
+<tr class="separator:gac3ffcfef4ba4507d5f2b9e17a08c7bf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memitem:ga009c17ab4fcedf73279638dd97b6edd4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga009c17ab4fcedf73279638dd97b6edd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab8156ff2a16b8efc0fcd3ed2b7ecf91a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gab8156ff2a16b8efc0fcd3ed2b7ecf91a">XTmrCtr_Stop</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:gab8156ff2a16b8efc0fcd3ed2b7ecf91a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga325269055bb6f9f7a0c7f703bd2f2174"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga325269055bb6f9f7a0c7f703bd2f2174">XTmrCtr_GetValue</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga325269055bb6f9f7a0c7f703bd2f2174"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga74b790866611a3ab1e96700feb48f6ea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga74b790866611a3ab1e96700feb48f6ea">XTmrCtr_SetResetValue</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber, u32 ResetValue)</td></tr>
+<tr class="separator:ga74b790866611a3ab1e96700feb48f6ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gad8f339bdf71ed11fa92f08720c9ce663"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gad8f339bdf71ed11fa92f08720c9ce663">XTmrCtr_GetCaptureValue</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:gad8f339bdf71ed11fa92f08720c9ce663"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa7b4ca5a0ac2199ee5341fddd8056500"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa7b4ca5a0ac2199ee5341fddd8056500">XTmrCtr_Reset</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:gaa7b4ca5a0ac2199ee5341fddd8056500"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga44d19561a31682753e4996c7b57d6982"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga44d19561a31682753e4996c7b57d6982">XTmrCtr_IsExpired</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga44d19561a31682753e4996c7b57d6982"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
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+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
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+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#nested-classes">Data Structures</a> &#124;
+<a href="#typedef-members">Typedefs</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xtmrctr.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr_stats.html">XTmrCtrStats</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Configuration options</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>These options are used in <a class="el" href="group__tmrctr__v4__0.html#ga93d796cf55144d6adb3c51fedf6c3b76" title="Enables the specified options for the specified timer counter. ">XTmrCtr_SetOptions()</a> and <a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b" title="Get the options for the specified timer counter. ">XTmrCtr_GetOptions()</a> </p>
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+<tr class="memitem:ga4fb085742ee50628791c81ff9a14bc2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga4fb085742ee50628791c81ff9a14bc2c">XTC_CASCADE_MODE_OPTION</a>&#160;&#160;&#160;0x00000080UL</td></tr>
+<tr class="separator:ga4fb085742ee50628791c81ff9a14bc2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:ga60d20c9562b95591c9d6000b21747135"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga60d20c9562b95591c9d6000b21747135">XTmrCtr_Handler</a>) (void *CallBackRef, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga60d20c9562b95591c9d6000b21747135"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga5186828a046cd32bbf69874524e983d2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga5186828a046cd32bbf69874524e983d2">XTmrCtr_CfgInitialize</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, <a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
+<tr class="separator:ga5186828a046cd32bbf69874524e983d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac3ffcfef4ba4507d5f2b9e17a08c7bf0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gac3ffcfef4ba4507d5f2b9e17a08c7bf0">XTmrCtr_InitHw</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr)</td></tr>
+<tr class="separator:gac3ffcfef4ba4507d5f2b9e17a08c7bf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gad5f9b6172f448d2dd13d1c200ca37928"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga009c17ab4fcedf73279638dd97b6edd4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga009c17ab4fcedf73279638dd97b6edd4">XTmrCtr_Start</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga009c17ab4fcedf73279638dd97b6edd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gab8156ff2a16b8efc0fcd3ed2b7ecf91a"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga74b790866611a3ab1e96700feb48f6ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gad8f339bdf71ed11fa92f08720c9ce663"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga93d796cf55144d6adb3c51fedf6c3b76"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga2c00e99b19f58b5821c5541069ffb20b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__g_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__g_8c.html
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
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+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__i_8h.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__i_8h.html
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
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+    </ul>
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+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">xtmrctr_i.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
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+</body>
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diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__intr_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__intr_8c.html
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: xtmrctr_intr.c File Reference</title>
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+<script type="text/javascript" src="dynsections.js"></script>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
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+</table>
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+<div id="nav-path" class="navpath">
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
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+<div class="title">xtmrctr_intr.c File Reference</div>  </div>
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+<div class="contents">
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+<tr class="separator:ga2c00e99b19f58b5821c5541069ffb20b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__l_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__l_8c.html
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
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+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__l_8h.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__l_8h.html
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
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+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">xtmrctr_l.h File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
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+<tr class="separator:gaa0563f5483d9fef6126df6b2e447da08"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__options_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__options_8c.html
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--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__options_8c.html
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: xtmrctr_options.c File Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xtmrctr_options.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
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+<tr class="separator:ga93d796cf55144d6adb3c51fedf6c3b76"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaaff209dc01c2946c239c6e5c1bdc1a5b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaaff209dc01c2946c239c6e5c1bdc1a5b">XTmrCtr_GetOptions</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:gaaff209dc01c2946c239c6e5c1bdc1a5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__selftest_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__selftest_8c.html
new file mode 100644
index 000000000..dc4cd07d0
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+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__selftest_8c.html
@@ -0,0 +1,65 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: xtmrctr_selftest.c File Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xtmrctr_selftest.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga42b972b6d7ae5d18a9bb2ca99446b1e7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga42b972b6d7ae5d18a9bb2ca99446b1e7">XTmrCtr_SelfTest</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, u8 TmrCtrNumber)</td></tr>
+<tr class="separator:ga42b972b6d7ae5d18a9bb2ca99446b1e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__sinit_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__sinit_8c.html
new file mode 100644
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+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__sinit_8c.html
@@ -0,0 +1,65 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>tmrctr_v4_0: xtmrctr_sinit.c File Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
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+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">tmrctr_v4_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+<div id="nav-path" class="navpath">
+  <ul>
+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_62817d2c99309a7e0bbbb270088b1c2e.html">tmrctr_v4_0</a></li><li class="navelem"><a class="el" href="dir_fe37dfe295cf33c9716c94c87e5a217e.html">src</a></li>  </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xtmrctr_sinit.c File Reference</div>  </div>
+</div><!--header-->
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+<tr class="memitem:ga59bced86622b77630d18e731fbcec7f5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_tmr_ctr___config.html">XTmrCtr_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga59bced86622b77630d18e731fbcec7f5">XTmrCtr_LookupConfig</a> (u16 DeviceId)</td></tr>
+<tr class="separator:ga59bced86622b77630d18e731fbcec7f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
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diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__stats_8c.html b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__stats_8c.html
new file mode 100644
index 000000000..11181cf66
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/doc/html/api/xtmrctr__stats_8c.html
@@ -0,0 +1,67 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
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+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
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+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xtmrctr_stats.c File Reference</div>  </div>
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+Functions</h2></td></tr>
+<tr class="memitem:ga3c99744f99aef2a019616e712206f1b0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga3c99744f99aef2a019616e712206f1b0">XTmrCtr_GetStats</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr, <a class="el" href="struct_x_tmr_ctr_stats.html">XTmrCtrStats</a> *StatsPtr)</td></tr>
+<tr class="separator:ga3c99744f99aef2a019616e712206f1b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6f51d8030e9d1a4edc588b0846e22e49"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga6f51d8030e9d1a4edc588b0846e22e49">XTmrCtr_ClearStats</a> (<a class="el" href="struct_x_tmr_ctr.html">XTmrCtr</a> *InstancePtr)</td></tr>
+<tr class="separator:ga6f51d8030e9d1a4edc588b0846e22e49"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
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diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/index.html b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/index.html
new file mode 100644
index 000000000..c2b4bcd5b
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/index.html
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver tmrctr_v3_0 </h1>
+<HR>
+<ul>
+  <li>xtmrctr_intr_64bit_example.c <a href="xtmrctr_intr_64bit_example.c">(source)</a> </li>
+  <li>xtmrctr_intr_example.c <a href="xtmrctr_intr_example.c">(source)</a> </li>
+  <li>xtmrctr_low_level_example.c <a href="xtmrctr_low_level_example.c">(source)</a> </li>
+  <li>xtmrctr_polled_example.c <a href="xtmrctr_polled_example.c">(source)</a> </li>
+  <li>xtmrctr_selftest_example.c <a href="xtmrctr_selftest_example.c">(source)</a> </li>
+  <li>xtmrctr_fast_intr_example.c <a href="xtmrctr_fast_intr_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright © 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
\ No newline at end of file
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_fast_intr_example.c b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_fast_intr_example.c
new file mode 100644
index 000000000..c12e25766
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_fast_intr_example.c
@@ -0,0 +1,451 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file  xtmrctr_fast_intr_example.c
+*
+* This file contains a design example using the timer counter driver
+* (XTmCtr) and hardware device using fast interrupt mode.This example assumes
+* that the interrupt controller is also present as a part of the system
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a bss  07/31/12 First release
+*
+*</pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xtmrctr.h"
+#include "xintc.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TMRCTR_DEVICE_ID	XPAR_TMRCTR_0_DEVICE_ID
+#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
+#define TMRCTR_INTERRUPT_ID	XPAR_INTC_0_TMRCTR_0_VEC_ID
+
+/*
+ * The following constant determines which timer counter of the device that is
+ * used for this example, there are currently 2 timer counters in a device
+ * and this example uses the first one, 0, the timer numbers are 0 based
+ */
+#define TIMER_CNTR_0	 0
+
+
+/*
+ * The following constant is used to set the reset value of the timer counter,
+ * making this number larger reduces the amount of time this example consumes
+ * because it is the value the timer counter is loaded with when it is started
+ */
+#define RESET_VALUE	 0xF0000000
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int TmrCtrFastIntrExample(XIntc* IntcInstancePtr,
+			XTmrCtr* InstancePtr,
+			u16 DeviceId,
+			u16 IntrId,
+			u8 TmrCtrNumber);
+
+static int TmrCtrSetupIntrSystem(XIntc* IntcInstancePtr,
+				XTmrCtr* InstancePtr,
+				u16 DeviceId,
+				u16 IntrId,
+				u8 TmrCtrNumber);
+
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber);
+
+void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId);
+
+void TmrCtr_FastHandler(void) __attribute__ ((fast_interrupt));
+
+/************************** Variable Definitions *****************************/
+
+XIntc InterruptController;  /* The instance of the Interrupt Controller */
+XTmrCtr TimerCounterInst;   /* The instance of the Timer Counter */
+
+/*
+ * The following variables are shared between non-interrupt processing and
+ * interrupt processing such that they must be global.
+ */
+volatile int TimerExpired;
+
+
+/*****************************************************************************/
+/**
+* This is the main function of the Tmrctr example using Fast Interrupt feature
+* in MicroBlaze and Intc controller.
+*
+* @param	None.
+*
+* @return	- XST_SUCCESS to indicate success.
+*		- XST_FAILURE to indicate a failure.
+*
+* @note		None.
+*
+******************************************************************************/
+
+int main(void)
+{
+
+	int Status;
+
+	/*
+	 * Run the Timer Counter Fast Interrupt example.
+	 */
+	Status = TmrCtrFastIntrExample(&InterruptController,
+				  &TimerCounterInst,
+				  TMRCTR_DEVICE_ID,
+				  TMRCTR_INTERRUPT_ID,
+				  TIMER_CNTR_0);
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+
+/*****************************************************************************/
+/**
+* This function does a minimal test on the timer counter device and driver as a
+* design example.  The purpose of this function is to illustrate how to use the
+* XTmrCtr component.  It initializes a timer counter and then sets it up in
+* compare mode with auto reload such that a periodic interrupt is generated.
+*
+* This function uses interrupt driven mode of the timer counter.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance
+* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance
+* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
+*		xparameters.h
+* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
+*		value from xparameters.h
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return
+*		- XST_SUCCESS if the Test is successful
+*		- XST_FAILURE if the Test is not successful
+*
+* @note		This function contains an infinite loop such that if interrupts
+*		are not working it may never return.
+*
+*****************************************************************************/
+int TmrCtrFastIntrExample(XIntc* IntcInstancePtr,
+			XTmrCtr* TmrCtrInstancePtr,
+			u16 DeviceId,
+			u16 IntrId,
+			u8 TmrCtrNumber)
+{
+	int Status;
+	int LastTimerExpired = 0;
+
+	/*
+	 * Initialize the timer counter so that it's ready to use,
+	 * specify the device ID that is generated in xparameters.h
+	 */
+	Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly, use the 1st timer in the device (0)
+	 */
+	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the timer counter to the interrupt subsystem such that
+	 * interrupts can occur.  This function is application specific.
+	 */
+	Status = TmrCtrSetupIntrSystem(IntcInstancePtr,
+					TmrCtrInstancePtr,
+					DeviceId,
+					IntrId,
+					TmrCtrNumber);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup the handler for the timer counter that will be called from the
+	 * interrupt context when the timer expires, specify a pointer to the
+	 * timer counter driver instance as the callback reference so the
+	 * handler is able to access the instance data
+	 */
+	XTmrCtr_SetHandler(TmrCtrInstancePtr, TimerCounterHandler,
+					   TmrCtrInstancePtr);
+
+	/*
+	 * Enable the interrupt of the timer counter so interrupts will occur
+	 * and use auto reload mode such that the timer counter will reload
+	 * itself automatically and continue repeatedly, without this option
+	 * it would expire once only
+	 */
+	XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber,
+				XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);
+
+	/*
+	 * Set a reset value for the timer counter such that it will expire
+	 * eariler than letting it roll over from 0, the reset value is loaded
+	 * into the timer counter when it is started
+	 */
+	XTmrCtr_SetResetValue(TmrCtrInstancePtr, TmrCtrNumber, RESET_VALUE);
+
+	/*
+	 * Start the timer counter such that it's incrementing by default,
+	 * then wait for it to timeout a number of times
+	 */
+	XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber);
+
+	while (1) {
+		/*
+		 * Wait for the first timer counter to expire as indicated by
+		 * the shared variable which the handler will increment
+		 */
+		while (TimerExpired == LastTimerExpired) {
+		}
+		LastTimerExpired = TimerExpired;
+
+		/*
+		 * If it has expired a number of times, then stop the timer
+		 * counter and stop this example
+		 */
+		if (TimerExpired == 3) {
+
+			XTmrCtr_Stop(TmrCtrInstancePtr, TmrCtrNumber);
+			break;
+		}
+	}
+
+	TmrCtrDisableIntr(IntcInstancePtr, DeviceId);
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the handler which performs processing for the timer counter.
+* It is called from an interrupt context such that the amount of processing
+* performed should be minimized.  It is called when the timer counter expires
+* if interrupts are enabled.
+*
+* This handler provides an example of how to handle timer counter interrupts
+* but is application specific.
+*
+* @param	CallBackRef is a pointer to the callback function
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber)
+{
+	XTmrCtr *InstancePtr = (XTmrCtr *)CallBackRef;
+
+	/*
+	 * Check if the timer counter has expired, checking is not necessary
+	 * since that's the reason this function is executed, this just shows
+	 * how the callback reference can be used as a pointer to the instance
+	 * of the timer counter that expired, increment a shared variable so
+	 * the main thread of execution can see the timer expired
+	 */
+	if (XTmrCtr_IsExpired(InstancePtr, TmrCtrNumber)) {
+		TimerExpired++;
+		if(TimerExpired == 3) {
+			XTmrCtr_SetOptions(InstancePtr, TmrCtrNumber, 0);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+* This function setups the interrupt system such that interrupts can occur
+* for the timer counter. This function is application specific since the actual
+* system may or may not have an interrupt controller.  The timer counter could
+* be directly connected to a processor without an interrupt controller.  The
+* user should modify this function to fit the application.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance.
+* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance.
+* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
+*		xparameters.h.
+* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
+*		value from xparameters.h.
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return
+*		- XST_SUCCESS if the initialization is successful
+*		- XST_FAILURE if the initialization is not successful
+*
+* @note		None
+*
+*
+******************************************************************************/
+static int TmrCtrSetupIntrSystem(XIntc* IntcInstancePtr,
+				 XTmrCtr* TmrCtrInstancePtr,
+				 u16 DeviceId,
+				 u16 IntrId,
+				 u8 TmrCtrNumber)
+{
+	 int Status;
+
+	/*
+	 * Initialize the interrupt controller driver so that
+	 * it's ready to use, specify the device ID that is generated in
+	 * xparameters.h
+	 */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect a Fast handler that will be called when an interrupt
+	 * for the device occurs.
+	 */
+	Status = XIntc_ConnectFastHandler(IntcInstancePtr, IntrId,
+				(XFastInterruptHandler)TmrCtr_FastHandler);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Start the interrupt controller such that interrupts are enabled for
+	 * all devices that cause interrupts, specific real mode so that
+	 * the timer counter can cause interrupts through the
+	 * interrupt controller.
+	 */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the interrupt for the timer counter
+	 */
+	XIntc_Enable(IntcInstancePtr, IntrId);
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+					(Xil_ExceptionHandler)
+					XIntc_InterruptHandler,
+					IntcInstancePtr);
+	/*
+	 * Enable non-critical exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts for the Timer.
+*
+* @param	IntcInstancePtr is a reference to the Interrupt Controller
+*		driver Instance.
+* @param	IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID
+*		value from xparameters.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId)
+{
+	/*
+	 * Disable the interrupt for the timer counter
+	 */
+	XIntc_Disable(IntcInstancePtr, IntrId);
+
+	return;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This is the Fast Interrupt Handler for the Timer.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void TmrCtr_FastHandler(void)
+{
+
+	/* Call the TmrCtr Interrupt handler */
+ 	XTmrCtr_InterruptHandler(&TimerCounterInst);
+}
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_intr_64bit_example.c b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_intr_64bit_example.c
new file mode 100644
index 000000000..4bdf801fb
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_intr_64bit_example.c
@@ -0,0 +1,464 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file  xtmrctr_intr_64bit_example.c
+*
+* This file contains a design example using the timer counter driver
+* (XTmCtr) and hardware device using interrupt mode with the counters configured
+* in  cascasde mode for a 64 bit operation. Both the timers should enabled in
+* HW configuration for the cascade mode of operation.
+*
+* The cascade mode of operation is present in the new versions of the
+* axi_timer IP. Please check the HW Datasheet to see whether this feature
+* is present in the version of the IP that you are using.
+*
+* This example assumes that the interrupt controller is also present as a part of
+* the system.
+*
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.04a sdm  07/15/11 Created based on the xtmrctr_intr_example
+*
+*</pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xtmrctr.h"
+#include "xintc.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TMRCTR_DEVICE_ID	XPAR_TMRCTR_0_DEVICE_ID
+#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
+#define TMRCTR_INTERRUPT_ID	XPAR_INTC_0_TMRCTR_0_VEC_ID
+
+/*
+ * The following constant determines which timer counter of the device that is
+ * used for this example, there are currently 2 timer counters in a device
+ * and this example uses the first one, 0, the timer numbers are 0 based
+ */
+#define TIMER_CNTR_0	 0
+#define TIMER_CNTR_1	 1
+
+/*
+ * The following constants are used to set the reset value of the timer counter,
+ * making this number larger reduces the amount of time this example consumes
+ * because it is the value the timer counter is loaded with when it is started
+ */
+#define RESET_VALUE_CNTR_0	 0xF0000000
+#define RESET_VALUE_CNTR_1	 0xFFFFFF00
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int TmrCtrCascadeIntrExample(XIntc* IntcInstancePtr,
+			XTmrCtr* InstancePtr,
+			u16 DeviceId,
+			u16 IntrId);
+
+static int TmrCtrSetupIntrSystem(XIntc* IntcInstancePtr,
+				XTmrCtr* InstancePtr,
+				u16 DeviceId,
+				u16 IntrId);
+
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber);
+
+void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId);
+
+/************************** Variable Definitions *****************************/
+
+XIntc InterruptController;  /* The instance of the Interrupt Controller */
+XTmrCtr TimerCounterInst;   /* The instance of the Timer Counter */
+
+/*
+ * The following variables are shared between non-interrupt processing and
+ * interrupt processing such that they must be global.
+ */
+volatile int TimerExpired;
+
+
+/*****************************************************************************/
+/**
+* This function is the main function of the Tmrctr 64 bit example using
+* Interrupts.
+*
+* @param	None.
+*
+* @return
+*
+*		- XST_SUCCESS to indicate success
+*		- XST_FAILURE to indicate a failure.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+
+	int Status;
+
+	/*
+	 * Run the Timer Counter Cascade mode - Interrupt example.
+	 */
+	Status = TmrCtrCascadeIntrExample(&InterruptController,
+				  &TimerCounterInst,
+				  TMRCTR_DEVICE_ID,
+				  TMRCTR_INTERRUPT_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+/*****************************************************************************/
+/**
+* This function does a minimal test on the timer counter device and driver as a
+* design example.  The purpose of this function is to illustrate how to use the
+* XTmrCtr driver in cascade mode of operation.  It initializes a timer counter
+* and then sets it up in compare mode with auto reload such that a periodic
+* interrupt is generated.
+*
+* This function uses interrupt driven mode of the timer counter.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance
+* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance
+* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
+*		xparameters.h
+* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
+*		value from xparameters.h
+*
+* @return
+*		- XST_SUCCESS if the Test is successful.
+*		- XST_FAILURE if the Test is Not Successful.
+*
+* @note		This function contains an infinite loop such that if interrupts
+*		are not working it may never return.
+*
+*****************************************************************************/
+int TmrCtrCascadeIntrExample(XIntc *IntcInstancePtr,
+				XTmrCtr *TmrCtrInstancePtr,
+				u16 DeviceId,
+				u16 IntrId)
+{
+	int Status;
+	int LastTimerExpired = 0;
+
+	/*
+	 * Initialize the timer counter so that it's ready to use,
+	 * specify the device ID that is generated in xparameters.h
+	 */
+	Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly, use the 1st timer in the device (0)
+	 */
+	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TIMER_CNTR_0);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly, use the 2nd timer in the device (0)
+	 */
+	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TIMER_CNTR_1);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the timer counter to the interrupt subsystem such that
+	 * interrupts can occur.  This function is application specific.
+	 * In the cascade mode only the interrupt from Timer Zero is valid.
+	 */
+	Status = TmrCtrSetupIntrSystem(IntcInstancePtr,
+					TmrCtrInstancePtr,
+					DeviceId,
+					IntrId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup the handler for the timer counter that will be called from the
+	 * interrupt context when the timer expires, specify a pointer to the
+	 * timer counter driver instance as the callback reference so the handler
+	 * is able to access the instance data
+	 */
+	XTmrCtr_SetHandler(TmrCtrInstancePtr, TimerCounterHandler,
+					   TmrCtrInstancePtr);
+
+
+	/*
+	 * Set a reset value for the timer counter such that it will expire
+	 * eariler than letting it roll over from 0, the reset value is loaded
+	 * into the timer counter when it is started
+	 */
+	XTmrCtr_SetResetValue(TmrCtrInstancePtr, TIMER_CNTR_0,
+				RESET_VALUE_CNTR_0);
+	XTmrCtr_SetResetValue(TmrCtrInstancePtr, TIMER_CNTR_1,
+				RESET_VALUE_CNTR_1);
+
+
+	/*
+	 * Enable the interrupt of the timer counter so interrupts will occur
+	 * and use auto reload mode such that the timer counter will reload
+	 * itself automatically and continue repeatedly, without this option
+	 * it would expire once only and set the Cascade mode.
+	 */
+	XTmrCtr_SetOptions(TmrCtrInstancePtr, TIMER_CNTR_0,
+				XTC_INT_MODE_OPTION |
+				XTC_AUTO_RELOAD_OPTION |
+				XTC_CASCADE_MODE_OPTION);
+
+	/*
+	 * Reset the timer counters such that it's incrementing by default
+	 */
+	 XTmrCtr_Reset(TmrCtrInstancePtr, TIMER_CNTR_0);
+	 XTmrCtr_Reset(TmrCtrInstancePtr, TIMER_CNTR_1);
+
+	/*
+	 * Start the timer counter 0 such that it's incrementing by default,
+	 * then wait for it to timeout a number of times.
+	 */
+	XTmrCtr_Start(TmrCtrInstancePtr, TIMER_CNTR_0);
+
+
+	while (1) {
+		/*
+		 * Wait for the first timer counter to expire as indicated by the
+		 * shared variable which the handler will increment
+		 */
+		while (TimerExpired == LastTimerExpired) {
+		}
+		LastTimerExpired = TimerExpired;
+
+		/*
+		 * If it has expired a number of times, then stop the timer counter
+		 * and stop this example
+		 */
+		if (TimerExpired == 3) {
+
+			XTmrCtr_Stop(TmrCtrInstancePtr, TIMER_CNTR_0);
+			break;
+		}
+	}
+
+	TmrCtrDisableIntr(IntcInstancePtr, DeviceId);
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the handler which performs processing for the timer counter.
+* It is called from an interrupt context such that the amount of processing
+* performed should be minimized.  It is called when the timer counter expires
+* if interrupts are enabled.
+*
+* This handler provides an example of how to handle timer counter interrupts
+* but is application specific.
+*
+* @param	CallBackRef is a pointer to the callback function
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber)
+{
+	XTmrCtr *InstancePtr = (XTmrCtr *)CallBackRef;
+
+	/*
+	 * Check if the timer counter has expired, checking is not necessary
+	 * since that's the reason this function is executed, this just shows
+	 * how the callback reference can be used as a pointer to the instance
+	 * of the timer counter that expired, increment a shared variable so
+	 * the main thread of execution can see the timer expired
+	 */
+	if (XTmrCtr_IsExpired(InstancePtr, TmrCtrNumber)) {
+		TimerExpired++;
+		if(TimerExpired == 3) {
+			XTmrCtr_SetOptions(InstancePtr, TmrCtrNumber, 0);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+* This function setups the interrupt system such that interrupts can occur
+* for the timer counter. This function is application specific since the actual
+* system may or may not have an interrupt controller.  The timer counter could
+* be directly connected to a processor without an interrupt controller.  The
+* user should modify this function to fit the application.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance.
+* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance.
+* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
+*		xparameters.h.
+* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
+*		value from xparameters.h.
+*
+* @return
+*		- XST_SUCCESS if the Test is successful
+*		- XST_FAILURE if the Test is not successful
+*
+* @note		This function contains an infinite loop such that if interrupts
+*		are not working it may never return.
+*
+******************************************************************************/
+static int TmrCtrSetupIntrSystem(XIntc* IntcInstancePtr,
+				 XTmrCtr* TmrCtrInstancePtr,
+				 u16 DeviceId,
+				 u16 IntrId)
+{
+	 int Status;
+
+
+	/*
+	 * Initialize the interrupt controller driver so that
+	 * it's ready to use, specify the device ID that is generated in
+	 * xparameters.h
+	 */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect a device driver handler that will be called when an interrupt
+	 * for the device occurs, the device driver handler performs the specific
+	 * interrupt processing for the device
+	 */
+	Status = XIntc_Connect(IntcInstancePtr, IntrId,
+				(XInterruptHandler)XTmrCtr_InterruptHandler,
+				(void *)TmrCtrInstancePtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Start the interrupt controller such that interrupts are enabled for
+	 * all devices that cause interrupts, specific real mode so that
+	 * the timer counter can cause interrupts thru the interrupt controller.
+	 */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Enable the interrupt for the timer counter
+	 */
+	XIntc_Enable(IntcInstancePtr, IntrId);
+
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+					(Xil_ExceptionHandler)
+					XIntc_InterruptHandler,
+					IntcInstancePtr);
+
+	/*
+	 * Enable non-critical exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+
+	return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function disables the interrupts for the Timer.
+*
+* @param	IntcInstancePtr is a reference to the Interrupt Controller
+*		driver Instance.
+* @param	IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID
+*		value from xparameters.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void TmrCtrDisableIntr(XIntc* IntcInstancePtr, u16 IntrId)
+{
+	/*
+	 * Disable the interrupt for the timer counter
+	 */
+	XIntc_Disable(IntcInstancePtr, IntrId);
+
+	return;
+}
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_intr_example.c b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_intr_example.c
new file mode 100644
index 000000000..1032d55fe
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_intr_example.c
@@ -0,0 +1,519 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file  xtmrctr_intr_example.c
+*
+* This file contains a design example using the timer counter driver
+* (XTmCtr) and hardware device using interrupt mode.This example assumes
+* that the interrupt controller is also present as a part of the system
+*
+* This file can be used as a standalone example or by the TestAppGen utility
+* to include a test for Timer interrupts.
+*
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/13/02 First release
+* 1.00b sv   04/26/05 Minor changes to comply to Doxygen and coding guidelines
+* 1.00b sn   05/09/06 Modified to be used by TestAppGen to include test for
+*		      interrupts.
+* 2.00a ktn  10/30/09 Updated to use HAL API's and minor changes as per coding
+*		      guidelines.
+* 2.00a ssb  01/11/01 Updated the example to be used with the SCUGIC in
+*		      Zynq.
+*</pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xtmrctr.h"
+#include "xil_exception.h"
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#include "xintc.h"
+#include <stdio.h>
+#else
+#include "xscugic.h"
+#include "xil_printf.h"
+#endif
+
+
+/************************** Constant Definitions *****************************/
+#ifndef TESTAPP_GEN
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TMRCTR_DEVICE_ID	XPAR_TMRCTR_0_DEVICE_ID
+#define TMRCTR_INTERRUPT_ID	XPAR_INTC_0_TMRCTR_0_VEC_ID
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
+#else
+#define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
+#endif /* XPAR_INTC_0_DEVICE_ID */
+
+
+/*
+ * The following constant determines which timer counter of the device that is
+ * used for this example, there are currently 2 timer counters in a device
+ * and this example uses the first one, 0, the timer numbers are 0 based
+ */
+#define TIMER_CNTR_0	 0
+
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC		XIntc
+#define INTC_HANDLER	XIntc_InterruptHandler
+#else
+#define INTC		XScuGic
+#define INTC_HANDLER	XScuGic_InterruptHandler
+#endif /* XPAR_INTC_0_DEVICE_ID */
+
+
+/*
+ * The following constant is used to set the reset value of the timer counter,
+ * making this number larger reduces the amount of time this example consumes
+ * because it is the value the timer counter is loaded with when it is started
+ */
+#define RESET_VALUE	 0xF0000000
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int TmrCtrIntrExample(INTC* IntcInstancePtr,
+			XTmrCtr* InstancePtr,
+			u16 DeviceId,
+			u16 IntrId,
+			u8 TmrCtrNumber);
+
+static int TmrCtrSetupIntrSystem(INTC* IntcInstancePtr,
+				XTmrCtr* InstancePtr,
+				u16 DeviceId,
+				u16 IntrId,
+				u8 TmrCtrNumber);
+
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber);
+
+void TmrCtrDisableIntr(INTC* IntcInstancePtr, u16 IntrId);
+
+/************************** Variable Definitions *****************************/
+#ifndef TESTAPP_GEN
+INTC InterruptController;  /* The instance of the Interrupt Controller */
+
+XTmrCtr TimerCounterInst;   /* The instance of the Timer Counter */
+#endif
+/*
+ * The following variables are shared between non-interrupt processing and
+ * interrupt processing such that they must be global.
+ */
+volatile int TimerExpired;
+
+
+/*****************************************************************************/
+/**
+* This function is the main function of the Tmrctr example using Interrupts.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, else XST_FAILURE to indicate a
+*		Failure.
+*
+* @note		None.
+*
+******************************************************************************/
+#ifndef TESTAPP_GEN
+int main(void)
+{
+
+	int Status;
+
+	/*
+	 * Run the Timer Counter - Interrupt example.
+	 */
+	Status = TmrCtrIntrExample(&InterruptController,
+				  &TimerCounterInst,
+				  TMRCTR_DEVICE_ID,
+				  TMRCTR_INTERRUPT_ID,
+				  TIMER_CNTR_0);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+* This function does a minimal test on the timer counter device and driver as a
+* design example.  The purpose of this function is to illustrate how to use the
+* XTmrCtr component.  It initializes a timer counter and then sets it up in
+* compare mode with auto reload such that a periodic interrupt is generated.
+*
+* This function uses interrupt driven mode of the timer counter.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance
+* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance
+* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
+*		xparameters.h
+* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_INTERRUPT_INTR
+*		value from xparameters.h
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return	XST_SUCCESS if the Test is successful, otherwise XST_FAILURE
+*
+* @note		This function contains an infinite loop such that if interrupts
+*		are not working it may never return.
+*
+*****************************************************************************/
+int TmrCtrIntrExample(INTC* IntcInstancePtr,
+			XTmrCtr* TmrCtrInstancePtr,
+			u16 DeviceId,
+			u16 IntrId,
+			u8 TmrCtrNumber)
+{
+	int Status;
+	int LastTimerExpired = 0;
+
+	/*
+	 * Initialize the timer counter so that it's ready to use,
+	 * specify the device ID that is generated in xparameters.h
+	 */
+	Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly, use the 1st timer in the device (0)
+	 */
+	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the timer counter to the interrupt subsystem such that
+	 * interrupts can occur.  This function is application specific.
+	 */
+	Status = TmrCtrSetupIntrSystem(IntcInstancePtr,
+					TmrCtrInstancePtr,
+					DeviceId,
+					IntrId,
+					TmrCtrNumber);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup the handler for the timer counter that will be called from the
+	 * interrupt context when the timer expires, specify a pointer to the
+	 * timer counter driver instance as the callback reference so the handler
+	 * is able to access the instance data
+	 */
+	XTmrCtr_SetHandler(TmrCtrInstancePtr, TimerCounterHandler,
+					   TmrCtrInstancePtr);
+
+	/*
+	 * Enable the interrupt of the timer counter so interrupts will occur
+	 * and use auto reload mode such that the timer counter will reload
+	 * itself automatically and continue repeatedly, without this option
+	 * it would expire once only
+	 */
+	XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber,
+				XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);
+
+	/*
+	 * Set a reset value for the timer counter such that it will expire
+	 * eariler than letting it roll over from 0, the reset value is loaded
+	 * into the timer counter when it is started
+	 */
+	XTmrCtr_SetResetValue(TmrCtrInstancePtr, TmrCtrNumber, RESET_VALUE);
+
+	/*
+	 * Start the timer counter such that it's incrementing by default,
+	 * then wait for it to timeout a number of times
+	 */
+	XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber);
+
+	while (1) {
+		/*
+		 * Wait for the first timer counter to expire as indicated by the
+		 * shared variable which the handler will increment
+		 */
+		while (TimerExpired == LastTimerExpired) {
+		}
+		LastTimerExpired = TimerExpired;
+
+		/*
+		 * If it has expired a number of times, then stop the timer counter
+		 * and stop this example
+		 */
+		if (TimerExpired == 3) {
+
+			XTmrCtr_Stop(TmrCtrInstancePtr, TmrCtrNumber);
+			break;
+		}
+	}
+
+	TmrCtrDisableIntr(IntcInstancePtr, DeviceId);
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the handler which performs processing for the timer counter.
+* It is called from an interrupt context such that the amount of processing
+* performed should be minimized.  It is called when the timer counter expires
+* if interrupts are enabled.
+*
+* This handler provides an example of how to handle timer counter interrupts
+* but is application specific.
+*
+* @param	CallBackRef is a pointer to the callback function
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber)
+{
+	XTmrCtr *InstancePtr = (XTmrCtr *)CallBackRef;
+
+	/*
+	 * Check if the timer counter has expired, checking is not necessary
+	 * since that's the reason this function is executed, this just shows
+	 * how the callback reference can be used as a pointer to the instance
+	 * of the timer counter that expired, increment a shared variable so
+	 * the main thread of execution can see the timer expired
+	 */
+	if (XTmrCtr_IsExpired(InstancePtr, TmrCtrNumber)) {
+		TimerExpired++;
+		if(TimerExpired == 3) {
+			XTmrCtr_SetOptions(InstancePtr, TmrCtrNumber, 0);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+* This function setups the interrupt system such that interrupts can occur
+* for the timer counter. This function is application specific since the actual
+* system may or may not have an interrupt controller.  The timer counter could
+* be directly connected to a processor without an interrupt controller.  The
+* user should modify this function to fit the application.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance.
+* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance.
+* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
+*		xparameters.h.
+* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
+*		value from xparameters.h.
+* @param	TmrCtrNumber is the number of the timer to which this
+*		handler is associated with.
+*
+* @return	XST_SUCCESS if the Test is successful, otherwise XST_FAILURE.
+*
+* @note		This function contains an infinite loop such that if interrupts
+*		are not working it may never return.
+*
+******************************************************************************/
+static int TmrCtrSetupIntrSystem(INTC* IntcInstancePtr,
+				 XTmrCtr* TmrCtrInstancePtr,
+				 u16 DeviceId,
+				 u16 IntrId,
+				 u8 TmrCtrNumber)
+{
+	 int Status;
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#ifndef TESTAPP_GEN
+	/*
+	 * Initialize the interrupt controller driver so that
+	 * it's ready to use, specify the device ID that is generated in
+	 * xparameters.h
+	 */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+#endif
+	/*
+	 * Connect a device driver handler that will be called when an interrupt
+	 * for the device occurs, the device driver handler performs the specific
+	 * interrupt processing for the device
+	 */
+	Status = XIntc_Connect(IntcInstancePtr, IntrId,
+				(XInterruptHandler)XTmrCtr_InterruptHandler,
+				(void *)TmrCtrInstancePtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+#ifndef TESTAPP_GEN
+	/*
+	 * Start the interrupt controller such that interrupts are enabled for
+	 * all devices that cause interrupts, specific real mode so that
+	 * the timer counter can cause interrupts thru the interrupt controller.
+	 */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+#endif
+
+	/*
+	 * Enable the interrupt for the timer counter
+	 */
+	XIntc_Enable(IntcInstancePtr, IntrId);
+
+#else
+
+#ifndef TESTAPP_GEN
+	XScuGic_Config *IntcConfig;
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+					IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+#endif /* TESTAPP_GEN */
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, IntrId,
+					0xA0, 0x3);
+
+	/*
+	 * Connect the interrupt handler that will be called when an
+	 * interrupt occurs for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, IntrId,
+				 (Xil_ExceptionHandler)XTmrCtr_InterruptHandler,
+				 TmrCtrInstancePtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Enable the interrupt for the Timer device.
+	 */
+	XScuGic_Enable(IntcInstancePtr, IntrId);
+#endif /* XPAR_INTC_0_DEVICE_ID */
+
+
+#ifndef TESTAPP_GEN
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+					(Xil_ExceptionHandler)
+					INTC_HANDLER,
+					IntcInstancePtr);
+
+	/*
+	 * Enable non-critical exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+#endif
+	return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function disables the interrupts for the Timer.
+*
+* @param	IntcInstancePtr is a reference to the Interrupt Controller
+*		driver Instance.
+* @param	IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID
+*		value from xparameters.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void TmrCtrDisableIntr(INTC* IntcInstancePtr, u16 IntrId)
+{
+	/*
+	 * Disable the interrupt for the timer counter
+	 */
+#ifdef XPAR_INTC_0_DEVICE_ID
+	XIntc_Disable(IntcInstancePtr, IntrId);
+#else
+	/* Disconnect the interrupt */
+	XScuGic_Disable(IntcInstancePtr, IntrId);
+	XScuGic_Disconnect(IntcInstancePtr, IntrId);
+#endif
+
+	return;
+}
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_low_level_example.c b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_low_level_example.c
new file mode 100644
index 000000000..45df19806
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_low_level_example.c
@@ -0,0 +1,200 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file  xtmrctr_low_level_example.c
+*
+* This file contains a design example using the Timer Counter (XTmrCtr)
+* low level driver and hardware device in a polled mode.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/13/02 First release
+* 1.00b sv   04/26/05 Minor changes to comply to Doxygen and coding guidelines
+* 2.00a ktn  10/30/09 Updated the example as the macros in the driver are
+*                     renamed by removing _m in the definition.
+*                     Minor changes as per coding guidelines are done.
+*</pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xtmrctr_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TMRCTR_BASEADDR		XPAR_TMRCTR_0_BASEADDR
+
+/*
+ * This example only uses the 1st of the 2 timer counters contained in a
+ * single timer counter hardware device
+ */
+#define TIMER_COUNTER_0	 0
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int TmrCtrLowLevelExample(u32 TmrCtrBaseAddress, u8 TimerCounter);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* This function is the main function of the Tmrctr low level example.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, else XST_FAILURE to indicate
+*		a Failure.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the Timer Counter - Low Level example .
+	 */
+	Status = TmrCtrLowLevelExample(TMRCTR_BASEADDR, TIMER_COUNTER_0);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+/*****************************************************************************/
+/**
+* This function does a minimal test on the timer counter device and
+* the low level driver as a design example.  The purpose of this function is
+* to illustrate how to use the XTmrCtr low level driver.
+*
+*
+* @param	TmrCtrBaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters.
+*		The timer number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	XST_SUCCESS to indicate success, else XST_FAILURE to indicate
+*		a Failure.
+*
+* @note
+*
+* This function contains a loop which waits for the value of a timer counter
+* to change.  If the hardware is not working correctly, this function may not
+* return.
+*
+****************************************************************************/
+int TmrCtrLowLevelExample(u32 TmrCtrBaseAddress, u8 TmrCtrNumber)
+{
+	u32 Value1;
+	u32 Value2;
+	u32 ControlStatus;
+
+	/*
+	 * Clear the Control Status Register
+	 */
+	XTmrCtr_SetControlStatusReg(TmrCtrBaseAddress, TmrCtrNumber,0x0);
+
+	/*
+	 * Set the value that is loaded into the timer counter and cause it to
+	 * be loaded into the timer counter
+	 */
+	XTmrCtr_SetLoadReg(TmrCtrBaseAddress, TmrCtrNumber, 0xDEADBEEF);
+	XTmrCtr_LoadTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber);
+
+	/*
+	 * Clear the Load Timer bit in the Control Status Register
+	 */
+	ControlStatus = XTmrCtr_GetControlStatusReg(TmrCtrBaseAddress,
+						 TmrCtrNumber);
+	XTmrCtr_SetControlStatusReg(TmrCtrBaseAddress, TmrCtrNumber,
+				 ControlStatus & (~XTC_CSR_LOAD_MASK));
+
+	/*
+	 * Get a snapshot of the timer counter value before it's started
+	 * to compare against later
+	 */
+	Value1 = XTmrCtr_GetTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber);
+
+	/*
+	 * Start the timer counter such that it's incrementing by default
+	 */
+	XTmrCtr_Enable(TmrCtrBaseAddress, TmrCtrNumber);
+
+	/*
+	 * Read the value of the timer counter and wait for it to change,
+	 * since it's incrementing it should change, if the hardware is not
+	 * working for some reason, this loop could be infinite such that the
+	 * function does not return
+	 */
+	while (1) {
+		Value2 = XTmrCtr_GetTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber);
+
+		if (Value1 != Value2) {
+			break;
+		}
+	}
+
+	/*
+	 * Disable the timer counter such that it stops incrementing
+	 */
+	XTmrCtr_Disable(TmrCtrBaseAddress, TmrCtrNumber);
+
+	return XST_SUCCESS;
+}
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_polled_example.c b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_polled_example.c
new file mode 100644
index 000000000..b47d2effb
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_polled_example.c
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file  xtmrctr_polled_example.c
+*
+* This file contains a design example using the Timer Counter driver (XTmrCtr)
+* and hardware device in a polled mode.
+*
+* @note
+*
+* None.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/13/02 First release
+* 1.00b sv   04/26/05 Minor changes to comply to Doxygen and coding guidelines.
+* 2.00a ktn  11/26/09 Minor changes as per coding guidelines.
+*
+*</pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xtmrctr.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TMRCTR_DEVICE_ID	XPAR_TMRCTR_0_DEVICE_ID
+
+
+/*
+ * This example only uses the 1st of the 2 timer counters contained in a
+ * single timer counter hardware device
+ */
+#define TIMER_COUNTER_0	 0
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int TmrCtrPolledExample(u16 DeviceId, u8 TmrCtrNumber);
+
+/************************** Variable Definitions *****************************/
+
+XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */
+
+
+/*****************************************************************************/
+/**
+* Main function to call the polled example.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, else XST_FAILURE to indicate
+*		a Failure.
+*
+* @note		None.
+*
+******************************************************************************/
+int main(void)
+{
+
+	int Status;
+
+	/*
+	 * Run the Timer Counter - Polled Example
+	 */
+	Status = TmrCtrPolledExample(TMRCTR_DEVICE_ID, TIMER_COUNTER_0);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+
+/*****************************************************************************/
+/**
+* This function does a minimal test on the timer counter device and
+* driver as a design example. The purpose of this function is to illustrate
+* how to use the XTmrCtr component in a polled mode.
+*
+*
+* @param	DeviceId is the XPAR_<TMRCTR_instance>_DEVICE_ID value from
+*		xparameters.h
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		 Each device may contain multiple timer counters.
+*		The timer number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	XST_SUCCESS to indicate success, else XST_FAILURE to indicate
+*		a Failure.
+*
+* @note
+*
+* This function contains a loop which waits for the value of a timer counter
+* to change. If the hardware is not working correctly, this function may not
+* return.
+*
+****************************************************************************/
+int TmrCtrPolledExample(u16 DeviceId, u8 TmrCtrNumber)
+{
+	int Status;
+	u32 Value1;
+	u32 Value2;
+	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
+
+	/*
+	 * Initialize the timer counter so that it's ready to use,
+	 * specify the device ID that is generated in xparameters.h
+	 */
+	Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly, use the 1st timer in the device (0)
+	 */
+	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Enable the Autoreload mode of the timer counters.
+	 */
+	XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber,
+				XTC_AUTO_RELOAD_OPTION);
+
+	/*
+	 * Get a snapshot of the timer counter value before it's started
+	 * to compare against later
+	 */
+	Value1 = XTmrCtr_GetValue(TmrCtrInstancePtr, TmrCtrNumber);
+
+	/*
+	 * Start the timer counter such that it's incrementing by default
+	 */
+	XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber);
+
+	/*
+	 * Read the value of the timer counter and wait for it to change,
+	 * since it's incrementing it should change, if the hardware is not
+	 * working for some reason, this loop could be infinite such that the
+	 * function does not return
+	 */
+	while (1) {
+		Value2 = XTmrCtr_GetValue(TmrCtrInstancePtr, TmrCtrNumber);
+		if (Value1 != Value2) {
+			break;
+		}
+	}
+
+	/*
+	 * Disable the Autoreload mode of the timer counters.
+	 */
+	XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber, 0);
+
+	return XST_SUCCESS;
+}
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_selftest_example.c b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_selftest_example.c
new file mode 100644
index 000000000..142fb8d5d
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/examples/xtmrctr_selftest_example.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtmrctr_selftest_example.c
+*
+* This file contains a example for  using the Timer Counter hardware and
+* driver
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   04/25/05 Initial release for TestApp integration.
+* 2.00a ktn  11/26/09 Minor changes as per coding guidelines.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xtmrctr.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TMRCTR_DEVICE_ID  XPAR_TMRCTR_0_DEVICE_ID
+
+/*
+ * This example only uses the 1st of the 2 timer counters contained in a
+ * single timer counter hardware device
+ */
+#define TIMER_COUNTER_0	 0
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *******************/
+
+
+/************************** Function Prototypes ****************************/
+
+int TmrCtrSelfTestExample(u16 DeviceId, u8 TmrCtrNumber);
+
+/************************** Variable Definitions **************************/
+
+XTmrCtr TimerCounter; /* The instance of the timer counter */
+
+
+/*****************************************************************************/
+/**
+* Main function to call the example. This function is not included if the
+* example is generated from the TestAppGen test tool.
+*
+* @param	None
+*
+* @return   XST_SUCCESS to indicate success, else XST_FAILURE to indicate
+*		   a Failure.
+*
+* @note	 None
+*
+******************************************************************************/
+#ifndef TESTAPP_GEN
+int main(void)
+{
+	int Status;
+
+	Status = TmrCtrSelfTestExample(TMRCTR_DEVICE_ID, TIMER_COUNTER_0);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* This function does a minimal test on the TmrCtr device and driver as a
+* design example. The purpose of this function is to illustrate
+* how to use the XTmrCtr component.
+*
+*
+* @param	DeviceId is the XPAR_<TMRCTR_instance>_DEVICE_ID value from
+*		xparameters.h
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters.
+*		The timer number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	XST_SUCCESS if successful, XST_FAILURE if unsuccessful
+*
+* @note		None
+*
+****************************************************************************/
+int TmrCtrSelfTestExample(u16 DeviceId, u8 TmrCtrNumber)
+{
+	int Status;
+	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
+
+	/*
+	 * Initialize the TmrCtr driver so that it iss ready to use
+	 */
+	Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built
+	 * correctly, use the 1st timer in the device (0)
+	 */
+	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/Makefile b/thirdparty/xilinx/orig/tmrctr_v4_0/src/Makefile
new file mode 100644
index 000000000..20fb57c34
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/Makefile
@@ -0,0 +1,28 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o 
+
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+	echo "Compiling tmrctr"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr.c
new file mode 100644
index 000000000..cba0c0d84
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr.c
@@ -0,0 +1,536 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* Contains required functions for the XTmrCtr driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.05a adk  15/05/13 Fixed the CR:693066
+*		      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
+*		      XTmrCtr instance structure.
+*		      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
+*		      the XTmrCtr_Start function.
+*		      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
+*		      There will be no Initialization done in the
+*		      XTmrCtr_Initialize if both the timers have already started and
+*		      the XST_DEVICE_IS_STARTED Status is returned.
+*		      Removed the logic in the XTmrCtr_Initialize function
+*		      which was checking the Register Value to know whether
+*		      a timer has started or not.
+* 4.0   als  09/30/15 Updated initialization API.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xtmrctr.h"
+#include "xtmrctr_i.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+static void XTmrCtr_StubCallback(void *CallBackRef, u8 TmrCtrNumber);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function populates the timer counter's configuration structure and sets
+* some configurations defaults.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	ConfigPtr is a pointer to the configuration structure that will
+*		be used to copy the settings from.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		space. If the address translation is not used, then the physical
+*		address is passed.
+*
+* @return	None.
+*
+* @note		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+******************************************************************************/
+void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
+		u32 EffectiveAddr)
+{
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(ConfigPtr != NULL);
+	Xil_AssertVoid(EffectiveAddr != 0x0);
+
+	InstancePtr->IsReady = 0;
+	InstancePtr->Config = *ConfigPtr;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->BaseAddress = EffectiveAddr;
+
+	InstancePtr->Handler = XTmrCtr_StubCallback;
+	InstancePtr->CallBackRef = InstancePtr;
+	InstancePtr->Stats.Interrupts = 0;
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+}
+
+/*****************************************************************************/
+/**
+* (Re-)initialzes all timer counters which aren't started already.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+*
+* @return
+*		- XST_SUCCESS if at least one timer counter is stopped.
+*		- XST_DEVICE_IS_STARTED otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+int XTmrCtr_InitHw(XTmrCtr *InstancePtr)
+{
+	int Status = XST_DEVICE_IS_STARTED;
+	u8 TmrIndex;
+	u32 TmrCtrStarted[XTC_DEVICE_TIMER_COUNT];
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	TmrCtrStarted[0] = InstancePtr->IsStartedTmrCtr0;
+	TmrCtrStarted[1] = InstancePtr->IsStartedTmrCtr1;
+
+	for (TmrIndex = 0; TmrIndex < XTC_DEVICE_TIMER_COUNT; TmrIndex++) {
+		/* Only initialize timers counters which aren't started. */
+		if (TmrCtrStarted[TmrIndex] == XIL_COMPONENT_IS_STARTED) {
+			continue;
+		}
+
+		/* Set the compare register to 0. */
+		XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrIndex,
+				  XTC_TLR_OFFSET, 0);
+		/* Reset the timer and the interrupt. */
+		XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrIndex,
+				  XTC_TCSR_OFFSET,
+				  XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
+		/* Release the reset. */
+		XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrIndex,
+				  XTC_TCSR_OFFSET, 0);
+
+		/* Indicate that at least one timer is not running and has been
+		 * initialized. */
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Initializes a specific timer/counter instance/driver. Initialize fields of
+* the XTmrCtr structure, then reset the timer/counter.If a timer is already
+* running then it is not initialized.
+*
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	DeviceId is the unique id of the device controlled by this
+*		XTmrCtr component.  Passing in a device id associates the
+*		generic XTmrCtr component to a specific device, as chosen by
+*		the caller or application developer.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*		- XST_DEVICE_IS_STARTED if the device has already been started
+*		- XST_DEVICE_NOT_FOUND if the device doesn't exist
+*
+* @note		None.
+*
+******************************************************************************/
+int XTmrCtr_Initialize(XTmrCtr *InstancePtr, u16 DeviceId)
+{
+	XTmrCtr_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* In case all timer counters are already started, don't proceed with
+	 * re-initialization. */
+	if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED) &&
+	    (InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/* Retrieve configuration of timer counter core with matching ID. */
+	ConfigPtr = XTmrCtr_LookupConfig(DeviceId);
+	if (!ConfigPtr) {
+		return XST_DEVICE_NOT_FOUND;
+	}
+
+	XTmrCtr_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddress);
+
+	return XTmrCtr_InitHw(InstancePtr);
+}
+
+/*****************************************************************************/
+/**
+*
+* Starts the specified timer counter of the device such that it starts running.
+* The timer counter is reset before it is started and the reset value is
+* loaded into the timer counter.
+*
+* If interrupt mode is specified in the options, it is necessary for the caller
+* to connect the interrupt handler of the timer/counter to the interrupt source,
+* typically an interrupt controller, and enable the interrupt within the
+* interrupt controller.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+	u32 ControlStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the current register contents such that only the necessary bits
+	 * of the register are modified in the following operations
+	 */
+	ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+					      TmrCtrNumber, XTC_TCSR_OFFSET);
+	/*
+	 * Reset the timer counter such that it reloads from the compare
+	 * register and the interrupt is cleared simultaneously, the interrupt
+	 * can only be cleared after reset such that the interrupt condition is
+	 * cleared
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET,
+			  XTC_CSR_LOAD_MASK);
+
+
+
+	/*
+	 * Indicate that the timer is started before enabling it
+	 */
+	if (TmrCtrNumber == 0) {
+		InstancePtr->IsStartedTmrCtr0 = XIL_COMPONENT_IS_STARTED;
+	} else {
+		InstancePtr->IsStartedTmrCtr1 = XIL_COMPONENT_IS_STARTED;
+	}
+
+
+	/*
+	 * Remove the reset condition such that the timer counter starts running
+	 * with the value loaded from the compare register
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET,
+			  ControlStatusReg | XTC_CSR_ENABLE_TMR_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* Stops the timer counter by disabling it.
+*
+* It is the callers' responsibility to disconnect the interrupt handler of the
+* timer_counter from the interrupt source, typically an interrupt controller,
+* and disable the interrupt within the interrupt controller.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+	u32 ControlStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the current register contents
+	 */
+	ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+					      TmrCtrNumber, XTC_TCSR_OFFSET);
+	/*
+	 * Disable the timer counter such that it's not running
+	 */
+	ControlStatusReg &= ~(XTC_CSR_ENABLE_TMR_MASK);
+
+	/*
+	 * Write out the updated value to the actual register.
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET, ControlStatusReg);
+
+	/*
+	 * Indicate that the timer is stopped
+	 */
+	if (TmrCtrNumber == 0) {
+		InstancePtr->IsStartedTmrCtr0 = 0;
+	} else {
+		InstancePtr->IsStartedTmrCtr1 = 0;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the current value of the specified timer counter.  The timer counter
+* may be either incrementing or decrementing based upon the current mode of
+* operation.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number  with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The current value for the timer counter.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+				  TmrCtrNumber, XTC_TCR_OFFSET);
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the reset value for the specified timer counter. This is the value
+* that is loaded into the timer counter when it is reset. This value is also
+* loaded when the timer counter is started.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number  with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	ResetValue contains the value to be used to reset the timer
+*		counter.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
+			   u32 ResetValue)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TLR_OFFSET, ResetValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* Returns the timer counter value that was captured the last time the external
+* capture input was asserted.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number  with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The current capture value for the indicated timer counter.
+*
+* @note		None.
+*
+*******************************************************************************/
+u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+				  TmrCtrNumber, XTC_TLR_OFFSET);
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the specified timer counter of the device. A reset causes the timer
+* counter to set it's value to the reset value.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number  with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+	u32 CounterControlReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read current contents of the register so it won't be destroyed
+	 */
+	CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+					       TmrCtrNumber, XTC_TCSR_OFFSET);
+	/*
+	 * Reset the timer by toggling the reset bit in the register
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET,
+			  CounterControlReg | XTC_CSR_LOAD_MASK);
+
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET, CounterControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks if the specified timer counter of the device has expired. In capture
+* mode, expired is defined as a capture occurred. In compare mode, expired is
+* defined as the timer counter rolled over/under for up/down counting.
+*
+* When interrupts are enabled, the expiration causes an interrupt. This function
+* is typically used to poll a timer counter to determine when it has expired.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number  with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	TRUE if the timer has expired, and FALSE otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+	u32 CounterControlReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check if timer is expired
+	 */
+	CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+					       TmrCtrNumber, XTC_TCSR_OFFSET);
+
+	return ((CounterControlReg & XTC_CSR_INT_OCCURED_MASK) ==
+		XTC_CSR_INT_OCCURED_MASK);
+}
+
+/*****************************************************************************/
+/**
+* Default callback for the driver does nothing. It matches the signature of the
+* XTmrCtr_Handler type.
+*
+* @param	CallBackRef is a pointer to the callback's data.
+* @param	TmrCtrNumber is the ID of the timer counter which a user-defined
+*		callback would normally operate on.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XTmrCtr_StubCallback(void *CallBackRef, u8 TmrCtrNumber)
+{
+	Xil_AssertVoid(CallBackRef != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+}
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr.h b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr.h
new file mode 100644
index 000000000..5b8238043
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr.h
@@ -0,0 +1,303 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr.h
+* @addtogroup tmrctr_v4_0
+* @{
+* @details
+*
+* The Xilinx timer/counter component. This component supports the Xilinx
+* timer/counter. More detailed description of the driver operation can
+* be found in the xtmrctr.c file.
+*
+* The Xilinx timer/counter supports the following features:
+*   - Polled mode.
+*   - Interrupt driven mode
+*   - enabling and disabling specific timers
+*   - PWM operation
+*   - Cascade Operation (This is to be used for getting a 64 bit timer and this
+*     feature is present in the latest versions of the axi_timer IP)
+*
+* The driver does not currently support the PWM operation of the device.
+*
+* The timer counter operates in 2 primary modes, compare and capture. In
+* either mode, the timer counter may count up or down, with up being the
+* default.
+*
+* Compare mode is typically used for creating a single time period or multiple
+* repeating time periods in the auto reload mode, such as a periodic interrupt.
+* When started, the timer counter loads an initial value, referred to as the
+* compare value, into the timer counter and starts counting down or up. The
+* timer counter expires when it rolls over/under depending upon the mode of
+* counting. An external compare output signal may be configured such that a
+* pulse is generated with this signal when it hits the compare value.
+*
+* Capture mode is typically used for measuring the time period between
+* external events. This mode uses an external capture input signal to cause
+* the value of the timer counter to be captured. When started, the timer
+* counter loads an initial value, referred to as the compare value,
+
+* The timer can be configured to either cause an interrupt when the count
+* reaches the compare value in compare mode or latch the current count
+* value in the capture register when an external input is asserted
+* in capture mode. The external capture input can be enabled/disabled using the
+* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
+* drive an external output when the compare value is reached in the count
+* register The external compare output can be enabled/disabled using the
+* XTmrCtr_SetOptions function.
+*
+* <b>Interrupts</b>
+*
+* It is the responsibility of the application to connect the interrupt
+* handler of the timer/counter to the interrupt source. The interrupt
+* handler function, XTmrCtr_InterruptHandler, is visible such that the user
+* can connect it to the interrupt source. Note that this interrupt handler
+* does not provide interrupt context save and restore processing, the user
+* must perform this processing.
+*
+* The driver services interrupts and passes timeouts to the upper layer
+* software through callback functions. The upper layer software must register
+* its callback functions during initialization. The driver requires callback
+* functions for timers.
+*
+* @note
+* The default settings for the timers are:
+*   - Interrupt generation disabled
+*   - Count up mode
+*   - Compare mode
+*   - Hold counter (will not reload the timer)
+*   - External compare output disabled
+*   - External capture input disabled
+*   - Pulse width modulation disabled
+*   - Timer disabled, waits for Start function to be called
+* <br><br>
+* A timer counter device may contain multiple timer counters. The symbol
+* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
+* The device currently contains 2 timer counters.
+* <br><br>
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.10b mta  03/21/07 Updated to new coding style.
+* 1.11a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+*		      file
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+*		      for naming consistency (CR 559142).
+* 2.02a sdm  09/28/10 Updated the driver tcl to generate the xparameters
+*		      for the timer clock frequency (CR 572679).
+* 2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
+*		      processing for CR 584557.
+* 2.04a sdm  07/12/11 Added support for cascade mode operation.
+* 		      The cascade mode of operation is present in the latest
+*		      versions of the axi_timer IP. Please check the HW
+*		      Datasheet to see whether this feature is present in the
+*		      version of the IP that you are using.
+* 2.05a adk  15/05/13 Fixed the CR:693066
+*		      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
+*		      XTmrCtr instance structure.
+*		      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
+*		      the XTmrCtr_Start function.
+*		      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
+*		      There will be no Initialization done in the
+*		      XTmrCtr_Initialize if both the timers have already started and
+*		      the XST_DEVICE_IS_STARTED Status is returned.
+*		      Removed the logic in the XTmrCtr_Initialize function
+*		      which was checking the Register Value to know whether
+*		      a timer has started or not.
+* 3.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.0   als  09/30/15 Updated initialization API.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_H		/* prevent circular inclusions */
+#define XTMRCTR_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xtmrctr_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Configuration options
+ * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
+ * @{
+ */
+/**
+ * Used to configure the timer counter device.
+ * <pre>
+ * XTC_CASCADE_MODE_OPTION	Enables the Cascade Mode only valid for TCSRO.
+ * XTC_ENABLE_ALL_OPTION	Enables all timer counters at once.
+ * XTC_DOWN_COUNT_OPTION	Configures the timer counter to count down from
+ *				start value, the default is to count up.
+ * XTC_CAPTURE_MODE_OPTION	Configures the timer to capture the timer
+ *				counter value when the external capture line is
+ *				asserted. The default mode is compare mode.
+ * XTC_INT_MODE_OPTION		Enables the timer counter interrupt output.
+ * XTC_AUTO_RELOAD_OPTION	In compare mode, configures the timer counter to
+ *				reload from the compare value. The default mode
+ *				causes the timer counter to hold when the
+ *				compare value is hit.
+ *				In capture mode, configures the timer counter to
+ *				not hold the previous capture value if a new
+ *				event occurs. The default mode cause the timer
+ *				counter to hold the capture value until
+ *				recognized.
+ * XTC_EXT_COMPARE_OPTION	Enables the external compare output signal.
+ * </pre>
+ */
+#define XTC_CASCADE_MODE_OPTION		0x00000080UL
+#define XTC_ENABLE_ALL_OPTION		0x00000040UL
+#define XTC_DOWN_COUNT_OPTION		0x00000020UL
+#define XTC_CAPTURE_MODE_OPTION		0x00000010UL
+#define XTC_INT_MODE_OPTION		0x00000008UL
+#define XTC_AUTO_RELOAD_OPTION		0x00000004UL
+#define XTC_EXT_COMPARE_OPTION		0x00000002UL
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	u32 SysClockFreqHz;	/**< The AXI bus clock frequency */
+} XTmrCtr_Config;
+
+/**
+ * Signature for the callback function.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions, and passed back to the
+ *		upper layer when the callback is invoked. Its type is
+ *		 unimportant to the driver, so it is a void pointer.
+ * @param 	TmrCtrNumber is the number of the timer/counter within the
+ *		device. The device typically contains at least two
+ *		timer/counters. The timer number is a zero based number with a
+ *		range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
+ */
+typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
+
+
+/**
+ * Timer/Counter statistics
+ */
+typedef struct {
+	u32 Interrupts;	 /**< The number of interrupts that have occurred */
+} XTmrCtrStats;
+
+/**
+ * The XTmrCtr driver instance data. The user is required to allocate a
+ * variable of this type for every timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XTmrCtr_Config Config;   /**< Core configuration. */
+	XTmrCtrStats Stats;	 /**< Component Statistics */
+	u32 BaseAddress;	 /**< Base address of registers */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 IsStartedTmrCtr0;	 /**< Is Timer Counter 0 started */
+	u32 IsStartedTmrCtr1;	 /**< Is Timer Counter 1 started */
+
+	XTmrCtr_Handler Handler; /**< Callback function */
+	void *CallBackRef;	 /**< Callback reference for handler */
+} XTmrCtr;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* Required functions, in file xtmrctr.c */
+void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
+		u32 EffectiveAddr);
+int XTmrCtr_InitHw(XTmrCtr *InstancePtr);
+int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
+void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
+			   u32 ResetValue);
+u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Lookup configuration in xtmrctr_sinit.c */
+XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
+
+/* Functions for options, in file xtmrctr_options.c */
+void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
+u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Functions for statistics, in file xtmrctr_stats.c */
+void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
+void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
+
+/* Functions for self-test, in file xtmrctr_selftest.c */
+int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Functions for interrupts, in file xtmrctr_intr.c */
+void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
+			void *CallBackRef);
+void XTmrCtr_InterruptHandler(void *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_g.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_g.c
new file mode 100644
index 000000000..074550e73
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_g.c
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_g.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* This file contains a configuration table that specifies the configuration of
+* timer/counter devices in the system. Each timer/counter device should have
+* an entry in this table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.10b mta  03/21/07 Updated to new coding style
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xtmrctr.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Prototypes ******************************/
+
+/**
+ * The timer/counter configuration table, sized by the number of instances
+ * defined in xparameters.h.
+ */
+XTmrCtr_Config XTmrCtr_ConfigTable[] = {
+#if defined(XPAR_XTMRCTR_NUM_INSTANCES) && (XPAR_XTMRCTR_NUM_INSTANCES > 0)
+	{
+		XPAR_TMRCTR_0_DEVICE_ID,
+		XPAR_TMRCTR_0_BASEADDR,
+		XPAR_TMRCTR_0_CLOCK_FREQ_HZ,
+	}
+#endif
+};
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_i.h b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_i.h
new file mode 100644
index 000000000..6cbbc0a46
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_i.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_i.h
+* @addtogroup tmrctr_v3_0
+* @{
+*
+* This file contains data which is shared between files internal to the
+* XTmrCtr component. It is intended for internal use only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 _m is removed from all the macro definitions.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_I_H		/* prevent circular inclusions */
+#define XTMRCTR_I_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern u8 XTmrCtr_Offsets[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_intr.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_intr.c
new file mode 100644
index 000000000..d432837e2
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_intr.c
@@ -0,0 +1,233 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_intr.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* Contains interrupt-related functions for the XTmrCtr component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
+*		      processing for CR 584557.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xtmrctr.h"
+
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Sets the timer callback function, which the driver calls when the specified
+* timer times out.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance .
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context so the function that is
+* called should either be short or pass the more extensive processing off
+* to another task to allow the interrupt to return and normal processing
+* to continue.
+*
+******************************************************************************/
+void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
+			void *CallBackRef)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* Interrupt Service Routine (ISR) for the driver.  This function only performs
+* processing for the device and does not save and restore the interrupt context.
+*
+* @param	InstancePtr contains a pointer to the timer/counter instance for
+*		the interrupt.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_InterruptHandler(void *InstancePtr)
+{
+	XTmrCtr *TmrCtrPtr = NULL;
+	u8 TmrCtrNumber;
+	u32 ControlStatusReg;
+
+	/*
+	 * Verify that each of the inputs are valid.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/*
+	 * Convert the non-typed pointer to an timer/counter instance pointer
+	 * such that there is access to the timer/counter
+	 */
+	TmrCtrPtr = (XTmrCtr *) InstancePtr;
+
+	/*
+	 * Loop thru each timer counter in the device and call the callback
+	 * function for each timer which has caused an interrupt
+	 */
+	for (TmrCtrNumber = 0;
+		TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) {
+
+		ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
+						   TmrCtrNumber,
+						   XTC_TCSR_OFFSET);
+		/*
+		 * Check if interrupt is enabled
+		 */
+		if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) {
+
+			/*
+			 * Check if timer expired and interrupt occured
+			 */
+			if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) {
+				/*
+				 * Increment statistics for the number of
+				 * interrupts and call the callback to handle
+				 * any application specific processing
+				 */
+				TmrCtrPtr->Stats.Interrupts++;
+				TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef,
+						   TmrCtrNumber);
+				/*
+				 * Read the new Control/Status Register content.
+				 */
+				ControlStatusReg =
+					XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
+								TmrCtrNumber,
+								XTC_TCSR_OFFSET);
+				/*
+				 * If in compare mode and a single shot rather
+				 * than auto reload mode then disable the timer
+				 * and reset it such so that the interrupt can
+				 * be acknowledged, this should be only temporary
+				 * till the hardware is fixed
+				 */
+				if (((ControlStatusReg &
+					XTC_CSR_AUTO_RELOAD_MASK) == 0) &&
+					((ControlStatusReg &
+					  XTC_CSR_CAPTURE_MODE_MASK)== 0)) {
+						/*
+						 * Disable the timer counter and
+						 * reset it such that the timer
+						 * counter is loaded with the
+						 * reset value allowing the
+						 * interrupt to be acknowledged
+						 */
+						ControlStatusReg &=
+							~XTC_CSR_ENABLE_TMR_MASK;
+
+						XTmrCtr_WriteReg(
+							TmrCtrPtr->BaseAddress,
+							TmrCtrNumber,
+							XTC_TCSR_OFFSET,
+							ControlStatusReg |
+							XTC_CSR_LOAD_MASK);
+
+						/*
+						 * Clear the reset condition,
+						 * the reset bit must be
+						 * manually cleared by a 2nd write
+						 * to the register
+						 */
+						XTmrCtr_WriteReg(
+							TmrCtrPtr->BaseAddress,
+							TmrCtrNumber,
+							XTC_TCSR_OFFSET,
+							ControlStatusReg);
+				}
+
+				/*
+				 * Acknowledge the interrupt by clearing the
+				 * interrupt bit in the timer control status
+				 * register, this is done after calling the
+				 * handler so the application could call
+				 * IsExpired, the interrupt is cleared by
+				 * writing a 1 to the interrupt bit of the
+				 * register without changing any of the other
+				 * bits
+				 */
+				XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress,
+						 TmrCtrNumber,
+						 XTC_TCSR_OFFSET,
+						 ControlStatusReg |
+						 XTC_CSR_INT_OCCURED_MASK);
+			}
+		}
+	}
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_l.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_l.c
new file mode 100644
index 000000000..e19558d0c
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_l.c
@@ -0,0 +1,79 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_l.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xtmrctr_l.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/* The following table contains the offset from the base address of a timer
+ * counter device for each timer counter.  A single device may contain multiple
+ * timer counters and the functions specify which one to operate on.
+ */
+u8 XTmrCtr_Offsets[] = { 0, XTC_TIMER_COUNTER_OFFSET };
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_l.h b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_l.h
new file mode 100644
index 000000000..f5fd773ee
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_l.h
@@ -0,0 +1,429 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_l.h
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* High-level driver functions are defined in xtmrctr.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+*		      for naming consistency (CR 559142).
+* 2.04a sdm  07/12/11 Added the CASC mode bit in the TCSRO register for the
+*		      cascade mode operation.
+*		      The cascade mode of operation is present in the latest
+*		      versions of the axi_timer IP. Please check the HW
+*		      Datasheet to see whether this feature is present in the
+*		      version of the IP that you are using.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_L_H		/* prevent circular inclusions */
+#define XTMRCTR_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * Defines the number of timer counters within a single hardware device. This
+ * number is not currently parameterized in the hardware but may be in the
+ * future.
+ */
+#define XTC_DEVICE_TIMER_COUNT		2
+
+/* Each timer counter consumes 16 bytes of address space */
+
+#define XTC_TIMER_COUNTER_OFFSET	16
+
+/** @name Register Offset Definitions
+ * Register offsets within a timer counter, there are multiple
+ * timer counters within a single device
+ * @{
+ */
+
+#define XTC_TCSR_OFFSET		0	/**< Control/Status register */
+#define XTC_TLR_OFFSET		4	/**< Load register */
+#define XTC_TCR_OFFSET		8	/**< Timer counter register */
+
+/* @} */
+
+/** @name Control Status Register Bit Definitions
+ * Control Status Register bit masks
+ * Used to configure the timer counter device.
+ * @{
+ */
+
+#define XTC_CSR_CASC_MASK		0x00000800 /**< Cascade Mode */
+#define XTC_CSR_ENABLE_ALL_MASK		0x00000400 /**< Enables all timer
+							counters */
+#define XTC_CSR_ENABLE_PWM_MASK		0x00000200 /**< Enables the Pulse Width
+							Modulation */
+#define XTC_CSR_INT_OCCURED_MASK	0x00000100 /**< If bit is set, an
+							interrupt has occured.
+							If set and '1' is
+							written to this bit
+							position, bit is
+							cleared. */
+#define XTC_CSR_ENABLE_TMR_MASK		0x00000080 /**< Enables only the
+							specific timer */
+#define XTC_CSR_ENABLE_INT_MASK		0x00000040 /**< Enables the interrupt
+							output. */
+#define XTC_CSR_LOAD_MASK		0x00000020 /**< Loads the timer using
+							the load value provided
+							earlier in the Load
+							Register,
+							XTC_TLR_OFFSET. */
+#define XTC_CSR_AUTO_RELOAD_MASK	0x00000010 /**< In compare mode,
+							configures
+							the timer counter to
+							reload  from the
+							Load Register. The
+							default  mode
+							causes the timer counter
+							to hold when the compare
+							value is hit. In capture
+							mode, configures  the
+							timer counter to not
+							hold the previous
+							capture value if a new
+							event occurs. The
+							default mode cause the
+							timer counter to hold
+							the capture value until
+							recognized. */
+#define XTC_CSR_EXT_CAPTURE_MASK	0x00000008 /**< Enables the
+							external input
+							to the timer counter. */
+#define XTC_CSR_EXT_GENERATE_MASK	0x00000004 /**< Enables the
+							external generate output
+							for the timer. */
+#define XTC_CSR_DOWN_COUNT_MASK		0x00000002 /**< Configures the timer
+							counter to count down
+							from start value, the
+							default is to count
+							up.*/
+#define XTC_CSR_CAPTURE_MODE_MASK	0x00000001 /**< Enables the timer to
+							capture the timer
+							counter value when the
+							external capture line is
+							asserted. The default
+							mode is compare mode.*/
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+extern u8 XTmrCtr_Offsets[];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Read one of the timer counter registers.
+*
+* @param	BaseAddress contains the base address of the timer counter
+*		device.
+* @param	TmrCtrNumber contains the specific timer counter within the
+*		device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegOffset contains the offset from the 1st register of the timer
+*		counter to select the specific register of the timer counter.
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
+					unsigned RegOffset);
+******************************************************************************/
+#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
+			(RegOffset))
+
+#ifndef XTimerCtr_ReadReg
+#define XTimerCtr_ReadReg XTmrCtr_ReadReg
+#endif
+
+/*****************************************************************************/
+/**
+* Write a specified value to a register of a timer counter.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegOffset contain the offset from the 1st register of the timer
+*		counter to select the specific register of the timer counter.
+* @param	ValueToWrite is the 32 bit value to be written to the register.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
+*					unsigned RegOffset, u32 ValueToWrite);
+******************************************************************************/
+#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (RegOffset)), (ValueToWrite))
+
+/****************************************************************************/
+/**
+*
+* Set the Control Status Register of a timer counter to the specified value.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegisterValue is the 32 bit value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
+*					u8 TmrCtrNumber,u32 RegisterValue);
+*****************************************************************************/
+#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the Control Status Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
+*						u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Get the Timer Counter Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
+*						u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber)		  \
+	XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
+
+/****************************************************************************/
+/**
+*
+* Set the Load Register of a timer counter to the specified value.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegisterValue is the 32 bit value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
+*						  u32 RegisterValue);
+*****************************************************************************/
+#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue)	 \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
+					   (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the Load Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber)	\
+XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable a timer counter such that it starts running.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber)			    \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
+			(XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
+			XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable a timer counter such that it stops running.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber)			  \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
+			XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
+
+/****************************************************************************/
+/**
+*
+* Enable the interrupt for a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber)			    \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),  \
+			XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the interrupt for a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber)			   \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,  \
+	(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),		   \
+		XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK))
+
+/****************************************************************************/
+/**
+*
+* Cause the timer counter to load it's Timer Counter Register with the value
+* in the Load Register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		   zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
+					u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber)		  \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
+			XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Determine if a timer counter event has occurred.  Events are defined to be
+* when a capture has occurred or the counter has roller over.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @note		C-Style signature:
+* 		int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber)		\
+		((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),	\
+		XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) ==		\
+		XTC_CSR_INT_OCCURED_MASK)
+
+/************************** Function Prototypes ******************************/
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_options.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_options.c
new file mode 100644
index 000000000..5f199dc69
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_options.c
@@ -0,0 +1,217 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_options.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* Contains configuration options functions for the XTmrCtr component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.04a sdm  07/12/11 Added support for the cascade mode operation.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xtmrctr.h"
+#include "xtmrctr_i.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * The following data type maps an option to a register mask such that getting
+ * and setting the options may be table driven.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+static Mapping OptionsTable[] = {
+	{XTC_CASCADE_MODE_OPTION, XTC_CSR_CASC_MASK},
+	{XTC_ENABLE_ALL_OPTION, XTC_CSR_ENABLE_ALL_MASK},
+	{XTC_DOWN_COUNT_OPTION, XTC_CSR_DOWN_COUNT_MASK},
+	{XTC_CAPTURE_MODE_OPTION, XTC_CSR_CAPTURE_MODE_MASK |
+	 XTC_CSR_EXT_CAPTURE_MASK},
+	{XTC_INT_MODE_OPTION, XTC_CSR_ENABLE_INT_MASK},
+	{XTC_AUTO_RELOAD_OPTION, XTC_CSR_AUTO_RELOAD_MASK},
+	{XTC_EXT_COMPARE_OPTION, XTC_CSR_EXT_GENERATE_MASK}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XTC_NUM_OPTIONS   (sizeof(OptionsTable) / sizeof(Mapping))
+
+/*****************************************************************************/
+/**
+*
+* Enables the specified options for the specified timer counter. This function
+* sets the options without regard to the current options of the driver. To
+* prevent a loss of the current options, the user should call
+* XTmrCtr_GetOptions() prior to this function and modify the retrieved options
+* to pass into this function to prevent loss of the current options.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	Options contains the desired options to be set or cleared.
+*		Setting the option to '1' enables the option, clearing the to
+*		'0' disables the option. The options are bit masks such that
+*		multiple options may be set or cleared. The options are
+*		described in xtmrctr.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options)
+{
+	u32 CounterControlReg = 0;
+	u32 Index;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop through the Options table, turning the enable on or off
+	 * depending on whether the bit is set in the incoming Options flag.
+	 */
+
+	for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+
+			/*
+			 * Turn the option on
+			 */
+			CounterControlReg |= OptionsTable[Index].Mask;
+		}
+		else {
+			/*
+			 * Turn the option off
+			 */
+			CounterControlReg &= ~OptionsTable[Index].Mask;
+		}
+	}
+
+	/*
+	 * Write out the updated value to the actual register
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET, CounterControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the options for the specified timer counter.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on
+*		Each device may contain multiple timer counters. The timer
+*		number is a zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return
+*
+* The currently set options. An option which is set to a '1' is enabled and
+* set to a '0' is disabled. The options are bit masks such that multiple
+* options may be set or cleared. The options are described in xtmrctr.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+
+	u32 Options = 0;
+	u32 CounterControlReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the current contents of the control status register to allow
+	 * the current options to be determined
+	 */
+	CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+					       TmrCtrNumber, XTC_TCSR_OFFSET);
+	/*
+	 * Loop through the Options table, turning the enable on or off
+	 * depending on whether the bit is set in the current register settings.
+	 */
+	for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
+		if (CounterControlReg & OptionsTable[Index].Mask) {
+			Options |= OptionsTable[Index].Option;	/* turn it on */
+		}
+		else {
+			Options &= ~OptionsTable[Index].Option;	/* turn it off */
+		}
+	}
+
+	return Options;
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_selftest.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_selftest.c
new file mode 100644
index 000000000..99b15f8d6
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_selftest.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* Contains diagnostic/self-test functions for the XTmrCtr component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+#include "xtmrctr.h"
+#include "xtmrctr_i.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. This test verifies that the specified
+* timer counter of the device can be enabled and increments.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	TmrCtrNumber is the timer counter of the device to operate on.
+*		Each device may contain multiple timer counters. The timer
+*		number is a  zero based number with a range of
+*		0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return
+* 		- XST_SUCCESS if self-test was successful
+*		- XST_FAILURE if the timer is not incrementing.
+*
+* @note
+*
+* This is a destructive test using the provided timer. The current settings
+* of the timer are returned to the initialized values and all settings at the
+* time this function is called are overwritten.
+*
+******************************************************************************/
+int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
+{
+	u32 TimerCount1 = 0;
+	u32 TimerCount2 = 0;
+	u16 Count = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the Capture register to 0
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TLR_OFFSET, 0);
+
+	/*
+	 * Reset the timer and the interrupt
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET,
+			  XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
+
+	/*
+	 * Set the control/status register to enable timer
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET, XTC_CSR_ENABLE_TMR_MASK);
+
+	/*
+	 * Read the timer
+	 */
+	TimerCount1 = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+					 TmrCtrNumber, XTC_TCR_OFFSET);
+	/*
+	 * Make sure timer is incrementing if the Count rolls over to zero
+	 * and the timer still has not incremented an error is returned
+	 */
+
+	do {
+		TimerCount2 = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
+						 TmrCtrNumber, XTC_TCR_OFFSET);
+		Count++;
+	}
+	while ((TimerCount1 == TimerCount2) && (Count != 0));
+
+	/*
+	 * Reset the timer and the interrupt
+	 */
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET,
+			  XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
+
+	/*
+	 * Set the control/status register to 0 to complete initialization
+	 * this disables the timer completely and allows it to be used again
+	 */
+
+	XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
+			  XTC_TCSR_OFFSET, 0);
+
+	if (TimerCount1 == TimerCount2) {
+		return XST_FAILURE;
+	}
+	else {
+		return XST_SUCCESS;
+	}
+}
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_sinit.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_sinit.c
new file mode 100644
index 000000000..1ed6d354c
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_sinit.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* This file contains static initialization methods for the XTmrCtr driver.
+*
+* @note	None.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 4.0   als  09/30/15 Creation of this file. Moved LookupConfig from xtmrctr.c.
+* </pre>
+*
+******************************************************************************/
+
+/******************************* Include Files *******************************/
+
+#include "xparameters.h"
+#include "xtmrctr.h"
+
+/************************** Constant Definitions *****************************/
+
+#ifndef XPAR_XTMRCTR_NUM_INSTANCES
+#define XPAR_XTMRCTR_NUM_INSTANCES	0
+#endif
+
+/*************************** Variable Declarations ***************************/
+
+/* A table of configuration structures containing the configuration information
+ * for each timer core in the system. */
+extern XTmrCtr_Config XTmrCtr_ConfigTable[XPAR_XTMRCTR_NUM_INSTANCES];
+
+/**************************** Function Definitions ***************************/
+
+/*****************************************************************************/
+/**
+* Looks up the device configuration based on the unique device ID. The table
+* TmrCtr_ConfigTable contains the configuration info for each device in the
+* system.
+*
+* @param	DeviceId is the unique device ID to search for in the config
+*		table.
+*
+* @return	A pointer to the configuration that matches the given device
+* 		ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId)
+{
+	XTmrCtr_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XTMRCTR_NUM_INSTANCES; Index++) {
+		if (XTmrCtr_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTmrCtr_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
+/** @} */
diff --git a/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_stats.c b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_stats.c
new file mode 100644
index 000000000..cf9eeaa7b
--- /dev/null
+++ b/thirdparty/xilinx/orig/tmrctr_v4_0/src/xtmrctr_stats.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_stats.c
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* Contains function to get and clear statistics for the XTmrCtr component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release.
+* 1.10b mta  03/21/07 Updated for new coding style.
+* 2.00a ktn  10/30/09 Updated to use HAL API's.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xtmrctr.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Get a copy of the XTmrCtrStats structure, which contains the current
+* statistics for this driver.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+* @param	StatsPtr is a pointer to a XTmrCtrStats structure which will get
+*		a copy of current statistics.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(StatsPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	StatsPtr->Interrupts = InstancePtr->Stats.Interrupts;
+}
+
+/*****************************************************************************/
+/**
+*
+* Clear the XTmrCtrStats structure for this driver.
+*
+* @param	InstancePtr is a pointer to the XTmrCtr instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XTmrCtr_ClearStats(XTmrCtr * InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Stats.Interrupts = 0;
+}
+/** @} */
diff --git a/thirdparty/xilinx/src/xil_io.c b/thirdparty/xilinx/src/xil_io.c
new file mode 100644
index 000000000..37b6c5a77
--- /dev/null
+++ b/thirdparty/xilinx/src/xil_io.c
@@ -0,0 +1,342 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex A9 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 3.06a sgd      05/15/12 Pointer volatile used for the all read functions
+* 3.07a sgd      08/17/12 Removed barriers (SYNCHRONIZE_IO) calls.
+* 3.09a sgd      02/05/13 Comments cleanup
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 Xil_In8(INTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16(INTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32(INTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out8(INTPTR Addr, u8 Value)
+{
+	u8 *LocalAddr = (u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16(INTPTR Addr, u16 Value)
+{
+	u16 *LocalAddr = (u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32(INTPTR Addr, u32 Value)
+{
+	u32 *LocalAddr = (u32 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16BE(INTPTR Addr)
+{
+	u16 temp;
+	u16 result;
+
+	temp = Xil_In16(Addr);
+
+	result = Xil_EndianSwap16(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32BE(INTPTR Addr)
+{
+	u32 temp;
+	u32 result;
+
+	temp = Xil_In32(Addr);
+
+	result = Xil_EndianSwap32(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16BE(INTPTR Addr, u16 Value)
+{
+	u16 temp;
+
+	temp = Xil_EndianSwap16(Value);
+
+    Xil_Out16(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32BE(INTPTR Addr, u32 Value)
+{
+	u32 temp;
+
+	temp = Xil_EndianSwap32(Value);
+
+    Xil_Out32(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}