From c9b599de4ba980bf9e1056cb37ec3937701425b9 Mon Sep 17 00:00:00 2001
From: Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
Date: Tue, 1 Jul 2014 15:26:34 +0000
Subject: [PATCH] added opal model
git-svn-id: https://zerberus.eonerc.rwth-aachen.de:8443/svn/s2ss/trunk@108 8ec27952-4edc-4aab-86aa-e87bb2611832
---
clients/opal/.project | 12 +
.../com.opalrt.rtlab.ui.application.prefs | 3 +
clients/opal/01_server2OPAL.llp | 18 +
.../opal/{ => models/AsyncIP_sl}/AsyncIP.c | 0
.../opal/{ => models/AsyncIP_sl}/AsyncIP.mk | 0
.../{ => models/AsyncIP_sl}/AsyncIPUtils.h | 0
clients/opal/models/AsyncIP_sl/AsyncIP_sl.llm | 96 +
clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl | 1497 ++++++
.../models/AsyncIP_sl/AsyncIP_sl.mdl.r2006b | 1226 +++++
.../models/AsyncIP_sl/AsyncIP_sl.mdl.r2010b | 1504 ++++++
.../opal/models/AsyncIP_sl/AsyncIP_sl.probe | 59 +
.../OpREDHAWKtarget/AsyncIP | Bin 0 -> 197339 bytes
.../OpREDHAWKtarget/OpalSnapshotUtil.c | 154 +
.../OpREDHAWKtarget/asyncip_sl_1_sm_ip_test | Bin 0 -> 1177196 bytes
.../asyncip_sl_1_sm_ip_test.bat | 2 +
.../OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.c | 1170 ++++
.../OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.h | 1371 +++++
.../asyncip_sl_1_sm_ip_test.log | 61 +
.../asyncip_sl_1_sm_ip_test.map | 156 +
.../asyncip_sl_1_sm_ip_test.mk | 637 +++
.../asyncip_sl_1_sm_ip_test.nvcmd | 1 +
.../asyncip_sl_1_sm_ip_test_147_123701.log | 46 +
.../asyncip_sl_1_sm_ip_test_147_123901.log | 42 +
.../asyncip_sl_1_sm_ip_test_147_124401.log | 46 +
.../asyncip_sl_1_sm_ip_test_147_125001.log | 42 +
.../asyncip_sl_1_sm_ip_test_147_125401.log | 42 +
.../asyncip_sl_1_sm_ip_test_data.c | 480 ++
...syncip_sl_1_sm_ip_test_last_simulation.log | 42 +
.../asyncip_sl_1_sm_ip_test_private.h | 38 +
.../asyncip_sl_1_sm_ip_test_ref.rsp | 0
.../asyncip_sl_1_sm_ip_test_types.h | 27 +
.../OpREDHAWKtarget/buildInfo.mat | Bin 0 -> 15540 bytes
.../compilation_target_report.xml | 648 +++
.../OpREDHAWKtarget/defines.txt | 8 +
.../OpREDHAWKtarget/modelsources.txt | 1 +
.../opasyncip_sl_sm_ip_test_0.snap | Bin 0 -> 4542 bytes
.../OpREDHAWKtarget/rtGetInf.c | 140 +
.../OpREDHAWKtarget/rtGetInf.h | 28 +
.../OpREDHAWKtarget/rtGetNaN.c | 100 +
.../OpREDHAWKtarget/rtGetNaN.h | 26 +
.../OpREDHAWKtarget/rt_defines.h | 49 +
.../OpREDHAWKtarget/rt_nonfinite.c | 70 +
.../OpREDHAWKtarget/rt_nonfinite.h | 54 +
.../OpREDHAWKtarget/rtmodel.h | 23 +
.../OpREDHAWKtarget/rtw_proj.tmw | 4 +
.../OpREDHAWKtarget/rtwtypes.h | 1191 ++++
.../OpREDHAWKtarget/rtwtypeschksum.mat | Bin 0 -> 1070 bytes
.../OpREDHAWKtarget/target_report.xml | 648 +++
.../rtlab_rtmodel/_sharedutils/tflSUInfo.mat | Bin 0 -> 182 bytes
.../tmwinternal/binfo.mat | Bin 0 -> 6326 bytes
.../tmwinternal/minfo.mat | Bin 0 -> 1592 bytes
.../AsyncIP_sl_sm_ip_test/slprj/sl_proj.tmw | 2 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl.Comm | 2 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl.acqgr | 2 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl.alias | 3 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl.param | 19 +
.../models/AsyncIP_sl/Opcommon/AsyncIP_sl.sig | 16 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl.signal | 29 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl.subsys | 2 +
...AsyncIP_sl_OpREDHAWKtarget_Compilation.log | 206 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl_info.ini | 63 +
.../AsyncIP_sl/Opcommon/AsyncIP_sl_info.mat | Bin 0 -> 10753 bytes
.../Opcommon/asyncip_sl_1_sm_ip_test.mdl | 1223 +++++
.../Opcommon/asyncip_sl_1_sm_ip_test.sfp | 7 +
.../AsyncIP_sl/Opcommon/host_report.xml | 3101 +++++++++++
clients/opal/models/AsyncIP_sl/actxlicense.m | 6 +
.../AsyncIP_sl/asyncip_sl_2_sc_console.mdl | 1827 +++++++
.../models/AsyncIP_sl/report/AsyncIP_sl.html | 17 +
.../models/AsyncIP_sl/report/AsyncIP_sl.zip | Bin 0 -> 39006 bytes
.../models/AsyncIP_sl/report/common/css.js | 3 +
.../models/AsyncIP_sl/report/css/print.css | 3 +
.../models/AsyncIP_sl/report/css/screen.css | 3 +
.../models/AsyncIP_sl/report/css/tree.css | 48 +
.../AsyncIP_sl/report/images/closeitem.gif | Bin 0 -> 854 bytes
.../AsyncIP_sl/report/images/openitem.gif | Bin 0 -> 857 bytes
.../AsyncIP_sl/report/images/property.gif | Bin 0 -> 833 bytes
.../report/temp/compilation_target_report.xml | 648 +++
.../AsyncIP_sl/report/temp/host_report.xml | 3184 +++++++++++
.../report/temp/sm_ip_test_target_report.xml | 648 +++
.../models/AsyncIP_sl/report/tree/tree.js | 301 ++
.../models/AsyncIP_sl/report/tree/tree.xsl | 249 +
.../AsyncIP_sl/report/xml/AsyncIP_sl.xml | 4776 +++++++++++++++++
.../models/AsyncIP_sl/report/xml/report.xml | 21 +
clients/opal/tmseq/SR13level2_AsyncIP_sl.tms | 90 +
84 files changed, 28261 insertions(+)
create mode 100644 clients/opal/.project
create mode 100644 clients/opal/.settings/com.opalrt.rtlab.ui.application.prefs
create mode 100644 clients/opal/01_server2OPAL.llp
rename clients/opal/{ => models/AsyncIP_sl}/AsyncIP.c (100%)
rename clients/opal/{ => models/AsyncIP_sl}/AsyncIP.mk (100%)
rename clients/opal/{ => models/AsyncIP_sl}/AsyncIPUtils.h (100%)
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl.llm
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2006b
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2010b
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl.probe
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/AsyncIP
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/OpalSnapshotUtil.c
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.bat
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.c
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.map
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.mk
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.nvcmd
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123701.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123901.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_124401.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125001.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125401.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_data.c
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_last_simulation.log
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_private.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_ref.rsp
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_types.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/buildInfo.mat
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/compilation_target_report.xml
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/defines.txt
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/modelsources.txt
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/opasyncip_sl_sm_ip_test_0.snap
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.c
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.c
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_defines.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.c
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtmodel.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtw_proj.tmw
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypes.h
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypeschksum.mat
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/target_report.xml
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/_sharedutils/tflSUInfo.mat
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/asyncip_sl_1_sm_ip_test/tmwinternal/binfo.mat
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/asyncip_sl_1_sm_ip_test/tmwinternal/minfo.mat
create mode 100644 clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/sl_proj.tmw
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.Comm
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.acqgr
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.alias
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.param
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.sig
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.signal
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.subsys
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_OpREDHAWKtarget_Compilation.log
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.ini
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.mat
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.mdl
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.sfp
create mode 100644 clients/opal/models/AsyncIP_sl/Opcommon/host_report.xml
create mode 100644 clients/opal/models/AsyncIP_sl/actxlicense.m
create mode 100644 clients/opal/models/AsyncIP_sl/asyncip_sl_2_sc_console.mdl
create mode 100644 clients/opal/models/AsyncIP_sl/report/AsyncIP_sl.html
create mode 100644 clients/opal/models/AsyncIP_sl/report/AsyncIP_sl.zip
create mode 100644 clients/opal/models/AsyncIP_sl/report/common/css.js
create mode 100644 clients/opal/models/AsyncIP_sl/report/css/print.css
create mode 100644 clients/opal/models/AsyncIP_sl/report/css/screen.css
create mode 100644 clients/opal/models/AsyncIP_sl/report/css/tree.css
create mode 100644 clients/opal/models/AsyncIP_sl/report/images/closeitem.gif
create mode 100644 clients/opal/models/AsyncIP_sl/report/images/openitem.gif
create mode 100644 clients/opal/models/AsyncIP_sl/report/images/property.gif
create mode 100644 clients/opal/models/AsyncIP_sl/report/temp/compilation_target_report.xml
create mode 100644 clients/opal/models/AsyncIP_sl/report/temp/host_report.xml
create mode 100644 clients/opal/models/AsyncIP_sl/report/temp/sm_ip_test_target_report.xml
create mode 100644 clients/opal/models/AsyncIP_sl/report/tree/tree.js
create mode 100644 clients/opal/models/AsyncIP_sl/report/tree/tree.xsl
create mode 100644 clients/opal/models/AsyncIP_sl/report/xml/AsyncIP_sl.xml
create mode 100644 clients/opal/models/AsyncIP_sl/report/xml/report.xml
create mode 100644 clients/opal/tmseq/SR13level2_AsyncIP_sl.tms
diff --git a/clients/opal/.project b/clients/opal/.project
new file mode 100644
index 000000000..040e84699
--- /dev/null
+++ b/clients/opal/.project
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>test</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ <nature>com.opalrt.rtlab.ui.rtlabnature</nature>
+ </natures>
+</projectDescription>
diff --git a/clients/opal/.settings/com.opalrt.rtlab.ui.application.prefs b/clients/opal/.settings/com.opalrt.rtlab.ui.application.prefs
new file mode 100644
index 000000000..098334753
--- /dev/null
+++ b/clients/opal/.settings/com.opalrt.rtlab.ui.application.prefs
@@ -0,0 +1,3 @@
+#Fri May 23 11:58:23 CEST 2014
+eclipse.preferences.version=1
+rtprojectfile=01_server2OPAL.llp
diff --git a/clients/opal/01_server2OPAL.llp b/clients/opal/01_server2OPAL.llp
new file mode 100644
index 000000000..439eb3aba
--- /dev/null
+++ b/clients/opal/01_server2OPAL.llp
@@ -0,0 +1,18 @@
+<?xml version="1.0" ?>
+<Project>
+ <General>
+ <att_name>test</att_name>
+ <att_description>This is a project!</att_description>
+ <att_autosave>ON</att_autosave>
+ <att_filename>D:\msv\svo\s2ss\clients\opal\01_server2OPAL.llp</att_filename>
+ </General>
+ <Models>
+ <Model>
+ <Path>
+ <Relative>models\AsyncIP_sl\AsyncIP_sl.mdl</Relative>
+ <Absolute>D:\msv\svo\s2ss\clients\opal\models\AsyncIP_sl\AsyncIP_sl.mdl</Absolute>
+ <UNC>D:\msv\svo\s2ss\clients\opal\models\AsyncIP_sl\AsyncIP_sl.mdl</UNC>
+ </Path>
+ </Model>
+ </Models>
+</Project>
diff --git a/clients/opal/AsyncIP.c b/clients/opal/models/AsyncIP_sl/AsyncIP.c
similarity index 100%
rename from clients/opal/AsyncIP.c
rename to clients/opal/models/AsyncIP_sl/AsyncIP.c
diff --git a/clients/opal/AsyncIP.mk b/clients/opal/models/AsyncIP_sl/AsyncIP.mk
similarity index 100%
rename from clients/opal/AsyncIP.mk
rename to clients/opal/models/AsyncIP_sl/AsyncIP.mk
diff --git a/clients/opal/AsyncIPUtils.h b/clients/opal/models/AsyncIP_sl/AsyncIPUtils.h
similarity index 100%
rename from clients/opal/AsyncIPUtils.h
rename to clients/opal/models/AsyncIP_sl/AsyncIPUtils.h
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl.llm b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.llm
new file mode 100644
index 000000000..62ab332dd
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.llm
@@ -0,0 +1,96 @@
+[EnvVars]
+ABORT_COMPILE_WHEN_NO_BITSTREAM=0
+ACTION_AFTER_N_OVERRUNS=10
+ACTION_ON_OVERRUNS=0
+AcquisitionMemory=0,2500,24,100
+ActiveGroups=7/0/24/25/26/27/28/29/
+CACHEABLE_DMA_MEMORY_ACCESS=ON
+COMM_RT=UDP/IP
+ClockPeriodMode=Free-Clock
+ClockPeriodTime=10
+DEBUG=0
+DETECT_OVERRUNS=ON
+ENABLE_WATCHDOG=ON
+EXT_CC_OPTS=
+EXT_LD_OPTS=
+EXT_LIB=
+EXT_LIBPATH=
+MODEL_PAUSE_TIME=0.000000
+MODEL_STOP_TIME=0.000000
+MONITORING=ON
+MONITORING_BLOCK=OFF
+MONITORING_DISPLAY=NEVER
+MSG_PRECISION_FACTOR=0
+MaxDynamicSignals=2/0/100/24/42/
+NB_STEP_WITHOUT_OVERRUNS=10
+OPAL_DEBUG=OFF
+OP_MATLABR2011B=1
+OS_COMPILE_RELEASE=2.6.29.6-opalrt-5
+PRINT_LOG_LEVEL=ALWAYS
+RESET_IO_MISSING=ON
+SYSNAME=linux
+USER_INCS=
+USER_SRCS=
+WATCHDOG_TIMEOUT=5000
+[EnvVars_REDHAWK_DYN_1]
+INTERNAL_IGN_SOURCE_FILE=sfun_gen_async_ctrl.c sfun_recv_async.c sfun_send_async.c
+INTERNAL_LIBRARY2=-lOpalAsyncApiR2011b
+INTERNAL_LIBRARY3=-lOpalAsyncApiCore
+[ExtraGetFilesComp]
+AsyncIP=Binary
+[ExtraPutFilesComp]
+AsyncIP.c=Ascii
+AsyncIP.mk=Ascii
+AsyncIPUtils.h=Ascii
+[ExtraPutFilesComp_1_RT_LAB]
+C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalAsyncApiCore.a=Binary
+[General]
+ATT_CHECKSUM1=3303931251
+ATT_CHECKSUM2=4180788877
+ATT_CHECKSUM3=2074112130
+ATT_CHECKSUM4=668397547
+ATT_CREATED_BY=jwu
+ATT_CREATED_ON=Thu Apr 15 08:21:54 1999
+ATT_ENABLE_PTA=OFF
+ATT_HANDLE_CONSOLE=ON
+ATT_LAST_SAVED_BY=ACS
+ATT_LAST_SAVED_ON=Wed May 28 12:53:21 2014
+ATT_REVISION=1.425
+AutoRetrieveFiles=ON
+AutoRetrieveRtlab=ON
+CompilerVersion=AUTOMATIC
+DESCRIPTION=Simple ping pong test between S2SS and OPAL$%CR%$$%CR%$Using sine waves no measure round trip time.
+DinamoFlag=OFF
+FILENAME=D:\msv\svo\s2ss\clients\opal\models\AsyncIP_sl\AsyncIP_sl.mdl
+FORCE_RECOMPILE=0
+IMPORTED_GLOBAL_VARIABLES=1
+LastCompileRtlabVersion=v10.5.9.356
+LastMatlabUsed=21
+LastMatlabUsedName=v7.13
+MATLAB_USED_IN_MODEL=21
+Name=AsyncIP_sl
+PRINT_CYCLE=OFF
+PostBuildCmd=
+PreBuildCmd=
+QNX_LAST_COMPILE_VERSION=
+RH64_LAST_COMPILE_VERSION=
+RH_LAST_COMPILE_VERSION=2.6.29.6-opalrt-5
+ReportFileId=
+RetrieveBuildTree=ON
+RetrieveRootDir=
+SimulationMode=2
+TLC=Automatic
+TMF=Automatic
+TRANSFERFILE_AT_LOAD=ON
+TargetCompileCmd=make -f /usr/opalrt/common/bin/opalmodelmk
+TargetPlatform=REDHAWK
+TimeFactor=1.000000000000000
+TimeStep=0.000050000000000
+sc_consoleTimeStep=-1.000000000000000
+sm_ip_testTimeStep=0.000049999998737
+[NodeMapping]
+sm_ip_test=ACS_OPAL_RT
+sm_ip_test_CORE_ASSIGNATION=1
+sm_ip_test_CPU=-1
+sm_ip_test_DEBUG=OFF
+sm_ip_test_XHP_ENABLE=FALSE
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl
new file mode 100644
index 000000000..c180c414e
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl
@@ -0,0 +1,1497 @@
+# $Revision: 1.1 $
+Model {
+ Name "AsyncIP_sl"
+ Version 7.8
+ MdlSubVersion 0
+ GraphicalInterface {
+ NumRootInports 0
+ NumRootOutports 0
+ ParameterArgumentNames ""
+ ComputedModelVersion "1.426"
+ NumModelReferences 0
+ NumTestPointedSignals 0
+ }
+ SavedCharacterEncoding "windows-1252"
+ SaveDefaultBlockParams on
+ ScopeRefreshTime 0.035000
+ OverrideScopeRefreshTime on
+ DisableAllScopes off
+ DataTypeOverride "UseLocalSettings"
+ DataTypeOverrideAppliesTo "AllNumericTypes"
+ MinMaxOverflowLogging "UseLocalSettings"
+ MinMaxOverflowArchiveMode "Overwrite"
+ FPTRunName "Run 1"
+ MaxMDLFileLineLength 120
+ Created "Thu Apr 15 08:21:54 1999"
+ Creator "jwu"
+ UpdateHistory "UpdateHistoryNever"
+ ModifiedByFormat "%<Auto>"
+ LastModifiedBy "ACS"
+ ModifiedDateFormat "%<Auto>"
+ LastModifiedDate "Wed May 28 13:45:50 2014"
+ RTWModifiedTimeStamp 323183499
+ ModelVersionFormat "1.%<AutoIncrement:426>"
+ ConfigurationManager "none"
+ SampleTimeColors off
+ SampleTimeAnnotations off
+ LibraryLinkDisplay "none"
+ WideLines off
+ ShowLineDimensions on
+ ShowPortDataTypes off
+ ShowDesignRanges off
+ ShowLoopsOnError on
+ IgnoreBidirectionalLines off
+ ShowStorageClass off
+ ShowTestPointIcons on
+ ShowSignalResolutionIcons on
+ ShowViewerIcons on
+ SortedOrder off
+ ExecutionContextIcon off
+ ShowLinearizationAnnotations on
+ BlockNameDataTip off
+ BlockParametersDataTip on
+ BlockDescriptionStringDataTip off
+ ToolBar on
+ StatusBar on
+ BrowserShowLibraryLinks off
+ BrowserLookUnderMasks off
+ SimulationMode "normal"
+ LinearizationMsg "none"
+ Profile off
+ ParamWorkspaceSource "MATLABWorkspace"
+ AccelSystemTargetFile "accel.tlc"
+ AccelTemplateMakefile "accel_default_tmf"
+ AccelMakeCommand "make_rtw"
+ TryForcingSFcnDF off
+ RecordCoverage off
+ CovPath "/"
+ CovSaveName "covdata"
+ CovMetricSettings "dw"
+ CovNameIncrementing off
+ CovHtmlReporting on
+ CovForceBlockReductionOff on
+ covSaveCumulativeToWorkspaceVar on
+ CovSaveSingleToWorkspaceVar on
+ CovCumulativeVarName "covCumulativeData"
+ CovCumulativeReport off
+ CovReportOnPause on
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+ Position [515, 249, 545, 281]
+ BackgroundColor "yellow"
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+ Location [826, 517, 1334, 952]
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+ BlockType Scope
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+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
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+ ListType ScopeGraphics
+ FigureColor "[0.5 0.5 0.5]"
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+ MarkerStyles "none|none|none|none|none|none"
+ }
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+ Block {
+ BlockType Scope
+ Name "message 4"
+ SID "43"
+ Ports [1]
+ Position [695, 299, 725, 331]
+ BackgroundColor "yellow"
+ Floating off
+ Location [826, 517, 1334, 952]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ List {
+ ListType ScopeGraphics
+ FigureColor "[0.5 0.5 0.5]"
+ AxesColor "[0 0 0]"
+ AxesTickColor "[1 1 1]"
+ LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
+ LineStyles "-|-|-|-|-|-"
+ LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
+ MarkerStyles "none|none|none|none|none|none"
+ }
+ YMin "-1.75"
+ YMax "4"
+ SaveName "ScopeData3"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Display
+ Name "reception status"
+ SID "12"
+ Ports [1]
+ Position [390, 148, 450, 172]
+ BackgroundColor "yellow"
+ FontName "Arial"
+ FontSize 8
+ Decimation "1"
+ Lockdown off
+ }
+ Line {
+ SrcBlock "errors_status"
+ SrcPort 1
+ Points [30, 0; 0, 5]
+ DstBlock "OpComm"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "OpComm"
+ SrcPort 2
+ Points [55, 0; 0, 80]
+ Branch {
+ Labels [1, 0]
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+ DstPort 1
+ }
+ Branch {
+ Points [0, -60]
+ DstBlock "message 1"
+ DstPort 1
+ }
+ }
+ Line {
+ SrcBlock "data recv"
+ SrcPort 1
+ DstBlock "OpComm"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "OpComm"
+ SrcPort 1
+ Points [20, 0]
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+ DstPort 1
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+ Line {
+ SrcBlock "Demux"
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+ Points [45, 0; 0, -20]
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+ SrcBlock "Demux"
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+ Labels [0, 0]
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+ DstBlock "message 2"
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+ Line {
+ SrcBlock "data send"
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+ Points [30, 0; 0, -5]
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+ }
+ Line {
+ SrcBlock "OpComm"
+ SrcPort 3
+ Points [35, 0; 0, 150]
+ Branch {
+ Points [0, 0]
+ DstBlock "Demux2"
+ DstPort 1
+ }
+ Branch {
+ Points [0, 60]
+ DstBlock "message 3"
+ DstPort 1
+ }
+ }
+ Line {
+ SrcBlock "Subtract"
+ SrcPort 1
+ DstBlock "message 4"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Demux1"
+ SrcPort 5
+ Points [15, 0; 0, -30]
+ Branch {
+ DstBlock "Mux"
+ DstPort 1
+ }
+ Branch {
+ Points [0, -20; 175, 0; 0, 70]
+ DstBlock "Subtract"
+ DstPort 1
+ }
+ }
+ Line {
+ SrcBlock "Demux2"
+ SrcPort 5
+ Points [30, 0; 0, -65]
+ Branch {
+ Points [0, -40]
+ DstBlock "Mux"
+ DstPort 2
+ }
+ Branch {
+ Points [0, 5]
+ DstBlock "Subtract"
+ DstPort 2
+ }
+ }
+ Annotation {
+ Name "Simple analysis of round trip time"
+ Position [488, 57]
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ }
+ }
+ Block {
+ BlockType SubSystem
+ Name "sm_ip_test"
+ SID "13"
+ Ports [0, 3]
+ Position [55, 97, 235, 193]
+ BackgroundColor "lightBlue"
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ System {
+ Name "sm_ip_test"
+ Location [86, 258, 1746, 1156]
+ Open on
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "A4"
+ PaperUnits "centimeters"
+ TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "183"
+ Block {
+ BlockType Mux
+ Name "Mux"
+ SID "16"
+ Ports [3, 1]
+ Position [845, 125, 850, 175]
+ ShowName off
+ Inputs "3"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Mux
+ Name "Mux1"
+ SID "17"
+ Ports [2, 1]
+ Position [255, 144, 260, 206]
+ BackgroundColor "yellow"
+ ShowName off
+ Inputs "2"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Reference
+ Name "OpIPSocketCtrl1"
+ SID "18"
+ Ports []
+ Position [15, 152, 144, 213]
+ LibraryVersion "1.10"
+ SourceBlock "rtio_generic_ip/OpIPSocketCtrl"
+ SourceType "OpAsyncIPCtrl"
+ ctl_id "1"
+ proto "UDP/IP"
+ ip_addr_remote "137.226.160.91"
+ ip_port_remote "10200"
+ ip_port_local "10201"
+ ip_addr_mcast "0.0.0.0"
+ exe_name "AsyncIP"
+ }
+ Block {
+ BlockType DiscretePulseGenerator
+ Name "Pulse\nGenerator"
+ SID "44"
+ Ports [0, 1]
+ Position [165, 198, 215, 232]
+ ZOrder -13
+ PulseType "Time based"
+ Amplitude "5"
+ Period "0.1"
+ PulseWidth "30"
+ }
+ Block {
+ BlockType Constant
+ Name "constants"
+ SID "19"
+ Position [165, 151, 235, 169]
+ BackgroundColor "yellow"
+ NamePlacement "alternate"
+ Value "[1 2 3 4]"
+ }
+ Block {
+ BlockType DiscretePulseGenerator
+ Name "data ready 1 kHz"
+ SID "20"
+ Ports [0, 1]
+ Position [265, 116, 310, 134]
+ NamePlacement "alternate"
+ SampleTime "0.001"
+ }
+ Block {
+ BlockType Reference
+ Name "receive message 1"
+ SID "21"
+ Ports [1, 3]
+ Position [600, 144, 775, 186]
+ LibraryVersion "1.348"
+ SourceBlock "rtlab/Communication/Asynchronous/OpAsyncRecv"
+ SourceType "OpAsyncRecv"
+ ctl_id "1"
+ recv_id "1"
+ enable_param off
+ fp1 "1"
+ fp2 "2"
+ fp3 "3"
+ fp4 "4"
+ fp5 "5"
+ sp1 "string1"
+ sp2 "string2"
+ sp3 "string3"
+ sp4 "string4"
+ sp5 "string5"
+ }
+ Block {
+ BlockType Reference
+ Name "send message 1"
+ SID "22"
+ Ports [2, 1]
+ Position [350, 114, 520, 156]
+ LibraryVersion "1.348"
+ SourceBlock "rtlab/Communication/Asynchronous/OpAsyncSend"
+ SourceType "OpAsyncSend"
+ ctl_id "1"
+ send_id "1"
+ mode "DONT_NEED_REPLY"
+ enable_param off
+ fp1 "1"
+ fp2 "2"
+ fp3 "3"
+ fp4 "4"
+ fp5 "5"
+ sp1 "string1"
+ sp2 "string2"
+ sp3 "string3"
+ sp4 "string4"
+ sp5 "string5"
+ }
+ Block {
+ BlockType SignalSpecification
+ Name "set width"
+ SID "23"
+ Position [805, 172, 830, 188]
+ Dimensions "5"
+ }
+ Block {
+ BlockType Sin
+ Name "sine"
+ SID "24"
+ Ports [0, 1]
+ Position [65, 37, 135, 73]
+ BackgroundColor "yellow"
+ Amplitude "1.5"
+ Frequency "50"
+ }
+ Block {
+ BlockType Constant
+ Name "timeout"
+ SID "25"
+ Position [555, 158, 585, 172]
+ Value "2"
+ }
+ Block {
+ BlockType Outport
+ Name "data recv"
+ SID "26"
+ Position [890, 172, 925, 188]
+ BackgroundColor "yellow"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "errors_status"
+ SID "27"
+ Position [890, 142, 925, 158]
+ BackgroundColor "yellow"
+ NamePlacement "alternate"
+ Port "2"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "data send"
+ SID "28"
+ Position [890, 217, 925, 233]
+ BackgroundColor "yellow"
+ Port "3"
+ IconDisplay "Port number"
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 3
+ DstBlock "set width"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 1
+ DstBlock "Mux"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 2
+ DstBlock "Mux"
+ DstPort 3
+ }
+ Line {
+ SrcBlock "timeout"
+ SrcPort 1
+ DstBlock "receive message 1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "send message 1"
+ SrcPort 1
+ DstBlock "Mux"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Mux"
+ SrcPort 1
+ DstBlock "errors_status"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "set width"
+ SrcPort 1
+ DstBlock "data recv"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "constants"
+ SrcPort 1
+ DstBlock "Mux1"
+ DstPort 1
+ }
+ Line {
+ Labels [0, 0]
+ SrcBlock "Mux1"
+ SrcPort 1
+ Points [55, 0]
+ Branch {
+ Points [0, -30]
+ DstBlock "send message 1"
+ DstPort 2
+ }
+ Branch {
+ Labels [1, 0]
+ Points [0, 50]
+ DstBlock "data send"
+ DstPort 1
+ }
+ }
+ Line {
+ SrcBlock "data ready 1 kHz"
+ SrcPort 1
+ DstBlock "send message 1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Pulse\nGenerator"
+ SrcPort 1
+ Points [0, -25]
+ DstBlock "Mux1"
+ DstPort 2
+ }
+ Annotation {
+ Name "Simple S2SS to OPAL test using UDP messages"
+ Position [433, 47]
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ }
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 1
+ DstBlock "sc_console"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 2
+ DstBlock "sc_console"
+ DstPort 2
+ }
+ Line {
+ Labels [0, 0]
+ SrcBlock "sm_ip_test"
+ SrcPort 3
+ DstBlock "sc_console"
+ DstPort 3
+ }
+ }
+}
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2006b b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2006b
new file mode 100644
index 000000000..1a40670f6
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2006b
@@ -0,0 +1,1226 @@
+# $Revision: 1.1 $
+Model {
+ Name "AsyncIP_sl"
+ Version 6.5
+ MdlSubVersion 0
+ GraphicalInterface {
+ NumRootInports 0
+ NumRootOutports 0
+ ParameterArgumentNames ""
+ ComputedModelVersion "1.384"
+ NumModelReferences 0
+ NumTestPointedSignals 0
+ }
+ SavedCharacterEncoding "windows-1252"
+ SaveDefaultBlockParams on
+ SampleTimeColors off
+ LibraryLinkDisplay "none"
+ WideLines off
+ ShowLineDimensions on
+ ShowPortDataTypes off
+ ShowLoopsOnError on
+ IgnoreBidirectionalLines off
+ ShowStorageClass off
+ ShowTestPointIcons on
+ ShowViewerIcons on
+ SortedOrder off
+ ExecutionContextIcon off
+ ShowLinearizationAnnotations on
+ ScopeRefreshTime 0.035000
+ OverrideScopeRefreshTime on
+ DisableAllScopes off
+ DataTypeOverride "UseLocalSettings"
+ MinMaxOverflowLogging "UseLocalSettings"
+ MinMaxOverflowArchiveMode "Overwrite"
+ BlockNameDataTip off
+ BlockParametersDataTip on
+ BlockDescriptionStringDataTip off
+ ToolBar on
+ StatusBar on
+ BrowserShowLibraryLinks off
+ BrowserLookUnderMasks off
+ Created "Thu Apr 15 08:21:54 1999"
+ Creator "jwu"
+ UpdateHistory "UpdateHistoryNever"
+ ModifiedByFormat "%<Auto>"
+ LastModifiedBy "BiaoYu"
+ ModifiedDateFormat "%<Auto>"
+ LastModifiedDate "Mon Dec 19 13:13:58 2011"
+ ModelVersionFormat "1.%<AutoIncrement:384>"
+ ConfigurationManager "none"
+ LinearizationMsg "none"
+ Profile off
+ ParamWorkspaceSource "MATLABWorkspace"
+ AccelSystemTargetFile "accel.tlc"
+ AccelTemplateMakefile "accel_default_tmf"
+ AccelMakeCommand "make_rtw"
+ TryForcingSFcnDF off
+ RecordCoverage off
+ CovPath "/"
+ CovSaveName "covdata"
+ CovMetricSettings "dw"
+ CovNameIncrementing off
+ CovHtmlReporting on
+ covSaveCumulativeToWorkspaceVar on
+ CovSaveSingleToWorkspaceVar on
+ CovCumulativeVarName "covCumulativeData"
+ CovCumulativeReport off
+ CovReportOnPause on
+ ExtModeBatchMode off
+ ExtModeEnableFloating on
+ ExtModeTrigType "manual"
+ ExtModeTrigMode "oneshot"
+ ExtModeTrigPort "1"
+ ExtModeTrigElement "any"
+ ExtModeTrigDuration 1000
+ ExtModeTrigDurationFloating "auto"
+ ExtModeTrigHoldOff 0
+ ExtModeTrigDelay 0
+ ExtModeTrigDirection "rising"
+ ExtModeTrigLevel 0
+ ExtModeArchiveMode "off"
+ ExtModeAutoIncOneShot off
+ ExtModeIncDirWhenArm off
+ ExtModeAddSuffixToVar off
+ ExtModeWriteAllDataToWs off
+ ExtModeArmWhenConnect off
+ ExtModeSkipDownloadWhenConnect off
+ ExtModeLogAll on
+ ExtModeAutoUpdateStatusClock on
+ BufferReuse off
+ ProdHWDeviceType "32-bit Generic"
+ ShowModelReferenceBlockVersion off
+ ShowModelReferenceBlockIO off
+ Array {
+ Type "Handle"
+ Dimension 1
+ Simulink.ConfigSet {
+ $ObjectID 1
+ Version "1.2.0"
+ Array {
+ Type "Handle"
+ Dimension 7
+ Simulink.SolverCC {
+ $ObjectID 2
+ Version "1.2.0"
+ StartTime "0.0"
+ StopTime "inf"
+ AbsTol "1e-6"
+ FixedStep ".001"
+ InitialStep "auto"
+ MaxNumMinSteps "-1"
+ MaxOrder 5
+ ConsecutiveZCsStepRelTol "10*128*eps"
+ MaxConsecutiveZCs "1000"
+ ExtrapolationOrder 4
+ NumberNewtonIterations 1
+ MaxStep "0.01"
+ MinStep "auto"
+ MaxConsecutiveMinStep "1"
+ RelTol "1e-3"
+ SolverMode "SingleTasking"
+ Solver "ode4"
+ SolverName "ode4"
+ ZeroCrossControl "UseLocalSettings"
+ AlgebraicLoopSolver "TrustRegion"
+ SolverResetMethod "Fast"
+ PositivePriorityOrder off
+ AutoInsertRateTranBlk off
+ SampleTimeConstraint "Unconstrained"
+ RateTranMode "Deterministic"
+ }
+ Simulink.DataIOCC {
+ $ObjectID 3
+ Version "1.2.0"
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+ ExternalInput "[]"
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+ LoadInitialState off
+ SaveFinalState off
+ SaveFormat "Array"
+ SaveOutput off
+ SaveState off
+ SignalLogging on
+ InspectSignalLogs off
+ SaveTime off
+ StateSaveName "xout"
+ TimeSaveName "tout"
+ OutputSaveName "yout"
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+ OutputOption "RefineOutputTimes"
+ OutputTimes "[]"
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+ Simulink.OptimizationCC {
+ $ObjectID 4
+ Array {
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+ Cell "ZeroExternalMemoryAtStartup"
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+ Cell "NoFixptDivByZeroProtection"
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+ MinAlgLoopOccurrences off
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+ FunctionWithSeparateData off
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+ System {
+ Name "sm_ip_test"
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+ Open off
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+ ScreenColor "white"
+ PaperOrientation "landscape"
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+ SourceType "OpDoc"
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+ RTWMemSecDataParameters "Inherit from model"
+ docfile "../../help/help.simulink.html"
+ }
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+ BlockType Reference
+ Name "Logo"
+ Ports []
+ Position [18, 15, 116, 64]
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+ SourceType "Opal-RT logo"
+ ShowPortLabels on
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+ }
+ Block {
+ BlockType Mux
+ Name "Mux"
+ Ports [3, 1]
+ Position [825, 125, 830, 175]
+ ShowName off
+ Inputs "3"
+ DisplayOption "bar"
+ }
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+ BlockType Mux
+ Name "Mux1"
+ Ports [2, 1]
+ Position [255, 144, 260, 206]
+ BackgroundColor "yellow"
+ ShowName off
+ Inputs "2"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Reference
+ Name "OpIPSocketCtrl1"
+ Ports []
+ Position [15, 152, 144, 213]
+ SourceBlock "rtio_generic_ip/OpIPSocketCtrl"
+ SourceType "OpAsyncIPCtrl"
+ ctl_id "1"
+ proto "UDP/IP"
+ ip_addr_remote "192.168.0.72"
+ ip_port_remote "50000"
+ ip_port_local "0"
+ ip_addr_mcast "0.0.0.0"
+ exe_name "AsyncIP"
+ }
+ Block {
+ BlockType Constant
+ Name "constants"
+ Position [165, 151, 235, 169]
+ BackgroundColor "yellow"
+ NamePlacement "alternate"
+ Value "[1 2 3 4]"
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+ FramePeriod "inf"
+ }
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+ Name "data ready 100Hz"
+ Ports [0, 1]
+ Position [275, 146, 320, 164]
+ NamePlacement "alternate"
+ Period "100"
+ SampleTime "0.001"
+ }
+ Block {
+ BlockType Reference
+ Name "receive message 1"
+ Ports [1, 3]
+ Position [600, 144, 775, 186]
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+"v"
+ SourceType "OpAsyncRecv"
+ ShowPortLabels on
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+ RTWMemSecDataParameters "Inherit from model"
+ ctl_id "1"
+ recv_id "1"
+ enable_param off
+ fp1 "1"
+ fp2 "2"
+ fp3 "3"
+ fp4 "4"
+ fp5 "5"
+ sp1 "string1"
+ sp2 "string2"
+ sp3 "string3"
+ sp4 "string4"
+ sp5 "string5"
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+ Position [345, 144, 515, 186]
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+"d"
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+ send_id "1"
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+ enable_param off
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+ fp4 "4"
+ fp5 "5"
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+ sp2 "string2"
+ sp3 "string3"
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+ sp5 "string5"
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+ BlockType SignalSpecification
+ Name "set width"
+ Position [795, 172, 820, 188]
+ Dimensions "5"
+ }
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+ BlockType Sin
+ Name "sine"
+ Ports [0, 1]
+ Position [165, 172, 235, 208]
+ BackgroundColor "yellow"
+ SineType "Time based"
+ Amplitude "1.5"
+ Bias "2.5"
+ }
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+ BlockType Constant
+ Name "timeout"
+ Position [555, 158, 585, 172]
+ Value "2"
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+ OutDataType "sfix(16)"
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+ OutScaling "2^0"
+ SampleTime "inf"
+ FramePeriod "inf"
+ }
+ Block {
+ BlockType Outport
+ Name "message 1 data"
+ Position [855, 172, 890, 188]
+ BackgroundColor "yellow"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "errors_status"
+ Position [855, 142, 890, 158]
+ BackgroundColor "yellow"
+ NamePlacement "alternate"
+ Port "2"
+ IconDisplay "Port number"
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 3
+ DstBlock "set width"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 1
+ DstBlock "Mux"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 2
+ DstBlock "Mux"
+ DstPort 3
+ }
+ Line {
+ SrcBlock "timeout"
+ SrcPort 1
+ DstBlock "receive message 1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Mux1"
+ SrcPort 1
+ DstBlock "send message 1"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "data ready 100Hz"
+ SrcPort 1
+ DstBlock "send message 1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "send message 1"
+ SrcPort 1
+ Points [10, 0; 0, -30]
+ DstBlock "Mux"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Mux"
+ SrcPort 1
+ DstBlock "errors_status"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "set width"
+ SrcPort 1
+ DstBlock "message 1 data"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "constants"
+ SrcPort 1
+ DstBlock "Mux1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "sine"
+ SrcPort 1
+ DstBlock "Mux1"
+ DstPort 2
+ }
+ Annotation {
+ Name "Simple Ethernet communication example"
+ Position [433, 47]
+ UseDisplayTextAsClickCallback off
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ }
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 1
+ DstBlock "sc_console"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 2
+ DstBlock "sc_console"
+ DstPort 2
+ }
+ Annotation {
+ Name "Simple Ethernet communication example"
+ Position [278, 27]
+ UseDisplayTextAsClickCallback off
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ Annotation {
+ Name "Procedure\n=================================\n-"
+" Launch the executable Server.exe located in the model's folder.\n- Specify a"
+" Port number. \n-"
+" Make sure that the OpIPAsyncCtrl icon uses the same Parameters displayed by "
+"the Server application.\n- Compile, Load and Execute this model."
+ Position [62, 257]
+ HorizontalAlignment "left"
+ UseDisplayTextAsClickCallback off
+ FontName "Arial"
+ FontSize 12
+ }
+ }
+}
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2010b b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2010b
new file mode 100644
index 000000000..81cc3da19
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2010b
@@ -0,0 +1,1504 @@
+# $Revision: 1.1 $
+Model {
+ Name "AsyncIP_sl"
+ Version 7.6
+ MdlSubVersion 0
+ GraphicalInterface {
+ NumRootInports 0
+ NumRootOutports 0
+ ParameterArgumentNames ""
+ ComputedModelVersion "1.395"
+ NumModelReferences 0
+ NumTestPointedSignals 0
+ }
+ SavedCharacterEncoding "windows-1252"
+ SaveDefaultBlockParams on
+ ScopeRefreshTime 0.035000
+ OverrideScopeRefreshTime on
+ DisableAllScopes off
+ DataTypeOverride "UseLocalSettings"
+ DataTypeOverrideAppliesTo "AllNumericTypes"
+ MinMaxOverflowLogging "UseLocalSettings"
+ MinMaxOverflowArchiveMode "Overwrite"
+ MaxMDLFileLineLength 120
+ Created "Thu Apr 15 08:21:54 1999"
+ Creator "jwu"
+ UpdateHistory "UpdateHistoryNever"
+ ModifiedByFormat "%<Auto>"
+ LastModifiedBy "E252"
+ ModifiedDateFormat "%<Auto>"
+ LastModifiedDate "Tue Feb 04 16:40:19 2014"
+ RTWModifiedTimeStamp 313432811
+ ModelVersionFormat "1.%<AutoIncrement:395>"
+ ConfigurationManager "none"
+ SampleTimeColors off
+ SampleTimeAnnotations off
+ LibraryLinkDisplay "none"
+ WideLines off
+ ShowLineDimensions on
+ ShowPortDataTypes off
+ ShowLoopsOnError on
+ IgnoreBidirectionalLines off
+ ShowStorageClass off
+ ShowTestPointIcons on
+ ShowSignalResolutionIcons on
+ ShowViewerIcons on
+ SortedOrder off
+ ExecutionContextIcon off
+ ShowLinearizationAnnotations on
+ BlockNameDataTip off
+ BlockParametersDataTip on
+ BlockDescriptionStringDataTip off
+ ToolBar on
+ StatusBar on
+ BrowserShowLibraryLinks off
+ BrowserLookUnderMasks off
+ SimulationMode "normal"
+ LinearizationMsg "none"
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+ RTWMemSecDataParameters "Inherit from model"
+ GeneratePreprocessorConditionals off
+ nbport "3"
+ groupe_acq "1"
+ subsys_rate "0"
+ st "0"
+ Synchronization on
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+ Threshold "1.0"
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+ }
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+ Lockdown off
+ }
+ Block {
+ BlockType Scope
+ Name "message 1"
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+ Ports [1]
+ Position [460, 199, 490, 231]
+ BackgroundColor "yellow"
+ Floating off
+ Location [644, 422, 968, 661]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ YMin "0"
+ YMax "10"
+ SaveName "ScopeData10"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Scope
+ Name "message 2"
+ SID "33"
+ Ports [1]
+ Position [545, 284, 575, 316]
+ BackgroundColor "yellow"
+ Floating off
+ Location [644, 422, 968, 661]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ YMin "0"
+ YMax "10"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Display
+ Name "reception status"
+ SID "12"
+ Ports [1]
+ Position [390, 163, 450, 187]
+ BackgroundColor "yellow"
+ FontName "Arial"
+ FontSize 8
+ Decimation "1"
+ Lockdown off
+ }
+ Line {
+ SrcBlock "errors_status"
+ SrcPort 1
+ Points [35, 0]
+ DstBlock "OpComm"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "OpComm"
+ SrcPort 2
+ Points [20, 0; 0, 50; 85, 0]
+ Branch {
+ DstBlock "message 1"
+ DstPort 1
+ }
+ Branch {
+ Points [0, 70]
+ DstBlock "Demux1"
+ DstPort 1
+ }
+ }
+ Line {
+ SrcBlock "message 1 data"
+ SrcPort 1
+ DstBlock "OpComm"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "OpComm"
+ SrcPort 1
+ Points [0, 5]
+ DstBlock "Demux"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Demux"
+ SrcPort 1
+ Points [35, 0; 0, -25]
+ DstBlock "errors"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Demux"
+ SrcPort 2
+ Points [35, 0; 0, 15]
+ DstBlock "reception status"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "data orgn"
+ SrcPort 1
+ Points [35, 0]
+ DstBlock "OpComm"
+ DstPort 3
+ }
+ Line {
+ SrcBlock "OpComm"
+ SrcPort 3
+ Points [0, 185; 205, 0]
+ DstBlock "Mux"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "Demux1"
+ SrcPort 5
+ Points [35, 0; 0, -25]
+ DstBlock "Mux"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Mux"
+ SrcPort 1
+ DstBlock "message 2"
+ DstPort 1
+ }
+ Annotation {
+ Name "Simple Ethernet communication example"
+ Position [298, 67]
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ }
+ }
+ Block {
+ BlockType SubSystem
+ Name "sm_ip_test"
+ SID "13"
+ Ports [0, 3]
+ Position [55, 97, 235, 193]
+ BackgroundColor "lightBlue"
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ System {
+ Name "sm_ip_test"
+ Location [71, 188, 995, 474]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "A4"
+ PaperUnits "centimeters"
+ TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ Block {
+ BlockType Constant
+ Name "Constant"
+ SID "37"
+ Position [290, 165, 320, 195]
+ }
+ Block {
+ BlockType Reference
+ Name "Help"
+ SID "14"
+ Ports []
+ Position [810, 20, 842, 52]
+ LibraryVersion "1.294"
+ FontName "Arial"
+ FontSize 12
+ FontWeight "bold"
+ SourceBlock "opal_lib/Help"
+ SourceType "OpDoc"
+ ShowPortLabels "FromPortIcon"
+ SystemSampleTime "-1"
+ FunctionWithSeparateData off
+ RTWMemSecFuncInitTerm "Inherit from model"
+ RTWMemSecFuncExecute "Inherit from model"
+ RTWMemSecDataConstants "Inherit from model"
+ RTWMemSecDataInternal "Inherit from model"
+ RTWMemSecDataParameters "Inherit from model"
+ GeneratePreprocessorConditionals off
+ docfile "../../help/help.simulink.html"
+ }
+ Block {
+ BlockType Reference
+ Name "Logo"
+ SID "15"
+ Ports []
+ Position [18, 15, 116, 64]
+ ShowName off
+ LibraryVersion "1.294"
+ SourceBlock "opal_lib/Logo1"
+ SourceType "Opal-RT logo"
+ ShowPortLabels "FromPortIcon"
+ SystemSampleTime "-1"
+ FunctionWithSeparateData off
+ RTWMemSecFuncInitTerm "Inherit from model"
+ RTWMemSecFuncExecute "Inherit from model"
+ RTWMemSecDataConstants "Inherit from model"
+ RTWMemSecDataInternal "Inherit from model"
+ RTWMemSecDataParameters "Inherit from model"
+ GeneratePreprocessorConditionals off
+ }
+ Block {
+ BlockType Mux
+ Name "Mux"
+ SID "16"
+ Ports [3, 1]
+ Position [825, 125, 830, 175]
+ ShowName off
+ Inputs "3"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Mux
+ Name "Mux1"
+ SID "17"
+ Ports [2, 1]
+ Position [255, 144, 260, 206]
+ BackgroundColor "yellow"
+ ShowName off
+ Inputs "2"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Reference
+ Name "OpIPSocketCtrl1"
+ SID "18"
+ Ports []
+ Position [15, 152, 144, 213]
+ LibraryVersion "1.10"
+ SourceBlock "rtio_generic_ip/OpIPSocketCtrl"
+ SourceType "OpAsyncIPCtrl"
+ ctl_id "1"
+ proto "UDP/IP"
+ ip_addr_remote "137.226.160.124"
+ ip_port_remote "51000"
+ ip_port_local "61556"
+ ip_addr_mcast "0.0.0.0"
+ exe_name "AsyncIP"
+ }
+ Block {
+ BlockType Constant
+ Name "constants"
+ SID "19"
+ Position [165, 151, 235, 169]
+ BackgroundColor "yellow"
+ NamePlacement "alternate"
+ Value "[1 2 3 4]"
+ }
+ Block {
+ BlockType DiscretePulseGenerator
+ Name "data ready 100Hz"
+ SID "20"
+ Ports [0, 1]
+ Position [370, 86, 415, 104]
+ NamePlacement "alternate"
+ Period "10"
+ SampleTime "0.00005"
+ }
+ Block {
+ BlockType DiscretePulseGenerator
+ Name "data ready 100Hz orgn"
+ SID "35"
+ Ports [0, 1]
+ Position [255, 111, 300, 129]
+ NamePlacement "alternate"
+ Period "1000"
+ SampleTime "0.001"
+ }
+ Block {
+ BlockType Reference
+ Name "receive message 1"
+ SID "21"
+ Ports [1, 3]
+ Position [600, 144, 775, 186]
+ LibraryVersion "1.348"
+ SourceBlock "rtlab/Communication/Asynchronous/OpAsyncRecv"
+ SourceType "OpAsyncRecv"
+ ShowPortLabels "FromPortIcon"
+ SystemSampleTime "-1"
+ FunctionWithSeparateData off
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+ RTWMemSecFuncExecute "Inherit from model"
+ RTWMemSecDataConstants "Inherit from model"
+ RTWMemSecDataInternal "Inherit from model"
+ RTWMemSecDataParameters "Inherit from model"
+ GeneratePreprocessorConditionals off
+ ctl_id "1"
+ recv_id "1"
+ enable_param off
+ fp1 "1"
+ fp2 "2"
+ fp3 "3"
+ fp4 "4"
+ fp5 "5"
+ sp1 "string1"
+ sp2 "string2"
+ sp3 "string3"
+ sp4 "string4"
+ sp5 "string5"
+ }
+ Block {
+ BlockType Reference
+ Name "send message 1"
+ SID "22"
+ Ports [2, 1]
+ Position [345, 144, 515, 186]
+ LibraryVersion "1.348"
+ SourceBlock "rtlab/Communication/Asynchronous/OpAsyncSend"
+ SourceType "OpAsyncSend"
+ ShowPortLabels "FromPortIcon"
+ SystemSampleTime "-1"
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+ RTWMemSecFuncExecute "Inherit from model"
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+ RTWMemSecDataInternal "Inherit from model"
+ RTWMemSecDataParameters "Inherit from model"
+ GeneratePreprocessorConditionals off
+ ctl_id "1"
+ send_id "1"
+ mode "DONT_NEED_REPLY"
+ enable_param off
+ fp1 "1"
+ fp2 "2"
+ fp3 "3"
+ fp4 "4"
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+ sp3 "string3"
+ sp4 "string4"
+ sp5 "string5"
+ }
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+ Name "set width"
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+ Position [795, 172, 820, 188]
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+ }
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+ SID "24"
+ Ports [0, 1]
+ Position [165, 172, 235, 208]
+ BackgroundColor "yellow"
+ Amplitude "1.5"
+ }
+ Block {
+ BlockType Constant
+ Name "timeout"
+ SID "25"
+ Position [555, 158, 585, 172]
+ Value "2"
+ }
+ Block {
+ BlockType Outport
+ Name "message 1 data"
+ SID "26"
+ Position [855, 172, 890, 188]
+ BackgroundColor "yellow"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "errors_status"
+ SID "27"
+ Position [855, 142, 890, 158]
+ BackgroundColor "yellow"
+ NamePlacement "alternate"
+ Port "2"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "data orgn"
+ SID "28"
+ Position [855, 217, 890, 233]
+ BackgroundColor "yellow"
+ Port "3"
+ IconDisplay "Port number"
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 3
+ DstBlock "set width"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 1
+ DstBlock "Mux"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "receive message 1"
+ SrcPort 2
+ DstBlock "Mux"
+ DstPort 3
+ }
+ Line {
+ SrcBlock "timeout"
+ SrcPort 1
+ DstBlock "receive message 1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "send message 1"
+ SrcPort 1
+ Points [10, 0; 0, -30]
+ DstBlock "Mux"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Mux"
+ SrcPort 1
+ DstBlock "errors_status"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "set width"
+ SrcPort 1
+ DstBlock "message 1 data"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "constants"
+ SrcPort 1
+ DstBlock "Mux1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "sine"
+ SrcPort 1
+ Points [0, 0]
+ Branch {
+ DstBlock "Mux1"
+ DstPort 2
+ }
+ Branch {
+ Points [0, 35]
+ DstBlock "data orgn"
+ DstPort 1
+ }
+ }
+ Line {
+ SrcBlock "data ready 100Hz orgn"
+ SrcPort 1
+ Points [10, 0; 0, 35]
+ DstBlock "send message 1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Constant"
+ SrcPort 1
+ Points [0, -5]
+ DstBlock "send message 1"
+ DstPort 2
+ }
+ Annotation {
+ Name "Simple Ethernet communication example"
+ Position [433, 47]
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ }
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 1
+ Points [85, 0]
+ DstBlock "sc_console"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 2
+ Points [0, -5]
+ DstBlock "sc_console"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "sm_ip_test"
+ SrcPort 3
+ Points [40, 0; 0, -5]
+ DstBlock "sc_console"
+ DstPort 3
+ }
+ Annotation {
+ Name "Simple Ethernet communication example"
+ Position [278, 27]
+ FontName "Verdana"
+ FontSize 14
+ FontWeight "bold"
+ }
+ Annotation {
+ Name "Procedure\n=================================\n- Launch the executable Server.exe located in the mod"
+ "el's folder.\n- Specify a Port number. \n- Make sure"
+ " that the OpIPAsyncCtrl icon uses the same Parameters displayed by the Server application.\n- Compile, Load and "
+ "Execute this model."
+ Position [62, 437]
+ HorizontalAlignment "left"
+ FontName "Arial"
+ FontSize 12
+ }
+ }
+}
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl.probe b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.probe
new file mode 100644
index 000000000..334568343
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl.probe
@@ -0,0 +1,59 @@
+[General]
+ATT_VERSION=6
+numClientsProbe=0
+fileVersion=6
+[Group_1]
+maxDynSignals=100
+fixSignalsList=13|1|2|3|4|5|6|7|8|9|10|11|12|13
+dynSignalsList=0
+signalName=
+trigSignalName=
+level=0.000000
+offset=0
+condition=0
+triggerEnabled=0
+trigType=0
+sigNameId=800
+trigSigNameId=0
+nodeId=0
+decimationFactor=1
+valueType=0
+numValues=200
+duration=0.010000
+newMemSize=2500
+triggerState=0
+repetitive=1
+rearmDelay=0.000000
+triggerButton=2
+writeEnabled=0
+writeFileName=
+writeFileVarName=
+fileLimit=1000000
+[Group_25]
+maxDynSignals=42
+signalName=
+trigSignalName=
+level=0.000000
+offset=0
+condition=0
+triggerEnabled=0
+trigType=0
+sigNameId=2033149028
+trigSigNameId=1684275321
+nodeId=539780196
+decimationFactor=1
+valueType=0
+numValues=100
+duration=0.005000
+newMemSize=100
+triggerState=0
+repetitive=1
+rearmDelay=0.000000
+triggerButton=2
+writeEnabled=0
+writeFileName=
+writeFileVarName=
+fileLimit=0
+dynSignalsList=0
+[DynGroup_1]
+[DynGroup_25]
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/AsyncIP b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/AsyncIP
new file mode 100644
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/OpalSnapshotUtil.c b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/OpalSnapshotUtil.c
new file mode 100644
index 000000000..83b70d0c0
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/OpalSnapshotUtil.c
@@ -0,0 +1,154 @@
+/**
+ * This function is generated by RT-LAB during model compilation (at 'generation' step).
+ * This function copies data from src to dst, ignoring pointers.
+ * Note that only PWork are supposed to be pointers within a DWork structure
+ * and that sub-structures are copied in one operation since they do not contain pointers.
+ */
+int OpalSnapshot_Copy_DWork(void * src, void * dst) {
+ D_Work * pSrc = (D_Work*)src;
+ D_Work * pDst = (D_Work*)dst;
+ int size = 0, eltSize = 0;
+
+ eltSize = sizeof(pSrc->SFunction_PreviousInput);
+ memcpy(&pDst->SFunction_PreviousInput, &pSrc->SFunction_PreviousInput, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->clockTickCounter);
+ memcpy(&pDst->clockTickCounter, &pSrc->clockTickCounter, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->clockTickCounter_c);
+ memcpy(&pDst->clockTickCounter_c, &pSrc->clockTickCounter_c, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->SFunction_IWORK);
+ memcpy(&pDst->SFunction_IWORK, &pSrc->SFunction_IWORK, eltSize);
+ size += eltSize;
+
+ return size;
+}
+
+/**
+ * This function is generated by RT-LAB during model compilation (at 'generation' step).
+ * This function copies data from a raw buffer (src)
+ * to an RT_MODEL structure(dst), ignoring pointers.
+ * Note that sub-structures are copied in one operation since they cannot contain pointers.
+ */
+int OpalSnapshot_Copy_TimingData(void * src, void * dst) {
+ RT_MODEL tmpBuffer;
+ RT_MODEL * pSrc = &tmpBuffer;
+ RT_MODEL * pDst = (RT_MODEL *)dst;
+ int TimingSize = sizeof(tmpBuffer.Timing);
+ int size = 0, eltSize = 0;
+
+ memcpy(&tmpBuffer.Timing, src, TimingSize);
+
+ eltSize = sizeof(pSrc->Timing.clockTick0);
+ memcpy(&pDst->Timing.clockTick0, &pSrc->Timing.clockTick0, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.clockTick1);
+ memcpy(&pDst->Timing.clockTick1, &pSrc->Timing.clockTick1, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.clockTickH0);
+ memcpy(&pDst->Timing.clockTickH0, &pSrc->Timing.clockTickH0, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.clockTickH1);
+ memcpy(&pDst->Timing.clockTickH1, &pSrc->Timing.clockTickH1, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.tFinal);
+ memcpy(&pDst->Timing.tFinal, &pSrc->Timing.tFinal, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.offsetTimesArray);
+ memcpy(&pDst->Timing.offsetTimesArray, &pSrc->Timing.offsetTimesArray, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.perTaskSampleHitsArray);
+ memcpy(&pDst->Timing.perTaskSampleHitsArray, &pSrc->Timing.perTaskSampleHitsArray, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.sampleHitArray);
+ memcpy(&pDst->Timing.sampleHitArray, &pSrc->Timing.sampleHitArray, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.sampleTimesArray);
+ memcpy(&pDst->Timing.sampleTimesArray, &pSrc->Timing.sampleTimesArray, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.sampleTimeTaskIDArray);
+ memcpy(&pDst->Timing.sampleTimeTaskIDArray, &pSrc->Timing.sampleTimeTaskIDArray, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.simTimeStep);
+ memcpy(&pDst->Timing.simTimeStep, &pSrc->Timing.simTimeStep, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.tStart);
+ memcpy(&pDst->Timing.tStart, &pSrc->Timing.tStart, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.stepSize);
+ memcpy(&pDst->Timing.stepSize, &pSrc->Timing.stepSize, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.stepSize0);
+ memcpy(&pDst->Timing.stepSize0, &pSrc->Timing.stepSize0, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.stepSize1);
+ memcpy(&pDst->Timing.stepSize1, &pSrc->Timing.stepSize1, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.stopRequestedFlag);
+ memcpy(&pDst->Timing.stopRequestedFlag, &pSrc->Timing.stopRequestedFlag, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.TaskCounters);
+ memcpy(&pDst->Timing.TaskCounters, &pSrc->Timing.TaskCounters, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.tArray);
+ memcpy(&pDst->Timing.tArray, &pSrc->Timing.tArray, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->Timing.timeOfLastOutput);
+ memcpy(&pDst->Timing.timeOfLastOutput, &pSrc->Timing.timeOfLastOutput, eltSize);
+ size += eltSize;
+
+ return size;
+}
+
+/**
+ * This function is generated by RT-LAB during model compilation (at 'generation' step).
+ * This function copies data from a raw buffer (src)
+ * to an RT_MODEL structure(dst), ignoring pointers.
+ * Note that ingData must not be copied since it contains pointers.
+ */
+int OpalSnapshot_Copy_ModelData(void * src, void * dst) {
+ RT_MODEL tmpBuffer;
+ RT_MODEL * pSrc = &tmpBuffer;
+ RT_MODEL * pDst = (RT_MODEL *)dst;
+ int ModelDataSize = sizeof(tmpBuffer.ModelData);
+ int size = 0, eltSize = 0;
+
+ memcpy(&tmpBuffer.ModelData, src, ModelDataSize);
+
+ eltSize = sizeof(pSrc->ModelData.blkStateChange);
+ memcpy(&pDst->ModelData.blkStateChange, &pSrc->ModelData.blkStateChange, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->ModelData.derivCacheNeedsReset);
+ memcpy(&pDst->ModelData.derivCacheNeedsReset, &pSrc->ModelData.derivCacheNeedsReset, eltSize);
+ size += eltSize;
+
+ eltSize = sizeof(pSrc->ModelData.zCCacheNeedsReset);
+ memcpy(&pDst->ModelData.zCCacheNeedsReset, &pSrc->ModelData.zCCacheNeedsReset, eltSize);
+ size += eltSize;
+
+ return size;
+}
+
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test
new file mode 100644
index 0000000000000000000000000000000000000000..e8199e2d9c0ed6825ee00dccae38d25c88147bd4
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.bat b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.bat
new file mode 100644
index 000000000..fbfd6e83d
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.bat
@@ -0,0 +1,2 @@
+set MATLAB=C:\Program Files (x86)\MATLAB\R2011b
+make -f asyncip_sl_1_sm_ip_test.mk GENERATE_REPORT=0 EXT_MODE=0 EXTMODE_STATIC_ALLOC=0 TMW_EXTMODE_TESTING=0 EXTMODE_STATIC_ALLOC_SIZE=1000000 EXTMODE_TRANSPORT=0
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.c b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.c
new file mode 100644
index 000000000..9a69cf368
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.c
@@ -0,0 +1,1170 @@
+/*
+ * asyncip_sl_1_sm_ip_test.c
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+#include "asyncip_sl_1_sm_ip_test.h"
+#include "asyncip_sl_1_sm_ip_test_private.h"
+
+/* Block signals (auto storage) */
+BlockIO_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_B;
+
+/* Block states (auto storage) */
+D_Work_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_DWork;
+
+/* Real-time model */
+RT_MODEL_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_M_;
+RT_MODEL_asyncip_sl_1_sm_ip_test *const asyncip_sl_1_sm_ip_test_M =
+ &asyncip_sl_1_sm_ip_test_M_;
+static void rate_scheduler(void);
+
+/*
+ * This function updates active task flag for each subrate.
+ * The function is called at model base rate, hence the
+ * generated code self-manages all its subrates.
+ */
+static void rate_scheduler(void)
+{
+ /* Compute which subrates run during the next base time step. Subrates
+ * are an integer multiple of the base rate counter. Therefore, the subtask
+ * counter is reset when it reaches its limit (zero means run).
+ */
+ (asyncip_sl_1_sm_ip_test_M->Timing.TaskCounters.TID[1])++;
+ if ((asyncip_sl_1_sm_ip_test_M->Timing.TaskCounters.TID[1]) > 19) {/* Sample time: [0.001s, 0.0s] */
+ asyncip_sl_1_sm_ip_test_M->Timing.TaskCounters.TID[1] = 0;
+ }
+
+ asyncip_sl_1_sm_ip_test_M->Timing.sampleHits[1] =
+ (asyncip_sl_1_sm_ip_test_M->Timing.TaskCounters.TID[1] == 0);
+}
+
+/* Model output function */
+static void asyncip_sl_1_sm_ip_test_output(int_T tid)
+{
+ /* Memory: '<S1>/S-Function' */
+ asyncip_sl_1_sm_ip_test_B.SFunction =
+ asyncip_sl_1_sm_ip_test_DWork.SFunction_PreviousInput;
+
+ /* Sum: '<S1>/Sum' incorporates:
+ * Constant: '<S1>/S-Function1'
+ */
+ asyncip_sl_1_sm_ip_test_B.Sum = asyncip_sl_1_sm_ip_test_P.SFunction1_Value +
+ asyncip_sl_1_sm_ip_test_B.SFunction;
+
+ /* Stop: '<S1>/Stop Simulation' */
+ if (asyncip_sl_1_sm_ip_test_B.Sum != 0.0) {
+ rtmSetStopRequested(asyncip_sl_1_sm_ip_test_M, 1);
+ }
+
+ /* End of Stop: '<S1>/Stop Simulation' */
+ if (asyncip_sl_1_sm_ip_test_M->Timing.TaskCounters.TID[1] == 0) {
+ /* DiscretePulseGenerator: '<S2>/data ready 1 kHz' */
+ asyncip_sl_1_sm_ip_test_B.dataready1kHz = ((real_T)
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter <
+ asyncip_sl_1_sm_ip_test_P.dataready1kHz_Duty) &&
+ (asyncip_sl_1_sm_ip_test_DWork.clockTickCounter >= 0) ?
+ asyncip_sl_1_sm_ip_test_P.dataready1kHz_Amp : 0.0;
+ if ((real_T)asyncip_sl_1_sm_ip_test_DWork.clockTickCounter >=
+ asyncip_sl_1_sm_ip_test_P.dataready1kHz_Period - 1.0) {
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter = 0;
+ } else {
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter =
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter + 1;
+ }
+
+ /* End of DiscretePulseGenerator: '<S2>/data ready 1 kHz' */
+ }
+
+ /* DiscretePulseGenerator: '<S2>/Pulse Generator' */
+ asyncip_sl_1_sm_ip_test_B.PulseGenerator = ((real_T)
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c <
+ asyncip_sl_1_sm_ip_test_P.PulseGenerator_Duty) &&
+ (asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c >= 0) ?
+ asyncip_sl_1_sm_ip_test_P.PulseGenerator_Amp : 0.0;
+ if ((real_T)asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c >=
+ asyncip_sl_1_sm_ip_test_P.PulseGenerator_Period - 1.0) {
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c = 0;
+ } else {
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c =
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c + 1;
+ }
+
+ /* End of DiscretePulseGenerator: '<S2>/Pulse Generator' */
+
+ /* Level2 S-Function Block: '<S5>/S-Function2' (sfun_send_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[0];
+ sfcnOutputs(rts, 0);
+ }
+
+ /* Level2 S-Function Block: '<S3>/S-Function1' (sfun_recv_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[1];
+ sfcnOutputs(rts, 0);
+ }
+
+ /* Level2 S-Function Block: '<S7>/S-Function' (OP_SEND) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[2];
+ sfcnOutputs(rts, 0);
+ }
+
+ /* Level2 S-Function Block: '<S2>/OpIPSocketCtrl1' (sfun_gen_async_ctrl) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[3];
+ sfcnOutputs(rts, 0);
+ }
+
+ /* tid is required for a uniform function interface.
+ * Argument tid is not used in the function. */
+ UNUSED_PARAMETER(tid);
+}
+
+/* Model update function */
+static void asyncip_sl_1_sm_ip_test_update(int_T tid)
+{
+ /* Update for Memory: '<S1>/S-Function' */
+ asyncip_sl_1_sm_ip_test_DWork.SFunction_PreviousInput =
+ asyncip_sl_1_sm_ip_test_B.Sum;
+
+ /* Update absolute time for base rate */
+ /* The "clockTick0" counts the number of times the code of this task has
+ * been executed. The absolute time is the multiplication of "clockTick0"
+ * and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
+ * overflow during the application lifespan selected.
+ * Timer of this task consists of two 32 bit unsigned integers.
+ * The two integers represent the low bits Timing.clockTick0 and the high bits
+ * Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
+ */
+ if (!(++asyncip_sl_1_sm_ip_test_M->Timing.clockTick0)) {
+ ++asyncip_sl_1_sm_ip_test_M->Timing.clockTickH0;
+ }
+
+ asyncip_sl_1_sm_ip_test_M->Timing.t[0] =
+ asyncip_sl_1_sm_ip_test_M->Timing.clockTick0 *
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize0 +
+ asyncip_sl_1_sm_ip_test_M->Timing.clockTickH0 *
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize0 * 4294967296.0;
+ if (asyncip_sl_1_sm_ip_test_M->Timing.TaskCounters.TID[1] == 0) {
+ /* Update absolute timer for sample time: [0.001s, 0.0s] */
+ /* The "clockTick1" counts the number of times the code of this task has
+ * been executed. The absolute time is the multiplication of "clockTick1"
+ * and "Timing.stepSize1". Size of "clockTick1" ensures timer will not
+ * overflow during the application lifespan selected.
+ * Timer of this task consists of two 32 bit unsigned integers.
+ * The two integers represent the low bits Timing.clockTick1 and the high bits
+ * Timing.clockTickH1. When the low bit overflows to 0, the high bits increment.
+ */
+ if (!(++asyncip_sl_1_sm_ip_test_M->Timing.clockTick1)) {
+ ++asyncip_sl_1_sm_ip_test_M->Timing.clockTickH1;
+ }
+
+ asyncip_sl_1_sm_ip_test_M->Timing.t[1] =
+ asyncip_sl_1_sm_ip_test_M->Timing.clockTick1 *
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize1 +
+ asyncip_sl_1_sm_ip_test_M->Timing.clockTickH1 *
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize1 * 4294967296.0;
+ }
+
+ rate_scheduler();
+
+ /* tid is required for a uniform function interface.
+ * Argument tid is not used in the function. */
+ UNUSED_PARAMETER(tid);
+}
+
+/* Model initialize function */
+void asyncip_sl_1_sm_ip_test_initialize(boolean_T firstTime)
+{
+ (void)firstTime;
+
+ /* Registration code */
+
+ /* initialize non-finites */
+ rt_InitInfAndNaN(sizeof(real_T));
+
+ /* initialize real-time model */
+ (void) memset((void *)asyncip_sl_1_sm_ip_test_M, 0,
+ sizeof(RT_MODEL_asyncip_sl_1_sm_ip_test));
+ rtsiSetSolverName(&asyncip_sl_1_sm_ip_test_M->solverInfo,"FixedStepDiscrete");
+ asyncip_sl_1_sm_ip_test_M->solverInfoPtr =
+ (&asyncip_sl_1_sm_ip_test_M->solverInfo);
+
+ /* Initialize timing info */
+ {
+ int_T *mdlTsMap = asyncip_sl_1_sm_ip_test_M->Timing.sampleTimeTaskIDArray;
+ mdlTsMap[0] = 0;
+ mdlTsMap[1] = 1;
+ asyncip_sl_1_sm_ip_test_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
+ asyncip_sl_1_sm_ip_test_M->Timing.sampleTimes =
+ (&asyncip_sl_1_sm_ip_test_M->Timing.sampleTimesArray[0]);
+ asyncip_sl_1_sm_ip_test_M->Timing.offsetTimes =
+ (&asyncip_sl_1_sm_ip_test_M->Timing.offsetTimesArray[0]);
+
+ /* task periods */
+ asyncip_sl_1_sm_ip_test_M->Timing.sampleTimes[0] = (5.0E-5);
+ asyncip_sl_1_sm_ip_test_M->Timing.sampleTimes[1] = (0.001);
+
+ /* task offsets */
+ asyncip_sl_1_sm_ip_test_M->Timing.offsetTimes[0] = (0.0);
+ asyncip_sl_1_sm_ip_test_M->Timing.offsetTimes[1] = (0.0);
+ }
+
+ rtmSetTPtr(asyncip_sl_1_sm_ip_test_M,
+ &asyncip_sl_1_sm_ip_test_M->Timing.tArray[0]);
+
+ {
+ int_T *mdlSampleHits = asyncip_sl_1_sm_ip_test_M->Timing.sampleHitArray;
+ mdlSampleHits[0] = 1;
+ mdlSampleHits[1] = 1;
+ asyncip_sl_1_sm_ip_test_M->Timing.sampleHits = (&mdlSampleHits[0]);
+ }
+
+ rtmSetTFinal(asyncip_sl_1_sm_ip_test_M, -1);
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize0 = 5.0E-5;
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize1 = 0.001;
+
+ /* Setup for data logging */
+ {
+ static RTWLogInfo rt_DataLoggingInfo;
+ asyncip_sl_1_sm_ip_test_M->rtwLogInfo = &rt_DataLoggingInfo;
+ }
+
+ /* Setup for data logging */
+ {
+ rtliSetLogXSignalInfo(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, (NULL));
+ rtliSetLogXSignalPtrs(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, (NULL));
+ rtliSetLogT(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, "");
+ rtliSetLogX(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, "");
+ rtliSetLogXFinal(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, "");
+ rtliSetSigLog(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, "");
+ rtliSetLogVarNameModifier(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, "rt_");
+ rtliSetLogFormat(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, 0);
+ rtliSetLogMaxRows(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, 0);
+ rtliSetLogDecimation(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, 1);
+ rtliSetLogY(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, "");
+ rtliSetLogYSignalInfo(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, (NULL));
+ rtliSetLogYSignalPtrs(asyncip_sl_1_sm_ip_test_M->rtwLogInfo, (NULL));
+ }
+
+ asyncip_sl_1_sm_ip_test_M->solverInfoPtr =
+ (&asyncip_sl_1_sm_ip_test_M->solverInfo);
+ asyncip_sl_1_sm_ip_test_M->Timing.stepSize = (5.0E-5);
+ rtsiSetFixedStepSize(&asyncip_sl_1_sm_ip_test_M->solverInfo, 5.0E-5);
+ rtsiSetSolverMode(&asyncip_sl_1_sm_ip_test_M->solverInfo,
+ SOLVER_MODE_SINGLETASKING);
+
+ /* block I/O */
+ asyncip_sl_1_sm_ip_test_M->ModelData.blockIO = ((void *)
+ &asyncip_sl_1_sm_ip_test_B);
+
+ {
+ int_T i;
+ for (i = 0; i < 5; i++) {
+ asyncip_sl_1_sm_ip_test_B.SFunction1_o3[i] = 0.0;
+ }
+
+ asyncip_sl_1_sm_ip_test_B.SFunction = 0.0;
+ asyncip_sl_1_sm_ip_test_B.Sum = 0.0;
+ asyncip_sl_1_sm_ip_test_B.dataready1kHz = 0.0;
+ asyncip_sl_1_sm_ip_test_B.PulseGenerator = 0.0;
+ asyncip_sl_1_sm_ip_test_B.SFunction2 = 0.0;
+ asyncip_sl_1_sm_ip_test_B.SFunction1_o1 = 0.0;
+ asyncip_sl_1_sm_ip_test_B.SFunction1_o2 = 0.0;
+ }
+
+ /* parameters */
+ asyncip_sl_1_sm_ip_test_M->ModelData.defaultParam = ((real_T *)
+ &asyncip_sl_1_sm_ip_test_P);
+
+ /* states (dwork) */
+ asyncip_sl_1_sm_ip_test_M->Work.dwork = ((void *)
+ &asyncip_sl_1_sm_ip_test_DWork);
+ (void) memset((void *)&asyncip_sl_1_sm_ip_test_DWork, 0,
+ sizeof(D_Work_asyncip_sl_1_sm_ip_test));
+ asyncip_sl_1_sm_ip_test_DWork.SFunction_PreviousInput = 0.0;
+
+ /* child S-Function registration */
+ {
+ RTWSfcnInfo *sfcnInfo = &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.sfcnInfo;
+ asyncip_sl_1_sm_ip_test_M->sfcnInfo = (sfcnInfo);
+ rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus
+ (asyncip_sl_1_sm_ip_test_M)));
+ rtssSetNumRootSampTimesPtr(sfcnInfo,
+ &asyncip_sl_1_sm_ip_test_M->Sizes.numSampTimes);
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.taskTimePtrs[0] = &(rtmGetTPtr
+ (asyncip_sl_1_sm_ip_test_M)[0]);
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.taskTimePtrs[1] = &(rtmGetTPtr
+ (asyncip_sl_1_sm_ip_test_M)[1]);
+ rtssSetTPtrPtr(sfcnInfo,
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.taskTimePtrs);
+ rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(asyncip_sl_1_sm_ip_test_M));
+ rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(asyncip_sl_1_sm_ip_test_M));
+ rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput
+ (asyncip_sl_1_sm_ip_test_M));
+ rtssSetStepSizePtr(sfcnInfo, &asyncip_sl_1_sm_ip_test_M->Timing.stepSize);
+ rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested
+ (asyncip_sl_1_sm_ip_test_M));
+ rtssSetDerivCacheNeedsResetPtr(sfcnInfo,
+ &asyncip_sl_1_sm_ip_test_M->ModelData.derivCacheNeedsReset);
+ rtssSetZCCacheNeedsResetPtr(sfcnInfo,
+ &asyncip_sl_1_sm_ip_test_M->ModelData.zCCacheNeedsReset);
+ rtssSetBlkStateChangePtr(sfcnInfo,
+ &asyncip_sl_1_sm_ip_test_M->ModelData.blkStateChange);
+ rtssSetSampleHitsPtr(sfcnInfo, &asyncip_sl_1_sm_ip_test_M->Timing.sampleHits);
+ rtssSetPerTaskSampleHitsPtr(sfcnInfo,
+ &asyncip_sl_1_sm_ip_test_M->Timing.perTaskSampleHits);
+ rtssSetSimModePtr(sfcnInfo, &asyncip_sl_1_sm_ip_test_M->simMode);
+ rtssSetSolverInfoPtr(sfcnInfo, &asyncip_sl_1_sm_ip_test_M->solverInfoPtr);
+ }
+
+ asyncip_sl_1_sm_ip_test_M->Sizes.numSFcns = (4);
+
+ /* register each child */
+ {
+ (void) memset((void *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.childSFunctions[0],
+ 0,
+ 4*sizeof(SimStruct));
+ asyncip_sl_1_sm_ip_test_M->childSfunctions =
+ (&asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.childSFunctionPtrs[0]);
+ asyncip_sl_1_sm_ip_test_M->childSfunctions[0] =
+ (&asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.childSFunctions[0]);
+ asyncip_sl_1_sm_ip_test_M->childSfunctions[1] =
+ (&asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.childSFunctions[1]);
+ asyncip_sl_1_sm_ip_test_M->childSfunctions[2] =
+ (&asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.childSFunctions[2]);
+ asyncip_sl_1_sm_ip_test_M->childSfunctions[3] =
+ (&asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.childSFunctions[3]);
+
+ /* Level2 S-Function Block: asyncip_sl_1_sm_ip_test/<S5>/S-Function2 (sfun_send_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[0];
+
+ /* timing info */
+ time_T *sfcnPeriod =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
+ time_T *sfcnOffset =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
+ int_T *sfcnTsMap =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
+ (void) memset((void*)sfcnPeriod, 0,
+ sizeof(time_T)*1);
+ (void) memset((void*)sfcnOffset, 0,
+ sizeof(time_T)*1);
+ ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
+ ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
+ ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
+
+ /* Set up the mdlInfo pointer */
+ {
+ ssSetBlkInfo2Ptr(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.blkInfo2[0]);
+ }
+
+ ssSetRTWSfcnInfo(rts, asyncip_sl_1_sm_ip_test_M->sfcnInfo);
+
+ /* Allocate memory of model methods 2 */
+ {
+ ssSetModelMethods2(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods2
+ [0]);
+ }
+
+ /* Allocate memory of model methods 3 */
+ {
+ ssSetModelMethods3(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods3
+ [0]);
+ }
+
+ /* Allocate memory for states auxilliary information */
+ {
+ ssSetStatesInfo2(rts,
+ &asyncip_sl_1_sm_ip_test_M->
+ NonInlinedSFcns.statesInfo2[0]);
+ }
+
+ /* inputs */
+ {
+ _ssSetNumInputPorts(rts, 2);
+ ssSetPortInfoForInputs(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
+
+ /* port 0 */
+ {
+ real_T const **sfcnUPtrs = (real_T const **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.UPtrs0;
+ sfcnUPtrs[0] = &asyncip_sl_1_sm_ip_test_B.dataready1kHz;
+ ssSetInputPortSignalPtrs(rts, 0, (InputPtrsType)&sfcnUPtrs[0]);
+ _ssSetInputPortNumDimensions(rts, 0, 1);
+ ssSetInputPortWidth(rts, 0, 1);
+ }
+
+ /* port 1 */
+ {
+ real_T const **sfcnUPtrs = (real_T const **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.UPtrs1;
+ sfcnUPtrs[0] = asyncip_sl_1_sm_ip_test_P.constants_Value;
+ sfcnUPtrs[1] = &asyncip_sl_1_sm_ip_test_P.constants_Value[1];
+ sfcnUPtrs[2] = &asyncip_sl_1_sm_ip_test_P.constants_Value[2];
+ sfcnUPtrs[3] = &asyncip_sl_1_sm_ip_test_P.constants_Value[3];
+ sfcnUPtrs[4] = &asyncip_sl_1_sm_ip_test_B.PulseGenerator;
+ ssSetInputPortSignalPtrs(rts, 1, (InputPtrsType)&sfcnUPtrs[0]);
+ _ssSetInputPortNumDimensions(rts, 1, 1);
+ ssSetInputPortWidth(rts, 1, 5);
+ }
+ }
+
+ /* outputs */
+ {
+ ssSetPortInfoForOutputs(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.outputPortInfo[0]);
+ _ssSetNumOutputPorts(rts, 1);
+
+ /* port 0 */
+ {
+ _ssSetOutputPortNumDimensions(rts, 0, 1);
+ ssSetOutputPortWidth(rts, 0, 1);
+ ssSetOutputPortSignal(rts, 0, ((real_T *)
+ &asyncip_sl_1_sm_ip_test_B.SFunction2));
+ }
+ }
+
+ /* path info */
+ ssSetModelName(rts, "S-Function2");
+ ssSetPath(rts,
+ "asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2");
+ ssSetRTModel(rts,asyncip_sl_1_sm_ip_test_M);
+ ssSetParentSS(rts, (NULL));
+ ssSetRootSS(rts, rts);
+ ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
+
+ /* parameters */
+ {
+ mxArray **sfcnParams = (mxArray **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.params;
+ ssSetSFcnParamsCount(rts, 13);
+ ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
+ ssSetSFcnParam(rts, 0, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P1_Size);
+ ssSetSFcnParam(rts, 1, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P2_Size);
+ ssSetSFcnParam(rts, 2, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P3_Size);
+ ssSetSFcnParam(rts, 3, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P4_Size);
+ ssSetSFcnParam(rts, 4, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P5_Size);
+ ssSetSFcnParam(rts, 5, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P6_Size);
+ ssSetSFcnParam(rts, 6, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P7_Size);
+ ssSetSFcnParam(rts, 7, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P8_Size);
+ ssSetSFcnParam(rts, 8, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P9_Size);
+ ssSetSFcnParam(rts, 9, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P10_Size);
+ ssSetSFcnParam(rts, 10, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P11_Size);
+ ssSetSFcnParam(rts, 11, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P12_Size);
+ ssSetSFcnParam(rts, 12, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction2_P13_Size);
+ }
+
+ /* work vectors */
+ ssSetPWork(rts, (void **) &asyncip_sl_1_sm_ip_test_DWork.SFunction2_PWORK);
+
+ {
+ struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.dWork;
+ struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn0.dWorkAux;
+ ssSetSFcnDWork(rts, dWorkRecord);
+ ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
+ _ssSetNumDWork(rts, 1);
+
+ /* PWORK */
+ ssSetDWorkWidth(rts, 0, 1);
+ ssSetDWorkDataType(rts, 0,SS_POINTER);
+ ssSetDWorkComplexSignal(rts, 0, 0);
+ ssSetDWork(rts, 0, &asyncip_sl_1_sm_ip_test_DWork.SFunction2_PWORK);
+ }
+
+ /* registration */
+ sfun_send_async(rts);
+ sfcnInitializeSizes(rts);
+ sfcnInitializeSampleTimes(rts);
+
+ /* adjust sample time */
+ ssSetSampleTime(rts, 0, 5.0E-5);
+ ssSetOffsetTime(rts, 0, 0.0);
+ sfcnTsMap[0] = 0;
+
+ /* set compiled values of dynamic vector attributes */
+ ssSetInputPortWidth(rts, 1, 5);
+ ssSetInputPortDataType(rts, 1, SS_DOUBLE);
+ ssSetInputPortComplexSignal(rts, 1, 0);
+ ssSetInputPortFrameData(rts, 1, 0);
+ ssSetNumNonsampledZCs(rts, 0);
+
+ /* Update connectivity flags for each port */
+ _ssSetInputPortConnected(rts, 0, 1);
+ _ssSetInputPortConnected(rts, 1, 1);
+ _ssSetOutputPortConnected(rts, 0, 1);
+ _ssSetOutputPortBeingMerged(rts, 0, 0);
+
+ /* Update the BufferDstPort flags for each input port */
+ ssSetInputPortBufferDstPort(rts, 0, -1);
+ ssSetInputPortBufferDstPort(rts, 1, -1);
+ }
+
+ /* Level2 S-Function Block: asyncip_sl_1_sm_ip_test/<S3>/S-Function1 (sfun_recv_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[1];
+
+ /* timing info */
+ time_T *sfcnPeriod =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.sfcnPeriod;
+ time_T *sfcnOffset =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.sfcnOffset;
+ int_T *sfcnTsMap =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.sfcnTsMap;
+ (void) memset((void*)sfcnPeriod, 0,
+ sizeof(time_T)*1);
+ (void) memset((void*)sfcnOffset, 0,
+ sizeof(time_T)*1);
+ ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
+ ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
+ ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
+
+ /* Set up the mdlInfo pointer */
+ {
+ ssSetBlkInfo2Ptr(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.blkInfo2[1]);
+ }
+
+ ssSetRTWSfcnInfo(rts, asyncip_sl_1_sm_ip_test_M->sfcnInfo);
+
+ /* Allocate memory of model methods 2 */
+ {
+ ssSetModelMethods2(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods2
+ [1]);
+ }
+
+ /* Allocate memory of model methods 3 */
+ {
+ ssSetModelMethods3(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods3
+ [1]);
+ }
+
+ /* Allocate memory for states auxilliary information */
+ {
+ ssSetStatesInfo2(rts,
+ &asyncip_sl_1_sm_ip_test_M->
+ NonInlinedSFcns.statesInfo2[1]);
+ }
+
+ /* inputs */
+ {
+ _ssSetNumInputPorts(rts, 1);
+ ssSetPortInfoForInputs(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.inputPortInfo[0]);
+
+ /* port 0 */
+ {
+ real_T const **sfcnUPtrs = (real_T const **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.UPtrs0;
+ sfcnUPtrs[0] = &asyncip_sl_1_sm_ip_test_P.timeout_Value;
+ ssSetInputPortSignalPtrs(rts, 0, (InputPtrsType)&sfcnUPtrs[0]);
+ _ssSetInputPortNumDimensions(rts, 0, 1);
+ ssSetInputPortWidth(rts, 0, 1);
+ }
+ }
+
+ /* outputs */
+ {
+ ssSetPortInfoForOutputs(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.outputPortInfo[0]);
+ _ssSetNumOutputPorts(rts, 3);
+
+ /* port 0 */
+ {
+ _ssSetOutputPortNumDimensions(rts, 0, 1);
+ ssSetOutputPortWidth(rts, 0, 1);
+ ssSetOutputPortSignal(rts, 0, ((real_T *)
+ &asyncip_sl_1_sm_ip_test_B.SFunction1_o1));
+ }
+
+ /* port 1 */
+ {
+ _ssSetOutputPortNumDimensions(rts, 1, 1);
+ ssSetOutputPortWidth(rts, 1, 1);
+ ssSetOutputPortSignal(rts, 1, ((real_T *)
+ &asyncip_sl_1_sm_ip_test_B.SFunction1_o2));
+ }
+
+ /* port 2 */
+ {
+ _ssSetOutputPortNumDimensions(rts, 2, 1);
+ ssSetOutputPortWidth(rts, 2, 5);
+ ssSetOutputPortSignal(rts, 2, ((real_T *)
+ asyncip_sl_1_sm_ip_test_B.SFunction1_o3));
+ }
+ }
+
+ /* path info */
+ ssSetModelName(rts, "S-Function1");
+ ssSetPath(rts,
+ "asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1");
+ ssSetRTModel(rts,asyncip_sl_1_sm_ip_test_M);
+ ssSetParentSS(rts, (NULL));
+ ssSetRootSS(rts, rts);
+ ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
+
+ /* parameters */
+ {
+ mxArray **sfcnParams = (mxArray **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.params;
+ ssSetSFcnParamsCount(rts, 12);
+ ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
+ ssSetSFcnParam(rts, 0, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P1_Size);
+ ssSetSFcnParam(rts, 1, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P2_Size);
+ ssSetSFcnParam(rts, 2, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P3_Size);
+ ssSetSFcnParam(rts, 3, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P4_Size);
+ ssSetSFcnParam(rts, 4, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P5_Size);
+ ssSetSFcnParam(rts, 5, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P6_Size);
+ ssSetSFcnParam(rts, 6, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P7_Size);
+ ssSetSFcnParam(rts, 7, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P8_Size);
+ ssSetSFcnParam(rts, 8, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P9_Size);
+ ssSetSFcnParam(rts, 9, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P10_Size);
+ ssSetSFcnParam(rts, 10, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P11_Size);
+ ssSetSFcnParam(rts, 11, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction1_P12_Size);
+ }
+
+ /* work vectors */
+ ssSetPWork(rts, (void **) &asyncip_sl_1_sm_ip_test_DWork.SFunction1_PWORK);
+
+ {
+ struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.dWork;
+ struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn1.dWorkAux;
+ ssSetSFcnDWork(rts, dWorkRecord);
+ ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
+ _ssSetNumDWork(rts, 1);
+
+ /* PWORK */
+ ssSetDWorkWidth(rts, 0, 1);
+ ssSetDWorkDataType(rts, 0,SS_POINTER);
+ ssSetDWorkComplexSignal(rts, 0, 0);
+ ssSetDWork(rts, 0, &asyncip_sl_1_sm_ip_test_DWork.SFunction1_PWORK);
+ }
+
+ /* registration */
+ sfun_recv_async(rts);
+ sfcnInitializeSizes(rts);
+ sfcnInitializeSampleTimes(rts);
+
+ /* adjust sample time */
+ ssSetSampleTime(rts, 0, 5.0E-5);
+ ssSetOffsetTime(rts, 0, 0.0);
+ sfcnTsMap[0] = 0;
+
+ /* set compiled values of dynamic vector attributes */
+ ssSetOutputPortWidth(rts, 2, 5);
+ ssSetOutputPortDataType(rts, 2, SS_DOUBLE);
+ ssSetOutputPortComplexSignal(rts, 2, 0);
+ ssSetOutputPortFrameData(rts, 2, 0);
+ ssSetNumNonsampledZCs(rts, 0);
+
+ /* Update connectivity flags for each port */
+ _ssSetInputPortConnected(rts, 0, 1);
+ _ssSetOutputPortConnected(rts, 0, 1);
+ _ssSetOutputPortConnected(rts, 1, 1);
+ _ssSetOutputPortConnected(rts, 2, 1);
+ _ssSetOutputPortBeingMerged(rts, 0, 0);
+ _ssSetOutputPortBeingMerged(rts, 1, 0);
+ _ssSetOutputPortBeingMerged(rts, 2, 0);
+
+ /* Update the BufferDstPort flags for each input port */
+ ssSetInputPortBufferDstPort(rts, 0, -1);
+ }
+
+ /* Level2 S-Function Block: asyncip_sl_1_sm_ip_test/<S7>/S-Function (OP_SEND) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[2];
+
+ /* timing info */
+ time_T *sfcnPeriod =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.sfcnPeriod;
+ time_T *sfcnOffset =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.sfcnOffset;
+ int_T *sfcnTsMap =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.sfcnTsMap;
+ (void) memset((void*)sfcnPeriod, 0,
+ sizeof(time_T)*1);
+ (void) memset((void*)sfcnOffset, 0,
+ sizeof(time_T)*1);
+ ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
+ ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
+ ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
+
+ /* Set up the mdlInfo pointer */
+ {
+ ssSetBlkInfo2Ptr(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.blkInfo2[2]);
+ }
+
+ ssSetRTWSfcnInfo(rts, asyncip_sl_1_sm_ip_test_M->sfcnInfo);
+
+ /* Allocate memory of model methods 2 */
+ {
+ ssSetModelMethods2(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods2
+ [2]);
+ }
+
+ /* Allocate memory of model methods 3 */
+ {
+ ssSetModelMethods3(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods3
+ [2]);
+ }
+
+ /* Allocate memory for states auxilliary information */
+ {
+ ssSetStatesInfo2(rts,
+ &asyncip_sl_1_sm_ip_test_M->
+ NonInlinedSFcns.statesInfo2[2]);
+ }
+
+ /* inputs */
+ {
+ _ssSetNumInputPorts(rts, 1);
+ ssSetPortInfoForInputs(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.inputPortInfo[0]);
+
+ /* port 0 */
+ {
+ real_T const **sfcnUPtrs = (real_T const **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.UPtrs0;
+ sfcnUPtrs[0] = &asyncip_sl_1_sm_ip_test_B.SFunction2;
+ sfcnUPtrs[1] = &asyncip_sl_1_sm_ip_test_B.SFunction1_o1;
+ sfcnUPtrs[2] = &asyncip_sl_1_sm_ip_test_B.SFunction1_o2;
+
+ {
+ int_T i1;
+ const real_T *u0 = &asyncip_sl_1_sm_ip_test_B.SFunction1_o3[0];
+ for (i1=0; i1 < 5; i1++) {
+ sfcnUPtrs[i1+ 3] = &u0[i1];
+ }
+
+ sfcnUPtrs[8] = asyncip_sl_1_sm_ip_test_P.constants_Value;
+ sfcnUPtrs[9] = &asyncip_sl_1_sm_ip_test_P.constants_Value[1];
+ sfcnUPtrs[10] = &asyncip_sl_1_sm_ip_test_P.constants_Value[2];
+ sfcnUPtrs[11] = &asyncip_sl_1_sm_ip_test_P.constants_Value[3];
+ sfcnUPtrs[12] = &asyncip_sl_1_sm_ip_test_B.PulseGenerator;
+ }
+
+ ssSetInputPortSignalPtrs(rts, 0, (InputPtrsType)&sfcnUPtrs[0]);
+ _ssSetInputPortNumDimensions(rts, 0, 1);
+ ssSetInputPortWidth(rts, 0, 13);
+ }
+ }
+
+ /* path info */
+ ssSetModelName(rts, "S-Function");
+ ssSetPath(rts,
+ "asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1/S-Function");
+ ssSetRTModel(rts,asyncip_sl_1_sm_ip_test_M);
+ ssSetParentSS(rts, (NULL));
+ ssSetRootSS(rts, rts);
+ ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
+
+ /* parameters */
+ {
+ mxArray **sfcnParams = (mxArray **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.params;
+ ssSetSFcnParamsCount(rts, 1);
+ ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
+ ssSetSFcnParam(rts, 0, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.SFunction_P1_Size);
+ }
+
+ /* work vectors */
+ ssSetIWork(rts, (int_T *) &asyncip_sl_1_sm_ip_test_DWork.SFunction_IWORK[0]);
+
+ {
+ struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.dWork;
+ struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn2.dWorkAux;
+ ssSetSFcnDWork(rts, dWorkRecord);
+ ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
+ _ssSetNumDWork(rts, 1);
+
+ /* IWORK */
+ ssSetDWorkWidth(rts, 0, 5);
+ ssSetDWorkDataType(rts, 0,SS_INTEGER);
+ ssSetDWorkComplexSignal(rts, 0, 0);
+ ssSetDWork(rts, 0, &asyncip_sl_1_sm_ip_test_DWork.SFunction_IWORK[0]);
+ }
+
+ /* registration */
+ OP_SEND(rts);
+ sfcnInitializeSizes(rts);
+ sfcnInitializeSampleTimes(rts);
+
+ /* adjust sample time */
+ ssSetSampleTime(rts, 0, 5.0E-5);
+ ssSetOffsetTime(rts, 0, 0.0);
+ sfcnTsMap[0] = 0;
+
+ /* set compiled values of dynamic vector attributes */
+ ssSetInputPortWidth(rts, 0, 13);
+ ssSetInputPortDataType(rts, 0, SS_DOUBLE);
+ ssSetInputPortComplexSignal(rts, 0, 0);
+ ssSetInputPortFrameData(rts, 0, 0);
+ ssSetNumNonsampledZCs(rts, 0);
+
+ /* Update connectivity flags for each port */
+ _ssSetInputPortConnected(rts, 0, 1);
+
+ /* Update the BufferDstPort flags for each input port */
+ ssSetInputPortBufferDstPort(rts, 0, -1);
+ }
+
+ /* Level2 S-Function Block: asyncip_sl_1_sm_ip_test/<S2>/OpIPSocketCtrl1 (sfun_gen_async_ctrl) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[3];
+
+ /* timing info */
+ time_T *sfcnPeriod =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn3.sfcnPeriod;
+ time_T *sfcnOffset =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn3.sfcnOffset;
+ int_T *sfcnTsMap =
+ asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn3.sfcnTsMap;
+ (void) memset((void*)sfcnPeriod, 0,
+ sizeof(time_T)*1);
+ (void) memset((void*)sfcnOffset, 0,
+ sizeof(time_T)*1);
+ ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
+ ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
+ ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
+
+ /* Set up the mdlInfo pointer */
+ {
+ ssSetBlkInfo2Ptr(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.blkInfo2[3]);
+ }
+
+ ssSetRTWSfcnInfo(rts, asyncip_sl_1_sm_ip_test_M->sfcnInfo);
+
+ /* Allocate memory of model methods 2 */
+ {
+ ssSetModelMethods2(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods2
+ [3]);
+ }
+
+ /* Allocate memory of model methods 3 */
+ {
+ ssSetModelMethods3(rts,
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.methods3
+ [3]);
+ }
+
+ /* Allocate memory for states auxilliary information */
+ {
+ ssSetStatesInfo2(rts,
+ &asyncip_sl_1_sm_ip_test_M->
+ NonInlinedSFcns.statesInfo2[3]);
+ }
+
+ /* path info */
+ ssSetModelName(rts, "OpIPSocketCtrl1");
+ ssSetPath(rts, "asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1");
+ ssSetRTModel(rts,asyncip_sl_1_sm_ip_test_M);
+ ssSetParentSS(rts, (NULL));
+ ssSetRootSS(rts, rts);
+ ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
+
+ /* parameters */
+ {
+ mxArray **sfcnParams = (mxArray **)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn3.params;
+ ssSetSFcnParamsCount(rts, 27);
+ ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
+ ssSetSFcnParam(rts, 0, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P1_Size);
+ ssSetSFcnParam(rts, 1, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P2_Size);
+ ssSetSFcnParam(rts, 2, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P3_Size);
+ ssSetSFcnParam(rts, 3, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P4_Size);
+ ssSetSFcnParam(rts, 4, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P5_Size);
+ ssSetSFcnParam(rts, 5, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P6_Size);
+ ssSetSFcnParam(rts, 6, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P7_Size);
+ ssSetSFcnParam(rts, 7, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P8_Size);
+ ssSetSFcnParam(rts, 8, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P9_Size);
+ ssSetSFcnParam(rts, 9, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P10_Size);
+ ssSetSFcnParam(rts, 10, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P11_Size);
+ ssSetSFcnParam(rts, 11, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P12_Size);
+ ssSetSFcnParam(rts, 12, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P13_Size);
+ ssSetSFcnParam(rts, 13, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P14_Size);
+ ssSetSFcnParam(rts, 14, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P15_Size);
+ ssSetSFcnParam(rts, 15, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P16_Size);
+ ssSetSFcnParam(rts, 16, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P17_Size);
+ ssSetSFcnParam(rts, 17, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P18_Size);
+ ssSetSFcnParam(rts, 18, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P19_Size);
+ ssSetSFcnParam(rts, 19, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P20_Size);
+ ssSetSFcnParam(rts, 20, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P21_Size);
+ ssSetSFcnParam(rts, 21, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P22_Size);
+ ssSetSFcnParam(rts, 22, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P23_Size);
+ ssSetSFcnParam(rts, 23, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P24_Size);
+ ssSetSFcnParam(rts, 24, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P25_Size);
+ ssSetSFcnParam(rts, 25, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P26_Size);
+ ssSetSFcnParam(rts, 26, (mxArray*)
+ asyncip_sl_1_sm_ip_test_P.OpIPSocketCtrl1_P27_Size);
+ }
+
+ /* work vectors */
+ ssSetPWork(rts, (void **)
+ &asyncip_sl_1_sm_ip_test_DWork.OpIPSocketCtrl1_PWORK);
+
+ {
+ struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn3.dWork;
+ struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
+ &asyncip_sl_1_sm_ip_test_M->NonInlinedSFcns.Sfcn3.dWorkAux;
+ ssSetSFcnDWork(rts, dWorkRecord);
+ ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
+ _ssSetNumDWork(rts, 1);
+
+ /* PWORK */
+ ssSetDWorkWidth(rts, 0, 1);
+ ssSetDWorkDataType(rts, 0,SS_POINTER);
+ ssSetDWorkComplexSignal(rts, 0, 0);
+ ssSetDWork(rts, 0, &asyncip_sl_1_sm_ip_test_DWork.OpIPSocketCtrl1_PWORK);
+ }
+
+ /* registration */
+ sfun_gen_async_ctrl(rts);
+ sfcnInitializeSizes(rts);
+ sfcnInitializeSampleTimes(rts);
+
+ /* adjust sample time */
+ ssSetSampleTime(rts, 0, 5.0E-5);
+ ssSetOffsetTime(rts, 0, 0.0);
+ sfcnTsMap[0] = 0;
+
+ /* set compiled values of dynamic vector attributes */
+ ssSetNumNonsampledZCs(rts, 0);
+
+ /* Update connectivity flags for each port */
+ /* Update the BufferDstPort flags for each input port */
+ }
+ }
+}
+
+/* Model terminate function */
+void asyncip_sl_1_sm_ip_test_terminate(void)
+{
+ /* Level2 S-Function Block: '<S5>/S-Function2' (sfun_send_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[0];
+ sfcnTerminate(rts);
+ }
+
+ /* Level2 S-Function Block: '<S3>/S-Function1' (sfun_recv_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[1];
+ sfcnTerminate(rts);
+ }
+
+ /* Level2 S-Function Block: '<S7>/S-Function' (OP_SEND) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[2];
+ sfcnTerminate(rts);
+ }
+
+ /* Level2 S-Function Block: '<S2>/OpIPSocketCtrl1' (sfun_gen_async_ctrl) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[3];
+ sfcnTerminate(rts);
+ }
+}
+
+/*========================================================================*
+ * Start of GRT compatible call interface *
+ *========================================================================*/
+void MdlOutputs(int_T tid)
+{
+ asyncip_sl_1_sm_ip_test_output(tid);
+}
+
+void MdlUpdate(int_T tid)
+{
+ asyncip_sl_1_sm_ip_test_update(tid);
+}
+
+void MdlInitializeSizes(void)
+{
+ asyncip_sl_1_sm_ip_test_M->Sizes.numContStates = (0);/* Number of continuous states */
+ asyncip_sl_1_sm_ip_test_M->Sizes.numY = (0);/* Number of model outputs */
+ asyncip_sl_1_sm_ip_test_M->Sizes.numU = (0);/* Number of model inputs */
+ asyncip_sl_1_sm_ip_test_M->Sizes.sysDirFeedThru = (0);/* The model is not direct feedthrough */
+ asyncip_sl_1_sm_ip_test_M->Sizes.numSampTimes = (2);/* Number of sample times */
+ asyncip_sl_1_sm_ip_test_M->Sizes.numBlocks = (12);/* Number of blocks */
+ asyncip_sl_1_sm_ip_test_M->Sizes.numBlockIO = (8);/* Number of block outputs */
+ asyncip_sl_1_sm_ip_test_M->Sizes.numBlockPrms = (249);/* Sum of parameter "widths" */
+}
+
+void MdlInitializeSampleTimes(void)
+{
+}
+
+void MdlInitialize(void)
+{
+ /* user code (Initialize function Body) */
+
+ /* System '<Root>' */
+ /* Opal-RT Technologies */
+ opalSizeDwork = sizeof(rtDWork);
+
+#ifdef USE_RTMODEL
+
+ if (Opal_rtmGetNumBlockIO(pRtModel) != 0)
+ opalSizeBlockIO = sizeof(rtB);
+ else
+ opalSizeBlockIO = 0;
+ if (Opal_rtmGetNumBlockParams(pRtModel) != 0)
+ opalSizeRTP = sizeof(rtP);
+ else
+ opalSizeRTP = 0;
+
+#else
+
+ if (ssGetNumBlockIO(rtS) != 0)
+ opalSizeBlockIO = sizeof(rtB);
+ else
+ opalSizeBlockIO = 0;
+ if (ssGetNumBlockParams(rtS) != 0)
+ opalSizeRTP = sizeof(rtP);
+ else
+ opalSizeRTP = 0;
+
+#endif
+
+ /* InitializeConditions for Memory: '<S1>/S-Function' */
+ asyncip_sl_1_sm_ip_test_DWork.SFunction_PreviousInput =
+ asyncip_sl_1_sm_ip_test_P.SFunction_X0;
+
+ /* Level2 S-Function Block: '<S5>/S-Function2' (sfun_send_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[0];
+ sfcnInitializeConditions(rts);
+ if (ssGetErrorStatus(rts) != (NULL))
+ return;
+ }
+
+ /* Level2 S-Function Block: '<S3>/S-Function1' (sfun_recv_async) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[1];
+ sfcnInitializeConditions(rts);
+ if (ssGetErrorStatus(rts) != (NULL))
+ return;
+ }
+
+ /* Level2 S-Function Block: '<S7>/S-Function' (OP_SEND) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[2];
+ sfcnInitializeConditions(rts);
+ if (ssGetErrorStatus(rts) != (NULL))
+ return;
+ }
+
+ /* Level2 S-Function Block: '<S2>/OpIPSocketCtrl1' (sfun_gen_async_ctrl) */
+ {
+ SimStruct *rts = asyncip_sl_1_sm_ip_test_M->childSfunctions[3];
+ sfcnInitializeConditions(rts);
+ if (ssGetErrorStatus(rts) != (NULL))
+ return;
+ }
+}
+
+void MdlStart(void)
+{
+ /* Start for DiscretePulseGenerator: '<S2>/data ready 1 kHz' */
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter = 0;
+
+ /* Start for DiscretePulseGenerator: '<S2>/Pulse Generator' */
+ asyncip_sl_1_sm_ip_test_DWork.clockTickCounter_c = 0;
+ MdlInitialize();
+}
+
+void MdlTerminate(void)
+{
+ asyncip_sl_1_sm_ip_test_terminate();
+}
+
+RT_MODEL_asyncip_sl_1_sm_ip_test *asyncip_sl_1_sm_ip_test(void)
+{
+ asyncip_sl_1_sm_ip_test_initialize(1);
+ return asyncip_sl_1_sm_ip_test_M;
+}
+
+/*========================================================================*
+ * End of GRT compatible call interface *
+ *========================================================================*/
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.h
new file mode 100644
index 000000000..7bebb7455
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.h
@@ -0,0 +1,1371 @@
+/*
+ * asyncip_sl_1_sm_ip_test.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+#ifndef RTW_HEADER_asyncip_sl_1_sm_ip_test_h_
+#define RTW_HEADER_asyncip_sl_1_sm_ip_test_h_
+#ifndef asyncip_sl_1_sm_ip_test_COMMON_INCLUDES_
+# define asyncip_sl_1_sm_ip_test_COMMON_INCLUDES_
+#include <stddef.h>
+#include <string.h>
+#include "rtwtypes.h"
+#include "simstruc.h"
+#include "fixedpoint.h"
+#include "rt_logging.h"
+#include "rt_defines.h"
+#include "rt_nonfinite.h"
+#endif /* asyncip_sl_1_sm_ip_test_COMMON_INCLUDES_ */
+
+#include "asyncip_sl_1_sm_ip_test_types.h"
+
+/* Macros for accessing real-time model data structure */
+#ifndef rtmGetBlkStateChangeFlag
+# define rtmGetBlkStateChangeFlag(rtm) ((rtm)->ModelData.blkStateChange)
+#endif
+
+#ifndef rtmSetBlkStateChangeFlag
+# define rtmSetBlkStateChangeFlag(rtm, val) ((rtm)->ModelData.blkStateChange = (val))
+#endif
+
+#ifndef rtmGetBlockIO
+# define rtmGetBlockIO(rtm) ((rtm)->ModelData.blockIO)
+#endif
+
+#ifndef rtmSetBlockIO
+# define rtmSetBlockIO(rtm, val) ((rtm)->ModelData.blockIO = (val))
+#endif
+
+#ifndef rtmGetChecksums
+# define rtmGetChecksums(rtm) ((rtm)->Sizes.checksums)
+#endif
+
+#ifndef rtmSetChecksums
+# define rtmSetChecksums(rtm, val) ((rtm)->Sizes.checksums = (val))
+#endif
+
+#ifndef rtmGetConstBlockIO
+# define rtmGetConstBlockIO(rtm) ((rtm)->ModelData.constBlockIO)
+#endif
+
+#ifndef rtmSetConstBlockIO
+# define rtmSetConstBlockIO(rtm, val) ((rtm)->ModelData.constBlockIO = (val))
+#endif
+
+#ifndef rtmGetContStateDisabled
+# define rtmGetContStateDisabled(rtm) ((rtm)->ModelData.contStateDisabled)
+#endif
+
+#ifndef rtmSetContStateDisabled
+# define rtmSetContStateDisabled(rtm, val) ((rtm)->ModelData.contStateDisabled = (val))
+#endif
+
+#ifndef rtmGetContStates
+# define rtmGetContStates(rtm) ((rtm)->ModelData.contStates)
+#endif
+
+#ifndef rtmSetContStates
+# define rtmSetContStates(rtm, val) ((rtm)->ModelData.contStates = (val))
+#endif
+
+#ifndef rtmGetDataMapInfo
+# define rtmGetDataMapInfo(rtm) ()
+#endif
+
+#ifndef rtmSetDataMapInfo
+# define rtmSetDataMapInfo(rtm, val) ()
+#endif
+
+#ifndef rtmGetDefaultParam
+# define rtmGetDefaultParam(rtm) ((rtm)->ModelData.defaultParam)
+#endif
+
+#ifndef rtmSetDefaultParam
+# define rtmSetDefaultParam(rtm, val) ((rtm)->ModelData.defaultParam = (val))
+#endif
+
+#ifndef rtmGetDerivCacheNeedsReset
+# define rtmGetDerivCacheNeedsReset(rtm) ((rtm)->ModelData.derivCacheNeedsReset)
+#endif
+
+#ifndef rtmSetDerivCacheNeedsReset
+# define rtmSetDerivCacheNeedsReset(rtm, val) ((rtm)->ModelData.derivCacheNeedsReset = (val))
+#endif
+
+#ifndef rtmGetDirectFeedThrough
+# define rtmGetDirectFeedThrough(rtm) ((rtm)->Sizes.sysDirFeedThru)
+#endif
+
+#ifndef rtmSetDirectFeedThrough
+# define rtmSetDirectFeedThrough(rtm, val) ((rtm)->Sizes.sysDirFeedThru = (val))
+#endif
+
+#ifndef rtmGetErrorStatusFlag
+# define rtmGetErrorStatusFlag(rtm) ((rtm)->errorStatus)
+#endif
+
+#ifndef rtmSetErrorStatusFlag
+# define rtmSetErrorStatusFlag(rtm, val) ((rtm)->errorStatus = (val))
+#endif
+
+#ifndef rtmGetFinalTime
+# define rtmGetFinalTime(rtm) ((rtm)->Timing.tFinal)
+#endif
+
+#ifndef rtmSetFinalTime
+# define rtmSetFinalTime(rtm, val) ((rtm)->Timing.tFinal = (val))
+#endif
+
+#ifndef rtmGetFirstInitCondFlag
+# define rtmGetFirstInitCondFlag(rtm) ()
+#endif
+
+#ifndef rtmSetFirstInitCondFlag
+# define rtmSetFirstInitCondFlag(rtm, val) ()
+#endif
+
+#ifndef rtmGetIntgData
+# define rtmGetIntgData(rtm) ()
+#endif
+
+#ifndef rtmSetIntgData
+# define rtmSetIntgData(rtm, val) ()
+#endif
+
+#ifndef rtmGetMdlRefGlobalTID
+# define rtmGetMdlRefGlobalTID(rtm) ()
+#endif
+
+#ifndef rtmSetMdlRefGlobalTID
+# define rtmSetMdlRefGlobalTID(rtm, val) ()
+#endif
+
+#ifndef rtmGetMdlRefTriggerTID
+# define rtmGetMdlRefTriggerTID(rtm) ()
+#endif
+
+#ifndef rtmSetMdlRefTriggerTID
+# define rtmSetMdlRefTriggerTID(rtm, val) ()
+#endif
+
+#ifndef rtmGetModelMappingInfo
+# define rtmGetModelMappingInfo(rtm) ((rtm)->SpecialInfo.mappingInfo)
+#endif
+
+#ifndef rtmSetModelMappingInfo
+# define rtmSetModelMappingInfo(rtm, val) ((rtm)->SpecialInfo.mappingInfo = (val))
+#endif
+
+#ifndef rtmGetModelName
+# define rtmGetModelName(rtm) ((rtm)->modelName)
+#endif
+
+#ifndef rtmSetModelName
+# define rtmSetModelName(rtm, val) ((rtm)->modelName = (val))
+#endif
+
+#ifndef rtmGetNonInlinedSFcns
+# define rtmGetNonInlinedSFcns(rtm) ((rtm)->NonInlinedSFcns)
+#endif
+
+#ifndef rtmSetNonInlinedSFcns
+# define rtmSetNonInlinedSFcns(rtm, val) ((rtm)->NonInlinedSFcns = (val))
+#endif
+
+#ifndef rtmGetNumBlockIO
+# define rtmGetNumBlockIO(rtm) ((rtm)->Sizes.numBlockIO)
+#endif
+
+#ifndef rtmSetNumBlockIO
+# define rtmSetNumBlockIO(rtm, val) ((rtm)->Sizes.numBlockIO = (val))
+#endif
+
+#ifndef rtmGetNumBlockParams
+# define rtmGetNumBlockParams(rtm) ((rtm)->Sizes.numBlockPrms)
+#endif
+
+#ifndef rtmSetNumBlockParams
+# define rtmSetNumBlockParams(rtm, val) ((rtm)->Sizes.numBlockPrms = (val))
+#endif
+
+#ifndef rtmGetNumBlocks
+# define rtmGetNumBlocks(rtm) ((rtm)->Sizes.numBlocks)
+#endif
+
+#ifndef rtmSetNumBlocks
+# define rtmSetNumBlocks(rtm, val) ((rtm)->Sizes.numBlocks = (val))
+#endif
+
+#ifndef rtmGetNumContStates
+# define rtmGetNumContStates(rtm) ((rtm)->Sizes.numContStates)
+#endif
+
+#ifndef rtmSetNumContStates
+# define rtmSetNumContStates(rtm, val) ((rtm)->Sizes.numContStates = (val))
+#endif
+
+#ifndef rtmGetNumDWork
+# define rtmGetNumDWork(rtm) ((rtm)->Sizes.numDwork)
+#endif
+
+#ifndef rtmSetNumDWork
+# define rtmSetNumDWork(rtm, val) ((rtm)->Sizes.numDwork = (val))
+#endif
+
+#ifndef rtmGetNumInputPorts
+# define rtmGetNumInputPorts(rtm) ((rtm)->Sizes.numIports)
+#endif
+
+#ifndef rtmSetNumInputPorts
+# define rtmSetNumInputPorts(rtm, val) ((rtm)->Sizes.numIports = (val))
+#endif
+
+#ifndef rtmGetNumNonSampledZCs
+# define rtmGetNumNonSampledZCs(rtm) ((rtm)->Sizes.numNonSampZCs)
+#endif
+
+#ifndef rtmSetNumNonSampledZCs
+# define rtmSetNumNonSampledZCs(rtm, val) ((rtm)->Sizes.numNonSampZCs = (val))
+#endif
+
+#ifndef rtmGetNumOutputPorts
+# define rtmGetNumOutputPorts(rtm) ((rtm)->Sizes.numOports)
+#endif
+
+#ifndef rtmSetNumOutputPorts
+# define rtmSetNumOutputPorts(rtm, val) ((rtm)->Sizes.numOports = (val))
+#endif
+
+#ifndef rtmGetNumSFcnParams
+# define rtmGetNumSFcnParams(rtm) ((rtm)->Sizes.numSFcnPrms)
+#endif
+
+#ifndef rtmSetNumSFcnParams
+# define rtmSetNumSFcnParams(rtm, val) ((rtm)->Sizes.numSFcnPrms = (val))
+#endif
+
+#ifndef rtmGetNumSFunctions
+# define rtmGetNumSFunctions(rtm) ((rtm)->Sizes.numSFcns)
+#endif
+
+#ifndef rtmSetNumSFunctions
+# define rtmSetNumSFunctions(rtm, val) ((rtm)->Sizes.numSFcns = (val))
+#endif
+
+#ifndef rtmGetNumSampleTimes
+# define rtmGetNumSampleTimes(rtm) ((rtm)->Sizes.numSampTimes)
+#endif
+
+#ifndef rtmSetNumSampleTimes
+# define rtmSetNumSampleTimes(rtm, val) ((rtm)->Sizes.numSampTimes = (val))
+#endif
+
+#ifndef rtmGetNumU
+# define rtmGetNumU(rtm) ((rtm)->Sizes.numU)
+#endif
+
+#ifndef rtmSetNumU
+# define rtmSetNumU(rtm, val) ((rtm)->Sizes.numU = (val))
+#endif
+
+#ifndef rtmGetNumY
+# define rtmGetNumY(rtm) ((rtm)->Sizes.numY)
+#endif
+
+#ifndef rtmSetNumY
+# define rtmSetNumY(rtm, val) ((rtm)->Sizes.numY = (val))
+#endif
+
+#ifndef rtmGetOdeF
+# define rtmGetOdeF(rtm) ()
+#endif
+
+#ifndef rtmSetOdeF
+# define rtmSetOdeF(rtm, val) ()
+#endif
+
+#ifndef rtmGetOdeY
+# define rtmGetOdeY(rtm) ()
+#endif
+
+#ifndef rtmSetOdeY
+# define rtmSetOdeY(rtm, val) ()
+#endif
+
+#ifndef rtmGetOffsetTimeArray
+# define rtmGetOffsetTimeArray(rtm) ((rtm)->Timing.offsetTimesArray)
+#endif
+
+#ifndef rtmSetOffsetTimeArray
+# define rtmSetOffsetTimeArray(rtm, val) ((rtm)->Timing.offsetTimesArray = (val))
+#endif
+
+#ifndef rtmGetOffsetTimePtr
+# define rtmGetOffsetTimePtr(rtm) ((rtm)->Timing.offsetTimes)
+#endif
+
+#ifndef rtmSetOffsetTimePtr
+# define rtmSetOffsetTimePtr(rtm, val) ((rtm)->Timing.offsetTimes = (val))
+#endif
+
+#ifndef rtmGetOptions
+# define rtmGetOptions(rtm) ((rtm)->Sizes.options)
+#endif
+
+#ifndef rtmSetOptions
+# define rtmSetOptions(rtm, val) ((rtm)->Sizes.options = (val))
+#endif
+
+#ifndef rtmGetParamIsMalloced
+# define rtmGetParamIsMalloced(rtm) ()
+#endif
+
+#ifndef rtmSetParamIsMalloced
+# define rtmSetParamIsMalloced(rtm, val) ()
+#endif
+
+#ifndef rtmGetPath
+# define rtmGetPath(rtm) ((rtm)->path)
+#endif
+
+#ifndef rtmSetPath
+# define rtmSetPath(rtm, val) ((rtm)->path = (val))
+#endif
+
+#ifndef rtmGetPerTaskSampleHits
+# define rtmGetPerTaskSampleHits(rtm) ()
+#endif
+
+#ifndef rtmSetPerTaskSampleHits
+# define rtmSetPerTaskSampleHits(rtm, val) ()
+#endif
+
+#ifndef rtmGetPerTaskSampleHitsArray
+# define rtmGetPerTaskSampleHitsArray(rtm) ((rtm)->Timing.perTaskSampleHitsArray)
+#endif
+
+#ifndef rtmSetPerTaskSampleHitsArray
+# define rtmSetPerTaskSampleHitsArray(rtm, val) ((rtm)->Timing.perTaskSampleHitsArray = (val))
+#endif
+
+#ifndef rtmGetPerTaskSampleHitsPtr
+# define rtmGetPerTaskSampleHitsPtr(rtm) ((rtm)->Timing.perTaskSampleHits)
+#endif
+
+#ifndef rtmSetPerTaskSampleHitsPtr
+# define rtmSetPerTaskSampleHitsPtr(rtm, val) ((rtm)->Timing.perTaskSampleHits = (val))
+#endif
+
+#ifndef rtmGetPrevZCSigState
+# define rtmGetPrevZCSigState(rtm) ((rtm)->ModelData.prevZCSigState)
+#endif
+
+#ifndef rtmSetPrevZCSigState
+# define rtmSetPrevZCSigState(rtm, val) ((rtm)->ModelData.prevZCSigState = (val))
+#endif
+
+#ifndef rtmGetRTWExtModeInfo
+# define rtmGetRTWExtModeInfo(rtm) ((rtm)->extModeInfo)
+#endif
+
+#ifndef rtmSetRTWExtModeInfo
+# define rtmSetRTWExtModeInfo(rtm, val) ((rtm)->extModeInfo = (val))
+#endif
+
+#ifndef rtmGetRTWGeneratedSFcn
+# define rtmGetRTWGeneratedSFcn(rtm) ((rtm)->Sizes.rtwGenSfcn)
+#endif
+
+#ifndef rtmSetRTWGeneratedSFcn
+# define rtmSetRTWGeneratedSFcn(rtm, val) ((rtm)->Sizes.rtwGenSfcn = (val))
+#endif
+
+#ifndef rtmGetRTWLogInfo
+# define rtmGetRTWLogInfo(rtm) ((rtm)->rtwLogInfo)
+#endif
+
+#ifndef rtmSetRTWLogInfo
+# define rtmSetRTWLogInfo(rtm, val) ((rtm)->rtwLogInfo = (val))
+#endif
+
+#ifndef rtmGetRTWRTModelMethodsInfo
+# define rtmGetRTWRTModelMethodsInfo(rtm) ()
+#endif
+
+#ifndef rtmSetRTWRTModelMethodsInfo
+# define rtmSetRTWRTModelMethodsInfo(rtm, val) ()
+#endif
+
+#ifndef rtmGetRTWSfcnInfo
+# define rtmGetRTWSfcnInfo(rtm) ((rtm)->sfcnInfo)
+#endif
+
+#ifndef rtmSetRTWSfcnInfo
+# define rtmSetRTWSfcnInfo(rtm, val) ((rtm)->sfcnInfo = (val))
+#endif
+
+#ifndef rtmGetRTWSolverInfo
+# define rtmGetRTWSolverInfo(rtm) ((rtm)->solverInfo)
+#endif
+
+#ifndef rtmSetRTWSolverInfo
+# define rtmSetRTWSolverInfo(rtm, val) ((rtm)->solverInfo = (val))
+#endif
+
+#ifndef rtmGetRTWSolverInfoPtr
+# define rtmGetRTWSolverInfoPtr(rtm) ((rtm)->solverInfoPtr)
+#endif
+
+#ifndef rtmSetRTWSolverInfoPtr
+# define rtmSetRTWSolverInfoPtr(rtm, val) ((rtm)->solverInfoPtr = (val))
+#endif
+
+#ifndef rtmGetReservedForXPC
+# define rtmGetReservedForXPC(rtm) ((rtm)->SpecialInfo.xpcData)
+#endif
+
+#ifndef rtmSetReservedForXPC
+# define rtmSetReservedForXPC(rtm, val) ((rtm)->SpecialInfo.xpcData = (val))
+#endif
+
+#ifndef rtmGetRootDWork
+# define rtmGetRootDWork(rtm) ((rtm)->Work.dwork)
+#endif
+
+#ifndef rtmSetRootDWork
+# define rtmSetRootDWork(rtm, val) ((rtm)->Work.dwork = (val))
+#endif
+
+#ifndef rtmGetSFunctions
+# define rtmGetSFunctions(rtm) ((rtm)->childSfunctions)
+#endif
+
+#ifndef rtmSetSFunctions
+# define rtmSetSFunctions(rtm, val) ((rtm)->childSfunctions = (val))
+#endif
+
+#ifndef rtmGetSampleHitArray
+# define rtmGetSampleHitArray(rtm) ((rtm)->Timing.sampleHitArray)
+#endif
+
+#ifndef rtmSetSampleHitArray
+# define rtmSetSampleHitArray(rtm, val) ((rtm)->Timing.sampleHitArray = (val))
+#endif
+
+#ifndef rtmGetSampleHitPtr
+# define rtmGetSampleHitPtr(rtm) ((rtm)->Timing.sampleHits)
+#endif
+
+#ifndef rtmSetSampleHitPtr
+# define rtmSetSampleHitPtr(rtm, val) ((rtm)->Timing.sampleHits = (val))
+#endif
+
+#ifndef rtmGetSampleTimeArray
+# define rtmGetSampleTimeArray(rtm) ((rtm)->Timing.sampleTimesArray)
+#endif
+
+#ifndef rtmSetSampleTimeArray
+# define rtmSetSampleTimeArray(rtm, val) ((rtm)->Timing.sampleTimesArray = (val))
+#endif
+
+#ifndef rtmGetSampleTimePtr
+# define rtmGetSampleTimePtr(rtm) ((rtm)->Timing.sampleTimes)
+#endif
+
+#ifndef rtmSetSampleTimePtr
+# define rtmSetSampleTimePtr(rtm, val) ((rtm)->Timing.sampleTimes = (val))
+#endif
+
+#ifndef rtmGetSampleTimeTaskIDArray
+# define rtmGetSampleTimeTaskIDArray(rtm) ((rtm)->Timing.sampleTimeTaskIDArray)
+#endif
+
+#ifndef rtmSetSampleTimeTaskIDArray
+# define rtmSetSampleTimeTaskIDArray(rtm, val) ((rtm)->Timing.sampleTimeTaskIDArray = (val))
+#endif
+
+#ifndef rtmGetSampleTimeTaskIDPtr
+# define rtmGetSampleTimeTaskIDPtr(rtm) ((rtm)->Timing.sampleTimeTaskIDPtr)
+#endif
+
+#ifndef rtmSetSampleTimeTaskIDPtr
+# define rtmSetSampleTimeTaskIDPtr(rtm, val) ((rtm)->Timing.sampleTimeTaskIDPtr = (val))
+#endif
+
+#ifndef rtmGetSimMode
+# define rtmGetSimMode(rtm) ((rtm)->simMode)
+#endif
+
+#ifndef rtmSetSimMode
+# define rtmSetSimMode(rtm, val) ((rtm)->simMode = (val))
+#endif
+
+#ifndef rtmGetSimTimeStep
+# define rtmGetSimTimeStep(rtm) ((rtm)->Timing.simTimeStep)
+#endif
+
+#ifndef rtmSetSimTimeStep
+# define rtmSetSimTimeStep(rtm, val) ((rtm)->Timing.simTimeStep = (val))
+#endif
+
+#ifndef rtmGetStartTime
+# define rtmGetStartTime(rtm) ((rtm)->Timing.tStart)
+#endif
+
+#ifndef rtmSetStartTime
+# define rtmSetStartTime(rtm, val) ((rtm)->Timing.tStart = (val))
+#endif
+
+#ifndef rtmGetStepSize
+# define rtmGetStepSize(rtm) ((rtm)->Timing.stepSize)
+#endif
+
+#ifndef rtmSetStepSize
+# define rtmSetStepSize(rtm, val) ((rtm)->Timing.stepSize = (val))
+#endif
+
+#ifndef rtmGetStopRequestedFlag
+# define rtmGetStopRequestedFlag(rtm) ((rtm)->Timing.stopRequestedFlag)
+#endif
+
+#ifndef rtmSetStopRequestedFlag
+# define rtmSetStopRequestedFlag(rtm, val) ((rtm)->Timing.stopRequestedFlag = (val))
+#endif
+
+#ifndef rtmGetTaskCounters
+# define rtmGetTaskCounters(rtm) ((rtm)->Timing.TaskCounters)
+#endif
+
+#ifndef rtmSetTaskCounters
+# define rtmSetTaskCounters(rtm, val) ((rtm)->Timing.TaskCounters = (val))
+#endif
+
+#ifndef rtmGetTaskTimeArray
+# define rtmGetTaskTimeArray(rtm) ((rtm)->Timing.tArray)
+#endif
+
+#ifndef rtmSetTaskTimeArray
+# define rtmSetTaskTimeArray(rtm, val) ((rtm)->Timing.tArray = (val))
+#endif
+
+#ifndef rtmGetTimePtr
+# define rtmGetTimePtr(rtm) ((rtm)->Timing.t)
+#endif
+
+#ifndef rtmSetTimePtr
+# define rtmSetTimePtr(rtm, val) ((rtm)->Timing.t = (val))
+#endif
+
+#ifndef rtmGetTimingData
+# define rtmGetTimingData(rtm) ((rtm)->Timing.timingData)
+#endif
+
+#ifndef rtmSetTimingData
+# define rtmSetTimingData(rtm, val) ((rtm)->Timing.timingData = (val))
+#endif
+
+#ifndef rtmGetU
+# define rtmGetU(rtm) ((rtm)->ModelData.inputs)
+#endif
+
+#ifndef rtmSetU
+# define rtmSetU(rtm, val) ((rtm)->ModelData.inputs = (val))
+#endif
+
+#ifndef rtmGetVarNextHitTimesListPtr
+# define rtmGetVarNextHitTimesListPtr(rtm) ((rtm)->Timing.varNextHitTimesList)
+#endif
+
+#ifndef rtmSetVarNextHitTimesListPtr
+# define rtmSetVarNextHitTimesListPtr(rtm, val) ((rtm)->Timing.varNextHitTimesList = (val))
+#endif
+
+#ifndef rtmGetY
+# define rtmGetY(rtm) ((rtm)->ModelData.outputs)
+#endif
+
+#ifndef rtmSetY
+# define rtmSetY(rtm, val) ((rtm)->ModelData.outputs = (val))
+#endif
+
+#ifndef rtmGetZCCacheNeedsReset
+# define rtmGetZCCacheNeedsReset(rtm) ((rtm)->ModelData.zCCacheNeedsReset)
+#endif
+
+#ifndef rtmSetZCCacheNeedsReset
+# define rtmSetZCCacheNeedsReset(rtm, val) ((rtm)->ModelData.zCCacheNeedsReset = (val))
+#endif
+
+#ifndef rtmGetZCSignalValues
+# define rtmGetZCSignalValues(rtm) ((rtm)->ModelData.zcSignalValues)
+#endif
+
+#ifndef rtmSetZCSignalValues
+# define rtmSetZCSignalValues(rtm, val) ((rtm)->ModelData.zcSignalValues = (val))
+#endif
+
+#ifndef rtmGet_TimeOfLastOutput
+# define rtmGet_TimeOfLastOutput(rtm) ((rtm)->Timing.timeOfLastOutput)
+#endif
+
+#ifndef rtmSet_TimeOfLastOutput
+# define rtmSet_TimeOfLastOutput(rtm, val) ((rtm)->Timing.timeOfLastOutput = (val))
+#endif
+
+#ifndef rtmGetdX
+# define rtmGetdX(rtm) ((rtm)->ModelData.derivs)
+#endif
+
+#ifndef rtmSetdX
+# define rtmSetdX(rtm, val) ((rtm)->ModelData.derivs = (val))
+#endif
+
+#ifndef rtmGetChecksumVal
+# define rtmGetChecksumVal(rtm, idx) ((rtm)->Sizes.checksums[idx])
+#endif
+
+#ifndef rtmSetChecksumVal
+# define rtmSetChecksumVal(rtm, idx, val) ((rtm)->Sizes.checksums[idx] = (val))
+#endif
+
+#ifndef rtmGetDWork
+# define rtmGetDWork(rtm, idx) ((rtm)->Work.dwork[idx])
+#endif
+
+#ifndef rtmSetDWork
+# define rtmSetDWork(rtm, idx, val) ((rtm)->Work.dwork[idx] = (val))
+#endif
+
+#ifndef rtmGetOffsetTime
+# define rtmGetOffsetTime(rtm, idx) ((rtm)->Timing.offsetTimes[idx])
+#endif
+
+#ifndef rtmSetOffsetTime
+# define rtmSetOffsetTime(rtm, idx, val) ((rtm)->Timing.offsetTimes[idx] = (val))
+#endif
+
+#ifndef rtmGetSFunction
+# define rtmGetSFunction(rtm, idx) ((rtm)->childSfunctions[idx])
+#endif
+
+#ifndef rtmSetSFunction
+# define rtmSetSFunction(rtm, idx, val) ((rtm)->childSfunctions[idx] = (val))
+#endif
+
+#ifndef rtmGetSampleTime
+# define rtmGetSampleTime(rtm, idx) ((rtm)->Timing.sampleTimes[idx])
+#endif
+
+#ifndef rtmSetSampleTime
+# define rtmSetSampleTime(rtm, idx, val) ((rtm)->Timing.sampleTimes[idx] = (val))
+#endif
+
+#ifndef rtmGetSampleTimeTaskID
+# define rtmGetSampleTimeTaskID(rtm, idx) ((rtm)->Timing.sampleTimeTaskIDPtr[idx])
+#endif
+
+#ifndef rtmSetSampleTimeTaskID
+# define rtmSetSampleTimeTaskID(rtm, idx, val) ((rtm)->Timing.sampleTimeTaskIDPtr[idx] = (val))
+#endif
+
+#ifndef rtmGetVarNextHitTime
+# define rtmGetVarNextHitTime(rtm, idx) ((rtm)->Timing.varNextHitTimesList[idx])
+#endif
+
+#ifndef rtmSetVarNextHitTime
+# define rtmSetVarNextHitTime(rtm, idx, val) ((rtm)->Timing.varNextHitTimesList[idx] = (val))
+#endif
+
+#ifndef rtmIsContinuousTask
+# define rtmIsContinuousTask(rtm, tid) 0
+#endif
+
+#ifndef rtmGetErrorStatus
+# define rtmGetErrorStatus(rtm) ((rtm)->errorStatus)
+#endif
+
+#ifndef rtmSetErrorStatus
+# define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val))
+#endif
+
+#ifndef rtmIsSampleHit
+# define rtmIsSampleHit(rtm, sti, tid) ((rtm)->Timing.sampleHits[(rtm)->Timing.sampleTimeTaskIDPtr[sti]])
+#endif
+
+#ifndef rtmGetStopRequested
+# define rtmGetStopRequested(rtm) ((rtm)->Timing.stopRequestedFlag)
+#endif
+
+#ifndef rtmSetStopRequested
+# define rtmSetStopRequested(rtm, val) ((rtm)->Timing.stopRequestedFlag = (val))
+#endif
+
+#ifndef rtmGetStopRequestedPtr
+# define rtmGetStopRequestedPtr(rtm) (&((rtm)->Timing.stopRequestedFlag))
+#endif
+
+#ifndef rtmGetT
+# define rtmGetT(rtm) (rtmGetTPtr((rtm))[0])
+#endif
+
+#ifndef rtmSetT
+# define rtmSetT(rtm, val) /* Do Nothing */
+#endif
+
+#ifndef rtmGetTFinal
+# define rtmGetTFinal(rtm) ((rtm)->Timing.tFinal)
+#endif
+
+#ifndef rtmSetTFinal
+# define rtmSetTFinal(rtm, val) ((rtm)->Timing.tFinal = (val))
+#endif
+
+#ifndef rtmGetTPtr
+# define rtmGetTPtr(rtm) ((rtm)->Timing.t)
+#endif
+
+#ifndef rtmSetTPtr
+# define rtmSetTPtr(rtm, val) ((rtm)->Timing.t = (val))
+#endif
+
+#ifndef rtmGetTStart
+# define rtmGetTStart(rtm) ((rtm)->Timing.tStart)
+#endif
+
+#ifndef rtmSetTStart
+# define rtmSetTStart(rtm, val) ((rtm)->Timing.tStart = (val))
+#endif
+
+#ifndef rtmGetTaskTime
+# define rtmGetTaskTime(rtm, sti) (rtmGetTPtr((rtm))[(rtm)->Timing.sampleTimeTaskIDPtr[sti]])
+#endif
+
+#ifndef rtmSetTaskTime
+# define rtmSetTaskTime(rtm, sti, val) (rtmGetTPtr((rtm))[sti] = (val))
+#endif
+
+#ifndef rtmGetTimeOfLastOutput
+# define rtmGetTimeOfLastOutput(rtm) ((rtm)->Timing.timeOfLastOutput)
+#endif
+
+#ifdef rtmGetRTWSolverInfo
+#undef rtmGetRTWSolverInfo
+#endif
+
+#define rtmGetRTWSolverInfo(rtm) &((rtm)->solverInfo)
+
+/* Definition for use in the target main file */
+#define asyncip_sl_1_sm_ip_test_rtModel RT_MODEL_asyncip_sl_1_sm_ip_test
+
+/* user code (top of header file) */
+/* System '<Root>' */
+/* Opal-RT Technologies */
+extern int opalSizeDwork;
+extern int opalSizeBlockIO;
+extern int opalSizeRTP;
+
+#ifdef USE_RTMODEL
+
+extern void * pRtModel; //pointer on the RTmodel struc
+int_T Opal_rtmGetNumBlockParams(void *ptr);
+int_T Opal_rtmGetNumBlockIO(void *ptr);
+
+#endif
+
+/* Block signals (auto storage) */
+typedef struct {
+ real_T SFunction; /* '<S1>/S-Function' */
+ real_T Sum; /* '<S1>/Sum' */
+ real_T dataready1kHz; /* '<S2>/data ready 1 kHz' */
+ real_T PulseGenerator; /* '<S2>/Pulse Generator' */
+ real_T SFunction2; /* '<S5>/S-Function2' */
+ real_T SFunction1_o1; /* '<S3>/S-Function1' */
+ real_T SFunction1_o2; /* '<S3>/S-Function1' */
+ real_T SFunction1_o3[5]; /* '<S3>/S-Function1' */
+} BlockIO_asyncip_sl_1_sm_ip_test;
+
+/* Block states (auto storage) for system '<Root>' */
+typedef struct {
+ real_T SFunction_PreviousInput; /* '<S1>/S-Function' */
+ void *SFunction2_PWORK; /* '<S5>/S-Function2' */
+ void *SFunction1_PWORK; /* '<S3>/S-Function1' */
+ void *OpIPSocketCtrl1_PWORK; /* '<S2>/OpIPSocketCtrl1' */
+ int32_T clockTickCounter; /* '<S2>/data ready 1 kHz' */
+ int32_T clockTickCounter_c; /* '<S2>/Pulse Generator' */
+ int_T SFunction_IWORK[5]; /* '<S7>/S-Function' */
+} D_Work_asyncip_sl_1_sm_ip_test;
+
+/* Backward compatible GRT Identifiers */
+#define rtB asyncip_sl_1_sm_ip_test_B
+#define BlockIO BlockIO_asyncip_sl_1_sm_ip_test
+#define rtXdot asyncip_sl_1_sm_ip_test_Xdot
+#define StateDerivatives StateDerivatives_asyncip_sl_1_sm_ip_test
+#define tXdis asyncip_sl_1_sm_ip_test_Xdis
+#define StateDisabled StateDisabled_asyncip_sl_1_sm_ip_test
+#define rtP asyncip_sl_1_sm_ip_test_P
+#define Parameters Parameters_asyncip_sl_1_sm_ip_test
+#define rtDWork asyncip_sl_1_sm_ip_test_DWork
+#define D_Work D_Work_asyncip_sl_1_sm_ip_test
+
+/* Parameters (auto storage) */
+struct Parameters_asyncip_sl_1_sm_ip_test_ {
+ real_T SFunction1_Value; /* Expression: 0
+ * Referenced by: '<S1>/S-Function1'
+ */
+ real_T SFunction_X0; /* Expression: 0
+ * Referenced by: '<S1>/S-Function'
+ */
+ real_T dataready1kHz_Amp; /* Expression: 1
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ real_T dataready1kHz_Period; /* Expression: 2
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ real_T dataready1kHz_Duty; /* Expression: 1
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ real_T dataready1kHz_PhaseDelay; /* Expression: 0
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ real_T constants_Value[4]; /* Expression: [1 2 3 4]
+ * Referenced by: '<S2>/constants'
+ */
+ real_T PulseGenerator_Amp; /* Expression: 5
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ real_T PulseGenerator_Period; /* Computed Parameter: PulseGenerator_Period
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ real_T PulseGenerator_Duty; /* Computed Parameter: PulseGenerator_Duty
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ real_T PulseGenerator_PhaseDelay; /* Expression: 0
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ real_T SFunction2_P1_Size[2]; /* Computed Parameter: SFunction2_P1_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P1; /* Expression: ctl_id
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P2_Size[2]; /* Computed Parameter: SFunction2_P2_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P2; /* Expression: send_id
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P3_Size[2]; /* Computed Parameter: SFunction2_P3_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P3; /* Expression: mode
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P4_Size[2]; /* Computed Parameter: SFunction2_P4_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P4; /* Expression: fp1
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P5_Size[2]; /* Computed Parameter: SFunction2_P5_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P5; /* Expression: fp2
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P6_Size[2]; /* Computed Parameter: SFunction2_P6_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P6; /* Expression: fp3
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P7_Size[2]; /* Computed Parameter: SFunction2_P7_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P7; /* Expression: fp4
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P8_Size[2]; /* Computed Parameter: SFunction2_P8_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P8; /* Expression: fp5
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P9_Size[2]; /* Computed Parameter: SFunction2_P9_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P9[7]; /* Computed Parameter: SFunction2_P9
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P10_Size[2]; /* Computed Parameter: SFunction2_P10_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P10[7]; /* Computed Parameter: SFunction2_P10
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P11_Size[2]; /* Computed Parameter: SFunction2_P11_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P11[7]; /* Computed Parameter: SFunction2_P11
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P12_Size[2]; /* Computed Parameter: SFunction2_P12_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P12[7]; /* Computed Parameter: SFunction2_P12
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P13_Size[2]; /* Computed Parameter: SFunction2_P13_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T SFunction2_P13[7]; /* Computed Parameter: SFunction2_P13
+ * Referenced by: '<S5>/S-Function2'
+ */
+ real_T timeout_Value; /* Expression: 2
+ * Referenced by: '<S2>/timeout'
+ */
+ real_T SFunction1_P1_Size[2]; /* Computed Parameter: SFunction1_P1_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P1; /* Expression: ctl_id
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P2_Size[2]; /* Computed Parameter: SFunction1_P2_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P2; /* Expression: recv_id
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P3_Size[2]; /* Computed Parameter: SFunction1_P3_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P3; /* Expression: fp1
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P4_Size[2]; /* Computed Parameter: SFunction1_P4_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P4; /* Expression: fp2
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P5_Size[2]; /* Computed Parameter: SFunction1_P5_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P5; /* Expression: fp3
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P6_Size[2]; /* Computed Parameter: SFunction1_P6_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P6; /* Expression: fp4
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P7_Size[2]; /* Computed Parameter: SFunction1_P7_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P7; /* Expression: fp5
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P8_Size[2]; /* Computed Parameter: SFunction1_P8_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P8[7]; /* Computed Parameter: SFunction1_P8
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P9_Size[2]; /* Computed Parameter: SFunction1_P9_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P9[7]; /* Computed Parameter: SFunction1_P9
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P10_Size[2]; /* Computed Parameter: SFunction1_P10_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P10[7]; /* Computed Parameter: SFunction1_P10
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P11_Size[2]; /* Computed Parameter: SFunction1_P11_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P11[7]; /* Computed Parameter: SFunction1_P11
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P12_Size[2]; /* Computed Parameter: SFunction1_P12_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction1_P12[7]; /* Computed Parameter: SFunction1_P12
+ * Referenced by: '<S3>/S-Function1'
+ */
+ real_T SFunction_P1_Size[2]; /* Computed Parameter: SFunction_P1_Size
+ * Referenced by: '<S7>/S-Function'
+ */
+ real_T SFunction_P1; /* Expression: Acqu_group
+ * Referenced by: '<S7>/S-Function'
+ */
+ real_T OpIPSocketCtrl1_P1_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P1_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P1; /* Expression: ctl_id
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P2_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P2_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P2; /* Expression: proto
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P3_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P3_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P3; /* Expression: ip_port_remote
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P4_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P4_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P4; /* Expression: ip_port_local
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P5_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P5_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P5; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P6_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P6_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P6; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P7_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P7_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P7; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P8_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P8_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P8; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P9_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P9_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P9; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P10_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P10_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P10; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P11_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P11_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P11; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P12_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P12_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P12; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P13_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P13_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P13; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P14_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P14_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P14[14]; /* Computed Parameter: OpIPSocketCtrl1_P14
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P15_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P15_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P15[7]; /* Computed Parameter: OpIPSocketCtrl1_P15
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P16_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P16_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P17_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P17_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P18_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P18_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P19_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P19_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P20_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P20_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P21_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P21_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P22_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P22_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P23_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P23_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P24_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P24_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P25_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P25_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P26_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P26_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P26[7]; /* Computed Parameter: OpIPSocketCtrl1_P26
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P27_Size[2]; /* Computed Parameter: OpIPSocketCtrl1_P27_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ real_T OpIPSocketCtrl1_P27; /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+};
+
+/* Real-time Model Data Structure */
+struct RT_MODEL_asyncip_sl_1_sm_ip_test {
+ const char_T *path;
+ const char_T *modelName;
+ struct SimStruct_tag * *childSfunctions;
+ const char_T *errorStatus;
+ SS_SimMode simMode;
+ RTWLogInfo *rtwLogInfo;
+ RTWExtModeInfo *extModeInfo;
+ RTWSolverInfo solverInfo;
+ RTWSolverInfo *solverInfoPtr;
+ void *sfcnInfo;
+
+ /*
+ * NonInlinedSFcns:
+ * The following substructure contains information regarding
+ * non-inlined s-functions used in the model.
+ */
+ struct {
+ RTWSfcnInfo sfcnInfo;
+ time_T *taskTimePtrs[2];
+ SimStruct childSFunctions[4];
+ SimStruct *childSFunctionPtrs[4];
+ struct _ssBlkInfo2 blkInfo2[4];
+ struct _ssSFcnModelMethods2 methods2[4];
+ struct _ssSFcnModelMethods3 methods3[4];
+ struct _ssStatesInfo2 statesInfo2[4];
+ struct {
+ time_T sfcnPeriod[1];
+ time_T sfcnOffset[1];
+ int_T sfcnTsMap[1];
+ struct _ssPortInputs inputPortInfo[2];
+ real_T const *UPtrs0[1];
+ real_T const *UPtrs1[5];
+ struct _ssPortOutputs outputPortInfo[1];
+ uint_T attribs[13];
+ mxArray *params[13];
+ struct _ssDWorkRecord dWork[1];
+ struct _ssDWorkAuxRecord dWorkAux[1];
+ } Sfcn0;
+
+ struct {
+ time_T sfcnPeriod[1];
+ time_T sfcnOffset[1];
+ int_T sfcnTsMap[1];
+ struct _ssPortInputs inputPortInfo[1];
+ real_T const *UPtrs0[1];
+ struct _ssPortOutputs outputPortInfo[3];
+ uint_T attribs[12];
+ mxArray *params[12];
+ struct _ssDWorkRecord dWork[1];
+ struct _ssDWorkAuxRecord dWorkAux[1];
+ } Sfcn1;
+
+ struct {
+ time_T sfcnPeriod[1];
+ time_T sfcnOffset[1];
+ int_T sfcnTsMap[1];
+ struct _ssPortInputs inputPortInfo[1];
+ real_T const *UPtrs0[13];
+ uint_T attribs[1];
+ mxArray *params[1];
+ struct _ssDWorkRecord dWork[1];
+ struct _ssDWorkAuxRecord dWorkAux[1];
+ } Sfcn2;
+
+ struct {
+ time_T sfcnPeriod[1];
+ time_T sfcnOffset[1];
+ int_T sfcnTsMap[1];
+ uint_T attribs[27];
+ mxArray *params[27];
+ struct _ssDWorkRecord dWork[1];
+ struct _ssDWorkAuxRecord dWorkAux[1];
+ } Sfcn3;
+ } NonInlinedSFcns;
+
+ /*
+ * ModelData:
+ * The following substructure contains information regarding
+ * the data used in the model.
+ */
+ struct {
+ void *blockIO;
+ const void *constBlockIO;
+ real_T *defaultParam;
+ ZCSigState *prevZCSigState;
+ real_T *contStates;
+ real_T *derivs;
+ real_T *zcSignalValues;
+ void *inputs;
+ void *outputs;
+ boolean_T *contStateDisabled;
+ boolean_T zCCacheNeedsReset;
+ boolean_T derivCacheNeedsReset;
+ boolean_T blkStateChange;
+ } ModelData;
+
+ /*
+ * Sizes:
+ * The following substructure contains sizes information
+ * for many of the model attributes such as inputs, outputs,
+ * dwork, sample times, etc.
+ */
+ struct {
+ uint32_T checksums[4];
+ uint32_T options;
+ int_T numContStates;
+ int_T numU;
+ int_T numY;
+ int_T numSampTimes;
+ int_T numBlocks;
+ int_T numBlockIO;
+ int_T numBlockPrms;
+ int_T numDwork;
+ int_T numSFcnPrms;
+ int_T numSFcns;
+ int_T numIports;
+ int_T numOports;
+ int_T numNonSampZCs;
+ int_T sysDirFeedThru;
+ int_T rtwGenSfcn;
+ } Sizes;
+
+ /*
+ * SpecialInfo:
+ * The following substructure contains special information
+ * related to other components that are dependent on RTW.
+ */
+ struct {
+ const void *mappingInfo;
+ void *xpcData;
+ } SpecialInfo;
+
+ /*
+ * Timing:
+ * The following substructure contains information regarding
+ * the timing information for the model.
+ */
+ struct {
+ time_T stepSize;
+ uint32_T clockTick0;
+ uint32_T clockTickH0;
+ time_T stepSize0;
+ uint32_T clockTick1;
+ uint32_T clockTickH1;
+ time_T stepSize1;
+ struct {
+ uint8_T TID[2];
+ } TaskCounters;
+
+ time_T tStart;
+ time_T tFinal;
+ time_T timeOfLastOutput;
+ void *timingData;
+ real_T *varNextHitTimesList;
+ SimTimeStep simTimeStep;
+ boolean_T stopRequestedFlag;
+ time_T *sampleTimes;
+ time_T *offsetTimes;
+ int_T *sampleTimeTaskIDPtr;
+ int_T *sampleHits;
+ int_T *perTaskSampleHits;
+ time_T *t;
+ time_T sampleTimesArray[2];
+ time_T offsetTimesArray[2];
+ int_T sampleTimeTaskIDArray[2];
+ int_T sampleHitArray[2];
+ int_T perTaskSampleHitsArray[4];
+ time_T tArray[2];
+ } Timing;
+
+ /*
+ * Work:
+ * The following substructure contains information regarding
+ * the work vectors in the model.
+ */
+ struct {
+ void *dwork;
+ } Work;
+};
+
+/* Block parameters (auto storage) */
+extern Parameters_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_P;
+
+/* Block signals (auto storage) */
+extern BlockIO_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_B;
+
+/* Block states (auto storage) */
+extern D_Work_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_DWork;
+
+/* Real-time Model object */
+extern struct RT_MODEL_asyncip_sl_1_sm_ip_test *const asyncip_sl_1_sm_ip_test_M;
+
+/*-
+ * These blocks were eliminated from the model due to optimizations:
+ *
+ * Block '<S2>/sine' : Unused code path elimination
+ */
+
+/*-
+ * The generated code includes comments that allow you to trace directly
+ * back to the appropriate location in the model. The basic format
+ * is <system>/block_name, where system is the system number (uniquely
+ * assigned by Simulink) and block_name is the name of the block.
+ *
+ * Use the MATLAB hilite_system command to trace the generated code back
+ * to the model. For example,
+ *
+ * hilite_system('<S3>') - opens system 3
+ * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
+ *
+ * Here is the system hierarchy for this model
+ *
+ * '<Root>' : 'asyncip_sl_1_sm_ip_test'
+ * '<S1>' : 'asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch'
+ * '<S2>' : 'asyncip_sl_1_sm_ip_test/sm_ip_test'
+ * '<S3>' : 'asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1'
+ * '<S4>' : 'asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem'
+ * '<S5>' : 'asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1'
+ * '<S6>' : 'asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1'
+ * '<S7>' : 'asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1'
+ */
+#endif /* RTW_HEADER_asyncip_sl_1_sm_ip_test_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.log
new file mode 100644
index 000000000..63836b253
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.log
@@ -0,0 +1,61 @@
+
+--------------- Transferring files ... ------------------------------
+
+Transferring in binary mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test ... OK.
+
+--------------- Done transferring files -----------------------------
+
+
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_preload.py ... done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_preload.py ... done
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:54:01 2014
+
+Starting transfer of /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/opasyncip_sl_sm_ip_test_0.snap...
+Transfer of /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/opasyncip_sl_sm_ip_test_0.snap OK
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:54:24 2014
+
+ Main priority set to 99
+AsyncIP: SendToIPPort: Finished
+ [17891814]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 13:09:18 2014
+
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_postreset.py ... done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_postreset.py ... done
+
+
+--------------- Retrieving files ... ---------------------------------
+
+Setting local directory to D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\asyncip_sl_sm_ip_test\OpREDHAWKtarget\... OK.
+Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test_147_125401.log ... OK.
+Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/target_report.xml ... OK.
+
+--------------- Done retrieving files --------------------------------
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.map b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.map
new file mode 100644
index 000000000..defed65c1
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.map
@@ -0,0 +1,156 @@
+[Parameter]
+0=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/S-Function1|Value|0|Scalar|1|1|0.0|Constant|
+1=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/S-Function|X0|0|Scalar|1|1|0.0|Memory|
+2=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|Amplitude|1|Scalar|1|1|1.0|DiscretePulseGenerator|
+3=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|Period|2|Scalar|1|1|2.0|DiscretePulseGenerator|
+4=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|PulseWidth|1|Scalar|1|1|1.0|DiscretePulseGenerator|
+5=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|PhaseDelay|0|Scalar|1|1|0.0|DiscretePulseGenerator|
+6=asyncip_sl_1_sm_ip_test/sm_ip_test/constants|Value|[1 2 3 4]|RVector|1|4|1.0|2.0|3.0|4.0|Constant|
+7=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|Amplitude|5|Scalar|1|1|5.0|DiscretePulseGenerator|
+8=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|Period| |Scalar|1|1|2000.0|DiscretePulseGenerator|
+9=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|PulseWidth| |Scalar|1|1|600.0|DiscretePulseGenerator|
+10=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|PhaseDelay|0|Scalar|1|1|0.0|DiscretePulseGenerator|
+11=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P1Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+12=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P1|ctl_id|Scalar|1|1|1.0|S-Function sfun_send_async|
+13=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P2Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+14=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P2|send_id|Scalar|1|1|1.0|S-Function sfun_send_async|
+15=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P3Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+16=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P3|mode|Scalar|1|1|3.0|S-Function sfun_send_async|
+17=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P4Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+18=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P4|fp1|Scalar|1|1|1.0|S-Function sfun_send_async|
+19=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P5Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+20=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P5|fp2|Scalar|1|1|2.0|S-Function sfun_send_async|
+21=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P6Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+22=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P6|fp3|Scalar|1|1|3.0|S-Function sfun_send_async|
+23=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P7Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+24=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P7|fp4|Scalar|1|1|4.0|S-Function sfun_send_async|
+25=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P8Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
+26=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P8|fp5|Scalar|1|1|5.0|S-Function sfun_send_async|
+27=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P9Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
+28=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P9| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|49.0|S-Function sfun_send_async|
+29=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P10Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
+30=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P10| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|50.0|S-Function sfun_send_async|
+31=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P11Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
+32=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P11| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|51.0|S-Function sfun_send_async|
+33=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P12Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
+34=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P12| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|52.0|S-Function sfun_send_async|
+35=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P13Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
+36=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P13| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|53.0|S-Function sfun_send_async|
+37=asyncip_sl_1_sm_ip_test/sm_ip_test/timeout|Value|2|Scalar|1|1|2.0|Constant|
+38=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P1Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+39=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P1|ctl_id|Scalar|1|1|1.0|S-Function sfun_recv_async|
+40=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P2Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+41=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P2|recv_id|Scalar|1|1|1.0|S-Function sfun_recv_async|
+42=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P3Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+43=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P3|fp1|Scalar|1|1|1.0|S-Function sfun_recv_async|
+44=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P4Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+45=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P4|fp2|Scalar|1|1|2.0|S-Function sfun_recv_async|
+46=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P5Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+47=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P5|fp3|Scalar|1|1|3.0|S-Function sfun_recv_async|
+48=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P6Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+49=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P6|fp4|Scalar|1|1|4.0|S-Function sfun_recv_async|
+50=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P7Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
+51=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P7|fp5|Scalar|1|1|5.0|S-Function sfun_recv_async|
+52=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P8Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
+53=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P8| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|49.0|S-Function sfun_recv_async|
+54=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P9Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
+55=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P9| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|50.0|S-Function sfun_recv_async|
+56=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P10Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
+57=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P10| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|51.0|S-Function sfun_recv_async|
+58=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P11Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
+59=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P11| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|52.0|S-Function sfun_recv_async|
+60=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P12Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
+61=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P12| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|53.0|S-Function sfun_recv_async|
+62=asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1/S-Function|P1Size| |RVector|1|2|1.0|1.0|S-Function OP_SEND|
+63=asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1/S-Function|P1|Acqu_group|Scalar|1|1|1.0|S-Function OP_SEND|
+64=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P1Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+65=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P1|ctl_id|Scalar|1|1|1.0|S-Function sfun_gen_async_ctrl|
+66=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P2Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+67=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P2|proto|Scalar|1|1|1.0|S-Function sfun_gen_async_ctrl|
+68=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P3Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+69=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P3|ip_port_remote|Scalar|1|1|10200.0|S-Function sfun_gen_async_ctrl|
+70=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P4Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+71=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P4|ip_port_local|Scalar|1|1|10201.0|S-Function sfun_gen_async_ctrl|
+72=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P5Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+73=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P5|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+74=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P6Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+75=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P6|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+76=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P7Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+77=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P7|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+78=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P8Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+79=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P8|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+80=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P9Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+81=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P9|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+82=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P10Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+83=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P10|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+84=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P11Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+85=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P11|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+86=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P12Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+87=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P12|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+88=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P13Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+89=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P13|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+90=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P14Size| |RVector|1|2|1.0|14.0|S-Function sfun_gen_async_ctrl|
+91=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P14| |RVector|1|14|49.0|51.0|55.0|46.0|50.0|50.0|54.0|46.0|49.0|54.0|48.0|46.0|57.0|49.0|S-Function sfun_gen_async_ctrl|
+92=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P15Size| |RVector|1|2|1.0|7.0|S-Function sfun_gen_async_ctrl|
+93=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P15| |RVector|1|7|48.0|46.0|48.0|46.0|48.0|46.0|48.0|S-Function sfun_gen_async_ctrl|
+94=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P16Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+95=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P17Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+96=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P18Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+97=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P19Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+98=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P20Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+99=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P21Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+100=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P22Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+101=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P23Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+102=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P24Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+103=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P25Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
+104=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P26Size| |RVector|1|2|1.0|7.0|S-Function sfun_gen_async_ctrl|
+105=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P26| |RVector|1|7|65.0|115.0|121.0|110.0|99.0|73.0|80.0|S-Function sfun_gen_async_ctrl|
+106=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P27Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
+107=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P27|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
+nbParameters=108
+
+[Signal]
+0=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/S-Function|NULL|0|1|1|1|S|Memory|
+1=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/Sum|NULL|1|1|1|1|S|Sum|
+2=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|NULL|2|1|1|1|S|DiscretePulseGenerator|
+3=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|NULL|3|1|1|1|S|DiscretePulseGenerator|
+4=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|NULL|4|1|1|1|S|S-Function sfun_send_async|
+5=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|NULL|5|1|1|1|S|S-Function sfun_recv_async|
+6=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|NULL|6|1|1|1|S|S-Function sfun_recv_async|
+7=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|NULL|7|5|5|1|V|S-Function sfun_recv_async|
+nbSignals=8
+
+[ModelDataStructure]
+0=blkStateChange
+27=derivCacheNeedsReset
+137=zCCacheNeedsReset
+
+[dwork]
+0=SFunction_PreviousInput|real_T|
+4=clockTickCounter|int32_T|
+5=clockTickCounter_c|int32_T|
+6=SFunction_IWORK|IWORK|
+
+[TimingStructure]
+4=clockTick0
+5=clockTick1
+6=clockTickH0
+7=clockTickH1
+32=tFinal
+74=offsetTimesArray
+80=perTaskSampleHitsArray
+96=sampleHitArray
+100=sampleTimesArray
+103=sampleTimeTaskIDArray
+106=simTimeStep
+108=tStart
+109=stepSize
+110=stepSize0
+111=stepSize1
+114=stopRequestedFlag
+121=TaskCounters
+125=tArray
+139=timeOfLastOutput
+
+
+[dummy]
\ No newline at end of file
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.mk b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.mk
new file mode 100644
index 000000000..0c96e5ea8
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.mk
@@ -0,0 +1,637 @@
+# File : TARGET.tmf
+#
+# $Revision 1.1 $
+#
+# Abstract:
+# Real-Time Workshop template makefile for building a Neutrino-based
+# stand-alone real-time version of SIMULINK model using
+# generated C code.
+#
+# Note that this template is automatically customized by the Real-Time
+# Workshop build procedure to create "<model>.mk"
+#
+# The following defines can be used to modify the behavior of the
+# build:
+# OPTS - User specific compile options, such as
+# OPTS=-DMULTITASKING to enable multitasking mode.
+# OPT_OPTS - Optimization options. Default is -Oatx. To enable
+# debugging define DEBUG.
+# USER_SRCS - Additional user sources, such as files needed by
+# S-functions.
+# USER_INCS - Additional include paths
+# (i.e. USER_INCS="-Iwhere-ever -Iwhere-ever2")
+
+
+#------------------------ Macros read by make_rtw -----------------------------
+#
+# The following macros are read by the Real-Time Workshop build procedure:
+#
+# MAKE - This is the command used to invoke the make utility
+# HOST - What platform this template makefile is targeted for
+# (i.e. PC or UNIX)
+# BUILD - Invoke make from the Real-Time Workshop build procedure
+# (yes/no)?
+# SYS_TARGET_FILE - Name of system target file.
+
+MAKE = make
+HOST = PC
+BUILD = no
+SYS_TARGET_FILE = rtlab_rtmodel.tlc
+
+#---------------------- Tokens expanded by make_rtw ---------------------------
+#
+# The following tokens, when wrapped with "|>" and "|<" are expanded by the
+# Real-Time Workshop build procedure.
+#
+# MODEL_NAME - Name of the SIMULINK block diagram
+# MODEL_MODULES - Any additional generated source modules
+# MAKEFILE_NAME - Name of makefile created from template makefile <model>.mk
+# MATLAB_ROOT - Path to were MATLAB is installed.
+# S_FUNCTIONS - List of S-functions.
+# SOLVER - Solver source file name
+# NUMST - Number of sample times
+# TID01EQ - yes (1) or no (0): Are sampling rates of continuous task
+# (tid=0) and 1st discrete task equal.
+# NCSTATES - Number of continuous states
+# COMPUTER - Computer type. See the MATLAB computer command.
+# BUILDARGS - Options passed in at the command line.
+
+MODEL = asyncip_sl_1_sm_ip_test
+MODULES = asyncip_sl_1_sm_ip_test_data.c rtGetInf.c rtGetNaN.c rt_logging.c rt_matrx.c rt_nonfinite.c rt_printf.c
+MAKEFILE = asyncip_sl_1_sm_ip_test.mk
+MATLAB_ROOT = C:\Program Files (x86)\MATLAB\R2011b
+ALT_MATLAB_ROOT = C:\PROGRA~2\MATLAB\R2011b
+S_FUNCTIONS = sfun_send_async.c sfun_recv_async.c OP_SEND.c sfun_gen_async_ctrl.c
+SOLVER =
+NUMST = 2
+TID01EQ = 0
+NCSTATES = 0
+COMPUTER = PCWIN
+BUILDARGS = GENERATE_REPORT=0 EXT_MODE=0 EXTMODE_STATIC_ALLOC=0 TMW_EXTMODE_TESTING=0 EXTMODE_STATIC_ALLOC_SIZE=1000000 EXTMODE_TRANSPORT=0
+MULTITASKING = 0
+
+MODELREFS =
+MODELLIB = asyncip_sl_1_sm_ip_testlib.lib
+MODELREF_LINK_LIBS =
+MODELREF_LINK_RSPFILE = asyncip_sl_1_sm_ip_test_ref.rsp
+MODELREF_INC_PATH =
+RELATIVE_PATH_TO_ANCHOR = ..
+MODELREF_TARGET_TYPE = NONE
+
+SHARED_SRC =
+SHARED_SRC_DIR =
+SHARED_BIN_DIR =
+SHARED_LIB =
+
+# SHARED_BIN_DIR = unused
+# SHARED_LIB = unused
+UNAME = $(shell uname)
+
+ifeq "$(UNAME)" "QNX" ##### nto
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ SHARED_SRC := _sharedutils\*.c*
+ SHARED_SRC_DIR := _sharedutils
+ RELATIVE_PATH_TO_ANCHOR :=
+ MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
+ MODELLIB := $(MODELLIB:.lib=.a)
+
+ else
+ SHARED_SRC := ..\_sharedutils\*.c*
+ SHARED_SRC_DIR := ..\_sharedutils
+ RELATIVE_PATH_TO_ANCHOR := ..
+ MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
+ MODELLIB := $(MODELLIB:.lib=.a)
+ endif
+else
+ ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ SHARED_SRC := _sharedutils\*.c*
+ SHARED_SRC_DIR := _sharedutils
+ RELATIVE_PATH_TO_ANCHOR :=
+ MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
+ MODELLIB := $(MODELLIB:.lib=.a)
+ else
+ SHARED_SRC := ..\_sharedutils\*.c*
+ SHARED_SRC_DIR := ..\_sharedutils
+ RELATIVE_PATH_TO_ANCHOR := ..
+ MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
+ MODELLIB := $(MODELLIB:.lib=.a)
+ endif
+ else
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ SHARED_SRC := $(SHARED_SRC)
+ SHARED_SRC_DIR := $(SHARED_SRC_DIR)
+ RELATIVE_PATH_TO_ANCHOR := $(RELATIVE_PATH_TO_ANCHOR)
+ MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS)
+ MODELLIB := $(MODELLIB)
+ else
+ SHARED_SRC := $(SHARED_SRC)
+ SHARED_SRC_DIR := $(SHARED_SRC_DIR)
+ RELATIVE_PATH_TO_ANCHOR := $(RELATIVE_PATH_TO_ANCHOR)
+ MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS)
+ MODELLIB := $(MODELLIB)
+ endif
+ endif
+endif
+
+
+
+
+#----------------------------- Source Files ------------------------------
+MOD_TMP1 = $(MODULES:blms_an_wn_cc_rt.c= )
+MOD_TMP2 = $(MOD_TMP1:blms_an_wn_dd_rt.c= )
+MOD_TMP3 = $(MOD_TMP2:blms_an_wn_rr_rt.c= )
+MOD_TMP4 = $(MOD_TMP3:blms_an_wn_zz_rt.c= )
+MOD_TMP5 = $(MOD_TMP4:blms_an_wy_cc_rt.c= )
+MOD_TMP6 = $(MOD_TMP5:blms_an_wy_dd_rt.c= )
+MOD_TMP7 = $(MOD_TMP6:blms_an_wy_rr_rt.c= )
+MOD_TMP8 = $(MOD_TMP7:blms_an_wy_zz_rt.c= )
+MOD_TMP9 = $(MOD_TMP8:blms_ay_wn_cc_rt.c= )
+MOD_TMP10 = $(MOD_TMP9:blms_ay_wn_dd_rt.c= )
+MOD_TMP11 = $(MOD_TMP10:blms_ay_wn_rr_rt.c= )
+MOD_TMP12 = $(MOD_TMP11:blms_ay_wn_zz_rt.c= )
+MOD_TMP13 = $(MOD_TMP12:blms_ay_wy_cc_rt.c= )
+MOD_TMP14 = $(MOD_TMP13:blms_ay_wy_dd_rt.c= )
+MOD_TMP15 = $(MOD_TMP14:blms_ay_wy_rr_rt.c= )
+MOD_TMP16 = $(MOD_TMP15:blms_ay_wy_zz_rt.c= )
+MOD_TMP17 = $(MOD_TMP16:is_little_endian_rt.c= )
+MOD_TMP18 = $(MOD_TMP17:eph_zc_fcn_rt.c= )
+MOD_TMP19 = $(MOD_TMP18:2chabank_fr_df_cc_rt.c= )
+MOD_TMP20 = $(MOD_TMP19:2chabank_fr_df_cr_rt.c= )
+MOD_TMP21 = $(MOD_TMP20:2chabank_fr_df_dd_rt.c= )
+MOD_TMP22 = $(MOD_TMP21:2chabank_fr_df_rr_rt.c= )
+MOD_TMP23 = $(MOD_TMP22:2chabank_fr_df_zd_rt.c= )
+MOD_TMP24 = $(MOD_TMP23:2chabank_fr_df_zz_rt.c= )
+MOD_TMP25 = $(MOD_TMP24:2chsbank_df_cc_rt.c= )
+MOD_TMP26 = $(MOD_TMP25:2chsbank_df_cr_rt.c= )
+MOD_TMP27 = $(MOD_TMP26:2chsbank_df_dd_rt.c= )
+MOD_TMP28 = $(MOD_TMP27:2chsbank_df_rr_rt.c= )
+MOD_TMP29 = $(MOD_TMP28:2chsbank_df_zd_rt.c= )
+MOD_TMP30 = $(MOD_TMP29:2chsbank_df_zz_rt.c= )
+MOD_TMP31 = $(MOD_TMP30:ic_copy_channel_rt.c= )
+MOD_TMP32 = $(MOD_TMP31:ic_copy_matrix_rt.c= )
+MOD_TMP33 = $(MOD_TMP32:ic_copy_scalar_rt.c= )
+MOD_TMP34 = $(MOD_TMP33:ic_copy_vector_rt.c= )
+MOD_TMP35 = $(MOD_TMP34:ic_old_copy_fcns_rt.c= )
+MOD_TMP36 = $(MOD_TMP35:mmpcmaudio_rt.c= )
+MOD_TMP37 = $(MOD_TMP36:mmrgb24convert2gray_rt.c= )
+MOD_TMP38 = $(MOD_TMP37:mmrgb24convert_rt.c= )
+MOD_TMP39 = $(MOD_TMP38:mmrgb24output_rt.c= )
+MOD_TMP40 = $(MOD_TMP39:mmrgb24paddedoutput_rt.c= )
+MOD_TMP41 = $(MOD_TMP40:polyval_cc_rt.c= )
+MOD_TMP42 = $(MOD_TMP41:polyval_cr_rt.c= )
+MOD_TMP43 = $(MOD_TMP42:polyval_dd_rt.c= )
+MOD_TMP44 = $(MOD_TMP43:polyval_dz_rt.c= )
+MOD_TMP45 = $(MOD_TMP44:polyval_rc_rt.c= )
+MOD_TMP46 = $(MOD_TMP45:polyval_rr_rt.c= )
+MOD_TMP47 = $(MOD_TMP46:polyval_zd_rt.c= )
+MOD_TMP48 = $(MOD_TMP47:polyval_zz_rt.c= )
+MOD_TMP49 = $(MOD_TMP48:sort_ins_idx_d_rt.c= )
+MOD_TMP50 = $(MOD_TMP49:sort_ins_idx_r_rt.c= )
+MOD_TMP51 = $(MOD_TMP50:sort_ins_idx_s08_rt.c= )
+MOD_TMP52 = $(MOD_TMP51:sort_ins_idx_s16_rt.c= )
+MOD_TMP53 = $(MOD_TMP52:sort_ins_idx_s32_rt.c= )
+MOD_TMP54 = $(MOD_TMP53:sort_ins_idx_u08_rt.c= )
+MOD_TMP55 = $(MOD_TMP54:sort_ins_idx_u16_rt.c= )
+MOD_TMP56 = $(MOD_TMP55:sort_ins_idx_u32_rt.c= )
+MOD_TMP57 = $(MOD_TMP56:sort_ins_val_d_rt.c= )
+MOD_TMP58 = $(MOD_TMP57:sort_ins_val_r_rt.c= )
+MOD_TMP59 = $(MOD_TMP58:sort_ins_val_s08_rt.c= )
+MOD_TMP60 = $(MOD_TMP59:sort_ins_val_s16_rt.c= )
+MOD_TMP61 = $(MOD_TMP60:sort_ins_val_s32_rt.c= )
+MOD_TMP62 = $(MOD_TMP61:sort_ins_val_u08_rt.c= )
+MOD_TMP63 = $(MOD_TMP62:sort_ins_val_u16_rt.c= )
+MOD_TMP64 = $(MOD_TMP63:sort_ins_val_u32_rt.c= )
+MOD_TMP65 = $(MOD_TMP64:sort_qk_idx_d_rt.c= )
+MOD_TMP66 = $(MOD_TMP65:sort_qk_idx_r_rt.c= )
+MOD_TMP67 = $(MOD_TMP66:sort_qk_idx_s08_rt.c= )
+MOD_TMP68 = $(MOD_TMP67:sort_qk_idx_s16_rt.c= )
+MOD_TMP69 = $(MOD_TMP68:sort_qk_idx_s32_rt.c= )
+MOD_TMP70 = $(MOD_TMP69:sort_qk_idx_u08_rt.c= )
+MOD_TMP71 = $(MOD_TMP70:sort_qk_idx_u16_rt.c= )
+MOD_TMP72 = $(MOD_TMP71:sort_qk_idx_u32_rt.c= )
+MOD_TMP73 = $(MOD_TMP72:sort_qk_val_d_rt.c= )
+MOD_TMP74 = $(MOD_TMP73:sort_qk_val_r_rt.c= )
+MOD_TMP75 = $(MOD_TMP74:sort_qk_val_s08_rt.c= )
+MOD_TMP76 = $(MOD_TMP75:sort_qk_val_s16_rt.c= )
+MOD_TMP77 = $(MOD_TMP76:sort_qk_val_s32_rt.c= )
+MOD_TMP78 = $(MOD_TMP77:sort_qk_val_u08_rt.c= )
+MOD_TMP79 = $(MOD_TMP78:sort_qk_val_u16_rt.c= )
+MOD_TMP80 = $(MOD_TMP79:sort_qk_val_u32_rt.c= )
+MOD_TMP81 = $(MOD_TMP80:srt_qid_findpivot_d_rt.c= )
+MOD_TMP82 = $(MOD_TMP81:srt_qid_findpivot_r_rt.c= )
+MOD_TMP83 = $(MOD_TMP82:srt_qid_partition_d_rt.c= )
+MOD_TMP84 = $(MOD_TMP83:srt_qid_partition_r_rt.c= )
+MOD_TMP85 = $(MOD_TMP84:srt_qkrec_c_rt.c= )
+MOD_TMP86 = $(MOD_TMP85:srt_qkrec_d_rt.c= )
+MOD_TMP87 = $(MOD_TMP86:srt_qkrec_r_rt.c= )
+MOD_TMP88 = $(MOD_TMP87:srt_qkrec_z_rt.c= )
+MOD_TMP89 = $(MOD_TMP88:randsrccreateseeds_32_rt.c= )
+MOD_TMP90 = $(MOD_TMP89:randsrccreateseeds_64_rt.c= )
+MOD_TMP91 = $(MOD_TMP90:randsrcinitstate_gc_32_rt.c= )
+MOD_TMP92 = $(MOD_TMP91:randsrcinitstate_gc_64_rt.c= )
+MOD_TMP93 = $(MOD_TMP92:randsrcinitstate_gz_rt.c= )
+MOD_TMP94 = $(MOD_TMP93:randsrcinitstate_u_32_rt.c= )
+MOD_TMP95 = $(MOD_TMP94:randsrcinitstate_u_64_rt.c= )
+MOD_TMP96 = $(MOD_TMP95:randsrc_gc_c_rt.c= )
+MOD_TMP97 = $(MOD_TMP96:randsrc_gc_d_rt.c= )
+MOD_TMP98 = $(MOD_TMP97:randsrc_gc_r_rt.c= )
+MOD_TMP99 = $(MOD_TMP98:randsrc_gc_z_rt.c= )
+MOD_TMP100 = $(MOD_TMP99:randsrc_gz_c_rt.c= )
+MOD_TMP101 = $(MOD_TMP100:randsrc_gz_d_rt.c= )
+MOD_TMP102 = $(MOD_TMP101:randsrc_gz_r_rt.c= )
+MOD_TMP103 = $(MOD_TMP102:randsrc_gz_z_rt.c= )
+MOD_TMP104 = $(MOD_TMP103:randsrc_u_c_rt.c= )
+MOD_TMP105 = $(MOD_TMP104:randsrc_u_d_rt.c= )
+MOD_TMP106 = $(MOD_TMP105:randsrc_u_r_rt.c= )
+MOD_TMP107 = $(MOD_TMP106:randsrc_u_z_rt.c= )
+MOD_TMP108 = $(MOD_TMP107:buf_copy_frame_to_mem_OL_1ch_rt.c= )
+MOD_TMP109 = $(MOD_TMP108:buf_copy_frame_to_mem_OL_rt.c= )
+MOD_TMP110 = $(MOD_TMP109:buf_copy_input_to_output_1ch_rt.c= )
+MOD_TMP111 = $(MOD_TMP110:buf_copy_input_to_output_rt.c= )
+MOD_TMP112 = $(MOD_TMP111:buf_copy_scalar_to_mem_OL_1ch_rt.c= )
+MOD_TMP113 = $(MOD_TMP112:buf_copy_scalar_to_mem_OL_rt.c= )
+MOD_TMP114 = $(MOD_TMP113:buf_copy_scalar_to_mem_UL_1ch_rt.c= )
+MOD_TMP115 = $(MOD_TMP114:buf_copy_scalar_to_mem_UL_rt.c= )
+MOD_TMP116 = $(MOD_TMP115:buf_output_frame_1ch_rt.c= )
+MOD_TMP117 = $(MOD_TMP116:buf_output_frame_rt.c= )
+MOD_TMP118 = $(MOD_TMP117:buf_output_scalar_1ch_rt.c= )
+MOD_TMP119 = $(MOD_TMP118:buf_output_scalar_rt.c= )
+MOD_TMP120 = $(MOD_TMP119:svd_c_rt.c= )
+MOD_TMP121 = $(MOD_TMP120:svd_d_rt.c= )
+MOD_TMP122 = $(MOD_TMP121:svd_helper_rt.c= )
+MOD_TMP123 = $(MOD_TMP122:svd_r_rt.c= )
+MODULES_SRCS = $(MOD_TMP123:svd_z_rt.c= )
+
+# Remove Opal-RT block sources from the list of S-Functions: they are provided with RT-LAB
+# Leave any other S-Functions.
+SFS_TMP1 = $(S_FUNCTIONS:recv_param.c=)
+SFS_TMP1a = $(SFS_TMP1:RECV_Param.c=)
+SFS_TMP2 = $(SFS_TMP1a:recv_rt.c=)
+SFS_TMP3 = $(SFS_TMP2:op_send.c=)
+SFS_TMP3a = $(SFS_TMP3:OP_SEND.c=)
+SFS_TMP4 = $(SFS_TMP3a:send_rt.c=)
+SFS_TMP10 = $(SFS_TMP4:sfun_timing.c=)
+SFS_TMP11 = $(SFS_TMP10:optrigger.c=)
+SFS_TMP19 = $(SFS_TMP11:opsnapshot.c=)
+SFS_TMP20 = $(SFS_TMP19:opwritefile.c=)
+SFS_TMP21 = $(SFS_TMP20:send_fw.c=)
+SFS_TMP22 = $(SFS_TMP21:recv_fw.c=)
+SFS_TMP23 = $(SFS_TMP22:simulation_info.c=)
+SFS_TMP25 = $(SFS_TMP23:usr_delay.c=)
+SFS_TMP26 = $(SFS_TMP25:simulation_events2.c=)
+
+
+SFS_TMP56 = $(SFS_TMP26:sfun_opfromfile.c=)
+SFS_TMP78 = $(SFS_TMP56:sfun_opexternvar.c=)
+SFS_TMP79 = $(SFS_TMP78:sfun_time_factor.c=)
+SFS_TMP80 = $(SFS_TMP79:sfun_ohci_info.c=)
+SFS_TMP84 = $(SFS_TMP80:simulation_events.c=)
+SFS_TMP88 = $(SFS_TMP84:sfun_sync_vme200_2.c=)
+SFS_TMP92 = $(SFS_TMP88:read_dinamo.c=)
+SFS_TMP93 = $(SFS_TMP92:sfun_subsystem_trigger.c=)
+SFS_TMP110 = $(SFS_TMP93:sfun_async_st_emit.c=)
+
+SFS_TMP127 = $(SFS_TMP110:recv_ohci.c=)
+SFS_TMP128 = $(SFS_TMP127:send_ohci.c=)
+SFS_TMP129 = $(SFS_TMP128:error_status.c=)
+SFS_TMP130 = $(SFS_TMP129:fake_io.c=)
+SFS_TMP131 = $(SFS_TMP130:op_getpid.c=)
+SFS_TMP132 = $(SFS_TMP131:print_msg.c=)
+SFS_TMP133 = $(SFS_TMP132:read_pport.c=)
+SFS_TMP134 = $(SFS_TMP133:run_model.c=)
+
+SFS_TMP138 = $(SFS_TMP134:opAssertion.c=)
+SFS_TMP139 = $(SFS_TMP138:checkoutputwidth.c=)
+SFS_TMP140 = $(SFS_TMP139:signalCompression.c=)
+SFS_TMP141 = $(SFS_TMP140:signalUncompression.c=)
+SFS_TMP142 = $(SFS_TMP141:opendianswapper.c=)
+SFS_TMP143 = $(SFS_TMP142:signalcompression.c=)
+SFS_TMP144 = $(SFS_TMP143:signaluncompression.c=)
+
+SFS_TMP182 = $(SFS_TMP144:pause_model.c=)
+SFS_TMP183 = $(SFS_TMP182:opmonitor.c=)
+
+SFS_TMP215 = $(SFS_TMP183:mstack_ccp_cal.c=)
+SFS_TMP216 = $(SFS_TMP215:mstack_ccp_in.c=)
+SFS_TMP217 = $(SFS_TMP216:mstack_analog_in.c=)
+SFS_TMP218 = $(SFS_TMP217:mstack_digital_in.c=)
+SFS_TMP219 = $(SFS_TMP218:mstack_ccp_ctl.c=)
+
+SFS_TMP229 = $(SFS_TMP219:pycall.c=)
+
+SFS_TMP238 = $(SFS_TMP229:sfun_opdataset.c=)
+SFS_TMP239 = $(SFS_TMP238:sfun_opinterpol.c=)
+SFS_TMP240 = $(SFS_TMP239:nrt.c=)
+SFS_TMP241 = $(SFS_TMP240:opplotfile.c=)
+SFS_TMP242 = $(SFS_TMP241:pubhlaclassattr.c=)
+SFS_TMP243 = $(SFS_TMP242:subhlaclassattr.c=)
+SFS_TMP244 = $(SFS_TMP243:pubhlainteraction.c=)
+SFS_TMP245 = $(SFS_TMP244:subhlainteraction.c=)
+SFS_TMP246 = $(SFS_TMP245:pubentitytype.c=)
+SFS_TMP247 = $(SFS_TMP246:hlafedoptions.c=)
+
+SFS_TMP260 = $(SFS_TMP247:sfun_xplane.c=)
+SFS_TMP261 = $(SFS_TMP260:sfun_opjoystick.c=)
+
+SFS_TMP262 = $(SFS_TMP261:fts2abcd.c=)
+SFS_TMP263 = $(SFS_TMP262:fts2flux.c=)
+SFS_TMP264 = $(SFS_TMP263:fts2dla.c=)
+SFS_TMP265 = $(SFS_TMP264:fts2hfun.c=)
+SFS_TMP266 = $(SFS_TMP265:fts2abcd_dtc.c=)
+
+SFS_TMP270 = $(SFS_TMP266:sfun_conversion.c=)
+SFS_TMP271 = $(SFS_TMP270:sfun_elements_demux.c=)
+SFS_TMP272 = $(SFS_TMP271:sfun_blob_decimation.c=)
+SFS_TMP273 = $(SFS_TMP272:sfun_dynamic_rescale.c=)
+SFS_TMP274 = $(SFS_TMP273:DBL2SFP.c=)
+SFS_TMP275 = $(SFS_TMP274:SFP2DBL.c=)
+SFS_TMP276 = $(SFS_TMP275:OpDVP.c=)
+SFS_TMP277 = $(SFS_TMP276:OpRfm.c=)
+SFS_TMP278 = $(SFS_TMP277:OpHei.c=)
+SFS_TMP279 = $(SFS_TMP278:OpPickeringBattSim.c=)
+S_FUNC_SRCS = $(SFS_TMP279:optaketime.c=)
+
+
+#############################################################################
+#
+# For CarSim/VehSim/TruckSim by Mechanical SImulation Corp.
+#
+# The product name: MSC_PRODUCT_ID carsim, vehsim, trucksim
+# The product type: MSC_PRODUCT_TYPE i_i, i_s__ss, s_ss ...
+# Version Number: MSC_PRODUCT_VERSION 5.25, 6.02, 3.04 ...
+#
+#############################################################################
+ifeq "$(MSC_PRODUCT_TYPE)" ""
+# Do nothing here
+else
+ include /usr/$(MSC_PRODUCT_ID)/$(MSC_PRODUCT_VERSION)/$(MSC_PRODUCT_ID).opt
+endif
+#
+#############################################################################
+# End CarSim/TruckSim/VehSim
+#############################################################################
+
+SHARED_SRC := $(subst \,/,$(SHARED_SRC))
+SHARED_SRC := $(wildcard $(SHARED_SRC))
+
+SHARED_SRC_DIR := $(subst \,/,$(SHARED_SRC_DIR))
+
+ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ # Top model for RTW
+ SRCS1 += $(MODEL).c model_main.c rt_sim.c $(RTWLOG) $(SOLVER) $(EXT_SRC) $(MODULES_SRCS) $(SHARED_SRC)
+ SRCS1 += $(INTERNAL_ADD_SOURCE_FILE) $(S_FUNC_SRCS) $(USER_SRCS)
+ SRCS = $(filter-out $(INTERNAL_IGN_SOURCE_FILE), $(SRCS1))
+
+else
+ # sub-model for RTW
+ SRCS1 += $(MODULES_SRCS)
+ SRCS1 += $(INTERNAL_ADD_SOURCE_FILE) $(S_FUNC_SRCS) $(USER_SRCS)
+ SRCS = $(filter-out $(INTERNAL_IGN_SOURCE_FILE), $(SRCS1))
+endif
+
+
+ifeq "$(UNAME)" "QNX" ##### nto
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include qnxnto.opt
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/qnxnto.opt
+ endif
+else
+ ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
+ MACHINE = $(shell uname -m)
+ ifeq "$(MACHINE)" "x86_64"
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include linux64.opt
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/linux64.opt
+ endif
+ else
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include linux32.opt
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/linux32.opt
+ endif
+ endif
+ else
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include win32.opt
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/OpNTtarget/win32.opt
+ endif
+ endif
+endif
+
+#------------------------------ Include Path -----------------------------
+
+MATLAB_INCLUDES = -I$(TARGET_MATLAB_ROOT)/simulink/include \
+-I$(TARGET_MATLAB_ROOT)/extern/include \
+-I$(TARGET_MATLAB_ROOT)/rtw/c/src \
+-I$(TARGET_MATLAB_ROOT)/rtw/c/src/matrixmath \
+-I$(TARGET_MATLAB_ROOT)/rtw/c/libsrc \
+
+ifeq "$(UNAME)" "QNX" ##### nto
+ MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/drive \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/mech \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/foundation \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/network_engine \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/ne_sli \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/dspblks/include
+else
+ ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
+ MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/drive \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/mech \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/foundation \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/network_engine \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/ne_sli \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/dspblks/include
+ else
+ MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/drive/c \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/mech/c \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/foundation/c \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/ne_sli/c \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/simscape/engine/sli/c \
+ -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/network_engine/c
+
+ ifeq ($(OP_MATLABR2011A),1)
+ MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/dsp/include
+ else
+ ifeq ($(OP_MATLABR2011B),1)
+ MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/dsp/include
+ else
+ MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/dspblks/include
+ endif
+ endif
+ endif
+endif
+
+
+RTLAB_INCLUDES = \
+ -I$(TARGET_RTLAB_ROOT)/common/include \
+ -I$(TARGET_RTLAB_ROOT)/common/include_target \
+ -I$(TARGET_RTLAB_ROOT)/RT-LAB/include
+
+SHARED_INCLUDES =
+ifneq ($(SHARED_SRC_DIR),)
+ SHARED_INCLUDES = -I$(SHARED_SRC_DIR)
+endif
+
+INCLUDES = -I. $(MATLAB_INCLUDES) $(RTLAB_INCLUDES) $(INTERNAL_INCLUDE_PATH) $(USER_INCS) $(MODELREF_INC_PATH) $(SHARED_INCLUDES)
+
+
+#------------------------ rtModel ----------------------------------------------
+#define USE_RTMODEL 1
+RTM_CC_OPTS = -DUSE_RTMODEL
+ifeq ($(OP_DISCRETE_SOLVER),1)
+RTM_CC_OPTS = -DUSE_RTMODEL -DDISCRETE_SOLVER
+endif
+
+#-------------------------------- C Flags --------------------------------
+# General User Options
+#OLDMATLABVERSION = 0
+
+ifeq ($(OP_MATLABR2006B),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2006B
+#OLDMATLABVERSION = 1
+endif
+ifeq ($(OP_MATLABR2007B),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2007B
+#OLDMATLABVERSION = 1
+endif
+ifeq ($(OP_MATLABR2008A),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2008A
+endif
+ifeq ($(OP_MATLABR2008B),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2008B
+endif
+ifeq ($(OP_MATLABR2009B),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2009B
+endif
+ifeq ($(OP_MATLABR2010A),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2010A
+endif
+ifeq ($(OP_MATLABR2010B),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2010B
+endif
+ifeq ($(OP_MATLABR2011A),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2011A
+endif
+ifeq ($(OP_MATLABR2011B),1)
+MATLABVERSION_CFLAGS = -DOP_MATLABR2011B
+endif
+OPTS =
+
+ANSI_OPTS =
+
+CC_OPTS = -c $(OPT_OPTS) $(OPTS) $(ANSI_OPTS) $(EXT_CC_OPTS) $(RTM_CC_OPTS)
+CC_OPTS77 = -c $(OPT_OPTS77) $(OPTS) $(ANSI_OPTS) $(EXT_CC_OPTS) $(RTM_CC_OPTS)
+
+CPP_REQ_DEFINES = -DMODEL=$(MODEL) -DRT=RT -DNUMST=$(NUMST) \
+ -DTID01EQ=$(TID01EQ) -DNCSTATES=$(NCSTATES) \
+ -DMULTITASKING=$(MULTITASKING) -D_SIMULINK -DRTLAB $(MATLABVERSION_CFLAGS)
+
+CFLAGS = $(CC_OPTS) $(CPP_REQ_DEFINES) $(TARGET_CFLAGS) $(INCLUDES)
+CFLAGS77 = $(CC_OPTS77) $(CPP_REQ_DEFINES) $(TARGET_CFLAGS) $(INCLUDES)
+
+#------------------------------- LD Flags --------------------------------
+LDFLAGS = $(LD_DEBUG_OPTS) $(LIBPATH) $(EXT_LD_OPTS) $(RTLAB_LDFLAGS)
+
+
+#--------------------------------- Rules ---------------------------------
+
+ifeq "$(UNAME)" "QNX" ##### nto
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include posix.rules
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/posix.rules
+ endif
+else
+ ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include posix.rules
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/posix.rules
+ endif
+ else
+ ifeq ($(MODELREF_TARGET_TYPE), NONE)
+ include win32.rules
+ else
+ include $(RELATIVE_PATH_TO_ANCHOR)/OpNTtarget/win32.rules
+ endif
+
+# Libraries:
+ifeq ($(USE_EXPAND_RTWLIB),1)
+
+else
+
+MODULES_rtwlib = rt_backsubcc_dbl.obj \
+ rt_backsubcc_sgl.obj \
+ rt_backsubrc_dbl.obj \
+ rt_backsubrc_sgl.obj \
+ rt_backsubrr_dbl.obj \
+ rt_backsubrr_sgl.obj \
+ rt_forwardsubcc_dbl.obj \
+ rt_forwardsubcc_sgl.obj \
+ rt_forwardsubcr_dbl.obj \
+ rt_forwardsubcr_sgl.obj \
+ rt_forwardsubrc_dbl.obj \
+ rt_forwardsubrc_sgl.obj \
+ rt_forwardsubrr_dbl.obj \
+ rt_forwardsubrr_sgl.obj \
+ rt_lu_cplx.obj \
+ rt_lu_cplx_sgl.obj \
+ rt_lu_real.obj \
+ rt_lu_real_sgl.obj \
+ rt_matdivcc_dbl.obj \
+ rt_matdivcc_sgl.obj \
+ rt_matdivcr_dbl.obj \
+ rt_matdivcr_sgl.obj \
+ rt_matdivrc_dbl.obj \
+ rt_matdivrc_sgl.obj \
+ rt_matdivrr_dbl.obj \
+ rt_matdivrr_sgl.obj \
+ rt_matmultandinccc_dbl.obj \
+ rt_matmultandinccc_sgl.obj \
+ rt_matmultandinccr_dbl.obj \
+ rt_matmultandinccr_sgl.obj \
+ rt_matmultandincrc_dbl.obj \
+ rt_matmultandincrc_sgl.obj \
+ rt_matmultandincrr_dbl.obj \
+ rt_matmultandincrr_sgl.obj \
+ rt_matmultcc_dbl.obj \
+ rt_matmultcc_sgl.obj \
+ rt_matmultcr_dbl.obj \
+ rt_matmultcr_sgl.obj \
+ rt_matmultrc_dbl.obj \
+ rt_matmultrc_sgl.obj \
+ rt_matmultrr_dbl.obj \
+ rt_matmultrr_sgl.obj
+endif
+
+$(RTWLIB) :
+ @echo ### Creating $@
+ifeq ($(USE_EXPAND_RTWLIB),1)
+ $(CC) $(CFLAGS) $(ALT_MATLAB_ROOT)\rtw\c\libsrc\*.c
+else
+ $(CC) $(CFLAGS) $(ALT_MATLAB_ROOT)\rtw\c\src\matrixmath\*.c
+endif
+ $(LIBCMD) /nologo /out:$@ $(MODULES_rtwlib)
+ @echo ### Created $@
+
+endif
+endif
+
+
+
+ifeq "$(UNAME)" "QNX" ##### nto
+MODELREF_LINK_LIBS_MAIN :
+ @for A in $(MODELREFS); do $(MAKE) -C $(SHARED_SRC_DIR)/../$$A -f $$A.mk; done
+else
+ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
+MODELREF_LINK_LIBS_MAIN :
+ @for A in $(MODELREFS); do $(MAKE) -C $(SHARED_SRC_DIR)/../$$A -f $$A.mk; done
+else
+MODELREF_LINK_LIBS_MAIN :
+ @FOR %A IN ($(MODELREFS)) DO $(MAKE) -C $(SHARED_SRC_DIR)/../%A -f %A.mk
+endif
+endif
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.nvcmd b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.nvcmd
new file mode 100644
index 000000000..1d04ec42e
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.nvcmd
@@ -0,0 +1 @@
+!/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test 5e-005 1 6946817 327785 1 2 137.226.160.105:57515 8404994
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123701.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123701.log
new file mode 100644
index 000000000..18ff36cb2
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123701.log
@@ -0,0 +1,46 @@
+**************************************************************************
+** Execution log file generated by RT-LAB on Wed May 28 12:37:01 2014
+**************************************************************************
+
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:37:02 2014
+
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:37:08 2014
+
+ Main priority set to 99
+ [1919869]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:38:44 2014
+
+ [1919869]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 12:39:03 2014
+
+AsyncIP: SendToIPPort: Finished
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123901.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123901.log
new file mode 100644
index 000000000..ecdf01e7d
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123901.log
@@ -0,0 +1,42 @@
+**************************************************************************
+** Execution log file generated by RT-LAB on Wed May 28 12:39:01 2014
+**************************************************************************
+
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:39:01 2014
+
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:39:30 2014
+
+ Main priority set to 99
+ [2861676]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 12:41:53 2014
+
+AsyncIP: SendToIPPort: Finished
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_124401.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_124401.log
new file mode 100644
index 000000000..ba18d2404
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_124401.log
@@ -0,0 +1,46 @@
+**************************************************************************
+** Execution log file generated by RT-LAB on Wed May 28 12:44:01 2014
+**************************************************************************
+
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:44:01 2014
+
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:44:06 2014
+
+ Main priority set to 99
+ [6943768]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:49:54 2014
+
+ [6943768]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 12:49:56 2014
+
+AsyncIP: SendToIPPort: Finished
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125001.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125001.log
new file mode 100644
index 000000000..55580b4ca
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125001.log
@@ -0,0 +1,42 @@
+**************************************************************************
+** Execution log file generated by RT-LAB on Wed May 28 12:50:01 2014
+**************************************************************************
+
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:50:01 2014
+
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:50:04 2014
+
+ Main priority set to 99
+ [2816109]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 12:52:24 2014
+
+AsyncIP: SendToIPPort: Finished
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125401.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125401.log
new file mode 100644
index 000000000..a9d1ba63b
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125401.log
@@ -0,0 +1,42 @@
+**************************************************************************
+** Execution log file generated by RT-LAB on Wed May 28 12:54:01 2014
+**************************************************************************
+
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:54:01 2014
+
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:54:24 2014
+
+ Main priority set to 99
+AsyncIP: SendToIPPort: Finished
+ [17891814]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 13:09:18 2014
+
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_data.c b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_data.c
new file mode 100644
index 000000000..08bb47290
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_data.c
@@ -0,0 +1,480 @@
+/*
+ * asyncip_sl_1_sm_ip_test_data.c
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+#include "asyncip_sl_1_sm_ip_test.h"
+#include "asyncip_sl_1_sm_ip_test_private.h"
+
+/* Block parameters (auto storage) */
+Parameters_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_P = {
+ 0.0, /* Expression: 0
+ * Referenced by: '<S1>/S-Function1'
+ */
+ 0.0, /* Expression: 0
+ * Referenced by: '<S1>/S-Function'
+ */
+ 1.0, /* Expression: 1
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ 2.0, /* Expression: 2
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ 1.0, /* Expression: 1
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/data ready 1 kHz'
+ */
+
+ /* Expression: [1 2 3 4]
+ * Referenced by: '<S2>/constants'
+ */
+ { 1.0, 2.0, 3.0, 4.0 },
+ 5.0, /* Expression: 5
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ 2000.0, /* Computed Parameter: PulseGenerator_Period
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ 600.0, /* Computed Parameter: PulseGenerator_Duty
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/Pulse Generator'
+ */
+
+ /* Computed Parameter: SFunction2_P1_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: ctl_id
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P2_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: send_id
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P3_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 3.0, /* Expression: mode
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P4_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: fp1
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P5_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 2.0, /* Expression: fp2
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P6_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 3.0, /* Expression: fp3
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P7_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 4.0, /* Expression: fp4
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P8_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 1.0 },
+ 5.0, /* Expression: fp5
+ * Referenced by: '<S5>/S-Function2'
+ */
+
+ /* Computed Parameter: SFunction2_P9_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction2_P9
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 49.0 },
+
+ /* Computed Parameter: SFunction2_P10_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction2_P10
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 50.0 },
+
+ /* Computed Parameter: SFunction2_P11_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction2_P11
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 51.0 },
+
+ /* Computed Parameter: SFunction2_P12_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction2_P12
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 52.0 },
+
+ /* Computed Parameter: SFunction2_P13_Size
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction2_P13
+ * Referenced by: '<S5>/S-Function2'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 53.0 },
+ 2.0, /* Expression: 2
+ * Referenced by: '<S2>/timeout'
+ */
+
+ /* Computed Parameter: SFunction1_P1_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: ctl_id
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P2_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: recv_id
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P3_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: fp1
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P4_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 2.0, /* Expression: fp2
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P5_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 3.0, /* Expression: fp3
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P6_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 4.0, /* Expression: fp4
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P7_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 1.0 },
+ 5.0, /* Expression: fp5
+ * Referenced by: '<S3>/S-Function1'
+ */
+
+ /* Computed Parameter: SFunction1_P8_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction1_P8
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 49.0 },
+
+ /* Computed Parameter: SFunction1_P9_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction1_P9
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 50.0 },
+
+ /* Computed Parameter: SFunction1_P10_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction1_P10
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 51.0 },
+
+ /* Computed Parameter: SFunction1_P11_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction1_P11
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 52.0 },
+
+ /* Computed Parameter: SFunction1_P12_Size
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: SFunction1_P12
+ * Referenced by: '<S3>/S-Function1'
+ */
+ { 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 53.0 },
+
+ /* Computed Parameter: SFunction_P1_Size
+ * Referenced by: '<S7>/S-Function'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: Acqu_group
+ * Referenced by: '<S7>/S-Function'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P1_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: ctl_id
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P2_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 1.0, /* Expression: proto
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P3_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 10200.0, /* Expression: ip_port_remote
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P4_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 10201.0, /* Expression: ip_port_local
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P5_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P6_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P7_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P8_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P9_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P10_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P11_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P12_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P13_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0, /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+
+ /* Computed Parameter: OpIPSocketCtrl1_P14_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 14.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P14
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 49.0, 51.0, 55.0, 46.0, 50.0, 50.0, 54.0, 46.0, 49.0, 54.0, 48.0, 46.0, 57.0,
+ 49.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P15_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P15
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 48.0, 46.0, 48.0, 46.0, 48.0, 46.0, 48.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P16_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P17_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P18_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P19_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P20_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P21_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P22_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P23_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P24_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P25_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 0.0, 0.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P26_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 7.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P26
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 65.0, 115.0, 121.0, 110.0, 99.0, 73.0, 80.0 },
+
+ /* Computed Parameter: OpIPSocketCtrl1_P27_Size
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+ { 1.0, 1.0 },
+ 0.0 /* Expression: 0
+ * Referenced by: '<S2>/OpIPSocketCtrl1'
+ */
+};
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_last_simulation.log b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_last_simulation.log
new file mode 100644
index 000000000..a9d1ba63b
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_last_simulation.log
@@ -0,0 +1,42 @@
+**************************************************************************
+** Execution log file generated by RT-LAB on Wed May 28 12:54:01 2014
+**************************************************************************
+
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:54:01 2014
+
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:54:24 2014
+
+ Main priority set to 99
+AsyncIP: SendToIPPort: Finished
+ [17891814]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 13:09:18 2014
+
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_private.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_private.h
new file mode 100644
index 000000000..d04b3d0e6
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_private.h
@@ -0,0 +1,38 @@
+/*
+ * asyncip_sl_1_sm_ip_test_private.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+#ifndef RTW_HEADER_asyncip_sl_1_sm_ip_test_private_h_
+#define RTW_HEADER_asyncip_sl_1_sm_ip_test_private_h_
+#include "rtwtypes.h"
+#ifndef __RTWTYPES_H__
+#error This file requires rtwtypes.h to be included
+#else
+#ifdef TMWTYPES_PREVIOUSLY_INCLUDED
+#error This file requires rtwtypes.h to be included before tmwtypes.h
+#else
+
+/* Check for inclusion of an incorrect version of rtwtypes.h */
+#ifndef RTWTYPES_ID_C08S16I32L32N32F1
+#error This code was generated with a different "rtwtypes.h" than the file included
+#endif /* RTWTYPES_ID_C08S16I32L32N32F1 */
+#endif /* TMWTYPES_PREVIOUSLY_INCLUDED */
+#endif /* __RTWTYPES_H__ */
+
+extern void sfun_send_async(SimStruct *rts);
+extern void sfun_recv_async(SimStruct *rts);
+extern void OP_SEND(SimStruct *rts);
+extern void sfun_gen_async_ctrl(SimStruct *rts);
+
+#endif /* RTW_HEADER_asyncip_sl_1_sm_ip_test_private_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_ref.rsp b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_ref.rsp
new file mode 100644
index 000000000..e69de29bb
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_types.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_types.h
new file mode 100644
index 000000000..4b183a588
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_types.h
@@ -0,0 +1,27 @@
+/*
+ * asyncip_sl_1_sm_ip_test_types.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+#ifndef RTW_HEADER_asyncip_sl_1_sm_ip_test_types_h_
+#define RTW_HEADER_asyncip_sl_1_sm_ip_test_types_h_
+#include "rtwtypes.h"
+
+/* Parameters (auto storage) */
+typedef struct Parameters_asyncip_sl_1_sm_ip_test_
+ Parameters_asyncip_sl_1_sm_ip_test;
+
+/* Forward declaration for rtModel */
+typedef struct RT_MODEL_asyncip_sl_1_sm_ip_test RT_MODEL_asyncip_sl_1_sm_ip_test;
+
+#endif /* RTW_HEADER_asyncip_sl_1_sm_ip_test_types_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/buildInfo.mat b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/buildInfo.mat
new file mode 100644
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/compilation_target_report.xml b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/compilation_target_report.xml
new file mode 100644
index 000000000..535331506
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/compilation_target_report.xml
@@ -0,0 +1,648 @@
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+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 2">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 2
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 3">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 3
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 4">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 4
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 5">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 5
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 6">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 6
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 7">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 7
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 8">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 8
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 9">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 9
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ <item name="Network and internet">
+ <item name="Network">
+ <item name="General information">
+ <property name="Computer name">
+ <value>
+ localhost.localdomain
+ </value>
+ </property>
+ <property name="Local IP">
+ <value>
+ 137.226.160.69
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ <item name="Software system">
+ <item name="Installed programs">
+ <item name="ARTEMIS"/>
+ <item name="Gcc">
+ <property name="Current version">
+ <value>
+ 4.1.2
+ </value>
+ </property>
+ </item>
+ <item name="Python">
+ <property name="Current version">
+ <value>
+ 2.4.3
+ </value>
+ </property>
+ </item>
+ <item name="RT-EVENTS"/>
+ <item name="RT-LAB">
+ <property name="Current version">
+ <value>
+ v10.5.9.356
+ </value>
+ </property>
+ </item>
+ </item>
+ <item name="Operating system">
+ <property name="Release">
+ <value>
+ 2.6.29.6-opalrt-5
+ </value>
+ </property>
+ <property name="Type">
+ <value>
+ linux2
+ </value>
+ </property>
+ <property name="Version">
+ <value>
+ #6 SMP PREEMPT Tue Aug 3 10:13:38 EDT 2010
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+</item>
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/defines.txt b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/defines.txt
new file mode 100644
index 000000000..61fb20325
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/defines.txt
@@ -0,0 +1,8 @@
+MODEL=asyncip_sl_1_sm_ip_test
+NUMST=2
+NCSTATES=0
+HAVESTDIO
+RT
+USE_RTMODEL
+INTEGER_CODE=0
+MT=0
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/modelsources.txt b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/modelsources.txt
new file mode 100644
index 000000000..b7858a1ba
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/modelsources.txt
@@ -0,0 +1 @@
+ asyncip_sl_1_sm_ip_test.c rt_matrx.c rt_printf.c rt_logging.c
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/opasyncip_sl_sm_ip_test_0.snap b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/opasyncip_sl_sm_ip_test_0.snap
new file mode 100644
index 0000000000000000000000000000000000000000..8dfc30599b0c685821dfce3fbb6f2ca03f8b693f
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literal 0
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.c b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.c
new file mode 100644
index 000000000..2ef73cf10
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.c
@@ -0,0 +1,140 @@
+/*
+ * rtGetInf.c
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+/*
+ * Abstract:
+ * Function to intialize non-finite, Inf
+ */
+
+#include "rtGetInf.h"
+#define NumBitsPerChar 8U
+
+/*
+ * Initialize rtInf needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real_T rtGetInf(void)
+{
+ size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+ real_T inf = 0.0;
+ if (bitsPerReal == 32U) {
+ inf = rtGetInfF();
+ } else {
+ uint16_T one = 1U;
+ enum {
+ LittleEndian,
+ BigEndian
+ } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
+ switch (machByteOrder) {
+ case LittleEndian:
+ {
+ union {
+ LittleEndianIEEEDouble bitVal;
+ real_T fltVal;
+ } tmpVal;
+
+ tmpVal.bitVal.words.wordH = 0x7FF00000U;
+ tmpVal.bitVal.words.wordL = 0x00000000U;
+ inf = tmpVal.fltVal;
+ break;
+ }
+
+ case BigEndian:
+ {
+ union {
+ BigEndianIEEEDouble bitVal;
+ real_T fltVal;
+ } tmpVal;
+
+ tmpVal.bitVal.words.wordH = 0x7FF00000U;
+ tmpVal.bitVal.words.wordL = 0x00000000U;
+ inf = tmpVal.fltVal;
+ break;
+ }
+ }
+ }
+
+ return inf;
+}
+
+/*
+ * Initialize rtInfF needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real32_T rtGetInfF(void)
+{
+ IEEESingle infF;
+ infF.wordL.wordLuint = 0x7F800000U;
+ return infF.wordL.wordLreal;
+}
+
+/*
+ * Initialize rtMinusInf needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real_T rtGetMinusInf(void)
+{
+ size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+ real_T minf = 0.0;
+ if (bitsPerReal == 32U) {
+ minf = rtGetMinusInfF();
+ } else {
+ uint16_T one = 1U;
+ enum {
+ LittleEndian,
+ BigEndian
+ } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
+ switch (machByteOrder) {
+ case LittleEndian:
+ {
+ union {
+ LittleEndianIEEEDouble bitVal;
+ real_T fltVal;
+ } tmpVal;
+
+ tmpVal.bitVal.words.wordH = 0xFFF00000U;
+ tmpVal.bitVal.words.wordL = 0x00000000U;
+ minf = tmpVal.fltVal;
+ break;
+ }
+
+ case BigEndian:
+ {
+ union {
+ BigEndianIEEEDouble bitVal;
+ real_T fltVal;
+ } tmpVal;
+
+ tmpVal.bitVal.words.wordH = 0xFFF00000U;
+ tmpVal.bitVal.words.wordL = 0x00000000U;
+ minf = tmpVal.fltVal;
+ break;
+ }
+ }
+ }
+
+ return minf;
+}
+
+/*
+ * Initialize rtMinusInfF needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real32_T rtGetMinusInfF(void)
+{
+ IEEESingle minfF;
+ minfF.wordL.wordLuint = 0xFF800000U;
+ return minfF.wordL.wordLreal;
+}
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.h
new file mode 100644
index 000000000..1e764816b
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.h
@@ -0,0 +1,28 @@
+/*
+ * rtGetInf.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_rtGetInf_h_
+#define RTW_HEADER_rtGetInf_h_
+#include <stddef.h>
+#include "rtwtypes.h"
+#include "rt_nonfinite.h"
+
+extern real_T rtGetInf(void);
+extern real32_T rtGetInfF(void);
+extern real_T rtGetMinusInf(void);
+extern real32_T rtGetMinusInfF(void);
+
+#endif /* RTW_HEADER_rtGetInf_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.c b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.c
new file mode 100644
index 000000000..45efdc970
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.c
@@ -0,0 +1,100 @@
+/*
+ * rtGetNaN.c
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+/*
+ * Abstract:
+ * Function to intialize non-finite, NaN
+ */
+
+#include "rtGetNaN.h"
+#define NumBitsPerChar 8U
+
+/*
+ * Initialize rtNaN needed by the generated code.
+ * NaN is initialized as non-signaling. Assumes IEEE.
+ */
+real_T rtGetNaN(void)
+{
+ size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+ real_T nan = 0.0;
+ if (bitsPerReal == 32U) {
+ nan = rtGetNaNF();
+ } else {
+ uint16_T one = 1U;
+ enum {
+ LittleEndian,
+ BigEndian
+ } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
+ switch (machByteOrder) {
+ case LittleEndian:
+ {
+ union {
+ LittleEndianIEEEDouble bitVal;
+ real_T fltVal;
+ } tmpVal;
+
+ tmpVal.bitVal.words.wordH = 0xFFF80000U;
+ tmpVal.bitVal.words.wordL = 0x00000000U;
+ nan = tmpVal.fltVal;
+ break;
+ }
+
+ case BigEndian:
+ {
+ union {
+ BigEndianIEEEDouble bitVal;
+ real_T fltVal;
+ } tmpVal;
+
+ tmpVal.bitVal.words.wordH = 0x7FFFFFFFU;
+ tmpVal.bitVal.words.wordL = 0xFFFFFFFFU;
+ nan = tmpVal.fltVal;
+ break;
+ }
+ }
+ }
+
+ return nan;
+}
+
+/*
+ * Initialize rtNaNF needed by the generated code.
+ * NaN is initialized as non-signaling. Assumes IEEE.
+ */
+real32_T rtGetNaNF(void)
+{
+ IEEESingle nanF = { { 0 } };
+
+ uint16_T one = 1U;
+ enum {
+ LittleEndian,
+ BigEndian
+ } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
+ switch (machByteOrder) {
+ case LittleEndian:
+ {
+ nanF.wordL.wordLuint = 0xFFC00000U;
+ break;
+ }
+
+ case BigEndian:
+ {
+ nanF.wordL.wordLuint = 0x7FFFFFFFU;
+ break;
+ }
+ }
+
+ return nanF.wordL.wordLreal;
+}
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.h
new file mode 100644
index 000000000..1785c524f
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.h
@@ -0,0 +1,26 @@
+/*
+ * rtGetNaN.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_rtGetNaN_h_
+#define RTW_HEADER_rtGetNaN_h_
+#include <stddef.h>
+#include "rtwtypes.h"
+#include "rt_nonfinite.h"
+
+extern real_T rtGetNaN(void);
+extern real32_T rtGetNaNF(void);
+
+#endif /* RTW_HEADER_rtGetNaN_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_defines.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_defines.h
new file mode 100644
index 000000000..3512fc126
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_defines.h
@@ -0,0 +1,49 @@
+/*
+ * rt_defines.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_rt_defines_h_
+#define RTW_HEADER_rt_defines_h_
+
+/*===========*
+ * Constants *
+ *===========*/
+#define RT_PI 3.14159265358979323846
+#define RT_PIF 3.1415927F
+#define RT_LN_10 2.30258509299404568402
+#define RT_LN_10F 2.3025851F
+#define RT_LOG10E 0.43429448190325182765
+#define RT_LOG10EF 0.43429449F
+#define RT_E 2.7182818284590452354
+#define RT_EF 2.7182817F
+
+/*
+ * UNUSED_PARAMETER(x)
+ * Used to specify that a function parameter (argument) is required but not
+ * accessed by the function body.
+ */
+#ifndef UNUSED_PARAMETER
+# if defined(__LCC__)
+# define UNUSED_PARAMETER(x) /* do nothing */
+# else
+
+/*
+ * This is the semi-ANSI standard way of indicating that an
+ * unused function parameter is required.
+ */
+# define UNUSED_PARAMETER(x) (void) (x)
+# endif
+#endif
+#endif /* RTW_HEADER_rt_defines_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.c b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.c
new file mode 100644
index 000000000..253e00aa7
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.c
@@ -0,0 +1,70 @@
+/*
+ * rt_nonfinite.c
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+/*
+ * Abstract:
+ * Function to intialize non-finites,
+ * (Inf, NaN and -Inf).
+ */
+
+#include "rt_nonfinite.h"
+#include "rtGetNaN.h"
+#include "rtGetInf.h"
+
+real_T rtInf;
+real_T rtMinusInf;
+real_T rtNaN;
+real32_T rtInfF;
+real32_T rtMinusInfF;
+real32_T rtNaNF;
+
+/*
+ * Initialize the rtInf, rtMinusInf, and rtNaN needed by the
+ * generated code. NaN is initialized as non-signaling. Assumes IEEE.
+ */
+void rt_InitInfAndNaN(size_t realSize)
+{
+ (void) (realSize);
+ rtNaN = rtGetNaN();
+ rtNaNF = rtGetNaNF();
+ rtInf = rtGetInf();
+ rtInfF = rtGetInfF();
+ rtMinusInf = rtGetMinusInf();
+ rtMinusInfF = rtGetMinusInfF();
+}
+
+/* Test if value is infinite */
+boolean_T rtIsInf(real_T value)
+{
+ return (boolean_T)((value==rtInf || value==rtMinusInf) ? 1U : 0U);
+}
+
+/* Test if single-precision value is infinite */
+boolean_T rtIsInfF(real32_T value)
+{
+ return (boolean_T)(((value)==rtInfF || (value)==rtMinusInfF) ? 1U : 0U);
+}
+
+/* Test if value is not a number */
+boolean_T rtIsNaN(real_T value)
+{
+ return (boolean_T)((value!=value) ? 1U : 0U);
+}
+
+/* Test if single-precision value is not a number */
+boolean_T rtIsNaNF(real32_T value)
+{
+ return (boolean_T)(((value!=value) ? 1U : 0U));
+}
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.h
new file mode 100644
index 000000000..74197c3ef
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.h
@@ -0,0 +1,54 @@
+/*
+ * rt_nonfinite.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_rt_nonfinite_h_
+#define RTW_HEADER_rt_nonfinite_h_
+#include <stddef.h>
+#include "rtwtypes.h"
+
+extern real_T rtInf;
+extern real_T rtMinusInf;
+extern real_T rtNaN;
+extern real32_T rtInfF;
+extern real32_T rtMinusInfF;
+extern real32_T rtNaNF;
+extern void rt_InitInfAndNaN(size_t realSize);
+extern boolean_T rtIsInf(real_T value);
+extern boolean_T rtIsInfF(real32_T value);
+extern boolean_T rtIsNaN(real_T value);
+extern boolean_T rtIsNaNF(real32_T value);
+typedef struct {
+ struct {
+ uint32_T wordH;
+ uint32_T wordL;
+ } words;
+} BigEndianIEEEDouble;
+
+typedef struct {
+ struct {
+ uint32_T wordL;
+ uint32_T wordH;
+ } words;
+} LittleEndianIEEEDouble;
+
+typedef struct {
+ union {
+ real32_T wordLreal;
+ uint32_T wordLuint;
+ } wordL;
+} IEEESingle;
+
+#endif /* RTW_HEADER_rt_nonfinite_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtmodel.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtmodel.h
new file mode 100644
index 000000000..367506f3b
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtmodel.h
@@ -0,0 +1,23 @@
+/*
+ * rtmodel.h:
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+#ifndef RTW_HEADER_rtmodel_h_
+#define RTW_HEADER_rtmodel_h_
+
+/*
+ * Includes the appropriate headers when we are using rtModel
+ */
+#include "asyncip_sl_1_sm_ip_test.h"
+#endif /* RTW_HEADER_rtmodel_h_ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtw_proj.tmw b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtw_proj.tmw
new file mode 100644
index 000000000..236728b32
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtw_proj.tmw
@@ -0,0 +1,4 @@
+Simulink Coder project for asyncip_sl_1_sm_ip_test using C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf. MATLAB root = C:\Program Files (x86)\MATLAB\R2011b. SimStruct date: 11-Jul-2011 20:59:52
+This file is generated by Simulink Coder for use by the make utility
+to determine when to rebuild objects when the name of the current Simulink Coder project changes.
+The rtwinfomat located at: ..\slprj\rtlab_rtmodel\asyncip_sl_1_sm_ip_test\tmwinternal\binfo.mat
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypes.h b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypes.h
new file mode 100644
index 000000000..c5daca298
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypes.h
@@ -0,0 +1,1191 @@
+/*
+ * rtwtypes.h
+ *
+ * Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
+ *
+ * Model version : 1.426
+ * Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
+ * C source code generated on : Wed May 28 12:53:42 2014
+ *
+ * Target selection: rtlab_rtmodel.tlc
+ * Note: GRT includes extra infrastructure and instrumentation for prototyping
+ * Embedded hardware selection: 32-bit Generic
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef __RTWTYPES_H__
+#define __RTWTYPES_H__
+#include "tmwtypes.h"
+
+/* This ID is used to detect inclusion of an incompatible rtwtypes.h */
+#define RTWTYPES_ID_C08S16I32L32N32F1
+#include "simstruc_types.h"
+#ifndef POINTER_T
+# define POINTER_T
+
+typedef void * pointer_T;
+
+#endif
+
+#ifndef TRUE
+# define TRUE (1U)
+#endif
+
+#ifndef FALSE
+# define FALSE (0U)
+#endif
+
+#ifndef MAT_FILE
+# define MAT_FILE 1
+#endif
+
+/*
+ * Definitions supporting external data access
+ */
+typedef int32_T chunk_T;
+typedef uint32_T uchunk_T;
+
+/*
+ * MultiWord supporting definitions
+ */
+typedef long int long_T;
+
+/*
+ * MultiWord types
+ */
+typedef struct {
+ uint32_T chunks[2];
+} int64m_T;
+
+typedef struct {
+ int64m_T re;
+ int64m_T im;
+} cint64m_T;
+
+typedef struct {
+ uint32_T chunks[2];
+} uint64m_T;
+
+typedef struct {
+ uint64m_T re;
+ uint64m_T im;
+} cuint64m_T;
+
+typedef struct {
+ uint32_T chunks[3];
+} int96m_T;
+
+typedef struct {
+ int96m_T re;
+ int96m_T im;
+} cint96m_T;
+
+typedef struct {
+ uint32_T chunks[3];
+} uint96m_T;
+
+typedef struct {
+ uint96m_T re;
+ uint96m_T im;
+} cuint96m_T;
+
+typedef struct {
+ uint32_T chunks[4];
+} int128m_T;
+
+typedef struct {
+ int128m_T re;
+ int128m_T im;
+} cint128m_T;
+
+typedef struct {
+ uint32_T chunks[4];
+} uint128m_T;
+
+typedef struct {
+ uint128m_T re;
+ uint128m_T im;
+} cuint128m_T;
+
+typedef struct {
+ uint32_T chunks[5];
+} int160m_T;
+
+typedef struct {
+ int160m_T re;
+ int160m_T im;
+} cint160m_T;
+
+typedef struct {
+ uint32_T chunks[5];
+} uint160m_T;
+
+typedef struct {
+ uint160m_T re;
+ uint160m_T im;
+} cuint160m_T;
+
+typedef struct {
+ uint32_T chunks[6];
+} int192m_T;
+
+typedef struct {
+ int192m_T re;
+ int192m_T im;
+} cint192m_T;
+
+typedef struct {
+ uint32_T chunks[6];
+} uint192m_T;
+
+typedef struct {
+ uint192m_T re;
+ uint192m_T im;
+} cuint192m_T;
+
+typedef struct {
+ uint32_T chunks[7];
+} int224m_T;
+
+typedef struct {
+ int224m_T re;
+ int224m_T im;
+} cint224m_T;
+
+typedef struct {
+ uint32_T chunks[7];
+} uint224m_T;
+
+typedef struct {
+ uint224m_T re;
+ uint224m_T im;
+} cuint224m_T;
+
+typedef struct {
+ uint32_T chunks[8];
+} int256m_T;
+
+typedef struct {
+ int256m_T re;
+ int256m_T im;
+} cint256m_T;
+
+typedef struct {
+ uint32_T chunks[8];
+} uint256m_T;
+
+typedef struct {
+ uint256m_T re;
+ uint256m_T im;
+} cuint256m_T;
+
+typedef struct {
+ uint32_T chunks[9];
+} int288m_T;
+
+typedef struct {
+ int288m_T re;
+ int288m_T im;
+} cint288m_T;
+
+typedef struct {
+ uint32_T chunks[9];
+} uint288m_T;
+
+typedef struct {
+ uint288m_T re;
+ uint288m_T im;
+} cuint288m_T;
+
+typedef struct {
+ uint32_T chunks[10];
+} int320m_T;
+
+typedef struct {
+ int320m_T re;
+ int320m_T im;
+} cint320m_T;
+
+typedef struct {
+ uint32_T chunks[10];
+} uint320m_T;
+
+typedef struct {
+ uint320m_T re;
+ uint320m_T im;
+} cuint320m_T;
+
+typedef struct {
+ uint32_T chunks[11];
+} int352m_T;
+
+typedef struct {
+ int352m_T re;
+ int352m_T im;
+} cint352m_T;
+
+typedef struct {
+ uint32_T chunks[11];
+} uint352m_T;
+
+typedef struct {
+ uint352m_T re;
+ uint352m_T im;
+} cuint352m_T;
+
+typedef struct {
+ uint32_T chunks[12];
+} int384m_T;
+
+typedef struct {
+ int384m_T re;
+ int384m_T im;
+} cint384m_T;
+
+typedef struct {
+ uint32_T chunks[12];
+} uint384m_T;
+
+typedef struct {
+ uint384m_T re;
+ uint384m_T im;
+} cuint384m_T;
+
+typedef struct {
+ uint32_T chunks[13];
+} int416m_T;
+
+typedef struct {
+ int416m_T re;
+ int416m_T im;
+} cint416m_T;
+
+typedef struct {
+ uint32_T chunks[13];
+} uint416m_T;
+
+typedef struct {
+ uint416m_T re;
+ uint416m_T im;
+} cuint416m_T;
+
+typedef struct {
+ uint32_T chunks[14];
+} int448m_T;
+
+typedef struct {
+ int448m_T re;
+ int448m_T im;
+} cint448m_T;
+
+typedef struct {
+ uint32_T chunks[14];
+} uint448m_T;
+
+typedef struct {
+ uint448m_T re;
+ uint448m_T im;
+} cuint448m_T;
+
+typedef struct {
+ uint32_T chunks[15];
+} int480m_T;
+
+typedef struct {
+ int480m_T re;
+ int480m_T im;
+} cint480m_T;
+
+typedef struct {
+ uint32_T chunks[15];
+} uint480m_T;
+
+typedef struct {
+ uint480m_T re;
+ uint480m_T im;
+} cuint480m_T;
+
+typedef struct {
+ uint32_T chunks[16];
+} int512m_T;
+
+typedef struct {
+ int512m_T re;
+ int512m_T im;
+} cint512m_T;
+
+typedef struct {
+ uint32_T chunks[16];
+} uint512m_T;
+
+typedef struct {
+ uint512m_T re;
+ uint512m_T im;
+} cuint512m_T;
+
+typedef struct {
+ uint32_T chunks[17];
+} int544m_T;
+
+typedef struct {
+ int544m_T re;
+ int544m_T im;
+} cint544m_T;
+
+typedef struct {
+ uint32_T chunks[17];
+} uint544m_T;
+
+typedef struct {
+ uint544m_T re;
+ uint544m_T im;
+} cuint544m_T;
+
+typedef struct {
+ uint32_T chunks[18];
+} int576m_T;
+
+typedef struct {
+ int576m_T re;
+ int576m_T im;
+} cint576m_T;
+
+typedef struct {
+ uint32_T chunks[18];
+} uint576m_T;
+
+typedef struct {
+ uint576m_T re;
+ uint576m_T im;
+} cuint576m_T;
+
+typedef struct {
+ uint32_T chunks[19];
+} int608m_T;
+
+typedef struct {
+ int608m_T re;
+ int608m_T im;
+} cint608m_T;
+
+typedef struct {
+ uint32_T chunks[19];
+} uint608m_T;
+
+typedef struct {
+ uint608m_T re;
+ uint608m_T im;
+} cuint608m_T;
+
+typedef struct {
+ uint32_T chunks[20];
+} int640m_T;
+
+typedef struct {
+ int640m_T re;
+ int640m_T im;
+} cint640m_T;
+
+typedef struct {
+ uint32_T chunks[20];
+} uint640m_T;
+
+typedef struct {
+ uint640m_T re;
+ uint640m_T im;
+} cuint640m_T;
+
+typedef struct {
+ uint32_T chunks[21];
+} int672m_T;
+
+typedef struct {
+ int672m_T re;
+ int672m_T im;
+} cint672m_T;
+
+typedef struct {
+ uint32_T chunks[21];
+} uint672m_T;
+
+typedef struct {
+ uint672m_T re;
+ uint672m_T im;
+} cuint672m_T;
+
+typedef struct {
+ uint32_T chunks[22];
+} int704m_T;
+
+typedef struct {
+ int704m_T re;
+ int704m_T im;
+} cint704m_T;
+
+typedef struct {
+ uint32_T chunks[22];
+} uint704m_T;
+
+typedef struct {
+ uint704m_T re;
+ uint704m_T im;
+} cuint704m_T;
+
+typedef struct {
+ uint32_T chunks[23];
+} int736m_T;
+
+typedef struct {
+ int736m_T re;
+ int736m_T im;
+} cint736m_T;
+
+typedef struct {
+ uint32_T chunks[23];
+} uint736m_T;
+
+typedef struct {
+ uint736m_T re;
+ uint736m_T im;
+} cuint736m_T;
+
+typedef struct {
+ uint32_T chunks[24];
+} int768m_T;
+
+typedef struct {
+ int768m_T re;
+ int768m_T im;
+} cint768m_T;
+
+typedef struct {
+ uint32_T chunks[24];
+} uint768m_T;
+
+typedef struct {
+ uint768m_T re;
+ uint768m_T im;
+} cuint768m_T;
+
+typedef struct {
+ uint32_T chunks[25];
+} int800m_T;
+
+typedef struct {
+ int800m_T re;
+ int800m_T im;
+} cint800m_T;
+
+typedef struct {
+ uint32_T chunks[25];
+} uint800m_T;
+
+typedef struct {
+ uint800m_T re;
+ uint800m_T im;
+} cuint800m_T;
+
+typedef struct {
+ uint32_T chunks[26];
+} int832m_T;
+
+typedef struct {
+ int832m_T re;
+ int832m_T im;
+} cint832m_T;
+
+typedef struct {
+ uint32_T chunks[26];
+} uint832m_T;
+
+typedef struct {
+ uint832m_T re;
+ uint832m_T im;
+} cuint832m_T;
+
+typedef struct {
+ uint32_T chunks[27];
+} int864m_T;
+
+typedef struct {
+ int864m_T re;
+ int864m_T im;
+} cint864m_T;
+
+typedef struct {
+ uint32_T chunks[27];
+} uint864m_T;
+
+typedef struct {
+ uint864m_T re;
+ uint864m_T im;
+} cuint864m_T;
+
+typedef struct {
+ uint32_T chunks[28];
+} int896m_T;
+
+typedef struct {
+ int896m_T re;
+ int896m_T im;
+} cint896m_T;
+
+typedef struct {
+ uint32_T chunks[28];
+} uint896m_T;
+
+typedef struct {
+ uint896m_T re;
+ uint896m_T im;
+} cuint896m_T;
+
+typedef struct {
+ uint32_T chunks[29];
+} int928m_T;
+
+typedef struct {
+ int928m_T re;
+ int928m_T im;
+} cint928m_T;
+
+typedef struct {
+ uint32_T chunks[29];
+} uint928m_T;
+
+typedef struct {
+ uint928m_T re;
+ uint928m_T im;
+} cuint928m_T;
+
+typedef struct {
+ uint32_T chunks[30];
+} int960m_T;
+
+typedef struct {
+ int960m_T re;
+ int960m_T im;
+} cint960m_T;
+
+typedef struct {
+ uint32_T chunks[30];
+} uint960m_T;
+
+typedef struct {
+ uint960m_T re;
+ uint960m_T im;
+} cuint960m_T;
+
+typedef struct {
+ uint32_T chunks[31];
+} int992m_T;
+
+typedef struct {
+ int992m_T re;
+ int992m_T im;
+} cint992m_T;
+
+typedef struct {
+ uint32_T chunks[31];
+} uint992m_T;
+
+typedef struct {
+ uint992m_T re;
+ uint992m_T im;
+} cuint992m_T;
+
+typedef struct {
+ uint32_T chunks[32];
+} int1024m_T;
+
+typedef struct {
+ int1024m_T re;
+ int1024m_T im;
+} cint1024m_T;
+
+typedef struct {
+ uint32_T chunks[32];
+} uint1024m_T;
+
+typedef struct {
+ uint1024m_T re;
+ uint1024m_T im;
+} cuint1024m_T;
+
+typedef struct {
+ uint32_T chunks[33];
+} int1056m_T;
+
+typedef struct {
+ int1056m_T re;
+ int1056m_T im;
+} cint1056m_T;
+
+typedef struct {
+ uint32_T chunks[33];
+} uint1056m_T;
+
+typedef struct {
+ uint1056m_T re;
+ uint1056m_T im;
+} cuint1056m_T;
+
+typedef struct {
+ uint32_T chunks[34];
+} int1088m_T;
+
+typedef struct {
+ int1088m_T re;
+ int1088m_T im;
+} cint1088m_T;
+
+typedef struct {
+ uint32_T chunks[34];
+} uint1088m_T;
+
+typedef struct {
+ uint1088m_T re;
+ uint1088m_T im;
+} cuint1088m_T;
+
+typedef struct {
+ uint32_T chunks[35];
+} int1120m_T;
+
+typedef struct {
+ int1120m_T re;
+ int1120m_T im;
+} cint1120m_T;
+
+typedef struct {
+ uint32_T chunks[35];
+} uint1120m_T;
+
+typedef struct {
+ uint1120m_T re;
+ uint1120m_T im;
+} cuint1120m_T;
+
+typedef struct {
+ uint32_T chunks[36];
+} int1152m_T;
+
+typedef struct {
+ int1152m_T re;
+ int1152m_T im;
+} cint1152m_T;
+
+typedef struct {
+ uint32_T chunks[36];
+} uint1152m_T;
+
+typedef struct {
+ uint1152m_T re;
+ uint1152m_T im;
+} cuint1152m_T;
+
+typedef struct {
+ uint32_T chunks[37];
+} int1184m_T;
+
+typedef struct {
+ int1184m_T re;
+ int1184m_T im;
+} cint1184m_T;
+
+typedef struct {
+ uint32_T chunks[37];
+} uint1184m_T;
+
+typedef struct {
+ uint1184m_T re;
+ uint1184m_T im;
+} cuint1184m_T;
+
+typedef struct {
+ uint32_T chunks[38];
+} int1216m_T;
+
+typedef struct {
+ int1216m_T re;
+ int1216m_T im;
+} cint1216m_T;
+
+typedef struct {
+ uint32_T chunks[38];
+} uint1216m_T;
+
+typedef struct {
+ uint1216m_T re;
+ uint1216m_T im;
+} cuint1216m_T;
+
+typedef struct {
+ uint32_T chunks[39];
+} int1248m_T;
+
+typedef struct {
+ int1248m_T re;
+ int1248m_T im;
+} cint1248m_T;
+
+typedef struct {
+ uint32_T chunks[39];
+} uint1248m_T;
+
+typedef struct {
+ uint1248m_T re;
+ uint1248m_T im;
+} cuint1248m_T;
+
+typedef struct {
+ uint32_T chunks[40];
+} int1280m_T;
+
+typedef struct {
+ int1280m_T re;
+ int1280m_T im;
+} cint1280m_T;
+
+typedef struct {
+ uint32_T chunks[40];
+} uint1280m_T;
+
+typedef struct {
+ uint1280m_T re;
+ uint1280m_T im;
+} cuint1280m_T;
+
+typedef struct {
+ uint32_T chunks[41];
+} int1312m_T;
+
+typedef struct {
+ int1312m_T re;
+ int1312m_T im;
+} cint1312m_T;
+
+typedef struct {
+ uint32_T chunks[41];
+} uint1312m_T;
+
+typedef struct {
+ uint1312m_T re;
+ uint1312m_T im;
+} cuint1312m_T;
+
+typedef struct {
+ uint32_T chunks[42];
+} int1344m_T;
+
+typedef struct {
+ int1344m_T re;
+ int1344m_T im;
+} cint1344m_T;
+
+typedef struct {
+ uint32_T chunks[42];
+} uint1344m_T;
+
+typedef struct {
+ uint1344m_T re;
+ uint1344m_T im;
+} cuint1344m_T;
+
+typedef struct {
+ uint32_T chunks[43];
+} int1376m_T;
+
+typedef struct {
+ int1376m_T re;
+ int1376m_T im;
+} cint1376m_T;
+
+typedef struct {
+ uint32_T chunks[43];
+} uint1376m_T;
+
+typedef struct {
+ uint1376m_T re;
+ uint1376m_T im;
+} cuint1376m_T;
+
+typedef struct {
+ uint32_T chunks[44];
+} int1408m_T;
+
+typedef struct {
+ int1408m_T re;
+ int1408m_T im;
+} cint1408m_T;
+
+typedef struct {
+ uint32_T chunks[44];
+} uint1408m_T;
+
+typedef struct {
+ uint1408m_T re;
+ uint1408m_T im;
+} cuint1408m_T;
+
+typedef struct {
+ uint32_T chunks[45];
+} int1440m_T;
+
+typedef struct {
+ int1440m_T re;
+ int1440m_T im;
+} cint1440m_T;
+
+typedef struct {
+ uint32_T chunks[45];
+} uint1440m_T;
+
+typedef struct {
+ uint1440m_T re;
+ uint1440m_T im;
+} cuint1440m_T;
+
+typedef struct {
+ uint32_T chunks[46];
+} int1472m_T;
+
+typedef struct {
+ int1472m_T re;
+ int1472m_T im;
+} cint1472m_T;
+
+typedef struct {
+ uint32_T chunks[46];
+} uint1472m_T;
+
+typedef struct {
+ uint1472m_T re;
+ uint1472m_T im;
+} cuint1472m_T;
+
+typedef struct {
+ uint32_T chunks[47];
+} int1504m_T;
+
+typedef struct {
+ int1504m_T re;
+ int1504m_T im;
+} cint1504m_T;
+
+typedef struct {
+ uint32_T chunks[47];
+} uint1504m_T;
+
+typedef struct {
+ uint1504m_T re;
+ uint1504m_T im;
+} cuint1504m_T;
+
+typedef struct {
+ uint32_T chunks[48];
+} int1536m_T;
+
+typedef struct {
+ int1536m_T re;
+ int1536m_T im;
+} cint1536m_T;
+
+typedef struct {
+ uint32_T chunks[48];
+} uint1536m_T;
+
+typedef struct {
+ uint1536m_T re;
+ uint1536m_T im;
+} cuint1536m_T;
+
+typedef struct {
+ uint32_T chunks[49];
+} int1568m_T;
+
+typedef struct {
+ int1568m_T re;
+ int1568m_T im;
+} cint1568m_T;
+
+typedef struct {
+ uint32_T chunks[49];
+} uint1568m_T;
+
+typedef struct {
+ uint1568m_T re;
+ uint1568m_T im;
+} cuint1568m_T;
+
+typedef struct {
+ uint32_T chunks[50];
+} int1600m_T;
+
+typedef struct {
+ int1600m_T re;
+ int1600m_T im;
+} cint1600m_T;
+
+typedef struct {
+ uint32_T chunks[50];
+} uint1600m_T;
+
+typedef struct {
+ uint1600m_T re;
+ uint1600m_T im;
+} cuint1600m_T;
+
+typedef struct {
+ uint32_T chunks[51];
+} int1632m_T;
+
+typedef struct {
+ int1632m_T re;
+ int1632m_T im;
+} cint1632m_T;
+
+typedef struct {
+ uint32_T chunks[51];
+} uint1632m_T;
+
+typedef struct {
+ uint1632m_T re;
+ uint1632m_T im;
+} cuint1632m_T;
+
+typedef struct {
+ uint32_T chunks[52];
+} int1664m_T;
+
+typedef struct {
+ int1664m_T re;
+ int1664m_T im;
+} cint1664m_T;
+
+typedef struct {
+ uint32_T chunks[52];
+} uint1664m_T;
+
+typedef struct {
+ uint1664m_T re;
+ uint1664m_T im;
+} cuint1664m_T;
+
+typedef struct {
+ uint32_T chunks[53];
+} int1696m_T;
+
+typedef struct {
+ int1696m_T re;
+ int1696m_T im;
+} cint1696m_T;
+
+typedef struct {
+ uint32_T chunks[53];
+} uint1696m_T;
+
+typedef struct {
+ uint1696m_T re;
+ uint1696m_T im;
+} cuint1696m_T;
+
+typedef struct {
+ uint32_T chunks[54];
+} int1728m_T;
+
+typedef struct {
+ int1728m_T re;
+ int1728m_T im;
+} cint1728m_T;
+
+typedef struct {
+ uint32_T chunks[54];
+} uint1728m_T;
+
+typedef struct {
+ uint1728m_T re;
+ uint1728m_T im;
+} cuint1728m_T;
+
+typedef struct {
+ uint32_T chunks[55];
+} int1760m_T;
+
+typedef struct {
+ int1760m_T re;
+ int1760m_T im;
+} cint1760m_T;
+
+typedef struct {
+ uint32_T chunks[55];
+} uint1760m_T;
+
+typedef struct {
+ uint1760m_T re;
+ uint1760m_T im;
+} cuint1760m_T;
+
+typedef struct {
+ uint32_T chunks[56];
+} int1792m_T;
+
+typedef struct {
+ int1792m_T re;
+ int1792m_T im;
+} cint1792m_T;
+
+typedef struct {
+ uint32_T chunks[56];
+} uint1792m_T;
+
+typedef struct {
+ uint1792m_T re;
+ uint1792m_T im;
+} cuint1792m_T;
+
+typedef struct {
+ uint32_T chunks[57];
+} int1824m_T;
+
+typedef struct {
+ int1824m_T re;
+ int1824m_T im;
+} cint1824m_T;
+
+typedef struct {
+ uint32_T chunks[57];
+} uint1824m_T;
+
+typedef struct {
+ uint1824m_T re;
+ uint1824m_T im;
+} cuint1824m_T;
+
+typedef struct {
+ uint32_T chunks[58];
+} int1856m_T;
+
+typedef struct {
+ int1856m_T re;
+ int1856m_T im;
+} cint1856m_T;
+
+typedef struct {
+ uint32_T chunks[58];
+} uint1856m_T;
+
+typedef struct {
+ uint1856m_T re;
+ uint1856m_T im;
+} cuint1856m_T;
+
+typedef struct {
+ uint32_T chunks[59];
+} int1888m_T;
+
+typedef struct {
+ int1888m_T re;
+ int1888m_T im;
+} cint1888m_T;
+
+typedef struct {
+ uint32_T chunks[59];
+} uint1888m_T;
+
+typedef struct {
+ uint1888m_T re;
+ uint1888m_T im;
+} cuint1888m_T;
+
+typedef struct {
+ uint32_T chunks[60];
+} int1920m_T;
+
+typedef struct {
+ int1920m_T re;
+ int1920m_T im;
+} cint1920m_T;
+
+typedef struct {
+ uint32_T chunks[60];
+} uint1920m_T;
+
+typedef struct {
+ uint1920m_T re;
+ uint1920m_T im;
+} cuint1920m_T;
+
+typedef struct {
+ uint32_T chunks[61];
+} int1952m_T;
+
+typedef struct {
+ int1952m_T re;
+ int1952m_T im;
+} cint1952m_T;
+
+typedef struct {
+ uint32_T chunks[61];
+} uint1952m_T;
+
+typedef struct {
+ uint1952m_T re;
+ uint1952m_T im;
+} cuint1952m_T;
+
+typedef struct {
+ uint32_T chunks[62];
+} int1984m_T;
+
+typedef struct {
+ int1984m_T re;
+ int1984m_T im;
+} cint1984m_T;
+
+typedef struct {
+ uint32_T chunks[62];
+} uint1984m_T;
+
+typedef struct {
+ uint1984m_T re;
+ uint1984m_T im;
+} cuint1984m_T;
+
+typedef struct {
+ uint32_T chunks[63];
+} int2016m_T;
+
+typedef struct {
+ int2016m_T re;
+ int2016m_T im;
+} cint2016m_T;
+
+typedef struct {
+ uint32_T chunks[63];
+} uint2016m_T;
+
+typedef struct {
+ uint2016m_T re;
+ uint2016m_T im;
+} cuint2016m_T;
+
+typedef struct {
+ uint32_T chunks[64];
+} int2048m_T;
+
+typedef struct {
+ int2048m_T re;
+ int2048m_T im;
+} cint2048m_T;
+
+typedef struct {
+ uint32_T chunks[64];
+} uint2048m_T;
+
+typedef struct {
+ uint2048m_T re;
+ uint2048m_T im;
+} cuint2048m_T;
+
+#endif /* __RTWTYPES_H__ */
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypeschksum.mat b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtwtypeschksum.mat
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/target_report.xml b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/target_report.xml
new file mode 100644
index 000000000..f5093748b
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/target_report.xml
@@ -0,0 +1,648 @@
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+ </value>
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+ <property name="Speed">
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+ <property name="Vendor ID">
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+ <property name="Cache size">
+ <value>
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+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
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+ </property>
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+ </property>
+ <property name="Speed">
+ <value>
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+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 7">
+ <property name="Cache size">
+ <value>
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+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 7
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 8">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
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+ 8
+ </value>
+ </property>
+ <property name="Speed">
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+ </value>
+ </property>
+ <property name="Vendor ID">
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+ </property>
+ </item>
+ <item name="Processor 9">
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+ </property>
+ <property name="Model name">
+ <value>
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+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
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+ </value>
+ </property>
+ <property name="Speed">
+ <value>
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+ </property>
+ <property name="Vendor ID">
+ <value>
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+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ <item name="Network and internet">
+ <item name="Network">
+ <item name="General information">
+ <property name="Computer name">
+ <value>
+ localhost.localdomain
+ </value>
+ </property>
+ <property name="Local IP">
+ <value>
+ 137.226.160.69
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ <item name="Software system">
+ <item name="Installed programs">
+ <item name="ARTEMIS"/>
+ <item name="Gcc">
+ <property name="Current version">
+ <value>
+ 4.1.2
+ </value>
+ </property>
+ </item>
+ <item name="Python">
+ <property name="Current version">
+ <value>
+ 2.4.3
+ </value>
+ </property>
+ </item>
+ <item name="RT-EVENTS"/>
+ <item name="RT-LAB">
+ <property name="Current version">
+ <value>
+ v10.5.9.356
+ </value>
+ </property>
+ </item>
+ </item>
+ <item name="Operating system">
+ <property name="Release">
+ <value>
+ 2.6.29.6-opalrt-5
+ </value>
+ </property>
+ <property name="Type">
+ <value>
+ linux2
+ </value>
+ </property>
+ <property name="Version">
+ <value>
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+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+</item>
diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/_sharedutils/tflSUInfo.mat b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/_sharedutils/tflSUInfo.mat
new file mode 100644
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/asyncip_sl_1_sm_ip_test/tmwinternal/binfo.mat b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/rtlab_rtmodel/asyncip_sl_1_sm_ip_test/tmwinternal/binfo.mat
new file mode 100644
index 0000000000000000000000000000000000000000..293bd3849e33de38f59f8064581407225642b1d6
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diff --git a/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/sl_proj.tmw b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/sl_proj.tmw
new file mode 100644
index 000000000..4a1b00782
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/sl_proj.tmw
@@ -0,0 +1,2 @@
+Simulink Coder project marker file. Please don't change it.
+slprjVersion: 7.8_30
\ No newline at end of file
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.Comm b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.Comm
new file mode 100644
index 000000000..5b19a0f02
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.Comm
@@ -0,0 +1,2 @@
+AsyncIP_sl/sc_console/OpComm: 1,1,1 : 0.000000000000000 : 0.000000000000000, 0.000000000000000, 0.000000000000000 : 1 : 0 : [0,0,0]
+SampleTime=0.000050000000000
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.acqgr b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.acqgr
new file mode 100644
index 000000000..a1816a570
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.acqgr
@@ -0,0 +1,2 @@
+2
+1 0.000050000 1 13
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.alias b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.alias
new file mode 100644
index 000000000..b57c2bac0
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.alias
@@ -0,0 +1,3 @@
+[General]
+aliascnt=0
+[Alias]
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.param b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.param
new file mode 100644
index 000000000..6ecbfac8e
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.param
@@ -0,0 +1,19 @@
+[General]
+ATT_VERSION=1
+[Size]
+nbParameters=13
+nbValues=13
+nbVariables=0
+nbParamsVar=0
+[Parameter]
+0=AsyncIP_sl/sm_ip_test/data ready 1 kHz|Amplitude| |Scalar|1|1|2|1.0|1|1|
+1=AsyncIP_sl/sm_ip_test/data ready 1 kHz|Period| |Scalar|1|1|3|2.0|1|1|
+2=AsyncIP_sl/sm_ip_test/data ready 1 kHz|PulseWidth| |Scalar|1|1|4|1.0|1|1|
+3=AsyncIP_sl/sm_ip_test/data ready 1 kHz|PhaseDelay| |Scalar|1|1|5|0.0|1|1|
+4=AsyncIP_sl/sm_ip_test/constants|Value| |RVector|1|4|6|1.0|2.0|3.0|4.0|1|4|
+8=AsyncIP_sl/sm_ip_test/Pulse Generator|Amplitude| |Scalar|1|1|10|5.0|1|1|
+9=AsyncIP_sl/sm_ip_test/Pulse Generator|Period| |Scalar|1|1|11|2000.0|1|1|
+10=AsyncIP_sl/sm_ip_test/Pulse Generator|PulseWidth| |Scalar|1|1|12|600.0|1|1|
+11=AsyncIP_sl/sm_ip_test/Pulse Generator|PhaseDelay| |Scalar|1|1|13|0.0|1|1|
+12=AsyncIP_sl/sm_ip_test/timeout|Value| |Scalar|1|1|83|2.0|1|1|
+[Variable]
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.sig b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.sig
new file mode 100644
index 000000000..e2c9f1efd
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.sig
@@ -0,0 +1,16 @@
+[AcqGr1]
+1=AsyncIP_sl/sm_ip_test/port2(1)|signal1.signal1|1|1
+2=AsyncIP_sl/sm_ip_test/port2(2)|signal1.signal2|1|2
+3=AsyncIP_sl/sm_ip_test/port2(3)|signal1.signal3|1|3
+4=AsyncIP_sl/sm_ip_test/port1(1)|signal1(1)|2|1
+5=AsyncIP_sl/sm_ip_test/port1(2)|signal1(2)|2|2
+6=AsyncIP_sl/sm_ip_test/port1(3)|signal1(3)|2|3
+7=AsyncIP_sl/sm_ip_test/port1(4)|signal1(4)|2|4
+8=AsyncIP_sl/sm_ip_test/port1(5)|signal1(5)|2|5
+9=AsyncIP_sl/sm_ip_test/port3(1)|signal1.signal1(1)|3|1
+10=AsyncIP_sl/sm_ip_test/port3(2)|signal1.signal1(2)|3|2
+11=AsyncIP_sl/sm_ip_test/port3(3)|signal1.signal1(3)|3|3
+12=AsyncIP_sl/sm_ip_test/port3(4)|signal1.signal1(4)|3|4
+13=AsyncIP_sl/sm_ip_test/port3(5)|signal1.signal2|3|5
+nbsignals=13
+
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.signal b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.signal
new file mode 100644
index 000000000..a587b4a28
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.signal
@@ -0,0 +1,29 @@
+[Size]
+nbSignals=10
+nbFixedSignals=13
+nbControlSignal=0
+[Signal]
+1=AsyncIP_sl/sm_ip_test/data ready 1 kHz/port1|signal1|1|1|2|1|1|1|S|
+2=AsyncIP_sl/sm_ip_test/Pulse Generator/port1|signal1|1|1|3|1|1|1|S|
+3=AsyncIP_sl/sm_ip_test/send message 1/S-Function2/port1|signal1|1|1|4|1|1|1|S|
+4=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port1|signal1|1|1|5|1|1|1|S|
+5=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port2|signal2|1|2|6|1|1|1|S|
+6=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(1)|signal3(1)|1|3|7|1|5|1|V|
+7=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(2)|signal3(2)|1|3|8|1|5|1|V|
+8=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(3)|signal3(3)|1|3|9|1|5|1|V|
+9=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(4)|signal3(4)|1|3|10|1|5|1|V|
+10=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(5)|signal3(5)|1|3|11|1|5|1|V|
+[FixedSignal]
+1=AsyncIP_sl/sm_ip_test/port2(1)|signal1.signal1|1|1|0|1|
+2=AsyncIP_sl/sm_ip_test/port2(2)|signal1.signal2|1|1|0|1|
+3=AsyncIP_sl/sm_ip_test/port2(3)|signal1.signal3|1|1|0|1|
+4=AsyncIP_sl/sm_ip_test/port1(1)|signal1(1)|1|1|0|1|
+5=AsyncIP_sl/sm_ip_test/port1(2)|signal1(2)|1|1|0|1|
+6=AsyncIP_sl/sm_ip_test/port1(3)|signal1(3)|1|1|0|1|
+7=AsyncIP_sl/sm_ip_test/port1(4)|signal1(4)|1|1|0|1|
+8=AsyncIP_sl/sm_ip_test/port1(5)|signal1(5)|1|1|0|1|
+9=AsyncIP_sl/sm_ip_test/port3(1)|signal1.signal1(1)|1|1|0|1|
+10=AsyncIP_sl/sm_ip_test/port3(2)|signal1.signal1(2)|1|1|0|1|
+11=AsyncIP_sl/sm_ip_test/port3(3)|signal1.signal1(3)|1|1|0|1|
+12=AsyncIP_sl/sm_ip_test/port3(4)|signal1.signal1(4)|1|1|0|1|
+13=AsyncIP_sl/sm_ip_test/port3(5)|signal1.signal2|1|1|0|1|
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.subsys b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.subsys
new file mode 100644
index 000000000..698a108dc
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.subsys
@@ -0,0 +1,2 @@
+AsyncIP_sl/sm_ip_test,asyncip_sl_1_sm_ip_test,1
+AsyncIP_sl/sc_console,asyncip_sl_2_sc_console,2
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_OpREDHAWKtarget_Compilation.log b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_OpREDHAWKtarget_Compilation.log
new file mode 100644
index 000000000..9fe5f00ec
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_OpREDHAWKtarget_Compilation.log
@@ -0,0 +1,206 @@
+
+-------------------- Starting compilation --------------------
+Start at : Wednesday, May 28, 2014, 12:53:31
+
+The current RT-LAB version is: v10.5.9.356
+The current model is: D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl.mdl
+The current host platform is: XP/Vista/7
+The current target platform is: Redhat
+The current compiler is: Automatic
+
+Preparing original model for code separation and generation...
+
+The current Matlab version is: v7.13 (32 Bit)
+
+
+Diagnostics:
+
+Reported by: RT-LAB
+Source : AsyncIP_sl
+Message : Warning: Block Reduction Optimization is set to ON. Real Time Workshop will optimize and remove some
+ unused blocks in the model. Those signals might not be visible with Rt-Lab Dynamic Acquisition after
+ compilation. This option can be changed in the Simulink model : Simulation/Configuration Parameters/Optimization
+
+
+RtlabInfo not loaded
+Separating RT-LAB model (number of RT subsystems = 1, console detected).
+Separating RT-LAB subsystem 'sm_ip_test'.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+Separating RT-LAB subsystem 'sc_console'.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+
+Model preparation and separation duration : 00h:00m:07s
+-------------------- Completed successfully --------------------
+
+-------------------- Generating C code --------------------
+
+Using System Target File (TLC file) : rtlab_rtmodel.tlc...
+
+Using Template Makefile (TMF file) : rtlab_rtmodel.tmf...
+
+-------------------- Generating asyncip_sl_1_sm_ip_test C code --------------------
+Calling RTW Make Command make_rtw...
+### Starting build procedure for model: asyncip_sl_1_sm_ip_test
+### Generating code into build folder: D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\asyncip_sl_1_sm_ip_test_rtlab
+
+### Invoking Target Language Compiler on asyncip_sl_1_sm_ip_test.rtw
+### Using System Target File: C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tlc
+### Loading TLC function libraries
+.....
+### Initial pass through model to cache user defined code
+.....
+### Caching model source code
+...................................................................
+### Writing header file asyncip_sl_1_sm_ip_test.h
+### Writing header file asyncip_sl_1_sm_ip_test_types.h
+.
+### Writing header file rtwtypes.h
+### Writing source file asyncip_sl_1_sm_ip_test.c
+### Writing header file asyncip_sl_1_sm_ip_test_private.h
+.
+### Writing header file rtmodel.h
+### Writing source file asyncip_sl_1_sm_ip_test_data.c
+### Writing header file rt_nonfinite.h
+.
+### Writing source file rt_nonfinite.c
+### Writing header file rt_defines.h
+.
+### Writing header file rtGetInf.h
+### Writing source file rtGetInf.c
+### Writing header file rtGetNaN.h
+.
+### Writing source file rtGetNaN.c
+### TLC code generation complete.
+### Creating model mapping file asyncip_sl_1_sm_ip_test.map using map_r2011a.tlc
+...............................### Creating project marker file: rtw_proj.tmw
+.
+### Processing Template Makefile: C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf
+### Wrapping unrecognized make command (angle brackets added)
+### <make>
+### in default batch file
+### Creating asyncip_sl_1_sm_ip_test.mk from C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf
+### Successful completion of code generation for model: asyncip_sl_1_sm_ip_test
+
+
+asyncip_sl_1_sm_ip_test : Generating C code duration : 00h:00m:06s
+Generating C code total duration : 00h:00m:06s
+
+-------------------- Completed successfully --------------------
+
+-------------------- Creating the parameter database --------------------
+
+Parameter(s) with more than 20 values will be disabled.
+Use PARAM_VECTOR_SIZE_LIMIT environment variable to modify this limit.
+Parameter database creation duration: 00h:00m:00s
+-------------------- Parameter database created successfully --------------------
+
+
+-------------------- Creating the signals database --------------------
+
+Signal(s) with more than 20 values will be disabled.
+Use SIGNALS_VECTOR_SIZE_LIMIT environment variable to modify this limit.
+Signal database creation duration: 00h:00m:00s
+-------------------- Signal database created successfully --------------------
+
+
+-------------------- Transferring the generated C code --------------------
+
+Connecting to 137.226.160.69 ... OK.
+
+Setting remote directory to /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/... OK.
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink/rtw/c/common/linux32.opt ... OK.
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink/rtw/c/common/posix.rules ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\target_precompile.py ... Failed.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test*.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtGet* ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.mk ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.prm ... Failed.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.reg ... Failed.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rt_*.* ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtwtypes.* ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtmodel.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\drive_asyncip_sl_1_sm_ip_test*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\drive_asyncip_sl_1_sm_ip_test*.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\Opal*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.mk ... OK.
+
+Transferring common RT-LAB files:
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\include_target\*.h ... OK.
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\simulink\rtw\c\common\model_main.c ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalCore.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalUtils_redhawk.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalUtils.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalOhci.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libirc.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libimf.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\simulink\libR2011b\redhawk\libOpalRTE*.a ... OK.
+
+Transferring user extra files:
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP.mk ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIPUtils.h ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalAsyncApiCore.a ... OK.
+
+File transfer duration : 00h:00m:02s
+-------------------- Completed successfully --------------------
+
+-------------------- Building the generated C code --------------------
+
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_precompile.py ... done
+Removing relative includes from ./../asyncip_sl_sm_ip_test/model_main.c ... Done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_precompile.py ... done
+-------------------- Building asyncip_sl_1_sm_ip_test --------------------
+/usr/bin/make -f AsyncIP.mk
+make[1]: Entering directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+opicc -c -O -D_GNU_SOURCE -I. -c -o AsyncIP.o AsyncIP.c
+AsyncIP.c(167): warning #167: argument of type "int *" is incompatible with parameter of type "unsigned int *"
+ if((n = OpalWaitForAsyncSendRequest (&SendID)) != EOK)
+ ^
+
+opicpc -L. -o AsyncIP AsyncIP.o -lOpalAsyncApiCore -lOpalCore -lOpalUtils -lpthread -lm -ldl -lutil -lrt
+chmod 777 AsyncIP
+### Created executable: AsyncIP
+make[1]: Leaving directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+/usr/bin/make -f asyncip_sl_1_sm_ip_test.mk
+make[1]: Entering directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+rm -f asyncip_sl_1_sm_ip_test
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils asyncip_sl_1_sm_ip_test.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils model_main.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_sim.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils asyncip_sl_1_sm_ip_test_data.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rtGetInf.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rtGetNaN.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_logging.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_matrx.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rt_nonfinite.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_printf.c
+### Linking ...
+opicpc -Wl,-rpath=/usr/opalrt/v10.5.9.356/common/bin -Wl,-rpath='/opt/intel/Compiler/11.1/072/lib/ia32' -Wl,-rpath='/opt/intel/Compiler/11.1/056/lib/ia32' -diag-disable remark -L. -L/usr/opalrt/v10.5.9.356/RT-LAB/lib -L/usr/opalrt/v10.5.9.356/common/lib -L/usr/opalrt/v10.5.9.356/common/lib/redhawk -L/usr/opalrt/v10.5.9.356/common/bin -L/usr/opalrt/externals/lib -L/usr/matlab/v7.13/toolbox/dspblks/lib/redhawk -L/usr/matlab/v7.13/toolbox/simscape/lib/redhawk -o asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test.o model_main.o rt_sim.o asyncip_sl_1_sm_ip_test_data.o rtGetInf.o rtGetNaN.o rt_logging.o rt_matrx.o rt_nonfinite.o rt_printf.o -lOpalAsyncApiR2011b -lOpalAsyncApiCore -lOpalSfunR2011b -lOpalR2011b -lBlocksRT-2011b -lOpalCore -lOpalOhci -lOpalCore -llicenseRH32 -lSystem -lPlatform -lFramework -lMatio -lOpal -lInfrastructure -lNumeric -lSimulink -lNetwork -lOpalUtils -ldspblks -lsimscape -lpthread -lm -ldl -lutil -lrt /usr/matlab/v7.13/rtw/c/libsrc/rtwlibr_redhawk.a
+chmod a+x asyncip_sl_1_sm_ip_test
+### Created executable: asyncip_sl_1_sm_ip_test
+make[1]: Leaving directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+
+asyncip_sl_1_sm_ip_test : Building subsystem duration : 00h:00m:01s
+
+Building model total duration : 00h:00m:01s
+-------------------- Completed successfully --------------------
+
+-------------------- Transferring the built model --------------------
+
+Connecting to 137.226.160.69 ... OK.
+Transferring in binary mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test ... OK.
+Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/compilation_target_report.xml ... OK.
+Transferring in binary mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/AsyncIP ... OK.
+
+File transfer duration : 00h:00m:01s
+-------------------- Completed successfully --------------------
+
+End at : Wednesday, May 28, 2014, 12:53:50
+
+Compilation duration : 00h:00m:19s
+
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.ini b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.ini
new file mode 100644
index 000000000..0730b568c
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.ini
@@ -0,0 +1,63 @@
+[GENERAL]
+hostPlatform=PCWIN
+platform=REDHAWK
+[MATLAB_GENERAL]
+version=7.13
+release=R2011b
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diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.mat b/clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_info.mat
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diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.mdl b/clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.mdl
new file mode 100644
index 000000000..cfad75281
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.mdl
@@ -0,0 +1,1223 @@
+# $Revision: 1.1 $
+Model {
+ Name "asyncip_sl_1_sm_ip_test"
+ Version 7.8
+ MdlSubVersion 0
+ GraphicalInterface {
+ NumRootInports 0
+ NumRootOutports 0
+ ParameterArgumentNames ""
+ ComputedModelVersion "1.426"
+ NumModelReferences 0
+ NumTestPointedSignals 0
+ }
+ SavedCharacterEncoding "windows-1252"
+ SaveDefaultBlockParams on
+ ScopeRefreshTime 0.035000
+ OverrideScopeRefreshTime on
+ DisableAllScopes off
+ DataTypeOverride "UseLocalSettings"
+ DataTypeOverrideAppliesTo "AllNumericTypes"
+ MinMaxOverflowLogging "UseLocalSettings"
+ MinMaxOverflowArchiveMode "Overwrite"
+ FPTRunName "Run 1"
+ MaxMDLFileLineLength 120
+ Created "Thu Apr 15 08:21:54 1999"
+ Creator "jwu"
+ UpdateHistory "UpdateHistoryNever"
+ ModifiedByFormat "%<Auto>"
+ LastModifiedBy "ACS"
+ ModifiedDateFormat "%<Auto>"
+ LastModifiedDate "Wed May 28 12:53:39 2014"
+ RTWModifiedTimeStamp 323182419
+ ModelVersionFormat "1.%<AutoIncrement:426>"
+ ConfigurationManager "none"
+ SampleTimeColors off
+ SampleTimeAnnotations off
+ LibraryLinkDisplay "none"
+ WideLines off
+ ShowLineDimensions on
+ ShowPortDataTypes off
+ ShowDesignRanges off
+ ShowLoopsOnError on
+ IgnoreBidirectionalLines off
+ ShowStorageClass off
+ ShowTestPointIcons on
+ ShowSignalResolutionIcons on
+ ShowViewerIcons on
+ SortedOrder off
+ ExecutionContextIcon off
+ ShowLinearizationAnnotations on
+ BlockNameDataTip off
+ BlockParametersDataTip on
+ BlockDescriptionStringDataTip off
+ ToolBar on
+ StatusBar on
+ BrowserShowLibraryLinks off
+ BrowserLookUnderMasks off
+ SimulationMode "normal"
+ LinearizationMsg "none"
+ Profile off
+ ParamWorkspaceSource "MATLABWorkspace"
+ AccelSystemTargetFile "accel.tlc"
+ AccelTemplateMakefile "accel_default_tmf"
+ AccelMakeCommand "make_rtw"
+ TryForcingSFcnDF off
+ RecordCoverage off
+ CovPath "/"
+ CovSaveName "covdata"
+ CovMetricSettings "dw"
+ CovNameIncrementing off
+ CovHtmlReporting on
+ CovForceBlockReductionOff on
+ covSaveCumulativeToWorkspaceVar on
+ CovSaveSingleToWorkspaceVar on
+ CovCumulativeVarName "covCumulativeData"
+ CovCumulativeReport off
+ CovReportOnPause on
+ CovModelRefEnable "Off"
+ CovExternalEMLEnable off
+ ExtModeBatchMode off
+ ExtModeEnableFloating on
+ ExtModeTrigType "manual"
+ ExtModeTrigMode "oneshot"
+ ExtModeTrigPort "1"
+ ExtModeTrigElement "any"
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+ ExtModeTrigDurationFloating "auto"
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+ ExtModeTrigDelay 0
+ ExtModeTrigDirection "rising"
+ ExtModeTrigLevel 0
+ ExtModeArchiveMode "off"
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+ ExtModeIncDirWhenArm off
+ ExtModeAddSuffixToVar off
+ ExtModeWriteAllDataToWs off
+ ExtModeArmWhenConnect off
+ ExtModeSkipDownloadWhenConnect off
+ ExtModeLogAll on
+ ExtModeAutoUpdateStatusClock on
+ BufferReuse off
+ ShowModelReferenceBlockVersion off
+ ShowModelReferenceBlockIO off
+ Array {
+ Type "Handle"
+ Dimension 1
+ Simulink.ConfigSet {
+ $ObjectID 1
+ Version "1.11.1"
+ Array {
+ Type "Handle"
+ Dimension 8
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+ Version "1.11.1"
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+ MaxStep "0.01"
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+ MaxConsecutiveMinStep "1"
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+ SolverMode "SingleTasking"
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+ SolverName "ode4"
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+ ShapePreserveControl "DisableAll"
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+ ZeroCrossAlgorithm "Nonadaptive"
+ AlgebraicLoopSolver "TrustRegion"
+ SolverResetMethod "Fast"
+ PositivePriorityOrder off
+ AutoInsertRateTranBlk off
+ SampleTimeConstraint "Unconstrained"
+ InsertRTBMode "Whenever possible"
+ }
+ Simulink.DataIOCC {
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+ FinalStateName "xFinal"
+ InitialState "[]"
+ LimitDataPoints off
+ MaxDataPoints "1000"
+ LoadExternalInput off
+ LoadInitialState off
+ SaveFinalState off
+ SaveCompleteFinalSimState off
+ SaveFormat "Array"
+ SignalLoggingSaveFormat "ModelDataLogs"
+ SaveOutput off
+ SaveState off
+ SignalLogging on
+ DSMLogging on
+ InspectSignalLogs off
+ SaveTime off
+ ReturnWorkspaceOutputs off
+ StateSaveName "xout"
+ TimeSaveName "tout"
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+ SignalLoggingName "sigsOut"
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+ }
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+ Cell "NoFixptDivByZeroProtection"
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+ PropName "DisabledProps"
+ }
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+ SystemCodeInlineAuto off
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+ LifeSpan "inf"
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+ SimCompilerOptimization "Off"
+ AccelVerboseBuild off
+ AccelParallelForEachSubsystem on
+ }
+ Simulink.DebuggingCC {
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+ Version "1.11.1"
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+ UniqueDataStoreMsg "none"
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+ EnableOverflowDetection off
+ ModelReferenceIOMsg "none"
+ ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error"
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+ StateNameClashWarn "warning"
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+ BusNameAdapt "WarnAndRepair"
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+ }
+ Simulink.HardwareCC {
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+}
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.sfp b/clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.sfp
new file mode 100644
index 000000000..f643fb0a5
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/asyncip_sl_1_sm_ip_test.sfp
@@ -0,0 +1,7 @@
+[S-Function list]
+asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1=0
+asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1=0
+asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1/S-Function=0
+asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2=0
+
+[S-Function parameters]
diff --git a/clients/opal/models/AsyncIP_sl/Opcommon/host_report.xml b/clients/opal/models/AsyncIP_sl/Opcommon/host_report.xml
new file mode 100644
index 000000000..d60fd6d10
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/Opcommon/host_report.xml
@@ -0,0 +1,3101 @@
+<?xml version="1.0" encoding="utf-8"?>
+<item name="report">
+ <item name="diagnostic">
+ <item name="Development">
+ <item name="Command station">
+ <item name="Acs ::1">
+ <item name="Hardware system">
+ <item name="Processors">
+ <item name="Processor 1">
+ <property name="type">
+ <value>
+ 586
+ </value>
+ </property>
+ </item>
+ <item name="Processor 2">
+ <property name="type">
+ <value>
+ 586
+ </value>
+ </property>
+ </item>
+ <item name="Processor 3">
+ <property name="type">
+ <value>
+ 586
+ </value>
+ </property>
+ </item>
+ <item name="Processor 4">
+ <property name="type">
+ <value>
+ 586
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ <item name="Network and internet">
+ <item name="Network">
+ <item name="General information">
+ <property name="Computer name">
+ <value>
+ ACS
+ </value>
+ </property>
+ <property name="Current user">
+ <value>
+ ACS
+ </value>
+ </property>
+ <property name="Local IP">
+ <value>
+ ::1
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ <item name="Software system">
+ <item name="Operating system">
+ <property name="Other information">
+ <value>
+ Service Pack 1
+ </value>
+ </property>
+ <property name="Release">
+ <value>
+ post2008Server
+ </value>
+ </property>
+ <property name="Type">
+ <value>
+ Windows
+ </value>
+ </property>
+ <property name="Version">
+ <value>
+ 6.1.7601
+ </value>
+ </property>
+ </item>
+ <item name="Installed programs">
+ <item name="Matlab">
+ <property name="Version">
+ <value>
+ 7.13
+ </value>
+ </property>
+ <property name="Release">
+ <value>
+ R2011b
+ </value>
+ </property>
+ <item name="Path">
+ <property name="0">
+ <value>
+ C:\OPAL-RT\RT-LAB\v10.5.9.356\common\bin
+ </value>
+ </property>
+ <property name="1">
+ <value>
+ C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common
+ </value>
+ </property>
+ <property name="2">
+ <value>
+ C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\libR2011b
+ </value>
+ </property>
+ <property name="3">
+ <value>
+ C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\m
+ </value>
+ </property>
+ <property name="4">
+ <value>
+ C:\Users\ACS\Documents\MATLAB
+ </value>
+ </property>
+ <property name="5">
+ <value>
+ C:\OPAL-RT\ARTEMIS\v6.3.2.318\art_r2011b\lib
+ </value>
+ </property>
+ <property name="6">
+ <value>
+ C:\OPAL-RT\ARTEMIS\v6.3.2.318\art_r2011b\lib\tlc_c
+ </value>
+ </property>
+ <property name="7">
+ <value>
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+ </value>
+ </property>
+ <property name="8">
+ <value>
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+ </value>
+ </property>
+ <property name="9">
+ <value>
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+ </value>
+ </property>
+ <property name="10">
+ <value>
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+ </value>
+ </property>
+ <property name="11">
+ <value>
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+ </value>
+ </property>
+ <property name="12">
+ <value>
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+ </property>
+ <property name="13">
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+ C:\Program Files (x86)\MATLAB\R2011b\toolbox\matlab\graph2d
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+ <value>
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+ </property>
+ <property name="Gauges Blockset">
+ <value>
+ 2.0.6, (R2011b)
+ </value>
+ </property>
+ <property name="Fuzzy Logic Toolbox">
+ <value>
+ 2.2.14, (R2011b)
+ </value>
+ </property>
+ <property name="Signal Processing Toolbox">
+ <value>
+ 6.16, (R2011b)
+ </value>
+ </property>
+ <property name="Global Optimization Toolbox">
+ <value>
+ 3.2, (R2011b)
+ </value>
+ </property>
+ <property name="Fixed-Point Toolbox">
+ <value>
+ 3.4, (R2011b)
+ </value>
+ </property>
+ <property name="Embedded Coder">
+ <value>
+ 6.1, (R2011b)
+ </value>
+ </property>
+ <property name="Simscape">
+ <value>
+ 3.6, (R2011b)
+ </value>
+ </property>
+ <property name="SimRF">
+ <value>
+ 3.1, (R2011b)
+ </value>
+ </property>
+ <property name="Image Acquisition Toolbox">
+ <value>
+ 4.2, (R2011b)
+ </value>
+ </property>
+ <property name="Model Predictive Control Toolbox">
+ <value>
+ 4.0, (R2011b)
+ </value>
+ </property>
+ <property name="Instrument Control Toolbox">
+ <value>
+ 3.0, (R2011b)
+ </value>
+ </property>
+ <property name="Image Processing Toolbox">
+ <value>
+ 7.3, (R2011b)
+ </value>
+ </property>
+ <property name="MATLAB Coder">
+ <value>
+ 2.1, (R2011b)
+ </value>
+ </property>
+ <property name="xPC Target">
+ <value>
+ 5.1, (R2011b)
+ </value>
+ </property>
+ <property name="Robust Control Toolbox">
+ <value>
+ 4.0, (R2011b)
+ </value>
+ </property>
+ <property name="Neural Network Toolbox">
+ <value>
+ 7.0.2, (R2011b)
+ </value>
+ </property>
+ <property name="System Identification Toolbox">
+ <value>
+ 7.4.3, (R2011b)
+ </value>
+ </property>
+ <property name="SimMechanics">
+ <value>
+ 3.2.3, (R2011b)
+ </value>
+ </property>
+ <property name="Wavelet Toolbox">
+ <value>
+ 4.8, (R2011b)
+ </value>
+ </property>
+ <property name="Vehicle Network Toolbox">
+ <value>
+ 1.5, (R2011b)
+ </value>
+ </property>
+ <property name="SimDriveline">
+ <value>
+ 2.1, (R2011b)
+ </value>
+ </property>
+ <property name="xPC Target Embedded Option">
+ <value>
+ 5.1, (R2011b)
+ </value>
+ </property>
+ <property name="SimPowerSystems">
+ <value>
+ 5.5, (R2011b)
+ </value>
+ </property>
+ <property name="MATLAB">
+ <value>
+ 7.13, (R2011b)
+ </value>
+ </property>
+ <property name="Symbolic Math Toolbox">
+ <value>
+ 5.7, (R2011b)
+ </value>
+ </property>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+</item>
diff --git a/clients/opal/models/AsyncIP_sl/actxlicense.m b/clients/opal/models/AsyncIP_sl/actxlicense.m
new file mode 100644
index 000000000..06414f2b2
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/actxlicense.m
@@ -0,0 +1,6 @@
+function lic = actxlicense(progid)
+
+if strcmpi(progid, 'air.airctrl.1')
+lic = 'Copyright (c) 1996 ';
+return;
+end
diff --git a/clients/opal/models/AsyncIP_sl/asyncip_sl_2_sc_console.mdl b/clients/opal/models/AsyncIP_sl/asyncip_sl_2_sc_console.mdl
new file mode 100644
index 000000000..f02459bf8
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/asyncip_sl_2_sc_console.mdl
@@ -0,0 +1,1827 @@
+# $Revision: 1.1 $
+Model {
+ Name "asyncip_sl_2_sc_console"
+ Version 7.8
+ MdlSubVersion 0
+ GraphicalInterface {
+ NumRootInports 0
+ NumRootOutports 0
+ ParameterArgumentNames ""
+ ComputedModelVersion "1.426"
+ NumModelReferences 0
+ NumTestPointedSignals 0
+ }
+ SavedCharacterEncoding "windows-1252"
+ SaveDefaultBlockParams on
+ ScopeRefreshTime 0.035000
+ OverrideScopeRefreshTime on
+ DisableAllScopes off
+ DataTypeOverride "UseLocalSettings"
+ DataTypeOverrideAppliesTo "AllNumericTypes"
+ MinMaxOverflowLogging "UseLocalSettings"
+ MinMaxOverflowArchiveMode "Overwrite"
+ FPTRunName "Run 1"
+ MaxMDLFileLineLength 120
+ Created "Thu Apr 15 08:21:54 1999"
+ Creator "jwu"
+ UpdateHistory "UpdateHistoryNever"
+ ModifiedByFormat "%<Auto>"
+ LastModifiedBy "ACS"
+ ModifiedDateFormat "%<Auto>"
+ LastModifiedDate "Wed May 28 12:53:40 2014"
+ RTWModifiedTimeStamp 323182420
+ ModelVersionFormat "1.%<AutoIncrement:426>"
+ ConfigurationManager "none"
+ SampleTimeColors off
+ SampleTimeAnnotations off
+ LibraryLinkDisplay "none"
+ WideLines off
+ ShowLineDimensions on
+ ShowPortDataTypes off
+ ShowDesignRanges off
+ ShowLoopsOnError on
+ IgnoreBidirectionalLines off
+ ShowStorageClass off
+ ShowTestPointIcons on
+ ShowSignalResolutionIcons on
+ ShowViewerIcons on
+ SortedOrder off
+ ExecutionContextIcon off
+ ShowLinearizationAnnotations on
+ BlockNameDataTip off
+ BlockParametersDataTip on
+ BlockDescriptionStringDataTip off
+ ToolBar on
+ StatusBar on
+ BrowserShowLibraryLinks off
+ BrowserLookUnderMasks off
+ SimulationMode "normal"
+ LinearizationMsg "none"
+ Profile off
+ ParamWorkspaceSource "MATLABWorkspace"
+ AccelSystemTargetFile "accel.tlc"
+ AccelTemplateMakefile "accel_default_tmf"
+ AccelMakeCommand "make_rtw"
+ TryForcingSFcnDF off
+ RecordCoverage off
+ CovPath "/"
+ CovSaveName "covdata"
+ CovMetricSettings "dw"
+ CovNameIncrementing off
+ CovHtmlReporting on
+ CovForceBlockReductionOff on
+ covSaveCumulativeToWorkspaceVar on
+ CovSaveSingleToWorkspaceVar on
+ CovCumulativeVarName "covCumulativeData"
+ CovCumulativeReport off
+ CovReportOnPause on
+ CovModelRefEnable "Off"
+ CovExternalEMLEnable off
+ ExtModeBatchMode off
+ ExtModeEnableFloating on
+ ExtModeTrigType "manual"
+ ExtModeTrigMode "oneshot"
+ ExtModeTrigPort "1"
+ ExtModeTrigElement "any"
+ ExtModeTrigDuration 1000
+ ExtModeTrigDurationFloating "auto"
+ ExtModeTrigHoldOff 0
+ ExtModeTrigDelay 0
+ ExtModeTrigDirection "rising"
+ ExtModeTrigLevel 0
+ ExtModeArchiveMode "off"
+ ExtModeAutoIncOneShot off
+ ExtModeIncDirWhenArm off
+ ExtModeAddSuffixToVar off
+ ExtModeWriteAllDataToWs off
+ ExtModeArmWhenConnect off
+ ExtModeSkipDownloadWhenConnect off
+ ExtModeLogAll on
+ ExtModeAutoUpdateStatusClock on
+ BufferReuse off
+ ShowModelReferenceBlockVersion off
+ ShowModelReferenceBlockIO off
+ Array {
+ Type "Handle"
+ Dimension 1
+ Simulink.ConfigSet {
+ $ObjectID 1
+ Version "1.11.1"
+ Array {
+ Type "Handle"
+ Dimension 8
+ Simulink.SolverCC {
+ $ObjectID 2
+ Version "1.11.1"
+ StartTime "0.0"
+ StopTime "inf"
+ AbsTol "1e-6"
+ FixedStep "5e-005"
+ InitialStep "auto"
+ MaxNumMinSteps "-1"
+ MaxOrder 5
+ ZcThreshold "auto"
+ ConsecutiveZCsStepRelTol "10*128*eps"
+ MaxConsecutiveZCs "1000"
+ ExtrapolationOrder 4
+ NumberNewtonIterations 1
+ MaxStep "0.01"
+ MinStep "auto"
+ MaxConsecutiveMinStep "1"
+ RelTol "1e-3"
+ SolverMode "SingleTasking"
+ ConcurrentTasks off
+ Solver "ode4"
+ SolverName "ode4"
+ SolverJacobianMethodControl "auto"
+ ShapePreserveControl "DisableAll"
+ ZeroCrossControl "UseLocalSettings"
+ ZeroCrossAlgorithm "Nonadaptive"
+ AlgebraicLoopSolver "TrustRegion"
+ SolverResetMethod "Fast"
+ PositivePriorityOrder off
+ AutoInsertRateTranBlk off
+ SampleTimeConstraint "Unconstrained"
+ InsertRTBMode "Whenever possible"
+ }
+ Simulink.DataIOCC {
+ $ObjectID 3
+ Version "1.11.1"
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+ ExternalInput "[]"
+ FinalStateName "xFinal"
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+ MaxDataPoints "1000"
+ LoadExternalInput off
+ LoadInitialState off
+ SaveFinalState off
+ SaveCompleteFinalSimState off
+ SaveFormat "Array"
+ SignalLoggingSaveFormat "ModelDataLogs"
+ SaveOutput off
+ SaveState off
+ SignalLogging on
+ DSMLogging on
+ InspectSignalLogs off
+ SaveTime off
+ ReturnWorkspaceOutputs off
+ StateSaveName "xout"
+ TimeSaveName "tout"
+ OutputSaveName "yout"
+ SignalLoggingName "sigsOut"
+ DSMLoggingName "dsmout"
+ OutputOption "RefineOutputTimes"
+ OutputTimes "[]"
+ ReturnWorkspaceOutputsName "out"
+ Refine "1"
+ }
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+ $ObjectID 4
+ Version "1.11.1"
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+ Dimension 4
+ Cell "ZeroExternalMemoryAtStartup"
+ Cell "ZeroInternalMemoryAtStartup"
+ Cell "NoFixptDivByZeroProtection"
+ Cell "OptimizeModelRefInitCode"
+ PropName "DisabledProps"
+ }
+ BlockReduction on
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+ InlineInvariantSignals off
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+ BufferReuse off
+ EnhancedBackFolding off
+ StrengthReduction off
+ ExpressionFolding off
+ BooleansAsBitfields off
+ BitfieldContainerType "uint_T"
+ EnableMemcpy on
+ MemcpyThreshold 64
+ PassReuseOutputArgsAs "Structure reference"
+ ExpressionDepthLimit 2147483647
+ FoldNonRolledExpr off
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+ SystemCodeInlineAuto off
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+ InitFltsAndDblsToZero on
+ NoFixptDivByZeroProtection off
+ EfficientFloat2IntCast off
+ EfficientMapNaN2IntZero on
+ OptimizeModelRefInitCode off
+ LifeSpan "inf"
+ MaxStackSize "Inherit from target"
+ BufferReusableBoundary on
+ SimCompilerOptimization "Off"
+ AccelVerboseBuild off
+ AccelParallelForEachSubsystem on
+ }
+ Simulink.DebuggingCC {
+ $ObjectID 5
+ Version "1.11.1"
+ RTPrefix "error"
+ ConsistencyChecking "none"
+ ArrayBoundsChecking "none"
+ SignalInfNanChecking "none"
+ SignalRangeChecking "none"
+ ReadBeforeWriteMsg "UseLocalSettings"
+ WriteAfterWriteMsg "UseLocalSettings"
+ WriteAfterReadMsg "UseLocalSettings"
+ AlgebraicLoopMsg "warning"
+ ArtificialAlgebraicLoopMsg "warning"
+ SaveWithDisabledLinksMsg "warning"
+ SaveWithParameterizedLinksMsg "none"
+ CheckSSInitialOutputMsg on
+ UnderspecifiedInitializationDetection "Classic"
+ MergeDetectMultiDrivingBlocksExec "none"
+ CheckExecutionContextPreStartOutputMsg off
+ CheckExecutionContextRuntimeOutputMsg off
+ SignalResolutionControl "TryResolveAllWithWarning"
+ BlockPriorityViolationMsg "warning"
+ MinStepSizeMsg "warning"
+ TimeAdjustmentMsg "none"
+ MaxConsecutiveZCsMsg "error"
+ MaskedZcDiagnostic "warning"
+ IgnoredZcDiagnostic "warning"
+ SolverPrmCheckMsg "none"
+ InheritedTsInSrcMsg "none"
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+ SigSpecEnsureSampleTimeMsg "warning"
+ CheckMatrixSingularityMsg "none"
+ IntegerOverflowMsg "warning"
+ Int32ToFloatConvMsg "warning"
+ ParameterDowncastMsg "error"
+ ParameterOverflowMsg "error"
+ ParameterUnderflowMsg "none"
+ ParameterPrecisionLossMsg "warning"
+ ParameterTunabilityLossMsg "warning"
+ FixptConstUnderflowMsg "none"
+ FixptConstOverflowMsg "none"
+ FixptConstPrecisionLossMsg "none"
+ UnderSpecifiedDataTypeMsg "none"
+ UnnecessaryDatatypeConvMsg "none"
+ VectorMatrixConversionMsg "none"
+ InvalidFcnCallConnMsg "error"
+ FcnCallInpInsideContextMsg "Use local settings"
+ SignalLabelMismatchMsg "none"
+ UnconnectedInputMsg "warning"
+ UnconnectedOutputMsg "warning"
+ UnconnectedLineMsg "warning"
+ SFcnCompatibilityMsg "none"
+ FrameProcessingCompatibilityMsg "warning"
+ UniqueDataStoreMsg "none"
+ BusObjectLabelMismatch "warning"
+ RootOutportRequireBusObject "warning"
+ AssertControl "UseLocalSettings"
+ EnableOverflowDetection off
+ ModelReferenceIOMsg "none"
+ ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error"
+ ModelReferenceVersionMismatchMessage "none"
+ ModelReferenceIOMismatchMessage "none"
+ ModelReferenceCSMismatchMessage "none"
+ UnknownTsInhSupMsg "warning"
+ ModelReferenceDataLoggingMessage "warning"
+ ModelReferenceSymbolNameMessage "warning"
+ ModelReferenceExtraNoncontSigs "error"
+ StateNameClashWarn "warning"
+ SimStateInterfaceChecksumMismatchMsg "warning"
+ SimStateOlderReleaseMsg "error"
+ InitInArrayFormatMsg "warning"
+ StrictBusMsg "None"
+ BusNameAdapt "WarnAndRepair"
+ NonBusSignalsTreatedAsBus "none"
+ LoggingUnavailableSignals "error"
+ BlockIODiagnostic "none"
+ SFUnusedDataAndEventsDiag "warning"
+ SFUnexpectedBacktrackingDiag "warning"
+ SFInvalidInputDataAccessInChartInitDiag "warning"
+ SFNoUnconditionalDefaultTransitionDiag "warning"
+ SFTransitionOutsideNaturalParentDiag "warning"
+ SFUnconditionalTransitionShadowingDiag "warning"
+ }
+ Simulink.HardwareCC {
+ $ObjectID 6
+ Version "1.11.1"
+ ProdBitPerChar 8
+ ProdBitPerShort 16
+ ProdBitPerInt 32
+ ProdBitPerLong 32
+ ProdBitPerFloat 32
+ ProdBitPerDouble 64
+ ProdBitPerPointer 32
+ ProdLargestAtomicInteger "Char"
+ ProdLargestAtomicFloat "None"
+ ProdIntDivRoundTo "Undefined"
+ ProdEndianess "Unspecified"
+ ProdWordSize 32
+ ProdShiftRightIntArith on
+ ProdHWDeviceType "32-bit Generic"
+ TargetBitPerChar 8
+ TargetBitPerShort 16
+ TargetBitPerInt 32
+ TargetBitPerLong 32
+ TargetBitPerFloat 32
+ TargetBitPerDouble 64
+ TargetBitPerPointer 32
+ TargetLargestAtomicInteger "Char"
+ TargetLargestAtomicFloat "None"
+ TargetShiftRightIntArith on
+ TargetIntDivRoundTo "Undefined"
+ TargetEndianess "Unspecified"
+ TargetWordSize 32
+ TargetTypeEmulationWarnSuppressLevel 0
+ TargetPreprocMaxBitsSint 32
+ TargetPreprocMaxBitsUint 32
+ TargetHWDeviceType "Specified"
+ TargetUnknown on
+ ProdEqTarget on
+ }
+ Simulink.ModelReferenceCC {
+ $ObjectID 7
+ Version "1.11.1"
+ UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
+ CheckModelReferenceTargetMessage "error"
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+ ParallelModelReferenceErrorOnInvalidPool on
+ ParallelModelReferenceMATLABWorkerInit "None"
+ ModelReferenceNumInstancesAllowed "Multi"
+ PropagateVarSize "Infer from blocks in model"
+ ModelReferencePassRootInputsByReference on
+ ModelReferenceMinAlgLoopOccurrences off
+ PropagateSignalLabelsOutOfModel off
+ SupportModelReferenceSimTargetCustomCode off
+ }
+ Simulink.SFSimCC {
+ $ObjectID 8
+ Version "1.11.1"
+ SFSimEnableDebug on
+ SFSimOverflowDetection on
+ SFSimEcho on
+ SimBlas on
+ SimCtrlC on
+ SimExtrinsic on
+ SimIntegrity on
+ SimUseLocalCustomCode off
+ SimParseCustomCode on
+ SimBuildMode "sf_incremental_build"
+ }
+ Simulink.RTWCC {
+ $BackupClass "Simulink.RTWCC"
+ $ObjectID 9
+ Version "1.11.1"
+ Array {
+ Type "Cell"
+ Dimension 1
+ Cell "IncludeHyperlinkInReport"
+ PropName "DisabledProps"
+ }
+ SystemTargetFile "grt.tlc"
+ GenCodeOnly on
+ MakeCommand "make_rtw"
+ GenerateMakefile on
+ TemplateMakefile "grt_default_tmf"
+ GenerateReport off
+ SaveLog off
+ RTWVerbose on
+ RetainRTWFile off
+ ProfileTLC off
+ TLCDebug off
+ TLCCoverage off
+ TLCAssert off
+ ProcessScriptMode "Default"
+ ConfigurationMode "Optimized"
+ ConfigAtBuild off
+ RTWUseLocalCustomCode off
+ RTWUseSimCustomCode off
+ IncludeHyperlinkInReport off
+ LaunchReport off
+ TargetLang "C"
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+ GenerateTraceInfo off
+ GenerateTraceReport off
+ GenerateTraceReportSl off
+ GenerateTraceReportSf off
+ GenerateTraceReportEml off
+ GenerateCodeInfo off
+ GenerateSLWebview off
+ GenerateCodeMetricsReport off
+ RTWCompilerOptimization "Off"
+ CheckMdlBeforeBuild "Off"
+ CustomRebuildMode "OnUpdate"
+ Array {
+ Type "Handle"
+ Dimension 2
+ Simulink.CodeAppCC {
+ $ObjectID 10
+ Version "1.11.1"
+ Array {
+ Type "Cell"
+ Dimension 16
+ Cell "IgnoreCustomStorageClasses"
+ Cell "InsertBlockDesc"
+ Cell "SFDataObjDesc"
+ Cell "SimulinkDataObjDesc"
+ Cell "DefineNamingRule"
+ Cell "SignalNamingRule"
+ Cell "ParamNamingRule"
+ Cell "InlinedPrmAccess"
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+ Cell "CustomSymbolStrBlkIO"
+ Cell "CustomSymbolStrTmpVar"
+ Cell "CustomSymbolStrMacro"
+ PropName "DisabledProps"
+ }
+ ForceParamTrailComments off
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+ IgnoreCustomStorageClasses off
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+ Version "1.11.1"
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+ Cell "ERTCustomFileBanners"
+ Cell "GenerateSampleERTMain"
+ Cell "GenerateTestInterfaces"
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+ Cell "PurelyIntegerCode"
+ Cell "SupportNonInlinedSFcns"
+ Cell "SupportComplex"
+ Cell "SupportAbsoluteTime"
+ Cell "SupportContinuousTime"
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+ ExtModeStaticAlloc off
+ ExtModeTesting off
+ ExtModeStaticAllocSize 1000000
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+ GenerateASAP2 off
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+ Name "Configuration"
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+ ConfigPrmDlgPosition [ 400, 210, 1280, 840 ]
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+ }
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+ $PropName "ActiveConfigurationSet"
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+ }
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+ }
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+ OutDataTypeStr "Inherit: auto"
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+ }
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+ BlockType Goto
+ IconDisplay "Tag"
+ }
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+ Port "1"
+ OutputFunctionCall off
+ OutMin "[]"
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+ PortDimensions "-1"
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+ SampleTime "-1"
+ SignalType "auto"
+ SamplingMode "auto"
+ LatchByDelayingOutsideSignal off
+ LatchInputForFeedbackSignals off
+ Interpolate on
+ }
+ Block {
+ BlockType Mux
+ Inputs "4"
+ DisplayOption "none"
+ UseBusObject off
+ BusObject "BusObject"
+ NonVirtualBus off
+ }
+ Block {
+ BlockType Outport
+ Port "1"
+ OutMin "[]"
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+ LockScale off
+ BusOutputAsStruct off
+ PortDimensions "-1"
+ VarSizeSig "Inherit"
+ SampleTime "-1"
+ SignalType "auto"
+ SamplingMode "auto"
+ SourceOfInitialOutputValue "Dialog"
+ OutputWhenDisabled "held"
+ InitialOutput "[]"
+ }
+ Block {
+ BlockType Scope
+ ModelBased off
+ TickLabels "OneTimeTick"
+ ZoomMode "on"
+ Grid "on"
+ TimeRange "auto"
+ YMin "-5"
+ YMax "5"
+ SaveToWorkspace off
+ SaveName "ScopeData"
+ LimitDataPoints on
+ MaxDataPoints "5000"
+ Decimation "1"
+ SampleInput off
+ SampleTime "-1"
+ }
+ Block {
+ BlockType SubSystem
+ ShowPortLabels "FromPortIcon"
+ Permissions "ReadWrite"
+ PermitHierarchicalResolution "All"
+ TreatAsAtomicUnit off
+ CheckFcnCallInpInsideContextMsg off
+ SystemSampleTime "-1"
+ RTWFcnNameOpts "Auto"
+ RTWFileNameOpts "Auto"
+ RTWMemSecFuncInitTerm "Inherit from model"
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+ RTWMemSecDataConstants "Inherit from model"
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+ RTWMemSecDataParameters "Inherit from model"
+ SimViewingDevice off
+ DataTypeOverride "UseLocalSettings"
+ DataTypeOverrideAppliesTo "AllNumericTypes"
+ MinMaxOverflowLogging "UseLocalSettings"
+ SFBlockType "NONE"
+ Variant off
+ GeneratePreprocessorConditionals off
+ }
+ Block {
+ BlockType Sum
+ IconShape "rectangular"
+ Inputs "++"
+ CollapseMode "All dimensions"
+ CollapseDim "1"
+ InputSameDT on
+ AccumDataTypeStr "Inherit: Inherit via internal rule"
+ OutMin "[]"
+ OutMax "[]"
+ OutDataTypeStr "Inherit: Same as first input"
+ LockScale off
+ RndMeth "Floor"
+ SaturateOnIntegerOverflow on
+ SampleTime "-1"
+ }
+ Block {
+ BlockType Terminator
+ }
+ }
+ System {
+ Name "asyncip_sl_2_sc_console"
+ Location [2, 82, 1645, 997]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 247
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "usletter"
+ PaperUnits "inches"
+ TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ ReportName "simulink-default.rpt"
+ SIDHighWatermark "142"
+ Block {
+ BlockType Demux
+ Name "Demux"
+ SID "48"
+ Ports [1, 2]
+ Position [285, 116, 290, 154]
+ BackgroundColor "black"
+ ShowName off
+ Outputs "[2 1]"
+ }
+ Block {
+ BlockType Demux
+ Name "Demux1"
+ SID "49"
+ Ports [1, 5]
+ Position [375, 211, 380, 299]
+ ShowName off
+ Outputs "5"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Demux
+ Name "Demux2"
+ SID "50"
+ Ports [1, 5]
+ Position [375, 306, 380, 394]
+ ShowName off
+ Outputs "5"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType Mux
+ Name "Mux"
+ SID "51"
+ Ports [2, 1]
+ Position [465, 246, 470, 284]
+ ShowName off
+ Inputs "2"
+ DisplayOption "bar"
+ }
+ Block {
+ BlockType SubSystem
+ Name "OpComm"
+ SID "101"
+ Ports [0, 3]
+ Position [240, 138, 245, 212]
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ MaskInitialization "opmaskdisplay('maskdisplay_block',gcb,'disp(''OpComm'')');"
+ MaskDisplay "patch([0 0.5 0.7 0],[1 1 0 0],[0.7 0.75 0.9]);\npatch([1 0.53 0.73 1],[1 1 0 0],[1 0.8 0.7]);"
+ "\nplot([0 0 1 1 0],[0 1 1 0 0]);\ndisp('OpComm')\n"
+ MaskIconFrame off
+ MaskIconOpaque on
+ MaskIconRotate "none"
+ MaskPortRotate "default"
+ MaskIconUnits "autoscale"
+ System {
+ Name "OpComm"
+ Location [10, 10, 350, 130]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "usletter"
+ PaperUnits "inches"
+ TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ Block {
+ BlockType Demux
+ Name "Demux"
+ SID "102"
+ Ports [1, 3]
+ Position [150, 17, 160, 173]
+ Outputs "[3 5 5]"
+ }
+ Block {
+ BlockType Reference
+ Name "Receive"
+ SID "103"
+ Ports [0, 6]
+ Position [30, 52, 130, 133]
+ LibraryVersion "1.294"
+ SourceBlock "opal_lib/Communication/OpRecFromQNX"
+ SourceType "OPAL Receive Icon"
+ Node_num "1"
+ Acqu_Group "1"
+ Data_Width "13"
+ Synchronization on
+ Interpolation on
+ Threshold "1.0"
+ modelname "AsyncIP_sl.mdl"
+ sampletime "5e-005"
+ }
+ Block {
+ BlockType SubSystem
+ Name "busStruct"
+ SID "104"
+ Ports [3, 3]
+ Position [200, 17, 240, 173]
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ System {
+ Name "busStruct"
+ Location [484, 93, 1020, 382]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "usletter"
+ PaperUnits "inches"
+ TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ Block {
+ BlockType Inport
+ Name "In1"
+ SID "105"
+ Position [50, 52, 80, 68]
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Inport
+ Name "In2"
+ SID "106"
+ Position [50, 102, 80, 118]
+ Port "2"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Inport
+ Name "In3"
+ SID "107"
+ Position [50, 152, 80, 168]
+ Port "3"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType SubSystem
+ Name "Sub1"
+ SID "108"
+ Ports [1, 1]
+ Position [165, 42, 265, 78]
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ System {
+ Name "Sub1"
+ Location [484, 93, 1020, 382]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "usletter"
+ PaperUnits "inches"
+ TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ Block {
+ BlockType Inport
+ Name "from_signal1"
+ SID "109"
+ Position [95, 54, 125, 66]
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType BusCreator
+ Name "buscre_signal1"
+ SID "110"
+ Ports [3, 1]
+ Position [160, 120, 165, 160]
+ Inputs "3"
+ Port {
+ PortNumber 1
+ Name "signal1"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType Demux
+ Name "demux_signal1"
+ SID "111"
+ Ports [1, 3]
+ Position [160, 40, 165, 80]
+ Outputs "[1 1 1]"
+ }
+ Block {
+ BlockType From
+ Name "from2_signal1signal1"
+ SID "112"
+ Position [95, 119, 135, 131]
+ ShowName off
+ GotoTag "rtlab_tag_1"
+ Port {
+ PortNumber 1
+ Name "signal1"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType From
+ Name "from2_signal1signal2"
+ SID "113"
+ Position [95, 134, 135, 146]
+ ShowName off
+ GotoTag "rtlab_tag_2"
+ Port {
+ PortNumber 1
+ Name "signal2"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType From
+ Name "from2_signal1signal3"
+ SID "114"
+ Position [95, 149, 135, 161]
+ ShowName off
+ GotoTag "rtlab_tag_3"
+ Port {
+ PortNumber 1
+ Name "signal3"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType Goto
+ Name "goto_signal1signal1"
+ SID "115"
+ Position [190, 39, 230, 51]
+ ShowName off
+ GotoTag "rtlab_tag_1"
+ TagVisibility "local"
+ }
+ Block {
+ BlockType Goto
+ Name "goto_signal1signal2"
+ SID "116"
+ Position [190, 54, 230, 66]
+ ShowName off
+ GotoTag "rtlab_tag_2"
+ TagVisibility "local"
+ }
+ Block {
+ BlockType Goto
+ Name "goto_signal1signal3"
+ SID "117"
+ Position [190, 69, 230, 81]
+ ShowName off
+ GotoTag "rtlab_tag_3"
+ TagVisibility "local"
+ }
+ Block {
+ BlockType Outport
+ Name "goto_signal1"
+ SID "118"
+ Position [210, 134, 240, 146]
+ IconDisplay "Port number"
+ }
+ Line {
+ Name "signal1"
+ Labels [0, 0]
+ SrcBlock "buscre_signal1"
+ SrcPort 1
+ DstBlock "goto_signal1"
+ DstPort 1
+ }
+ Line {
+ Name "signal3"
+ Labels [0, 0]
+ SrcBlock "from2_signal1signal3"
+ SrcPort 1
+ DstBlock "buscre_signal1"
+ DstPort 3
+ }
+ Line {
+ Name "signal2"
+ Labels [0, 0]
+ SrcBlock "from2_signal1signal2"
+ SrcPort 1
+ DstBlock "buscre_signal1"
+ DstPort 2
+ }
+ Line {
+ Name "signal1"
+ Labels [0, 0]
+ SrcBlock "from2_signal1signal1"
+ SrcPort 1
+ DstBlock "buscre_signal1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "demux_signal1"
+ SrcPort 3
+ DstBlock "goto_signal1signal3"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "demux_signal1"
+ SrcPort 2
+ DstBlock "goto_signal1signal2"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "demux_signal1"
+ SrcPort 1
+ DstBlock "goto_signal1signal1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "from_signal1"
+ SrcPort 1
+ DstBlock "demux_signal1"
+ DstPort 1
+ }
+ }
+ }
+ Block {
+ BlockType SubSystem
+ Name "Sub2"
+ SID "119"
+ Ports [1, 1]
+ Position [165, 92, 265, 128]
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ System {
+ Name "Sub2"
+ Location [484, 93, 1020, 382]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "usletter"
+ PaperUnits "inches"
+ TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ Block {
+ BlockType Inport
+ Name "in"
+ SID "120"
+ Position [50, 52, 75, 68]
+ IconDisplay "Port number"
+ Port {
+ PortNumber 1
+ Name "signal1"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType Outport
+ Name "out"
+ SID "121"
+ Position [150, 52, 175, 68]
+ IconDisplay "Port number"
+ }
+ Line {
+ Name "signal1"
+ Labels [0, 0]
+ SrcBlock "in"
+ SrcPort 1
+ DstBlock "out"
+ DstPort 1
+ }
+ }
+ }
+ Block {
+ BlockType SubSystem
+ Name "Sub3"
+ SID "122"
+ Ports [1, 1]
+ Position [165, 142, 265, 178]
+ MinAlgLoopOccurrences off
+ PropExecContextOutsideSubsystem off
+ RTWSystemCode "Auto"
+ FunctionWithSeparateData off
+ Opaque off
+ RequestExecContextInheritance off
+ MaskHideContents off
+ System {
+ Name "Sub3"
+ Location [484, 93, 1020, 382]
+ Open off
+ ModelBrowserVisibility off
+ ModelBrowserWidth 200
+ ScreenColor "white"
+ PaperOrientation "landscape"
+ PaperPositionMode "auto"
+ PaperType "usletter"
+ PaperUnits "inches"
+ TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
+ TiledPageScale 1
+ ShowPageBoundaries off
+ ZoomFactor "100"
+ Block {
+ BlockType Inport
+ Name "from_signal1"
+ SID "123"
+ Position [95, 54, 125, 66]
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType BusCreator
+ Name "buscre_signal1"
+ SID "124"
+ Ports [2, 1]
+ Position [160, 120, 165, 160]
+ Inputs "2"
+ Port {
+ PortNumber 1
+ Name "signal1"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType Demux
+ Name "demux_signal1"
+ SID "125"
+ Ports [1, 2]
+ Position [160, 40, 165, 80]
+ Outputs "[4 1]"
+ }
+ Block {
+ BlockType From
+ Name "from2_signal1signal1"
+ SID "126"
+ Position [95, 124, 135, 136]
+ ShowName off
+ GotoTag "rtlab_tag_1"
+ Port {
+ PortNumber 1
+ Name "signal1"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType From
+ Name "from2_signal1signal2"
+ SID "127"
+ Position [95, 144, 135, 156]
+ ShowName off
+ GotoTag "rtlab_tag_2"
+ Port {
+ PortNumber 1
+ Name "signal2"
+ RTWStorageClass "Auto"
+ DataLoggingNameMode "SignalName"
+ }
+ }
+ Block {
+ BlockType Goto
+ Name "goto_signal1signal1"
+ SID "128"
+ Position [190, 44, 230, 56]
+ ShowName off
+ GotoTag "rtlab_tag_1"
+ TagVisibility "local"
+ }
+ Block {
+ BlockType Goto
+ Name "goto_signal1signal2"
+ SID "129"
+ Position [190, 64, 230, 76]
+ ShowName off
+ GotoTag "rtlab_tag_2"
+ TagVisibility "local"
+ }
+ Block {
+ BlockType Outport
+ Name "goto_signal1"
+ SID "130"
+ Position [210, 134, 240, 146]
+ IconDisplay "Port number"
+ }
+ Line {
+ Name "signal1"
+ Labels [0, 0]
+ SrcBlock "buscre_signal1"
+ SrcPort 1
+ DstBlock "goto_signal1"
+ DstPort 1
+ }
+ Line {
+ Name "signal2"
+ Labels [0, 0]
+ SrcBlock "from2_signal1signal2"
+ SrcPort 1
+ DstBlock "buscre_signal1"
+ DstPort 2
+ }
+ Line {
+ Name "signal1"
+ Labels [0, 0]
+ SrcBlock "from2_signal1signal1"
+ SrcPort 1
+ DstBlock "buscre_signal1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "demux_signal1"
+ SrcPort 2
+ DstBlock "goto_signal1signal2"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "demux_signal1"
+ SrcPort 1
+ DstBlock "goto_signal1signal1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "from_signal1"
+ SrcPort 1
+ DstBlock "demux_signal1"
+ DstPort 1
+ }
+ }
+ }
+ Block {
+ BlockType Outport
+ Name "Out1"
+ SID "131"
+ Position [350, 52, 380, 68]
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "Out2"
+ SID "132"
+ Position [350, 102, 380, 118]
+ Port "2"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "Out3"
+ SID "133"
+ Position [350, 152, 380, 168]
+ Port "3"
+ IconDisplay "Port number"
+ }
+ Line {
+ SrcBlock "Sub3"
+ SrcPort 1
+ DstBlock "Out3"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "In3"
+ SrcPort 1
+ DstBlock "Sub3"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Sub2"
+ SrcPort 1
+ DstBlock "Out2"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "In2"
+ SrcPort 1
+ DstBlock "Sub2"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Sub1"
+ SrcPort 1
+ DstBlock "Out1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "In1"
+ SrcPort 1
+ DstBlock "Sub1"
+ DstPort 1
+ }
+ }
+ }
+ Block {
+ BlockType Terminator
+ Name "dynsig"
+ SID "134"
+ Position [260, 477, 290, 493]
+ }
+ Block {
+ BlockType Terminator
+ Name "missedData"
+ SID "135"
+ Position [260, 277, 290, 293]
+ }
+ Block {
+ BlockType Terminator
+ Name "offset"
+ SID "136"
+ Position [260, 327, 290, 343]
+ }
+ Block {
+ BlockType Terminator
+ Name "samples"
+ SID "137"
+ Position [260, 427, 290, 443]
+ }
+ Block {
+ BlockType Terminator
+ Name "sim_time"
+ SID "138"
+ Position [260, 377, 290, 393]
+ }
+ Block {
+ BlockType Outport
+ Name "Out1"
+ SID "139"
+ Position [300, 32, 330, 48]
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "Out2"
+ SID "140"
+ Position [300, 82, 330, 98]
+ Port "2"
+ IconDisplay "Port number"
+ }
+ Block {
+ BlockType Outport
+ Name "Out3"
+ SID "141"
+ Position [300, 132, 330, 148]
+ Port "3"
+ IconDisplay "Port number"
+ }
+ Line {
+ SrcBlock "Demux"
+ SrcPort 3
+ DstBlock "busStruct"
+ DstPort 3
+ }
+ Line {
+ SrcBlock "Demux"
+ SrcPort 2
+ DstBlock "busStruct"
+ DstPort 2
+ }
+ Line {
+ SrcBlock "Demux"
+ SrcPort 1
+ DstBlock "busStruct"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "busStruct"
+ SrcPort 3
+ DstBlock "Out3"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "busStruct"
+ SrcPort 2
+ DstBlock "Out2"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "busStruct"
+ SrcPort 1
+ DstBlock "Out1"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Receive"
+ SrcPort 1
+ DstBlock "Demux"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Receive"
+ SrcPort 6
+ DstBlock "dynsig"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Receive"
+ SrcPort 5
+ DstBlock "samples"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Receive"
+ SrcPort 4
+ DstBlock "sim_time"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Receive"
+ SrcPort 3
+ DstBlock "offset"
+ DstPort 1
+ }
+ Line {
+ SrcBlock "Receive"
+ SrcPort 2
+ DstBlock "missedData"
+ DstPort 1
+ }
+ }
+ }
+ Block {
+ BlockType Sum
+ Name "Subtract"
+ SID "53"
+ Ports [2, 1]
+ Position [615, 297, 645, 328]
+ ZOrder -31
+ Inputs "+-"
+ InputSameDT off
+ OutDataTypeStr "Inherit: Inherit via internal rule"
+ SaturateOnIntegerOverflow off
+ }
+ Block {
+ BlockType Display
+ Name "errors"
+ SID "54"
+ Ports [1]
+ Position [385, 82, 455, 128]
+ BackgroundColor "yellow"
+ FontName "Arial"
+ FontSize 8
+ Decimation "5000"
+ Lockdown off
+ }
+ Block {
+ BlockType Scope
+ Name "message 1"
+ SID "55"
+ Ports [1]
+ Position [515, 179, 545, 211]
+ BackgroundColor "yellow"
+ Floating off
+ Location [826, 517, 1334, 952]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ List {
+ ListType ScopeGraphics
+ FigureColor "[0.5 0.5 0.5]"
+ AxesColor "[0 0 0]"
+ AxesTickColor "[1 1 1]"
+ LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
+ LineStyles "-|-|-|-|-|-"
+ LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
+ MarkerStyles "none|none|none|none|none|none"
+ }
+ YMin "-1.75"
+ YMax "4"
+ SaveName "ScopeData1"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Scope
+ Name "message 2"
+ SID "56"
+ Ports [1]
+ Position [515, 249, 545, 281]
+ BackgroundColor "yellow"
+ Floating off
+ Location [826, 517, 1334, 952]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ List {
+ ListType ScopeGraphics
+ FigureColor "[0.5 0.5 0.5]"
+ AxesColor "[0 0 0]"
+ AxesTickColor "[1 1 1]"
+ LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
+ LineStyles "-|-|-|-|-|-"
+ LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
+ MarkerStyles "none|none|none|none|none|none"
+ }
+ YMin "-1.75"
+ YMax "4"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Scope
+ Name "message 3"
+ SID "57"
+ Ports [1]
+ Position [520, 394, 550, 426]
+ BackgroundColor "yellow"
+ Floating off
+ Location [826, 517, 1334, 952]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ List {
+ ListType ScopeGraphics
+ FigureColor "[0.5 0.5 0.5]"
+ AxesColor "[0 0 0]"
+ AxesTickColor "[1 1 1]"
+ LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
+ LineStyles "-|-|-|-|-|-"
+ LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
+ MarkerStyles "none|none|none|none|none|none"
+ }
+ YMin "-1.75"
+ YMax "4"
+ SaveName "ScopeData2"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Scope
+ Name "message 4"
+ SID "58"
+ Ports [1]
+ Position [695, 299, 725, 331]
+ BackgroundColor "yellow"
+ Floating off
+ Location [826, 517, 1334, 952]
+ Open off
+ NumInputPorts "1"
+ List {
+ ListType AxesTitles
+ axes1 "%<SignalLabel>"
+ }
+ List {
+ ListType ScopeGraphics
+ FigureColor "[0.5 0.5 0.5]"
+ AxesColor "[0 0 0]"
+ AxesTickColor "[1 1 1]"
+ LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
+ LineStyles "-|-|-|-|-|-"
+ LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
+ MarkerStyles "none|none|none|none|none|none"
+ }
+ YMin "-1.75"
+ YMax "4"
+ SaveName "ScopeData3"
+ DataFormat "StructureWithTime"
+ SampleTime "0"
+ }
+ Block {
+ BlockType Display
+ Name "reception status"
+ SID "59"
+ Ports [1]
+ Position [390, 148, 450, 172]
+ BackgroundColor "yellow"
+ FontName "Arial"
+ FontSize 8
+ Decimation "5000"
+ Lockdown off
+ }
+ Block {
+ BlockType SubSystem
+ Name "rtlab_send_subsystem"
+ SID "142"
+ Ports []
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diff --git a/clients/opal/models/AsyncIP_sl/report/temp/host_report.xml b/clients/opal/models/AsyncIP_sl/report/temp/host_report.xml
new file mode 100644
index 000000000..cf756f9ed
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/report/temp/host_report.xml
@@ -0,0 +1,3184 @@
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index 000000000..3ffe5f50b
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+ if (noXSLT)
+ {
+ alert("Sorry, this doesn't work in your browser");
+ return;
+ }
+
+ urlXML = get_report_filename()
+ urlXSL = "tree/tree.xsl";
+ target = document.getElementById("xmlContent");
+
+ DefaultTreeMode = defTreeMode;
+ Transform();
+}
+
+function get_report_filename()
+{
+ var filename;
+ var i;
+ var j;
+ var c;
+ var fileId;
+
+ filename = document.URL;
+ j = filename.length;
+ k = 0
+ for (i=filename.length-1; i>=0; i--)
+ {
+
+ c = filename.charAt(i)
+
+ if ( (j == filename.length) && (c == '.') )
+ {
+ j = i;
+ }
+ if ( (c == '/') || (c == '\\') )
+ {
+ break;
+ }
+ }
+ if (i != -1)
+ {
+ return 'xml/' + filename.substring(i+1,j) + '.xml'
+ }
+ else
+ {
+ return 'xml/report.xml'
+ }
+}
+
+
+function CreateDocument()
+{
+ var doc = null;
+
+ if (platformMoz)
+ {
+ doc = document.implementation.createDocument('', '', null);
+ }
+ else if (platformIE6)
+ {
+ doc = new ActiveXObject('Msxml2.FreeThreadedDOMDocument.' + msxmlVersion);
+ }
+ return doc;
+}
+
+function Transform()
+{
+
+
+ docXML = CreateDocument();
+ docXSL = CreateDocument();
+ if (platformMoz)
+ {
+ docXML.addEventListener('load', DoLoadXSL, false);
+ docXML.load(urlXML);
+ }
+ else if (platformIE6)
+ {
+ docXML.async = false;
+ docXML.load(urlXML);
+ docXSL.async = false;
+ docXSL.load(urlXSL);
+ DoTransform();
+ }
+}
+
+function DoLoadXSL()
+{
+ if (platformMoz)
+ {
+ docXSL.addEventListener('load', DoTransform, false);
+ docXSL.load(urlXSL);
+ }
+}
+
+function DoTransform()
+{
+ if (platformMoz)
+ {
+ processor = new XSLTProcessor();
+ processor.importStylesheet(docXSL);
+
+ processor.setParameter(null, "DefaultTreeMode", DefaultTreeMode);
+
+ var fragment = processor.transformToFragment(docXML, document);
+ while (target.hasChildNodes())
+ {
+ target.removeChild(target.childNodes[0]);
+ }
+ target.appendChild(fragment);
+ }
+ else if (platformIE6)
+ {
+ cache.stylesheet = docXSL;
+
+ processor = cache.createProcessor();
+ processor.input = docXML;
+ processor.addParameter("DefaultTreeMode", DefaultTreeMode);
+
+ processor.transform();
+ target.innerHTML = processor.output;
+ }
+
+}
+
+//----------------------------------------------------
+function cancelBuble(event)
+{
+ if (window.event)
+ {
+ window.event.cancelBubble = true;
+ window.event.returnValue = false;
+ }
+ else if (event && event.preventDefault && event.stopPropagation)
+ {
+ event.preventDefault();
+ event.stopPropagation();
+ }
+}
+
+//----------------------------------------------------
+function clickOnEntity(event, entity)
+{
+ // cancel buble
+ cancelBuble(event)
+
+ if(entity.getAttribute("open") == "false")
+ {
+ expand(entity)
+ }
+ else
+ {
+ collapse(entity)
+ }
+
+ // cancel buble
+ cancelBuble(event)
+
+}
+
+//----------------------------------------------------
+function expand(entity)
+{
+ // Variable declarations
+ var oImage
+ var i
+
+
+ // Get class name
+ if (platformMoz)
+ cl = entity.getAttribute("CLASS");
+ else if (platformIE6)
+ cl = entity.className
+
+ // Get and change image
+ if (cl == "item")
+ {
+ oImage = entity.childNodes[0].childNodes[0].childNodes[0].childNodes[0].childNodes[0]
+ oImage.src = entity.getAttribute("openimage")
+ }
+
+ for(i=0; i < entity.childNodes.length; i++)
+ {
+ node = entity.childNodes[i]
+ if((node.tagName == "DIV") || (node.tagName == "div"))
+ {
+ // Display child
+ node.style.display = "block"
+ }
+ }
+ entity.setAttribute("open","true")
+}
+
+//----------------------------------------------------
+function collapse(entity)
+{
+
+ // Variable declarations
+ var oImage
+ var i
+
+ // Get class name
+ if (platformMoz)
+ cl = entity.getAttribute("CLASS");
+ else if (platformIE6)
+ cl = entity.className
+
+ // Get and change image
+ if (cl == "item")
+ {
+ oImage = entity.childNodes[0].childNodes[0].childNodes[0].childNodes[0].childNodes[0]
+ oImage.src = entity.getAttribute("closeimage")
+ }
+ for(i=0; i < entity.childNodes.length; i++)
+ {
+ node = entity.childNodes[i]
+ if((node.tagName == "DIV") || (node.tagName == "div"))
+ {
+ // Display child
+ node.style.display = "none"
+ }
+ }
+
+ entity.setAttribute("open","false")
+}
+
+//----------------------------------------------------
+function expandAllFromString(entityString)
+{
+ entity = document.getElementById(entityString);
+ expandAll(entity, 1)
+}
+
+function expandAll(entity, isRoot)
+{
+ var i
+ // expand current node
+ expand(entity)
+
+ // expand children
+ for(i=0; i < entity.childNodes.length; i++)
+ {
+ if ((entity.childNodes[i].tagName == "DIV") || (entity.childNodes[i].tagName == "div"))
+ {
+ expandAll(entity.childNodes[i], 0)
+ }
+ }
+}
+
+//----------------------------------------------------
+
+function collapseAllFromString(entityString)
+{
+ entity = document.getElementById(entityString);
+ collapseAll(entity, 1)
+}
+
+function collapseAll(entity, isRoot)
+{
+
+ var i
+ // collapse current node
+ idStr = entity.id
+ if ( isRoot == 0 )
+ {
+ collapse(entity)
+ }
+ // expand children
+ for(i=0; i < entity.childNodes.length; i++)
+ {
+ if((entity.childNodes[i].tagName == "DIV") || (entity.childNodes[i].tagName == "div"))
+ {
+ collapseAll(entity.childNodes[i], 0)
+ }
+ }
+}
\ No newline at end of file
diff --git a/clients/opal/models/AsyncIP_sl/report/tree/tree.xsl b/clients/opal/models/AsyncIP_sl/report/tree/tree.xsl
new file mode 100644
index 000000000..0cfb88967
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/report/tree/tree.xsl
@@ -0,0 +1,249 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
+<xsl:output method="html" indent="yes" encoding="iso-8859-1"/>
+
+<!-- To display treeview as expanded or minimized use external variable 'DefaultTreeMode' = 'expand' or 'minize'-->
+<xsl:param name="DefaultTreeMode" select="'expand'"/>
+
+<!-- _____ ITEM ________________________________________-->
+<xsl:template match="item">
+
+ <!-- REPORT ITEM (ROOT ITEM) -->
+ <xsl:if test="count(ancestor::item)=0">
+ <h1>RT-LAB Report</h1>
+ <xsl:apply-templates select="item"/>
+ </xsl:if>
+
+ <!-- SECTION ITEM (SECOND LEVEL ITEM) -->
+ <xsl:if test="(count(ancestor::item)=1)">
+
+ <h2>
+ <xsl:value-of select="concat(translate(substring(@name,1,1),'abcdefghijklmnopqrstuvwxyz','ABCDEFGHIJKLMNOPQRSTUVWXYZ'),substring(@name,2))"/>
+ </h2>
+ <hr class="hidescreen" style="border:1px" width="100%"/>
+
+ <table class="hideprint" border="0" cellspacing="0" cellpadding="0">
+ <col width="0%"/>
+ <col width="0%"/>
+ <col width="100%"/>
+ <tbody>
+ <tr>
+ <td>
+ <div class="bOut" onmouseover="swapClass(this, 'bOver')" onmouseout="swapClass(this, 'bOut')">
+ <xsl:attribute name="onclick">
+ expandAllFromString('<xsl:value-of select="@name"/>')
+ </xsl:attribute>
+ Expand
+ </div>
+ </td>
+ <td>
+ <div class="bOut" onmouseover="swapClass(this, 'bOver')" onmouseout="swapClass(this, 'bOut')">
+ <xsl:attribute name="onclick">
+ collapseAllFromString('<xsl:value-of select="@name"/>')
+ </xsl:attribute>
+ Minimize
+ </div>
+ </td>
+ <td>
+ <div class="bOut"><br/></div>
+ </td>
+ </tr>
+ </tbody>
+ </table>
+ <div style="padding-top: 8px;">
+ <xsl:attribute name="id"><xsl:value-of select="@name"/></xsl:attribute>
+ <xsl:apply-templates select="property"/>
+ <xsl:apply-templates select="textlog"/>
+ <xsl:apply-templates select="item"/>
+ </div>
+ </xsl:if>
+
+
+ <!-- ITEM -->
+ <xsl:if test="count(ancestor::item)>1">
+ <DIV CLASS="item" onclick="clickOnEntity(event, this);" onselectstart="return false" ondragstart="return false">
+
+ <xsl:attribute name="id"><xsl:value-of select="@name"/></xsl:attribute>
+
+ <!-- Add open attribute to DIV -->
+ <xsl:choose>
+ <xsl:when test="$DefaultTreeMode='minimize'">
+ <xsl:attribute name="open">false</xsl:attribute>
+ </xsl:when>
+ <xsl:otherwise>
+ <xsl:attribute name="open">true</xsl:attribute>
+ </xsl:otherwise>
+ </xsl:choose>
+
+ <!-- Add style attribute to DIV -->
+ <xsl:attribute name="STYLE">
+ padding-left: 20px;
+ cursor: pointer;
+ <xsl:if test="(count(ancestor::item)>2) and ($DefaultTreeMode='minimize')">
+ display: none;
+ </xsl:if>
+ </xsl:attribute>
+
+ <!-- Add openImage attribute to DIV -->
+ <xsl:attribute name="openImage">
+ images/openitem.gif
+ </xsl:attribute>
+
+ <!-- Add closeImage attribute to DIV -->
+ <xsl:attribute name="closeImage">
+ images/closeitem.gif
+ </xsl:attribute>
+
+ <!-- Add table -->
+ <table border="0" cellspacing="0" cellpadding="0">
+
+ <!-- Add row to the table -->
+ <tr>
+
+ <!-- Add cell element to the row -->
+ <td valign="middle">
+
+ <!-- Add image to the cell -->
+
+ <xsl:choose>
+ <xsl:when test="$DefaultTreeMode='minimize'">
+ <img border="0" id="image" SRC="images/closeitem.gif">
+ </img>
+ </xsl:when>
+ <xsl:otherwise>
+ <img border="0" id="image" SRC="images/openitem.gif">
+ </img>
+ </xsl:otherwise>
+ </xsl:choose>
+ </td>
+
+ <!-- Add cell element to the row -->
+ <td valign="middle"
+ nowrap="true"
+ class="notsel"
+ onmouseover="swapClass(this, 'sel')"
+ onmouseout="swapClass(this, 'notsel')">
+ <!-- Add text to the cell -->
+ <xsl:value-of select="@name"/>
+ </td>
+ </tr>
+ </table>
+
+ <!-- Display sub element -->
+ <xsl:apply-templates select="property"/>
+ <xsl:apply-templates select="textlog"/>
+ <xsl:apply-templates select="item"/>
+
+ </DIV>
+ </xsl:if>
+</xsl:template>
+
+<!-- PROPERTY -->
+<xsl:template match="property">
+ <DIV CLASS="property" onclick="cancelBuble(event);" onselectstart="return false" ondragstart="return false">
+
+ <!-- Add open attribute to DIV -->
+ <xsl:choose>
+ <xsl:when test="$DefaultTreeMode='minimize'">
+ <xsl:attribute name="open">false</xsl:attribute>
+ </xsl:when>
+ <xsl:otherwise>
+ <xsl:attribute name="open">true</xsl:attribute>
+ </xsl:otherwise>
+ </xsl:choose>
+
+ <!-- Add style attribute to DIV -->
+ <xsl:attribute name="STYLE">
+ padding-left: 20px;
+ cursor: pointer;
+ <xsl:if test="(count(ancestor::item)>2) and ($DefaultTreeMode='minimize')">
+ display: none;
+ </xsl:if>
+ </xsl:attribute>
+
+ <!-- Add table -->
+ <table border="0" cellspacing="0" cellpadding="0">
+
+ <!-- Add row to the table -->
+ <tr>
+
+ <!-- Add cell element to the row -->
+ <td valign="middle">
+
+ <!-- Add image to the cell -->
+ <img border="0" id="image" SRC="images/property.gif">
+ </img>
+ </td>
+
+ <!-- Add cell element to the row -->
+ <td valign="middle"
+ class="notsel"
+ onmouseover="swapClass(this, 'sel')"
+ onmouseout="swapClass(this, 'notsel')"
+ nowrap="true">
+
+ <!-- Add text to the cell -->
+ <xsl:if test="not(translate(@name,' ','')='')">
+ <xsl:value-of select="@name"/>=
+ </xsl:if>
+ <xsl:value-of select="value"/>
+
+ </td>
+ </tr>
+ </table>
+ </DIV>
+</xsl:template>
+
+<!-- TEXTLOG -->
+<xsl:template match="textlog">
+ <DIV CLASS="textlog" onclick="cancelBuble(event);" onselectstart="return false" ondragstart="return false">
+ <!-- Add open attribute to DIV -->
+ <xsl:choose>
+ <xsl:when test="$DefaultTreeMode='minimize'">
+ <xsl:attribute name="open">false</xsl:attribute>
+ </xsl:when>
+ <xsl:otherwise>
+ <xsl:attribute name="open">true</xsl:attribute>
+ </xsl:otherwise>
+ </xsl:choose>
+
+
+ <!-- Add style attribute to DIV -->
+ <xsl:attribute name="STYLE">
+ padding-left: 20px;
+ cursor: pointer;
+ <xsl:if test="(count(ancestor::item)>2) and ($DefaultTreeMode='minimize')">
+ display: none;
+ </xsl:if>
+ </xsl:attribute>
+
+ <!-- Add section -->
+
+ <table>
+ <div style="padding-top: 4px; padding-right: 10px;">
+ <!-- Display log file -->
+ <xsl:call-template name="replaceBackSlashN">
+ <xsl:with-param name="string" select="."/>
+ </xsl:call-template>
+ </div>
+ </table>
+ </DIV>
+</xsl:template>
+
+<xsl:template name="replaceBackSlashN">
+ <xsl:param name="string"/>
+ <xsl:choose>
+ <xsl:when test="contains($string,' ')">
+ <xsl:value-of select="substring-before($string,' ')"/>
+ <br/>
+ <xsl:call-template name="replaceBackSlashN">
+ <xsl:with-param name="string" select="substring-after($string,' ')"/>
+ </xsl:call-template>
+ </xsl:when>
+ <xsl:otherwise>
+ <xsl:value-of select="$string"/>
+ </xsl:otherwise>
+ </xsl:choose>
+</xsl:template>
+
+</xsl:stylesheet>
\ No newline at end of file
diff --git a/clients/opal/models/AsyncIP_sl/report/xml/AsyncIP_sl.xml b/clients/opal/models/AsyncIP_sl/report/xml/AsyncIP_sl.xml
new file mode 100644
index 000000000..f39406aaf
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/report/xml/AsyncIP_sl.xml
@@ -0,0 +1,4776 @@
+<?xml version="1.0" encoding="utf-8"?>
+<item name="report">
+ <item name="general">
+ <property name="User">
+ <value>
+ ACS
+ </value>
+ </property>
+ <property name="Command station">
+ <value>
+ ACS
+ </value>
+ </property>
+ <property name="Date">
+ <value>
+ Wed, 28 May 2014 13:09:36
+ </value>
+ </property>
+ </item>
+ <item name="diagnostic">
+ <item name="Development">
+ <item name="Target">
+ <item name="Localhost">
+ <item name="localdomain 137:226:160:69">
+ <item name="Hardware system">
+ <item name="Memory">
+ <property name="Active">
+ <value>
+ 345928 kB
+ </value>
+ </property>
+ <property name="Active(anon)">
+ <value>
+ 8040 kB
+ </value>
+ </property>
+ <property name="Active(file)">
+ <value>
+ 337888 kB
+ </value>
+ </property>
+ <property name="AnonPages">
+ <value>
+ 6896 kB
+ </value>
+ </property>
+ <property name="Bounce">
+ <value>
+ 3900 kB
+ </value>
+ </property>
+ <property name="Buffers">
+ <value>
+ 202412 kB
+ </value>
+ </property>
+ <property name="Cached">
+ <value>
+ 547580 kB
+ </value>
+ </property>
+ <property name="CommitLimit">
+ <value>
+ 7173860 kB
+ </value>
+ </property>
+ <property name="Committed_AS">
+ <value>
+ 14588 kB
+ </value>
+ </property>
+ <property name="DirectMap2M">
+ <value>
+ 907264 kB
+ </value>
+ </property>
+ <property name="DirectMap4k">
+ <value>
+ 4088 kB
+ </value>
+ </property>
+ <property name="Dirty">
+ <value>
+ 5388 kB
+ </value>
+ </property>
+ <property name="HighFree">
+ <value>
+ 4749896 kB
+ </value>
+ </property>
+ <property name="HighTotal">
+ <value>
+ 5312008 kB
+ </value>
+ </property>
+ <property name="Inactive">
+ <value>
+ 410964 kB
+ </value>
+ </property>
+ <property name="Inactive(anon)">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ <property name="Inactive(file)">
+ <value>
+ 410964 kB
+ </value>
+ </property>
+ <property name="LowFree">
+ <value>
+ 533868 kB
+ </value>
+ </property>
+ <property name="LowTotal">
+ <value>
+ 842588 kB
+ </value>
+ </property>
+ <property name="Mapped">
+ <value>
+ 4964 kB
+ </value>
+ </property>
+ <property name="MemFree">
+ <value>
+ 5283764 kB
+ </value>
+ </property>
+ <property name="MemTotal">
+ <value>
+ 6154596 kB
+ </value>
+ </property>
+ <property name="Mlocked">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ <property name="NFS_Unstable">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ <property name="PageTables">
+ <value>
+ 588 kB
+ </value>
+ </property>
+ <property name="SReclaimable">
+ <value>
+ 50892 kB
+ </value>
+ </property>
+ <property name="SUnreclaim">
+ <value>
+ 11096 kB
+ </value>
+ </property>
+ <property name="Slab">
+ <value>
+ 61988 kB
+ </value>
+ </property>
+ <property name="SwapCached">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ <property name="SwapFree">
+ <value>
+ 4096564 kB
+ </value>
+ </property>
+ <property name="SwapTotal">
+ <value>
+ 4096564 kB
+ </value>
+ </property>
+ <property name="Unevictable">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ <property name="VmallocChunk">
+ <value>
+ 80348 kB
+ </value>
+ </property>
+ <property name="VmallocTotal">
+ <value>
+ 122880 kB
+ </value>
+ </property>
+ <property name="VmallocUsed">
+ <value>
+ 4300 kB
+ </value>
+ </property>
+ <property name="Writeback">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ <property name="WritebackTmp">
+ <value>
+ 0 kB
+ </value>
+ </property>
+ </item>
+ <item name="Processors">
+ <item name="Processor 0">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 1">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 10">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 10
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 11">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 1
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 11
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 2">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 2
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 3">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 3
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
+ <property name="Vendor ID">
+ <value>
+ GenuineIntel
+ </value>
+ </property>
+ </item>
+ <item name="Processor 4">
+ <property name="Cache size">
+ <value>
+ 12288 KB
+ </value>
+ </property>
+ <property name="Model name">
+ <value>
+ Intel(R) Xeon(R) CPU X5690 @ 3.47GHz
+ </value>
+ </property>
+ <property name="Physical ID">
+ <value>
+ 0
+ </value>
+ </property>
+ <property name="Processor ID">
+ <value>
+ 4
+ </value>
+ </property>
+ <property name="Speed">
+ <value>
+ 3466.473mhz
+ </value>
+ </property>
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+-------------------- Starting compilation --------------------
+Start at : Wednesday, May 28, 2014, 12:53:31
+
+The current RT-LAB version is: v10.5.9.356
+The current model is: D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl.mdl
+The current host platform is: XP/Vista/7
+The current target platform is: Redhat
+The current compiler is: Automatic
+
+Preparing original model for code separation and generation...
+
+The current Matlab version is: v7.13 (32 Bit)
+
+
+Diagnostics:
+
+Reported by: RT-LAB
+Source : AsyncIP_sl
+Message : Warning: Block Reduction Optimization is set to ON. Real Time Workshop will optimize and remove some
+ unused blocks in the model. Those signals might not be visible with Rt-Lab Dynamic Acquisition after
+ compilation. This option can be changed in the Simulink model : Simulation/Configuration Parameters/Optimization
+
+
+RtlabInfo not loaded
+Separating RT-LAB model (number of RT subsystems = 1, console detected).
+Separating RT-LAB subsystem 'sm_ip_test'.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+Separating RT-LAB subsystem 'sc_console'.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
+
+Model preparation and separation duration : 00h:00m:07s
+-------------------- Completed successfully --------------------
+
+-------------------- Generating C code --------------------
+
+Using System Target File (TLC file) : rtlab_rtmodel.tlc...
+
+Using Template Makefile (TMF file) : rtlab_rtmodel.tmf...
+
+-------------------- Generating asyncip_sl_1_sm_ip_test C code --------------------
+Calling RTW Make Command make_rtw...
+### Starting build procedure for model: asyncip_sl_1_sm_ip_test
+### Generating code into build folder: D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\asyncip_sl_1_sm_ip_test_rtlab
+
+### Invoking Target Language Compiler on asyncip_sl_1_sm_ip_test.rtw
+### Using System Target File: C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tlc
+### Loading TLC function libraries
+.....
+### Initial pass through model to cache user defined code
+.....
+### Caching model source code
+...................................................................
+### Writing header file asyncip_sl_1_sm_ip_test.h
+### Writing header file asyncip_sl_1_sm_ip_test_types.h
+.
+### Writing header file rtwtypes.h
+### Writing source file asyncip_sl_1_sm_ip_test.c
+### Writing header file asyncip_sl_1_sm_ip_test_private.h
+.
+### Writing header file rtmodel.h
+### Writing source file asyncip_sl_1_sm_ip_test_data.c
+### Writing header file rt_nonfinite.h
+.
+### Writing source file rt_nonfinite.c
+### Writing header file rt_defines.h
+.
+### Writing header file rtGetInf.h
+### Writing source file rtGetInf.c
+### Writing header file rtGetNaN.h
+.
+### Writing source file rtGetNaN.c
+### TLC code generation complete.
+### Creating model mapping file asyncip_sl_1_sm_ip_test.map using map_r2011a.tlc
+...............................### Creating project marker file: rtw_proj.tmw
+.
+### Processing Template Makefile: C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf
+### Wrapping unrecognized make command (angle brackets added)
+### <make>
+### in default batch file
+### Creating asyncip_sl_1_sm_ip_test.mk from C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf
+### Successful completion of code generation for model: asyncip_sl_1_sm_ip_test
+
+
+asyncip_sl_1_sm_ip_test : Generating C code duration : 00h:00m:06s
+Generating C code total duration : 00h:00m:06s
+
+-------------------- Completed successfully --------------------
+
+-------------------- Creating the parameter database --------------------
+
+Parameter(s) with more than 20 values will be disabled.
+Use PARAM_VECTOR_SIZE_LIMIT environment variable to modify this limit.
+Parameter database creation duration: 00h:00m:00s
+-------------------- Parameter database created successfully --------------------
+
+
+-------------------- Creating the signals database --------------------
+
+Signal(s) with more than 20 values will be disabled.
+Use SIGNALS_VECTOR_SIZE_LIMIT environment variable to modify this limit.
+Signal database creation duration: 00h:00m:00s
+-------------------- Signal database created successfully --------------------
+
+
+-------------------- Transferring the generated C code --------------------
+
+Connecting to 137.226.160.69 ... OK.
+
+Setting remote directory to /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/... OK.
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink/rtw/c/common/linux32.opt ... OK.
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink/rtw/c/common/posix.rules ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\target_precompile.py ... Failed.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test*.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtGet* ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.mk ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.prm ... Failed.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.reg ... Failed.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rt_*.* ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtwtypes.* ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtmodel.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\drive_asyncip_sl_1_sm_ip_test*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\drive_asyncip_sl_1_sm_ip_test*.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\Opal*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.h ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.mk ... OK.
+
+Transferring common RT-LAB files:
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\include_target\*.h ... OK.
+Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\simulink\rtw\c\common\model_main.c ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalCore.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalUtils_redhawk.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalUtils.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalOhci.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libirc.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libimf.a ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\simulink\libR2011b\redhawk\libOpalRTE*.a ... OK.
+
+Transferring user extra files:
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP.c ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP.mk ... OK.
+Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIPUtils.h ... OK.
+Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalAsyncApiCore.a ... OK.
+
+File transfer duration : 00h:00m:02s
+-------------------- Completed successfully --------------------
+
+-------------------- Building the generated C code --------------------
+
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_precompile.py ... done
+Removing relative includes from ./../asyncip_sl_sm_ip_test/model_main.c ... Done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_precompile.py ... done
+-------------------- Building asyncip_sl_1_sm_ip_test --------------------
+/usr/bin/make -f AsyncIP.mk
+make[1]: Entering directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+opicc -c -O -D_GNU_SOURCE -I. -c -o AsyncIP.o AsyncIP.c
+AsyncIP.c(167): warning #167: argument of type "int *" is incompatible with parameter of type "unsigned int *"
+ if((n = OpalWaitForAsyncSendRequest (&SendID)) != EOK)
+ ^
+
+opicpc -L. -o AsyncIP AsyncIP.o -lOpalAsyncApiCore -lOpalCore -lOpalUtils -lpthread -lm -ldl -lutil -lrt
+chmod 777 AsyncIP
+### Created executable: AsyncIP
+make[1]: Leaving directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+/usr/bin/make -f asyncip_sl_1_sm_ip_test.mk
+make[1]: Entering directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+rm -f asyncip_sl_1_sm_ip_test
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils asyncip_sl_1_sm_ip_test.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils model_main.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_sim.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils asyncip_sl_1_sm_ip_test_data.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rtGetInf.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rtGetNaN.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_logging.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_matrx.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rt_nonfinite.c
+opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_printf.c
+### Linking ...
+opicpc -Wl,-rpath=/usr/opalrt/v10.5.9.356/common/bin -Wl,-rpath='/opt/intel/Compiler/11.1/072/lib/ia32' -Wl,-rpath='/opt/intel/Compiler/11.1/056/lib/ia32' -diag-disable remark -L. -L/usr/opalrt/v10.5.9.356/RT-LAB/lib -L/usr/opalrt/v10.5.9.356/common/lib -L/usr/opalrt/v10.5.9.356/common/lib/redhawk -L/usr/opalrt/v10.5.9.356/common/bin -L/usr/opalrt/externals/lib -L/usr/matlab/v7.13/toolbox/dspblks/lib/redhawk -L/usr/matlab/v7.13/toolbox/simscape/lib/redhawk -o asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test.o model_main.o rt_sim.o asyncip_sl_1_sm_ip_test_data.o rtGetInf.o rtGetNaN.o rt_logging.o rt_matrx.o rt_nonfinite.o rt_printf.o -lOpalAsyncApiR2011b -lOpalAsyncApiCore -lOpalSfunR2011b -lOpalR2011b -lBlocksRT-2011b -lOpalCore -lOpalOhci -lOpalCore -llicenseRH32 -lSystem -lPlatform -lFramework -lMatio -lOpal -lInfrastructure -lNumeric -lSimulink -lNetwork -lOpalUtils -ldspblks -lsimscape -lpthread -lm -ldl -lutil -lrt /usr/matlab/v7.13/rtw/c/libsrc/rtwlibr_redhawk.a
+chmod a+x asyncip_sl_1_sm_ip_test
+### Created executable: asyncip_sl_1_sm_ip_test
+make[1]: Leaving directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
+
+asyncip_sl_1_sm_ip_test : Building subsystem duration : 00h:00m:01s
+
+Building model total duration : 00h:00m:01s
+-------------------- Completed successfully --------------------
+
+-------------------- Transferring the built model --------------------
+
+Connecting to 137.226.160.69 ... OK.
+Transferring in binary mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test ... OK.
+Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/compilation_target_report.xml ... OK.
+Transferring in binary mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/AsyncIP ... OK.
+
+File transfer duration : 00h:00m:01s
+-------------------- Completed successfully --------------------
+
+End at : Wednesday, May 28, 2014, 12:53:50
+
+Compilation duration : 00h:00m:19s
+
+
+ </value>
+ </textlog>
+ </item>
+ </item>
+ </item>
+ <item name="Run">
+ <item name="Target">
+ <item name="Load">
+ <item name="sm_ip_test">
+ <textlog name="sm_ip_test">
+ <value>
+
+--------------- Transferring files ... ------------------------------
+
+Transferring in binary mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test ... OK.
+
+--------------- Done transferring files -----------------------------
+
+
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_preload.py ... done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_preload.py ... done
+ Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
+ 12 CPUs active on this Computer
+ libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
+ Highest active CPU: 12
+ Subsystem sm_ip_test allocates 1 cores.
+ model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
+ Monitoring is enabled
+ RECV: connection to host established
+ SEND: connection to host established
+ Display of standard output will be disabled
+AsyncIP: Version : Opal-RT_20060524
+AsyncIP: Protocol : UDP/IP
+AsyncIP: Remote Address : 137.226.160.91
+AsyncIP: Remote Port : 10200
+AsyncIP: Local Port : 10201
+AsyncIP: SendToIPPort thread started
+AsyncIP: RecvFromIPPort thread started
+ SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
+ Synchronized with software timer.
+ Real-time SingleTasking mode.
+ RT-LAB license ok. Unlimited time license.
+ Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
+ [0]: PAUSE mode, IO set to pause value.
+ Total of 0 Overrun detected.
+ Wed May 28 12:54:01 2014
+
+Starting transfer of /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/opasyncip_sl_sm_ip_test_0.snap...
+Transfer of /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/opasyncip_sl_sm_ip_test_0.snap OK
+ [1]: RUN mode, IO set to run value.
+ Synchronized step size = 50 us.
+ Wed May 28 12:54:24 2014
+
+ Main priority set to 99
+AsyncIP: SendToIPPort: Finished
+ [17891814]: Reset
+ Total of 0 Overrun detected.
+ Wed May 28 13:09:18 2014
+
+AsyncIP: RecvFromIPPort: Finished
+ Reset done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_postreset.py ... done
+Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_postreset.py ... done
+
+
+--------------- Retrieving files ... ---------------------------------
+
+Setting local directory to D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\asyncip_sl_sm_ip_test\OpREDHAWKtarget\... OK.
+Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test_147_125401.log ... OK.
+Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/target_report.xml ... OK.
+
+--------------- Done retrieving files --------------------------------
+
+ </value>
+ </textlog>
+ </item>
+ </item>
+ </item>
+ </item>
+ </item>
+</item>
diff --git a/clients/opal/models/AsyncIP_sl/report/xml/report.xml b/clients/opal/models/AsyncIP_sl/report/xml/report.xml
new file mode 100644
index 000000000..5b023ffb2
--- /dev/null
+++ b/clients/opal/models/AsyncIP_sl/report/xml/report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<item name="report">
+ <item name="general">
+ <property name="User">
+ <value>
+ UserName
+ </value>
+ </property>
+ <property name="Command station">
+ <value>
+ ComputerName
+ </value>
+ </property>
+ <property name="Date">
+ <value>
+ CurrentDate
+ </value>
+ </property>
+ </item>
+</item>
diff --git a/clients/opal/tmseq/SR13level2_AsyncIP_sl.tms b/clients/opal/tmseq/SR13level2_AsyncIP_sl.tms
new file mode 100644
index 000000000..dae75209f
--- /dev/null
+++ b/clients/opal/tmseq/SR13level2_AsyncIP_sl.tms
@@ -0,0 +1,90 @@
+<?xml version="1.0" ?>
+<tm>
+ <child attributes="[]" type="'TestFile'">
+ <modelname>'AsyncIP_sl.mdl'</modelname>
+ <name>'Execute'</name>
+ <rtlabInfo attributes="['paramIn','paramOut']">{"modelName": ''}</rtlabInfo>
+ <platformList attributes="['paramIn']">''</platformList>
+ <targetList attributes="['paramIn']">''</targetList>
+ <compilState attributes="['paramIn']">''</compilState>
+ <preExpression>'variables.testFile.name="Execute " + variables.testFile.modelname + " model";variables.testFile.rtlabInfo["modelName"] = variables.testFile.filePath + "/../models/Simulink/" + variables.testFile.modelname'</preExpression>
+ <result><platformResult>['', '', '', '']</platformResult></result>
+ <targetIdx>0</targetIdx>
+
+ <child type="'Loop'">
+ <name>'Platform Loop'</name>
+ <initExpression>'global platformIndex;platformIndex=0'</initExpression>
+ <conditionExpression>'platformIndex<len(variables.testFile.platformList)'</conditionExpression>
+ <incrementExpression>'platformIndex+=1'</incrementExpression>
+
+ <child type="'Test'">
+ <name>'Test - Execute example sequences'</name>
+ <preCondition>'variables.testFile.platformList[platformIndex] == 1'</preCondition>
+ <postExpression>'variables.testFile.targetIdx += 1'</postExpression>
+
+ <child type="'Step'">
+ <name>'step setplatform'</name>
+ <type>'RT-LAB/SetConfiguration'</type>
+ <preCondition>'True'</preCondition>
+ <configuration>{'TargetPlatform': -1}</configuration>
+ <preExpression>'variables.step.configuration["TargetPlatform"]=variables.root.platformListName[platformIndex]'</preExpression>
+ <paramIn>'variables.testFile.rtlabInfo, variables.step.configuration'</paramIn>
+ <paramOut>'variables.testFile.rtlabInfo'</paramOut>
+ </child>
+
+ <child type="'Step'">
+ <name>'step async. proc. compilation command'</name>
+ <type>'RT-LAB/SetConfiguration'</type>
+ <commandListPerPlatform>["","make -f /usr/opalrt/common/bin/opalmodelmk","/usr/bin/make -f /usr/opalrt/common/bin/opalmodelmk",""]</commandListPerPlatform>
+ <postCondition>'True'</postCondition>
+ <configuration>{'TargetCompileCmd': -1}</configuration>
+ <preExpression>'variables.step.configuration["TargetCompileCmd"]=variables.step.commandListPerPlatform[platformIndex]'</preExpression>
+ <paramIn>'variables.testFile.rtlabInfo, variables.step.configuration'</paramIn>
+ <paramOut>'variables.testFile.rtlabInfo'</paramOut>
+ </child>
+
+ <child type="'Step'">
+ <name>'Run CompileModel sequence'</name>
+ <preCondition>'variables.root.platformListName[platformIndex] != RtlabApi.REDHAWK64_TARGET'</preCondition>
+ <type>'SequenceCall'</type>
+ <mode>'dynamic'</mode>
+ <preExpression>''</preExpression>
+ <sequenceFilename>'variables.root.testPath + "/utils/sequence/compileModel.tms"'</sequenceFilename>
+ <paramIn>'variables.testFile.rtlabInfo,variables.testFile.compilState'</paramIn>
+ <paramOut>'variables.testFile.rtlabInfo'</paramOut>
+ <postExpression>''</postExpression>
+ </child>
+
+ <child type="'Step'">
+ <name>'Run testCompileModel sequence'</name>
+ <preCondition>'variables.root.platformListName[platformIndex] == RtlabApi.REDHAWK64_TARGET'</preCondition>
+ <type>'SequenceCall'</type>
+ <mode>'dynamic'</mode>
+ <sequenceFilename>'variables.root.testPath + "/utils/sequence/testCompileModel.tms"'</sequenceFilename>
+ <paramIn>'variables.testFile.rtlabInfo'</paramIn>
+ <paramOut>'variables.testFile.rtlabInfo'</paramOut>
+ <postExpression>''</postExpression>
+ </child>
+ </child>
+
+ <child type="'Step'">
+ <name>'Validation'</name>
+ <type>'Expression'</type>
+ <group>'cleanup'</group>
+ <paramIn>''</paramIn>
+ <paramOut>''</paramOut>
+ <preExpression>'variables.testFile.result.platformResult[platformIndex] = variables.step._getParent().children["Test - Execute example sequences"].result.status'</preExpression>
+ </child>
+ </child>
+
+ <child type="'Step'">
+ <name>'Test loop result'</name>
+ <type>'Expression'</type>
+ <group>'cleanup'</group>
+ <paramIn>''</paramIn>
+ <paramOut>''</paramOut>
+ <preExpression>''</preExpression>
+ <postExpression>'variables.root.result.TestDetail.append(variables.testFile.result.platformResult)'</postExpression>
+ </child>
+ </child>
+</tm>