diff --git a/fpga/include/villas/fpga/ips/zynq.hpp b/fpga/include/villas/fpga/ips/zynq.hpp
new file mode 100644
index 000000000..c79226a0c
--- /dev/null
+++ b/fpga/include/villas/fpga/ips/zynq.hpp
@@ -0,0 +1,65 @@
+/* Zynq node
+ *
+ * Author: Pascal Bauer <pascal.bauer@rwth-aachen.de>
+ * SPDX-FileCopyrightText: 2023-2024 Pascal Bauer <pascal.bauer@rwth-aachen.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <xilinx/xaxis_switch.h>
+
+#include <villas/fpga/node.hpp>
+
+namespace villas {
+namespace fpga {
+namespace ip {
+
+class Zynq : public Core {
+public:
+  friend class ZynqFactory;
+
+  virtual bool init() override;
+
+private:
+  static constexpr char axiInterface[] = "M_AXI";
+  static constexpr char pcieMemory[] = "BAR0";
+
+  struct AxiBar {
+    uintptr_t base;
+    size_t size;
+    uintptr_t translation;
+  };
+
+  struct PciBar {
+    uintptr_t translation;
+  };
+
+  std::map<std::string, AxiBar> axiToPcieTranslations;
+  std::map<std::string, PciBar> pcieToAxiTranslations;
+};
+
+class ZynqFactory : CoreFactory {
+
+public:
+  virtual std::string getName() const { return "Zynq"; }
+
+  virtual std::string getDescription() const {
+    return "Custom platform vfio connector";
+  }
+
+private:
+  virtual Vlnv getCompatibleVlnv() const {
+    return Vlnv("xilinx.com:ip:zynq_ultra_ps_e:");
+  }
+
+  // Create a concrete IP instance
+  Core *make() const { return new Zynq; };
+
+protected:
+  virtual void parse(Core &, json_t *) override;
+};
+
+} /* namespace ip */
+} /* namespace fpga */
+} /* namespace villas */
diff --git a/fpga/lib/ips/zynq.cpp b/fpga/lib/ips/zynq.cpp
new file mode 100644
index 000000000..3edd642c8
--- /dev/null
+++ b/fpga/lib/ips/zynq.cpp
@@ -0,0 +1,39 @@
+/* Zynq VFIO connector node
+ *
+ * Author: Pascal Bauer <pascal.bauer@rwth-aachen.de>
+ * SPDX-FileCopyrightText: 2023-2024 Pascal Bauer <pascal.bauer@rwth-aachen.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <jansson.h>
+#include <limits>
+
+#include <villas/exceptions.hpp>
+#include <villas/memory.hpp>
+
+#include <villas/fpga/card.hpp>
+#include <villas/fpga/ips/zynq.hpp>
+#include <villas/fpga/pcie_card.hpp>
+
+#include <villas/fpga/platform_card.hpp>
+
+using namespace villas::fpga::ip;
+
+bool Zynq::init() {
+  auto &mm = MemoryManager::get();
+
+  // Save ID in card so we can create mappings later when needed (e.g. when
+  // allocating DMA memory in host RAM)
+  card->addrSpaceIdDeviceToHost =
+      mm.getOrCreateAddressSpace("zynq_ultra_ps_e_0/HPC0_DDR_LOW");
+
+  return true;
+}
+
+void ZynqFactory::parse(Core &ip, json_t *cfg) {
+  CoreFactory::parse(ip, cfg);
+
+  auto logger = getLogger();
+}
+
+static ZynqFactory p;