From d2c1f55f212c325fc6670858f5b4a1c4c25e7ee7 Mon Sep 17 00:00:00 2001
From: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
Date: Mon, 17 Jun 2024 13:18:20 +0200
Subject: [PATCH] fpga: fix timestep being hardcoded

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
---
 lib/nodes/fpga.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/nodes/fpga.cpp b/lib/nodes/fpga.cpp
index c484b39cc..c273561ce 100644
--- a/lib/nodes/fpga.cpp
+++ b/lib/nodes/fpga.cpp
@@ -74,7 +74,7 @@ int FpgaNode::prepare() {
 
   if (reg != nullptr &&
       card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
-        fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
+    fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, timestep);
   } else {
     logger->warn("No DinoAdc or no Register found on FPGA.");
   }