From e2e78cf8b3f33104ba08247a5f9352e7c2f84112 Mon Sep 17 00:00:00 2001
From: daniel-k <github@daniel-krebs.net>
Date: Tue, 9 Jan 2018 16:35:47 +0100
Subject: [PATCH] lib: minor cleanup

---
 fpga/include/villas/fpga/ips/switch.hpp |  2 +-
 fpga/include/villas/fpga/ips/timer.hpp  |  4 +---
 fpga/lib/ip_node.cpp                    |  2 +-
 fpga/lib/ips/switch.cpp                 | 24 ++++++++++++------------
 fpga/lib/ips/timer.cpp                  |  4 ++--
 5 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/fpga/include/villas/fpga/ips/switch.hpp b/fpga/include/villas/fpga/ips/switch.hpp
index 1d5e08877..489e61920 100644
--- a/fpga/include/villas/fpga/ips/switch.hpp
+++ b/fpga/include/villas/fpga/ips/switch.hpp
@@ -61,7 +61,7 @@ private:
 		IpCore* slaveIn;
 	};
 
-	XAxis_Switch xilinxDriver;
+	XAxis_Switch xSwitch;
 	std::map<int, int> portMapping;
 };
 
diff --git a/fpga/include/villas/fpga/ips/timer.hpp b/fpga/include/villas/fpga/ips/timer.hpp
index 0f28c79b5..dd1147f89 100644
--- a/fpga/include/villas/fpga/ips/timer.hpp
+++ b/fpga/include/villas/fpga/ips/timer.hpp
@@ -40,12 +40,10 @@ namespace ip {
 class Timer : public IpCore
 {
 public:
-//	~Timer();
-
 	bool start();
 
 private:
-	XTmrCtr xtmr;
+	XTmrCtr xTmr;
 };
 
 
diff --git a/fpga/lib/ip_node.cpp b/fpga/lib/ip_node.cpp
index e456949a5..47539c674 100644
--- a/fpga/lib/ip_node.cpp
+++ b/fpga/lib/ip_node.cpp
@@ -30,7 +30,7 @@ IpNodeFactory::configureJson(IpCore& ip, json_t* json_ip)
 	const bool hasSlavePorts = json_is_array(json_slave);
 
 	if( (not hasMasterPorts) and (not hasSlavePorts)) {
-		cpp_error << "IpNode " << ip << " has not ports";
+		cpp_error << "IpNode " << ip << " has no ports";
 		return false;
 	}
 
diff --git a/fpga/lib/ips/switch.cpp b/fpga/lib/ips/switch.cpp
index d01e4791e..51148a895 100644
--- a/fpga/lib/ips/switch.cpp
+++ b/fpga/lib/ips/switch.cpp
@@ -42,15 +42,15 @@ AxiStreamSwitch::start()
 	sw_cfg.MaxNumMI = portsMaster.size();
 	sw_cfg.MaxNumSI = portsSlave.size();
 
-	if(XAxisScr_CfgInitialize(&xilinxDriver, &sw_cfg, getBaseaddr()) != XST_SUCCESS) {
+	if(XAxisScr_CfgInitialize(&xSwitch, &sw_cfg, getBaseaddr()) != XST_SUCCESS) {
 		cpp_error << "Cannot start " << *this;
 		return false;
 	}
 
 	/* Disable all masters */
-	XAxisScr_RegUpdateDisable(&xilinxDriver);
-	XAxisScr_MiPortDisableAll(&xilinxDriver);
-	XAxisScr_RegUpdateEnable(&xilinxDriver);
+	XAxisScr_RegUpdateDisable(&xSwitch);
+	XAxisScr_MiPortDisableAll(&xSwitch);
+	XAxisScr_RegUpdateEnable(&xSwitch);
 
 	// initialize internal mapping
 	for(int portMaster = 0; portMaster < portsMaster.size(); portMaster++) {
@@ -74,16 +74,16 @@ AxiStreamSwitch::connect(int portSlave, int portMaster)
 			cpp_warn << "Slave " << slave << " has already been connected to "
 			         << "master " << master << ". Disabling master " << master;
 
-			XAxisScr_RegUpdateDisable(&xilinxDriver);
-			XAxisScr_MiPortDisable(&xilinxDriver, master);
-			XAxisScr_RegUpdateEnable(&xilinxDriver);
+			XAxisScr_RegUpdateDisable(&xSwitch);
+			XAxisScr_MiPortDisable(&xSwitch, master);
+			XAxisScr_RegUpdateEnable(&xSwitch);
 		}
 	}
 
 	/* Reconfigure switch */
-	XAxisScr_RegUpdateDisable(&xilinxDriver);
-	XAxisScr_MiPortEnable(&xilinxDriver, portMaster, portSlave);
-	XAxisScr_RegUpdateEnable(&xilinxDriver);
+	XAxisScr_RegUpdateDisable(&xSwitch);
+	XAxisScr_MiPortEnable(&xSwitch, portMaster, portSlave);
+	XAxisScr_RegUpdateEnable(&xSwitch);
 
 	cpp_debug << "Connect slave " << portSlave << " to master " << portMaster;
 
@@ -96,7 +96,7 @@ AxiStreamSwitch::disconnectMaster(int port)
 	cpp_debug << "Disconnect slave " << portMapping[port]
 	          << " from master " << port;
 
-	XAxisScr_MiPortDisable(&xilinxDriver, port);
+	XAxisScr_MiPortDisable(&xSwitch, port);
 	portMapping[port] = PORT_DISABLED;
 	return true;
 }
@@ -107,7 +107,7 @@ AxiStreamSwitch::disconnectSlave(int port)
 	for(auto [master, slave] : portMapping) {
 		if(slave == port) {
 			cpp_debug << "Disconnect slave " << slave << " from master " << master;
-			XAxisScr_MiPortDisable(&xilinxDriver, master);
+			XAxisScr_MiPortDisable(&xSwitch, master);
 			return true;
 		}
 	}
diff --git a/fpga/lib/ips/timer.cpp b/fpga/lib/ips/timer.cpp
index 246bc9a78..8a67f515b 100644
--- a/fpga/lib/ips/timer.cpp
+++ b/fpga/lib/ips/timer.cpp
@@ -42,8 +42,8 @@ bool Timer::start()
 	XTmrCtr_Config xtmr_cfg;
 	xtmr_cfg.SysClockFreqHz = FPGA_AXI_HZ;
 
-	XTmrCtr_CfgInitialize(&xtmr, &xtmr_cfg, getBaseaddr());
-	XTmrCtr_InitHw(&xtmr);
+	XTmrCtr_CfgInitialize(&xTmr, &xtmr_cfg, getBaseaddr());
+	XTmrCtr_InitHw(&xTmr);
 
 	return true;
 }