From 8b7bbe27c6ba546539c8a69f081fc9ecbae2231a Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Sun, 14 Jun 2020 22:03:50 +0200 Subject: [PATCH 01/11] refactor: whitespaces for references --- fpga/gpu/include/villas/gpu.hpp | 20 +++++------ fpga/gpu/src/gpu.cpp | 42 +++++++++++------------ fpga/include/villas/fpga/card.hpp | 8 ++--- fpga/include/villas/fpga/core.hpp | 40 ++++++++++----------- fpga/include/villas/fpga/ips/bram.hpp | 2 +- fpga/include/villas/fpga/ips/dma.hpp | 12 +++---- fpga/include/villas/fpga/ips/hls.hpp | 2 +- fpga/include/villas/fpga/ips/pcie.hpp | 2 +- fpga/include/villas/fpga/ips/rtds2gpu.hpp | 6 ++-- fpga/include/villas/fpga/ips/switch.hpp | 8 ++--- fpga/include/villas/fpga/node.hpp | 18 +++++----- fpga/include/villas/fpga/vlnv.hpp | 6 ++-- fpga/lib/card.cpp | 22 ++++++------ fpga/lib/core.cpp | 26 +++++++------- fpga/lib/ips/bram.cpp | 4 +-- fpga/lib/ips/dma.cpp | 16 ++++----- fpga/lib/ips/intc.cpp | 6 ++-- fpga/lib/ips/pcie.cpp | 10 +++--- fpga/lib/ips/rtds2gpu/gpu2rtds.cpp | 8 ++--- fpga/lib/ips/rtds2gpu/rtds2gpu.cpp | 6 ++-- fpga/lib/ips/switch.cpp | 16 ++++----- fpga/lib/node.cpp | 14 ++++---- fpga/src/fpga.c | 2 +- fpga/src/villas-fpga-pipe.cpp | 6 ++-- fpga/tests/dma.cpp | 4 +-- fpga/tests/fifo.cpp | 2 +- fpga/tests/fpga.cpp | 2 +- fpga/tests/global.hpp | 2 +- fpga/tests/gpu.cpp | 22 ++++++------ fpga/tests/rtds.cpp | 2 +- fpga/tests/rtds2gpu.cpp | 12 +++---- fpga/tests/rtds_rtt.c | 2 +- fpga/tests/timer.cpp | 2 +- 33 files changed, 175 insertions(+), 177 deletions(-) diff --git a/fpga/gpu/include/villas/gpu.hpp b/fpga/gpu/include/villas/gpu.hpp index 738e09872..ec1b62376 100644 --- a/fpga/gpu/include/villas/gpu.hpp +++ b/fpga/gpu/include/villas/gpu.hpp @@ -45,25 +45,25 @@ public: std::string getName() const; - GpuAllocator& getAllocator() const + GpuAllocator &getAllocator() const { return *allocator; } - bool makeAccessibleToPCIeAndVA(const MemoryBlock& mem); + bool makeAccessibleToPCIeAndVA(const MemoryBlock &mem); /// Make some memory block accssible for this GPU - bool makeAccessibleFromPCIeOrHostRam(const MemoryBlock& mem); + bool makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem); - void memcpySync(const MemoryBlock& src, const MemoryBlock& dst, size_t size); + void memcpySync(const MemoryBlock &src, const MemoryBlock &dst, size_t size); - void memcpyKernel(const MemoryBlock& src, const MemoryBlock& dst, size_t size); + void memcpyKernel(const MemoryBlock &src, const MemoryBlock &dst, size_t size); MemoryTranslation - translate(const MemoryBlock& dst); + translate(const MemoryBlock &dst); private: - bool registerIoMemory(const MemoryBlock& mem); - bool registerHostMemory(const MemoryBlock& mem); + bool registerIoMemory(const MemoryBlock &mem); + bool registerHostMemory(const MemoryBlock &mem); private: class impl; @@ -86,7 +86,7 @@ class GpuAllocator : public BaseAllocator { public: static constexpr size_t GpuPageSize = 64UL << 10; - GpuAllocator(Gpu& gpu); + GpuAllocator(Gpu &gpu); std::string getName() const; @@ -94,7 +94,7 @@ public: allocateBlock(size_t size); private: - Gpu& gpu; + Gpu &gpu; // TODO: replace by multimap (key is available memory) std::list> chunks; }; diff --git a/fpga/gpu/src/gpu.cpp b/fpga/gpu/src/gpu.cpp index 7131ec873..2bafa26d0 100644 --- a/fpga/gpu/src/gpu.cpp +++ b/fpga/gpu/src/gpu.cpp @@ -30,7 +30,7 @@ #include #include -#include +#include #include #include @@ -44,7 +44,7 @@ namespace gpu { static GpuFactory gpuFactory; -GpuAllocator::GpuAllocator(Gpu& gpu) : +GpuAllocator::GpuAllocator(Gpu &gpu) : BaseAllocator(gpu.masterPciEAddrSpaceId), gpu(gpu) { @@ -77,7 +77,7 @@ GpuFactory::GpuFactory() : // required to be defined here for PIMPL to compile Gpu::~Gpu() { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); mm.removeAddressSpace(masterPciEAddrSpaceId); } @@ -104,9 +104,9 @@ std::string Gpu::getName() const return name.str(); } -bool Gpu::registerIoMemory(const MemoryBlock& mem) +bool Gpu::registerIoMemory(const MemoryBlock &mem) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); const auto pciAddrSpaceId = mm.getPciAddressSpace(); // Check if we need to map anything at all, maybe it's already reachable @@ -187,9 +187,9 @@ bool Gpu::registerIoMemory(const MemoryBlock& mem) } bool -Gpu::registerHostMemory(const MemoryBlock& mem) +Gpu::registerHostMemory(const MemoryBlock &mem) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); auto translation = mm.getTranslationFromProcess(mem.getAddrSpaceId()); auto localBase = reinterpret_cast(translation.getLocalAddr(0)); @@ -214,14 +214,14 @@ Gpu::registerHostMemory(const MemoryBlock& mem) return true; } -bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock& mem) +bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock &mem) { if (pImpl->gdr == nullptr) { logger->warn("GDRcopy not available"); return false; } - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); try { auto path = mm.findPath(masterPciEAddrSpaceId, mem.getAddrSpaceId()); @@ -311,14 +311,14 @@ bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock& mem) } bool -Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock& mem) +Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem) { // Check which kind of memory this is and where it resides // There are two possibilities: // - Host memory not managed by CUDA // - IO memory somewhere on the PCIe bus - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); bool isIoMemory = false; try { @@ -341,9 +341,9 @@ Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock& mem) } } -void Gpu::memcpySync(const MemoryBlock& src, const MemoryBlock& dst, size_t size) +void Gpu::memcpySync(const MemoryBlock &src, const MemoryBlock &dst, size_t size) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); auto src_translation = mm.getTranslation(masterPciEAddrSpaceId, src.getAddrSpaceId()); @@ -357,9 +357,9 @@ void Gpu::memcpySync(const MemoryBlock& src, const MemoryBlock& dst, size_t size cudaMemcpy(dst_buf, src_buf, size, cudaMemcpyDefault); } -void Gpu::memcpyKernel(const MemoryBlock& src, const MemoryBlock& dst, size_t size) +void Gpu::memcpyKernel(const MemoryBlock &src, const MemoryBlock &dst, size_t size) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); auto src_translation = mm.getTranslation(masterPciEAddrSpaceId, src.getAddrSpaceId()); @@ -375,9 +375,9 @@ void Gpu::memcpyKernel(const MemoryBlock& src, const MemoryBlock& dst, size_t si } MemoryTranslation -Gpu::translate(const MemoryBlock& dst) +Gpu::translate(const MemoryBlock &dst) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); return mm.getTranslation(masterPciEAddrSpaceId, dst.getAddrSpaceId()); } @@ -388,10 +388,10 @@ GpuAllocator::allocateBlock(size_t size) cudaSetDevice(gpu.gpuId); void* addr; - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); // search for an existing chunk that has enough free memory - auto chunk = std::find_if(chunks.begin(), chunks.end(), [&](const auto& chunk) { + auto chunk = std::find_if(chunks.begin(), chunks.end(), [&](const auto &chunk) { return chunk->getAvailableMemory() >= size; }); @@ -452,7 +452,7 @@ Gpu::Gpu(int gpuId) : bool Gpu::init() { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); const auto gpuPciEAddrSpaceName = mm.getMasterAddrSpaceName(getName(), "pcie"); masterPciEAddrSpaceId = mm.getOrCreateAddressSpace(gpuPciEAddrSpaceName); @@ -517,7 +517,7 @@ GpuFactory::make() } logger->info("Initialized {} GPUs", gpuList.size()); - for (auto& gpu : gpuList) { + for (auto &gpu : gpuList) { logger->debug(" - {}", gpu->getName()); } diff --git a/fpga/include/villas/fpga/card.hpp b/fpga/include/villas/fpga/card.hpp index 6c6d454e9..ceacebc44 100644 --- a/fpga/include/villas/fpga/card.hpp +++ b/fpga/include/villas/fpga/card.hpp @@ -75,12 +75,12 @@ public: bool reset() { return true; } void dump() { } - ip::Core::Ptr lookupIp(const std::string& name) const; - ip::Core::Ptr lookupIp(const Vlnv& vlnv) const; - ip::Core::Ptr lookupIp(const ip::IpIdentifier& id) const; + ip::Core::Ptr lookupIp(const std::string &name) const; + ip::Core::Ptr lookupIp(const Vlnv &vlnv) const; + ip::Core::Ptr lookupIp(const ip::IpIdentifier &id) const; bool - mapMemoryBlock(const MemoryBlock& block); + mapMemoryBlock(const MemoryBlock &block); private: /// Cache a set of already mapped memory blocks diff --git a/fpga/include/villas/fpga/core.hpp b/fpga/include/villas/fpga/core.hpp index 716deb334..aaeed05d4 100644 --- a/fpga/include/villas/fpga/core.hpp +++ b/fpga/include/villas/fpga/core.hpp @@ -74,11 +74,11 @@ public: { return vlnv; } friend std::ostream& - operator<< (std::ostream& stream, const IpIdentifier& id) + operator<< (std::ostream &stream, const IpIdentifier &id) { return stream << id.name << " vlnv=" << id.vlnv; } bool - operator==(const IpIdentifier& otherId) const { + operator==(const IpIdentifier &otherId) const { const bool vlnvWildcard = otherId.getVlnv() == Vlnv::getWildcard(); const bool nameWildcard = this->getName().empty() or otherId.getName().empty(); @@ -89,7 +89,7 @@ public: } bool - operator!=(const IpIdentifier& otherId) const + operator!=(const IpIdentifier &otherId) const { return !(*this == otherId); } private: @@ -144,66 +144,66 @@ public: /* Operators */ bool - operator==(const Vlnv& otherVlnv) const + operator==(const Vlnv &otherVlnv) const { return id.getVlnv() == otherVlnv; } bool - operator!=(const Vlnv& otherVlnv) const + operator!=(const Vlnv &otherVlnv) const { return id.getVlnv() != otherVlnv; } bool - operator==(const IpIdentifier& otherId) const + operator==(const IpIdentifier &otherId) const { return this->id == otherId; } bool - operator!=(const IpIdentifier& otherId) const + operator!=(const IpIdentifier &otherId) const { return this->id != otherId; } bool - operator==(const std::string& otherName) const + operator==(const std::string &otherName) const { return getInstanceName() == otherName; } bool - operator!=(const std::string& otherName) const + operator!=(const std::string &otherName) const { return getInstanceName() != otherName; } bool - operator==(const Core& otherIp) const + operator==(const Core &otherIp) const { return this->id == otherIp.id; } bool - operator!=(const Core& otherIp) const + operator!=(const Core &otherIp) const { return this->id != otherIp.id; } friend std::ostream& - operator<< (std::ostream& stream, const Core& ip) + operator<< (std::ostream &stream, const Core &ip) { return stream << ip.id; } protected: uintptr_t - getBaseAddr(const MemoryBlockName& block) const + getBaseAddr(const MemoryBlockName &block) const { return getLocalAddr(block, 0); } uintptr_t - getLocalAddr(const MemoryBlockName& block, uintptr_t address) const; + getLocalAddr(const MemoryBlockName &block, uintptr_t address) const; MemoryManager::AddressSpaceId - getAddressSpaceId(const MemoryBlockName& block) const + getAddressSpaceId(const MemoryBlockName &block) const { return slaveAddressSpaces.at(block); } InterruptController* - getInterruptController(const std::string& interruptName) const; + getInterruptController(const std::string &interruptName) const; MemoryManager::AddressSpaceId - getMasterAddrSpaceByInterface(const std::string& masterInterfaceName) const + getMasterAddrSpaceByInterface(const std::string &masterInterfaceName) const { return busMasterInterfaces.at(masterInterfaceName); } template - T readMemory(const std::string& block, uintptr_t address) const + T readMemory(const std::string &block, uintptr_t address) const { return *(reinterpret_cast(getLocalAddr(block, address))); } template - void writeMemory(const std::string& block, uintptr_t address, T value) + void writeMemory(const std::string &block, uintptr_t address, T value) { T* ptr = reinterpret_cast(getLocalAddr(block, address)); *ptr = value; } protected: @@ -266,7 +266,7 @@ protected: private: static CoreFactory* - lookup(const Vlnv& vlnv); + lookup(const Vlnv &vlnv); }; /** @} */ diff --git a/fpga/include/villas/fpga/ips/bram.hpp b/fpga/include/villas/fpga/ips/bram.hpp index 56139c6a1..eae15546b 100644 --- a/fpga/include/villas/fpga/ips/bram.hpp +++ b/fpga/include/villas/fpga/ips/bram.hpp @@ -59,7 +59,7 @@ private: class BramFactory : public CoreFactory { public: - bool configureJson(Core& ip, json_t *json_ip); + bool configureJson(Core &ip, json_t *json_ip); Core* create() { return new Bram; } diff --git a/fpga/include/villas/fpga/ips/dma.hpp b/fpga/include/villas/fpga/ips/dma.hpp index 77208ca20..cb8505367 100644 --- a/fpga/include/villas/fpga/ips/dma.hpp +++ b/fpga/include/villas/fpga/ips/dma.hpp @@ -44,10 +44,10 @@ public: bool reset(); // memory-mapped to stream (MM2S) - bool write(const MemoryBlock& mem, size_t len); + bool write(const MemoryBlock &mem, size_t len); // stream to memory-mapped (S2MM) - bool read(const MemoryBlock& mem, size_t len); + bool read(const MemoryBlock &mem, size_t len); size_t writeComplete() { return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple(); } @@ -55,10 +55,10 @@ public: size_t readComplete() { return hasScatterGather() ? readCompleteSG() : readCompleteSimple(); } - bool memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len); + bool memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len); - bool makeAccesibleFromVA(const MemoryBlock& mem); - bool makeInaccesibleFromVA(const MemoryBlock& mem); + bool makeAccesibleFromVA(const MemoryBlock &mem); + bool makeInaccesibleFromVA(const MemoryBlock &mem); inline bool hasScatterGather() const @@ -87,7 +87,7 @@ public: static constexpr const char* s2mmPort = "S2MM"; static constexpr const char* mm2sPort = "MM2S"; - bool isMemoryBlockAccesible(const MemoryBlock& mem, const std::string& interface); + bool isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface); virtual void dump(); diff --git a/fpga/include/villas/fpga/ips/hls.hpp b/fpga/include/villas/fpga/ips/hls.hpp index 96d794af9..b7ded443e 100644 --- a/fpga/include/villas/fpga/ips/hls.hpp +++ b/fpga/include/villas/fpga/ips/hls.hpp @@ -13,7 +13,7 @@ class Hls : public virtual Core public: virtual bool init() { - auto& registers = addressTranslations.at(registerMemory); + auto ®isters = addressTranslations.at(registerMemory); controlRegister = reinterpret_cast(registers.getLocalAddr(registerControlAddr)); globalIntRegister = reinterpret_cast(registers.getLocalAddr(registerGlobalIntEnableAddr)); diff --git a/fpga/include/villas/fpga/ips/pcie.hpp b/fpga/include/villas/fpga/ips/pcie.hpp index bf168759e..083222317 100644 --- a/fpga/include/villas/fpga/ips/pcie.hpp +++ b/fpga/include/villas/fpga/ips/pcie.hpp @@ -70,7 +70,7 @@ public: getCompatibleVlnvString() { return "xilinx.com:ip:axi_pcie:"; } - bool configureJson(Core& ip, json_t *json_ip); + bool configureJson(Core &ip, json_t *json_ip); Core* create() { return new AxiPciExpressBridge; } diff --git a/fpga/include/villas/fpga/ips/rtds2gpu.hpp b/fpga/include/villas/fpga/ips/rtds2gpu.hpp index fb24373b2..f1322a27f 100644 --- a/fpga/include/villas/fpga/ips/rtds2gpu.hpp +++ b/fpga/include/villas/fpga/ips/rtds2gpu.hpp @@ -34,16 +34,16 @@ public: void dump(spdlog::level::level_enum logLevel = spdlog::level::info); - bool startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset); + bool startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset); size_t getMaxFrameSize(); void dumpDoorbell(uint32_t doorbellRegister) const; - bool doorbellIsValid(const uint32_t& doorbellRegister) const + bool doorbellIsValid(const uint32_t &doorbellRegister) const { return reinterpret_cast(doorbellRegister).is_valid; } - void doorbellReset(uint32_t& doorbellRegister) const + void doorbellReset(uint32_t &doorbellRegister) const { doorbellRegister = 0; } static constexpr const char* registerMemory = "Reg"; diff --git a/fpga/include/villas/fpga/ips/switch.hpp b/fpga/include/villas/fpga/ips/switch.hpp index fe3cc9ef0..8fa9d81d0 100644 --- a/fpga/include/villas/fpga/ips/switch.hpp +++ b/fpga/include/villas/fpga/ips/switch.hpp @@ -46,11 +46,11 @@ public: bool init(); - bool connectInternal(const std::string& slavePort, - const std::string& masterPort); + bool connectInternal(const std::string &slavePort, + const std::string &masterPort); private: - int portNameToNum(const std::string& portName); + int portNameToNum(const std::string &portName); private: static constexpr const char* PORT_DISABLED = "DISABLED"; @@ -77,7 +77,7 @@ public: getCompatibleVlnvString() { return "xilinx.com:ip:axis_switch:"; } - bool configureJson(Core& ip, json_t *json_ip); + bool configureJson(Core &ip, json_t *json_ip); Core* create() { return new AxiStreamSwitch; } diff --git a/fpga/include/villas/fpga/node.hpp b/fpga/include/villas/fpga/node.hpp index 08f5b42d5..e879bb717 100644 --- a/fpga/include/villas/fpga/node.hpp +++ b/fpga/include/villas/fpga/node.hpp @@ -44,14 +44,14 @@ namespace ip { class StreamVertex : public graph::Vertex { public: - StreamVertex(const std::string& node, const std::string& port, bool isMaster) : + StreamVertex(const std::string &node, const std::string &port, bool isMaster) : nodeName(node), portName(port), isMaster(isMaster) {} std::string getName() const { return nodeName + "/" + portName + "(" + (isMaster ? "M" : "S") + ")"; } friend std::ostream& - operator<< (std::ostream& stream, const StreamVertex& vertex) + operator<< (std::ostream &stream, const StreamVertex &vertex) { return stream << vertex.getIdentifier() << ": " << vertex.getName(); } public: @@ -66,12 +66,12 @@ public: StreamGraph() : graph::DirectedGraph("StreamGraph") {} std::shared_ptr - getOrCreateStreamVertex(const std::string& node, - const std::string& port, + getOrCreateStreamVertex(const std::string &node, + const std::string &port, bool isMaster) { - for (auto& vertexEntry : vertices) { - auto& vertex = vertexEntry.second; + for (auto &vertexEntry : vertices) { + auto &vertex = vertexEntry.second; if (vertex->nodeName == node and vertex->portName == port and vertex->isMaster == isMaster) return vertex; } @@ -95,14 +95,12 @@ public: std::string nodeName; }; - bool connect(const StreamVertex& from, const StreamVertex& to); - const StreamVertex& - getMasterPort(const std::string& name) const + getMasterPort(const std::string &name) const { return *portsMaster.at(name); } const StreamVertex& - getSlavePort(const std::string& name) const + getSlavePort(const std::string &name) const { return *portsSlave.at(name); } // easy-usage assuming that the slave IP to connect to only has one slave diff --git a/fpga/include/villas/fpga/vlnv.hpp b/fpga/include/villas/fpga/vlnv.hpp index 63aac0611..5e524acd0 100644 --- a/fpga/include/villas/fpga/vlnv.hpp +++ b/fpga/include/villas/fpga/vlnv.hpp @@ -53,14 +53,14 @@ public: toString() const; bool - operator==(const Vlnv& other) const; + operator==(const Vlnv &other) const; bool - operator!=(const Vlnv& other) const + operator!=(const Vlnv &other) const { return !(*this == other); } friend std::ostream& - operator<< (std::ostream& stream, const Vlnv& vlnv) + operator<< (std::ostream &stream, const Vlnv &vlnv) { return stream << (vlnv.vendor.empty() ? "*" : vlnv.vendor) << ":" diff --git a/fpga/lib/card.cpp b/fpga/lib/card.cpp index aa383f13e..eccb2df4c 100644 --- a/fpga/lib/card.cpp +++ b/fpga/lib/card.cpp @@ -119,10 +119,10 @@ PCIeCardFactory::create() PCIeCard::~PCIeCard() { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); // unmap all memory blocks - for (auto& mappedMemoryBlock : memoryBlocksMapped) { + for (auto &mappedMemoryBlock : memoryBlocksMapped) { auto translation = mm.getTranslation(addrSpaceIdDeviceToHost, mappedMemoryBlock); @@ -137,9 +137,9 @@ PCIeCard::~PCIeCard() ip::Core::Ptr -PCIeCard::lookupIp(const std::string& name) const +PCIeCard::lookupIp(const std::string &name) const { - for (auto& ip : ips) { + for (auto &ip : ips) { if (*ip == name) { return ip; } @@ -150,9 +150,9 @@ PCIeCard::lookupIp(const std::string& name) const ip::Core::Ptr -PCIeCard::lookupIp(const Vlnv& vlnv) const +PCIeCard::lookupIp(const Vlnv &vlnv) const { - for (auto& ip : ips) { + for (auto &ip : ips) { if (*ip == vlnv) { return ip; } @@ -162,9 +162,9 @@ PCIeCard::lookupIp(const Vlnv& vlnv) const } ip::Core::Ptr -PCIeCard::lookupIp(const ip::IpIdentifier& id) const +PCIeCard::lookupIp(const ip::IpIdentifier &id) const { - for (auto& ip : ips) { + for (auto &ip : ips) { if (*ip == id) { return ip; } @@ -175,15 +175,15 @@ PCIeCard::lookupIp(const ip::IpIdentifier& id) const bool -PCIeCard::mapMemoryBlock(const MemoryBlock& block) +PCIeCard::mapMemoryBlock(const MemoryBlock &block) { if (not vfioContainer->isIommuEnabled()) { logger->warn("VFIO mapping not supported without IOMMU"); return false; } - auto& mm = MemoryManager::get(); - const auto& addrSpaceId = block.getAddrSpaceId(); + auto &mm = MemoryManager::get(); + const auto &addrSpaceId = block.getAddrSpaceId(); if (memoryBlocksMapped.find(addrSpaceId) != memoryBlocksMapped.end()) { // block already mapped diff --git a/fpga/lib/core.cpp b/fpga/lib/core.cpp index d1836a6ab..731ff1fe9 100644 --- a/fpga/lib/core.cpp +++ b/fpga/lib/core.cpp @@ -85,7 +85,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) // first to be initialized. vlnvInitializationOrder.reverse(); - for (auto& vlnvInitFirst : vlnvInitializationOrder) { + for (auto &vlnvInitFirst : vlnvInitializationOrder) { // iterate over IPs, if VLNV matches, push to front and remove from list for (auto it = allIps.begin(); it != allIps.end(); ++it) { if (vlnvInitFirst == it->getVlnv()) { @@ -99,12 +99,12 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) orderedIps.splice(orderedIps.end(), allIps); loggerStatic->debug("IP initialization order:"); - for (auto& id : orderedIps) { + for (auto &id : orderedIps) { loggerStatic->debug(" " CLR_BLD("{}"), id.getName()); } // configure all IPs - for (auto& id : orderedIps) { + for (auto &id : orderedIps) { loggerStatic->info("Configuring {}", id); // find the appropriate factory that can create the specified VLNV @@ -162,10 +162,10 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) continue; } - const std::string& irqControllerName = tokens[0]; + const std::string &irqControllerName = tokens[0]; InterruptController* intc = nullptr; - for (auto& configuredIp : configuredIps) { + for (auto &configuredIp : configuredIps) { if (*configuredIp == irqControllerName) { intc = dynamic_cast(configuredIp.get()); break; @@ -265,12 +265,12 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) } // Start and check IPs now - for (auto& ip : configuredIps) { + for (auto &ip : configuredIps) { // Translate all memory blocks that the IP needs to be accessible from // the process and cache in the instance, so this has not to be done at // runtime. - for (auto& memoryBlock : ip->getMemoryBlocks()) { + for (auto &memoryBlock : ip->getMemoryBlocks()) { // construct the global name of this address block const auto addrSpaceName = MemoryManager::getSlaveAddrSpaceName(ip->getInstanceName(), @@ -284,7 +284,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) ip->slaveAddressSpaces.emplace(memoryBlock, addrSpaceId); // get the translation to the address space - const auto& translation = + const auto &translation = MemoryManager::get().getTranslationFromProcess(addrSpaceId); // cache it in the IP instance only with local name @@ -309,7 +309,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) loggerStatic->debug("Initialized IPs:"); - for (auto& ip : initializedIps) { + for (auto &ip : initializedIps) { loggerStatic->debug(" {}", *ip); } @@ -335,7 +335,7 @@ Core::dump() CoreFactory* CoreFactory::lookup(const Vlnv &vlnv) { - for (auto& ip : plugin::Registry::lookup()) { + for (auto &ip : plugin::Registry::lookup()) { if (ip->getCompatibleVlnv() == vlnv) return ip; } @@ -345,17 +345,17 @@ CoreFactory::lookup(const Vlnv &vlnv) uintptr_t -Core::getLocalAddr(const MemoryBlockName& block, uintptr_t address) const +Core::getLocalAddr(const MemoryBlockName &block, uintptr_t address) const { // throws exception if block not present - auto& translation = addressTranslations.at(block); + auto &translation = addressTranslations.at(block); return translation.getLocalAddr(address); } InterruptController* -Core::getInterruptController(const std::string& interruptName) const +Core::getInterruptController(const std::string &interruptName) const { try { const IrqPort irq = irqs.at(interruptName); diff --git a/fpga/lib/ips/bram.cpp b/fpga/lib/ips/bram.cpp index 3894e39c3..b6227cf94 100644 --- a/fpga/lib/ips/bram.cpp +++ b/fpga/lib/ips/bram.cpp @@ -29,9 +29,9 @@ namespace ip { static BramFactory factory; bool -BramFactory::configureJson(Core& ip, json_t* json_ip) +BramFactory::configureJson(Core &ip, json_t* json_ip) { - auto& bram = dynamic_cast(ip); + auto &bram = dynamic_cast(ip); if (json_unpack(json_ip, "{ s: i }", "size", &bram.size) != 0) { getLogger()->error("Cannot parse 'size'"); diff --git a/fpga/lib/ips/dma.cpp b/fpga/lib/ips/dma.cpp index f5aabd3e9..b25b26352 100644 --- a/fpga/lib/ips/dma.cpp +++ b/fpga/lib/ips/dma.cpp @@ -126,7 +126,7 @@ Dma::reset() bool -Dma::memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len) +Dma::memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len) { if (len == 0) return true; @@ -151,9 +151,9 @@ Dma::memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len) bool -Dma::write(const MemoryBlock& mem, size_t len) +Dma::write(const MemoryBlock &mem, size_t len) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); // user has to make sure that memory is accessible, otherwise this will throw auto translation = mm.getTranslation(busMasterInterfaces[mm2sInterface], @@ -166,9 +166,9 @@ Dma::write(const MemoryBlock& mem, size_t len) bool -Dma::read(const MemoryBlock& mem, size_t len) +Dma::read(const MemoryBlock &mem, size_t len) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); // user has to make sure that memory is accessible, otherwise this will throw auto translation = mm.getTranslation(busMasterInterfaces[s2mmInterface], @@ -351,7 +351,7 @@ Dma::readCompleteSimple() bool -Dma::makeAccesibleFromVA(const MemoryBlock& mem) +Dma::makeAccesibleFromVA(const MemoryBlock &mem) { // only symmetric mapping supported currently if (isMemoryBlockAccesible(mem, s2mmInterface) and @@ -377,9 +377,9 @@ Dma::makeAccesibleFromVA(const MemoryBlock& mem) bool -Dma::isMemoryBlockAccesible(const MemoryBlock& mem, const std::string& interface) +Dma::isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); try { mm.findPath(getMasterAddrSpaceByInterface(interface), mem.getAddrSpaceId()); diff --git a/fpga/lib/ips/intc.cpp b/fpga/lib/ips/intc.cpp index 7080fade8..9467f1a1e 100644 --- a/fpga/lib/ips/intc.cpp +++ b/fpga/lib/ips/intc.cpp @@ -41,7 +41,7 @@ static InterruptControllerFactory factory; InterruptController::~InterruptController() { - card->vfioDevice->pciMsiDeinit(this->efds); + card->kernel::vfio::Device->pciMsiDeinit(this->efds); } bool @@ -49,11 +49,11 @@ InterruptController::init() { const uintptr_t base = getBaseAddr(registerMemory); - num_irqs = card->vfioDevice->pciMsiInit(efds); + num_irqs = card->kernel::vfio::Device->pciMsiInit(efds); if (num_irqs < 0) return false; - if (not card->vfioDevice->pciMsiFind(nos)) { + if (not card->kernel::vfio::Device->pciMsiFind(nos)) { return false; } diff --git a/fpga/lib/ips/pcie.cpp b/fpga/lib/ips/pcie.cpp index 3db756801..a205032bf 100644 --- a/fpga/lib/ips/pcie.cpp +++ b/fpga/lib/ips/pcie.cpp @@ -38,21 +38,21 @@ static AxiPciExpressBridgeFactory factory; bool AxiPciExpressBridge::init() { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); // Throw an exception if the is no bus master interface and thus no // address space we can use for translation -> error card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface); /* Map PCIe BAR0 via VFIO */ - const void* bar0_mapped = card->vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX); + const void* bar0_mapped = card->kernel::vfio::Device->regionMap(VFIO_PCI_BAR0_REGION_INDEX); if (bar0_mapped == MAP_FAILED) { logger->error("Failed to mmap() BAR0"); return false; } // determine size of BAR0 region - const size_t bar0_size = card->vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX); + const size_t bar0_size = card->kernel::vfio::Device->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX); // create a mapping from process address space to the FPGA card via vfio mm.createMapping(reinterpret_cast(bar0_mapped), @@ -122,10 +122,10 @@ AxiPciExpressBridge::init() } bool -AxiPciExpressBridgeFactory::configureJson(Core& ip, json_t* json_ip) +AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip) { auto logger = getLogger(); - auto& pcie = dynamic_cast(ip); + auto &pcie = dynamic_cast(ip); for (auto barType : std::list{"axi_bars", "pcie_bars"}) { json_t* json_bars = json_object_get(json_ip, barType.c_str()); diff --git a/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp b/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp index 6dbc78269..b5d44a003 100644 --- a/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp +++ b/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp @@ -15,7 +15,7 @@ bool Gpu2Rtds::init() { Hls::init(); - auto& registers = addressTranslations.at(registerMemory); + auto ®isters = addressTranslations.at(registerMemory); registerStatus = reinterpret_cast(registers.getLocalAddr(registerStatusOffset)); registerStatusCtrl = reinterpret_cast(registers.getLocalAddr(registerStatusCtrlOffset)); @@ -55,9 +55,9 @@ void Gpu2Rtds::dump(spdlog::level::level_enum logLevel) logger->log(logLevel, " Max. frame size: {}", status.max_frame_size); } -//bool Gpu2Rtds::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset) +//bool Gpu2Rtds::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset) //{ -// auto& mm = MemoryManager::get(); +// auto &mm = MemoryManager::get(); // if (frameSize > maxFrameSize) { // logger->error("Requested frame size of {} exceeds max. frame size of {}", @@ -123,7 +123,7 @@ Gpu2Rtds::getMaxFrameSize() //void //Gpu2Rtds::dumpDoorbell(uint32_t doorbellRegister) const //{ -// auto& doorbell = reinterpret_cast(doorbellRegister); +// auto &doorbell = reinterpret_cast(doorbellRegister); // logger->info("Doorbell register: {:#08x}", doorbell.value); // logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no")); diff --git a/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp b/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp index 84b202b18..881bc760a 100644 --- a/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp +++ b/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp @@ -52,9 +52,9 @@ void Rtds2Gpu::dump(spdlog::level::level_enum logLevel) logger->log(logLevel, " Max. frame size: {}", status.max_frame_size); } -bool Rtds2Gpu::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset) +bool Rtds2Gpu::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset) { - auto& mm = MemoryManager::get(); + auto &mm = MemoryManager::get(); if (frameSize > maxFrameSize) { logger->error("Requested frame size of {} exceeds max. frame size of {}", @@ -108,7 +108,7 @@ Rtds2Gpu::getMaxFrameSize() void Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const { - auto& doorbell = reinterpret_cast(doorbellRegister); + auto &doorbell = reinterpret_cast(doorbellRegister); logger->info("Doorbell register: {:#08x}", doorbell.value); logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no")); diff --git a/fpga/lib/ips/switch.cpp b/fpga/lib/ips/switch.cpp index d788ecc18..d79d7bb40 100644 --- a/fpga/lib/ips/switch.cpp +++ b/fpga/lib/ips/switch.cpp @@ -70,8 +70,8 @@ AxiStreamSwitch::init() } bool -AxiStreamSwitch::connectInternal(const std::string& portSlave, - const std::string& portMaster) +AxiStreamSwitch::connectInternal(const std::string &portSlave, + const std::string &portMaster) { // check if slave port exists try { @@ -129,21 +129,21 @@ AxiStreamSwitch::connectInternal(const std::string& portSlave, } int -AxiStreamSwitch::portNameToNum(const std::string& portName) +AxiStreamSwitch::portNameToNum(const std::string &portName) { const std::string number = portName.substr(1, 2); return std::stoi(number); } bool -AxiStreamSwitchFactory::configureJson(Core& ip, json_t* json_ip) +AxiStreamSwitchFactory::configureJson(Core &ip, json_t* json_ip) { if (not NodeFactory::configureJson(ip, json_ip)) return false; auto logger = getLogger(); - auto& axiSwitch = dynamic_cast(ip); + auto &axiSwitch = dynamic_cast(ip); if (json_unpack(json_ip, "{ s: i }", "num_ports", &axiSwitch.num_ports) != 0) { logger->error("Cannot parse 'num_ports'"); @@ -154,6 +154,6 @@ AxiStreamSwitchFactory::configureJson(Core& ip, json_t* json_ip) } -} // namespace ip -} // namespace fpga -} // namespace villas +} /* namespace ip */ +} /* namespace fpga */ +} /* namespace villas */ diff --git a/fpga/lib/node.cpp b/fpga/lib/node.cpp index a7ca3892c..e3167408b 100644 --- a/fpga/lib/node.cpp +++ b/fpga/lib/node.cpp @@ -39,9 +39,9 @@ StreamGraph Node::streamGraph; bool -NodeFactory::configureJson(Core& ip, json_t* json_ip) +NodeFactory::configureJson(Core &ip, json_t* json_ip) { - auto& Node = dynamic_cast(ip); + auto &Node = dynamic_cast(ip); auto logger = getLogger(); json_t* json_ports = json_object_get(json_ip, "ports"); @@ -115,7 +115,7 @@ Node::getLoopbackPorts() const return { "", "" }; } -bool Node::connect(const StreamVertex& from, const StreamVertex& to) +bool Node::connect(const StreamVertex &from, const StreamVertex &to) { if (from.nodeName != getInstanceName()) { logger->error("Cannot connect from a foreign StreamVertex: {}", from); @@ -192,8 +192,8 @@ Node::loopbackPossible() const } bool -Node::connectInternal(const std::string& slavePort, - const std::string& masterPort) +Node::connectInternal(const std::string &slavePort, + const std::string &masterPort) { (void) slavePort; (void) masterPort; @@ -206,8 +206,8 @@ bool Node::connectLoopback() { auto ports = getLoopbackPorts(); - const auto& portMaster = portsMaster[ports.first]; - const auto& portSlave = portsSlave[ports.second]; + const auto &portMaster = portsMaster[ports.first]; + const auto &portSlave = portsSlave[ports.second]; logger->debug("master port: {}", ports.first); logger->debug("slave port: {}", ports.second); diff --git a/fpga/src/fpga.c b/fpga/src/fpga.c index 6a059fa27..80e40ce5c 100644 --- a/fpga/src/fpga.c +++ b/fpga/src/fpga.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include diff --git a/fpga/src/villas-fpga-pipe.cpp b/fpga/src/villas-fpga-pipe.cpp index 9a49e41e1..418e47832 100644 --- a/fpga/src/villas-fpga-pipe.cpp +++ b/fpga/src/villas-fpga-pipe.cpp @@ -64,7 +64,7 @@ void setupColorHandling() } std::shared_ptr -setupFpgaCard(const std::string& configFile, const std::string& fpgaName) +setupFpgaCard(const std::string &configFile, const std::string &fpgaName) { if (pci_init(&pci) != 0) { logger->error("Cannot initialize PCI"); @@ -104,7 +104,7 @@ setupFpgaCard(const std::string& configFile, const std::string& fpgaName) // create all FPGA card instances using the corresponding plugin auto cards = fpgaCardPlugin->make(fpgas, &pci, vfioContainer); - for (auto& fpgaCard : cards) { + for (auto &fpgaCard : cards) { if (fpgaCard->name == fpgaName) { return fpgaCard; } @@ -192,7 +192,7 @@ int main(int argc, char* argv[]) size_t memIdx = 0; - for (auto& value: values) { + for (auto &value: values) { if (value.empty()) continue; const int32_t number = std::stoi(value); diff --git a/fpga/tests/dma.cpp b/fpga/tests/dma.cpp index f462c663f..4bb36094f 100644 --- a/fpga/tests/dma.cpp +++ b/fpga/tests/dma.cpp @@ -39,7 +39,7 @@ Test(fpga, dma, .description = "DMA") std::list> dmaIps; - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { if (*ip == fpga::Vlnv("xilinx.com:ip:axi_dma:")) { auto dma = std::dynamic_pointer_cast(ip); dmaIps.push_back(dma); @@ -47,7 +47,7 @@ Test(fpga, dma, .description = "DMA") } size_t count = 0; - for (auto& dma : dmaIps) { + for (auto &dma : dmaIps) { logger->info("Testing {}", *dma); if (not dma->loopbackPossible()) { diff --git a/fpga/tests/fifo.cpp b/fpga/tests/fifo.cpp index 5744f090d..3898b882a 100644 --- a/fpga/tests/fifo.cpp +++ b/fpga/tests/fifo.cpp @@ -40,7 +40,7 @@ Test(fpga, fifo, .description = "FIFO") auto logger = logging.get("unit-test:fifo"); - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { // skip non-fifo IPs if (*ip != fpga::Vlnv("xilinx.com:ip:axi_fifo_mm_s:")) continue; diff --git a/fpga/tests/fpga.cpp b/fpga/tests/fpga.cpp index 31a2806a8..97f2b6eb0 100644 --- a/fpga/tests/fpga.cpp +++ b/fpga/tests/fpga.cpp @@ -59,7 +59,7 @@ static void init() ret = pci_init(&pci); cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system"); - auto vfioContainer = VfioContainer::create(); + auto vfioContainer = kernel::vfio::Container::create(); /* Parse FPGA configuration */ char *fn = getenv("TEST_CONFIG"); diff --git a/fpga/tests/global.hpp b/fpga/tests/global.hpp index b0699edaa..b58ca8746 100644 --- a/fpga/tests/global.hpp +++ b/fpga/tests/global.hpp @@ -29,7 +29,7 @@ class FpgaState { public: // list of all available FPGA cards, only first will be tested at the moment - villas::fpga::CardList cards; + villas::fpga::PCIeCard::List cards; }; // global state to be shared by unittests diff --git a/fpga/tests/gpu.cpp b/fpga/tests/gpu.cpp index 33a6c76f6..7f85fb5fb 100644 --- a/fpga/tests/gpu.cpp +++ b/fpga/tests/gpu.cpp @@ -44,7 +44,7 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests") { auto logger = logging.get("unit-test:dma"); - auto& card = state.cards.front(); + auto &card = state.cards.front(); auto gpuPlugin = Plugin::Registry("cuda"); cr_assert_not_null(gpuPlugin, "No GPU plugin found"); @@ -53,10 +53,10 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests") cr_assert(gpus.size() > 0, "No GPUs found"); // just get first cpu - auto& gpu = gpus.front(); + auto &gpu = gpus.front(); size_t count = 0; - for (auto& ip : card->ips) { + for (auto &ip : card->ips) { // skip non-dma IPs if (*ip != fpga::Vlnv("xilinx.com:ip:axi_bram_ctrl:")) continue; @@ -97,17 +97,17 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests") gpu->makeAccessibleToPCIeAndVA(gpuMem1.getMemoryBlock()); -// auto& src = bram0; -// auto& dst = bram1; +// auto &src = bram0; +// auto &dst = bram1; -// auto& src = hostRam0; -// auto& dst = hostRam1; +// auto &src = hostRam0; +// auto &dst = hostRam1; - auto& src = dmaRam0; -// auto& dst = dmaRam1; + auto &src = dmaRam0; +// auto &dst = dmaRam1; -// auto& src = gpuMem0; - auto& dst = gpuMem1; +// auto &src = gpuMem0; + auto &dst = gpuMem1; std::list>> memcpyFuncs = { diff --git a/fpga/tests/rtds.cpp b/fpga/tests/rtds.cpp index 50e8e7e70..11b97bee8 100644 --- a/fpga/tests/rtds.cpp +++ b/fpga/tests/rtds.cpp @@ -49,7 +49,7 @@ Test(fpga, rtds, .description = "RTDS") std::list rtdsIps; std::list dmaIps; - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { if (*ip == villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) { auto rtds = reinterpret_cast(ip.get()); rtdsIps.push_back(rtds); diff --git a/fpga/tests/rtds2gpu.cpp b/fpga/tests/rtds2gpu.cpp index 382c96969..a405336ca 100644 --- a/fpga/tests/rtds2gpu.cpp +++ b/fpga/tests/rtds2gpu.cpp @@ -72,7 +72,7 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu") { auto logger = logging.get("unit-test:rtds2gpu"); - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:")) continue; @@ -191,11 +191,11 @@ Test(fpga, rtds2gpu_rtt_cpu, .description = "Rtds2Gpu RTT via CPU") cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found"); cr_assert_not_null(rtds2gpu, "No Rtds2Gpu IP not found"); - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) continue; - auto& rtds = dynamic_cast(*ip); + auto &rtds = dynamic_cast(*ip); logger->info("Testing {}", rtds); auto dmaRam = HostDmaRam::getAllocator().allocate(SAMPLE_COUNT + 1); @@ -269,7 +269,7 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU") cr_assert(gpus.size() > 0, "No GPUs found"); // just get first cpu - auto& gpu = gpus.front(); + auto &gpu = gpus.front(); // allocate memory on GPU and make accessible by to PCIe/FPGA auto gpuRam = gpu->getAllocator().allocate(SAMPLE_COUNT + 1); @@ -291,11 +291,11 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU") // auto doorbellInCpu = reinterpret_cast(&gpuRam[DOORBELL_OFFSET]); - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) continue; - auto& rtds = dynamic_cast(*ip); + auto &rtds = dynamic_cast(*ip); logger->info("Testing {}", rtds); diff --git a/fpga/tests/rtds_rtt.c b/fpga/tests/rtds_rtt.c index ce274ddae..532de1314 100644 --- a/fpga/tests/rtds_rtt.c +++ b/fpga/tests/rtds_rtt.c @@ -42,7 +42,7 @@ Test(fpga, rtds_rtt, .description = "RTDS: tight rtt") std::list dmaIps; /* Get IP cores */ - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { if (*ip == villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) { auto rtds = reinterpret_cast(ip.get()); rtdsIps.push_back(rtds); diff --git a/fpga/tests/timer.cpp b/fpga/tests/timer.cpp index d98f66f9c..53e71af9b 100644 --- a/fpga/tests/timer.cpp +++ b/fpga/tests/timer.cpp @@ -34,7 +34,7 @@ Test(fpga, timer, .description = "Timer Counter") auto logger = villas::logging.get("unit-test:timer"); size_t count = 0; - for (auto& ip : state.cards.front()->ips) { + for (auto &ip : state.cards.front()->ips) { // skip non-timer IPs if (*ip != villas::fpga::Vlnv("xilinx.com:ip:axi_timer:")) { continue; From a9f9dc4a37b8e243e4da4d1e2cf774885b05f924 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Sun, 14 Jun 2020 22:11:15 +0200 Subject: [PATCH 02/11] refactor: no namespace scoeps in source files --- fpga/gpu/src/gpu.cpp | 7 ++--- fpga/lib/card.cpp | 43 +++++++++++++----------------- fpga/lib/core.cpp | 9 +------ fpga/lib/ips/aurora.cpp | 8 +----- fpga/lib/ips/bram.cpp | 7 +---- fpga/lib/ips/dma.cpp | 8 +----- fpga/lib/ips/fifo.cpp | 7 +---- fpga/lib/ips/gpio.cpp | 7 +---- fpga/lib/ips/intc.cpp | 8 +----- fpga/lib/ips/pcie.cpp | 8 +----- fpga/lib/ips/rtds.cpp | 7 +---- fpga/lib/ips/rtds2gpu/gpu2rtds.cpp | 7 +---- fpga/lib/ips/rtds2gpu/rtds2gpu.cpp | 10 +------ fpga/lib/ips/timer.cpp | 9 +------ fpga/lib/memory.cpp | 4 +-- fpga/lib/node.cpp | 9 +------ fpga/lib/vlnv.cpp | 5 +--- 17 files changed, 36 insertions(+), 127 deletions(-) diff --git a/fpga/gpu/src/gpu.cpp b/fpga/gpu/src/gpu.cpp index 2bafa26d0..602a3a015 100644 --- a/fpga/gpu/src/gpu.cpp +++ b/fpga/gpu/src/gpu.cpp @@ -39,8 +39,8 @@ #include "kernels.hpp" -namespace villas { -namespace gpu { + +using namespace villas::gpu; static GpuFactory gpuFactory; @@ -523,6 +523,3 @@ GpuFactory::make() return gpuList; } - -} // namespace villas -} // namespace gpu diff --git a/fpga/lib/card.cpp b/fpga/lib/card.cpp index eccb2df4c..4e3fbfceb 100644 --- a/fpga/lib/card.cpp +++ b/fpga/lib/card.cpp @@ -24,24 +24,24 @@ #include #include +#include #include -#include +#include #include #include #include -namespace villas { -namespace fpga { +using namespace villas::fpga; // instantiate factory to register static PCIeCardFactory PCIeCardFactory; -CardList -PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptr vc) +PCIeCard::List +PCIeCardFactory::make(json_t *json, kernel::pci::DeviceList *pci, std::shared_ptr vc) { - CardList cards; + PCIeCard::List cards; auto logger = getStaticLogger(); const char *card_name; @@ -74,7 +74,7 @@ PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptrpci = pci; card->vfioContainer = std::move(vc); card->affinity = affinity; - card->do_reset = do_reset != 0; + card->doReset = do_reset != 0; const char* error; @@ -86,22 +86,20 @@ PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptrwarn("Failed to parse PCI ID: {}", error); } - if (not card->init()) { logger->warn("Cannot start FPGA card {}", card_name); continue; } - card->ips = ip::CoreFactory::make(card.get(), json_ips); - if (card->ips.empty()) { - logger->error("Cannot initialize IPs of FPGA card {}", card_name); - continue; - } + if (not json_is_object(json_ips)) + throw ConfigError(json_ips, "node-config-fpga-ips", "FPGA IP core list must be an object!"); - if (not card->check()) { - logger->warn("Checking of FPGA card {} failed", card_name); - continue; - } + card->ips = ip::CoreFactory::make(card.get(), json_ips); + if (card->ips.empty()) + throw ConfigError(json_ips, "node-config-fpga-ips", "Cannot initialize IPs of FPGA card {}", card_name); + + if (not card->check()) + throw RuntimeError("Checking of FPGA card {} failed", card_name); cards.push_back(std::move(card)); } @@ -231,8 +229,8 @@ PCIeCard::init() } /* Attach PCIe card to VFIO container */ - VfioDevice& device = vfioContainer->attachDevice(pdev); - this->vfioDevice = &device; + kernel::vfio::Device &device = vfioContainer->attachDevice(pdev); + this->kernel::vfio::Device = &device; /* Enable memory access and PCI bus mastering for DMA */ if (not device.pciEnable()) { @@ -241,9 +239,9 @@ PCIeCard::init() } /* Reset system? */ - if (do_reset) { + if (doReset) { /* Reset / detect PCI device */ - if (not vfioDevice->pciHotReset()) { + if (not kernel::vfio::Device->pciHotReset()) { logger->error("Failed to reset PCI device"); return false; } @@ -256,6 +254,3 @@ PCIeCard::init() return true; } - -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/core.cpp b/fpga/lib/core.cpp index 731ff1fe9..91297ebdc 100644 --- a/fpga/lib/core.cpp +++ b/fpga/lib/core.cpp @@ -37,9 +37,7 @@ #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; // Special IPs that have to be initialized first. Will be initialized in the // same order as they appear in this list, i.e. first here will be initialized @@ -364,8 +362,3 @@ Core::getInterruptController(const std::string &interruptName) const return nullptr; } } - - -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/aurora.cpp b/fpga/lib/ips/aurora.cpp index 4b80f7809..b6eda7c2b 100644 --- a/fpga/lib/ips/aurora.cpp +++ b/fpga/lib/ips/aurora.cpp @@ -66,9 +66,7 @@ #define AURORA_AXIS_CR_SEQ_ECHO (1 << 4) -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; static AuroraFactory auroraFactoryInstance; @@ -118,7 +116,3 @@ void Aurora::resetFrameCounters() writeMemory(registerMemory, AURORA_AXIS_CR_OFFSET, cr); } - -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/bram.cpp b/fpga/lib/ips/bram.cpp index b6227cf94..d1c2faf1a 100644 --- a/fpga/lib/ips/bram.cpp +++ b/fpga/lib/ips/bram.cpp @@ -22,9 +22,7 @@ #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; static BramFactory factory; @@ -49,6 +47,3 @@ bool Bram::init() return true; } -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/dma.cpp b/fpga/lib/ips/dma.cpp index b25b26352..1121384a8 100644 --- a/fpga/lib/ips/dma.cpp +++ b/fpga/lib/ips/dma.cpp @@ -35,9 +35,7 @@ #define FPGA_DMA_BOUNDARY 0x1000 -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; // instantiate factory to make available to plugin infrastructure static DmaFactory factory; @@ -401,7 +399,3 @@ Dma::dump() logger->info("S2MM_LENGTH: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET)); } - -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/fifo.cpp b/fpga/lib/ips/fifo.cpp index 7d481a727..35de585f9 100644 --- a/fpga/lib/ips/fifo.cpp +++ b/fpga/lib/ips/fifo.cpp @@ -32,9 +32,7 @@ #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; // instantiate factory to make available to plugin infrastructure static FifoFactory factory; @@ -113,6 +111,3 @@ size_t Fifo::read(void *buf, size_t len) return nextlen; } -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/gpio.cpp b/fpga/lib/ips/gpio.cpp index 6f287970c..37b10ce16 100644 --- a/fpga/lib/ips/gpio.cpp +++ b/fpga/lib/ips/gpio.cpp @@ -31,9 +31,7 @@ #include #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; // instantiate factory to make available to plugin infrastructure @@ -47,6 +45,3 @@ GeneralPurposeIO::init() return true; } -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/intc.cpp b/fpga/lib/ips/intc.cpp index 9467f1a1e..098886e3e 100644 --- a/fpga/lib/ips/intc.cpp +++ b/fpga/lib/ips/intc.cpp @@ -31,10 +31,7 @@ #include #include -namespace villas { -namespace fpga { -namespace ip { - +using namespace villas::fpga::ip; // instantiate factory to make available to plugin infrastructure static InterruptControllerFactory factory; @@ -171,6 +168,3 @@ InterruptController::waitForInterrupt(int irq) } } -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/pcie.cpp b/fpga/lib/ips/pcie.cpp index a205032bf..bb656dc7d 100644 --- a/fpga/lib/ips/pcie.cpp +++ b/fpga/lib/ips/pcie.cpp @@ -29,9 +29,7 @@ #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; static AxiPciExpressBridgeFactory factory; @@ -170,7 +168,3 @@ AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip) return true; } - -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/rtds.cpp b/fpga/lib/ips/rtds.cpp index c0061f575..13ce264c0 100644 --- a/fpga/lib/ips/rtds.cpp +++ b/fpga/lib/ips/rtds.cpp @@ -53,9 +53,7 @@ /* Control register bits */ #define RTDS_AXIS_CR_DISABLE_LINK 0 /**< Disable SFP TX when set */ -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; static RtdsFactory rtdsFactoryInstance; @@ -92,6 +90,3 @@ double Rtds::getDt() return (dt == 0xFFFF) ? 0.0 : (double) dt / RTDS_HZ; } -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp b/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp index b5d44a003..1c914cc83 100644 --- a/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp +++ b/fpga/lib/ips/rtds2gpu/gpu2rtds.cpp @@ -5,9 +5,7 @@ #include #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; static Gpu2RtdsFactory factory; @@ -131,6 +129,3 @@ Gpu2Rtds::getMaxFrameSize() // logger->info(" Seq. number: {}", doorbell.seq_nr); //} -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp b/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp index 881bc760a..416d6314b 100644 --- a/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp +++ b/fpga/lib/ips/rtds2gpu/rtds2gpu.cpp @@ -5,10 +5,7 @@ #include #include -namespace villas { -namespace fpga { -namespace ip { - +using namespace villas::fpga::ip; static Rtds2GpuFactory factory; bool Rtds2Gpu::init() @@ -28,8 +25,6 @@ bool Rtds2Gpu::init() return true; } - - void Rtds2Gpu::dump(spdlog::level::level_enum logLevel) { const auto baseaddr = XRtds2gpu_Get_baseaddr(&xInstance); @@ -116,6 +111,3 @@ Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const logger->info(" Seq. number: {}", doorbell.seq_nr); } -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/ips/timer.cpp b/fpga/lib/ips/timer.cpp index 2a0ef576f..ace98122a 100644 --- a/fpga/lib/ips/timer.cpp +++ b/fpga/lib/ips/timer.cpp @@ -30,9 +30,7 @@ #include #include -namespace villas { -namespace fpga { -namespace ip { +using namespace villas::fpga::ip; // instantiate factory to make available to plugin infrastructure @@ -80,8 +78,3 @@ uint32_t Timer::remaining() { return XTmrCtr_GetValue(&xTmr, 0); } - - -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/memory.cpp b/fpga/lib/memory.cpp index ca850782d..a2b8b2737 100644 --- a/fpga/lib/memory.cpp +++ b/fpga/lib/memory.cpp @@ -25,7 +25,7 @@ #include -namespace villas { +using namespace villas; bool HostRam::free(void* addr, size_t length) @@ -42,5 +42,3 @@ HostRam::allocate(size_t length, int flags) return mmap(nullptr, length, mmap_protection, mmap_flags, 0, 0); } - -} // namespace villas diff --git a/fpga/lib/node.cpp b/fpga/lib/node.cpp index e3167408b..810d1b63d 100644 --- a/fpga/lib/node.cpp +++ b/fpga/lib/node.cpp @@ -30,10 +30,7 @@ #include #include -namespace villas { -namespace fpga { -namespace ip { - +using namespace villas::fpga::ip; StreamGraph Node::streamGraph; @@ -214,7 +211,3 @@ Node::connectLoopback() return connect(*portMaster, *portSlave); } - -} // namespace ip -} // namespace fpga -} // namespace villas diff --git a/fpga/lib/vlnv.cpp b/fpga/lib/vlnv.cpp index 3e430c127..0d3dd208d 100644 --- a/fpga/lib/vlnv.cpp +++ b/fpga/lib/vlnv.cpp @@ -25,8 +25,7 @@ #include -namespace villas { -namespace fpga { +using namespace villas::fpga; bool Vlnv::operator==(const Vlnv &other) const @@ -74,5 +73,3 @@ Vlnv::toString() const return string; } -} // namespace fpga -} // namespace villas From d938bd95b15f6214b1a415e61e86ef835c349098 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Sun, 14 Jun 2020 22:11:58 +0200 Subject: [PATCH 03/11] cmake: fixups for inclusion into VILLASnode --- fpga/CMakeLists.txt | 19 ++++++++++++++++++- fpga/lib/CMakeLists.txt | 10 ++-------- fpga/tests/CMakeLists.txt | 8 ++++---- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/fpga/CMakeLists.txt b/fpga/CMakeLists.txt index 1cb70a547..2531ea8f9 100644 --- a/fpga/CMakeLists.txt +++ b/fpga/CMakeLists.txt @@ -29,9 +29,16 @@ project(VILLASfpga set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake) +# Several CMake settings/defaults set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra -Werror") +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME) + set(TOPLEVEL_PROJECT ON) +else() + set(TOPLEVEL_PROJECT OFF) +endif() + # GPU library is optional, check for CUDA presence include(CheckLanguage) check_language(CUDA) @@ -42,14 +49,24 @@ else() message("No CUDA support, not building GPU library") endif() +include(FindPkgConfig) + +pkg_check_modules(JANSSON REQUIRED IMPORTED_TARGET jansson) +pkg_check_modules(XIL REQUIRED IMPORTED_TARGET libxil) + +find_package(Threads) + include_directories(thirdparty/CLI11) include_directories(thirdparty/rang) -add_subdirectory(common) add_subdirectory(lib) add_subdirectory(src) add_subdirectory(tests) +if(NOT CMAKE_PROJECT_NAME STREQUAL "villas-node") + add_subdirectory(common) +endif() + # Project settings set(PROJECT_NAME "VILLASfpga") set(PROJECT_DESCRIPTION "Host library for configuring and communicating with VILLASfpga") diff --git a/fpga/lib/CMakeLists.txt b/fpga/lib/CMakeLists.txt index 08db15e33..c22f299e9 100644 --- a/fpga/lib/CMakeLists.txt +++ b/fpga/lib/CMakeLists.txt @@ -46,13 +46,6 @@ set(SOURCES set_source_files_properties(ips/rtds2gpu/xrtds2gpu.c PROPERTIES COMPILE_FLAGS -Wno-int-to-pointer-cast) -include(FindPkgConfig) - -pkg_check_modules(JANSSON jansson) -pkg_check_modules(XIL libxil) - -find_package(Threads) - add_library(villas-fpga SHARED ${SOURCES}) target_link_libraries(villas-fpga PUBLIC villas-common) @@ -64,7 +57,8 @@ target_compile_definitions(villas-fpga PRIVATE target_include_directories(villas-fpga PUBLIC - ../include + ${PROJECT_BINARY_DIR}/include + ${PROJECT_SOURCE_DIR}/include ${XIL_INCLUDE_DIRS} ${JANSSON_INCLUDE_DIRS} ) diff --git a/fpga/tests/CMakeLists.txt b/fpga/tests/CMakeLists.txt index 7d6050cde..6738b76a0 100644 --- a/fpga/tests/CMakeLists.txt +++ b/fpga/tests/CMakeLists.txt @@ -34,22 +34,22 @@ set(SOURCES # hls.cpp # intc.cpp -add_executable(unit-tests ${SOURCES}) +add_executable(unit-tests-fpga ${SOURCES}) if (CMAKE_CUDA_COMPILER) enable_language(CUDA) - target_sources(unit-tests PRIVATE + target_sources(unit-tests-fpga PRIVATE gpu.cpp rtds2gpu.cpp gpu_kernels.cu) endif () find_package(Criterion REQUIRED) -target_include_directories(unit-tests PUBLIC +target_include_directories(unit-tests-fpga PUBLIC ../include ${CRITERION_INCLUDE_DIRECTORIES} ) -target_link_libraries(unit-tests PUBLIC +target_link_libraries(unit-tests-fpga PUBLIC villas-fpga ${CRITERION_LIBRARIES} ) From cc456b652567779d013dbcfd9cf58fa58d8055ba Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Sun, 14 Jun 2020 22:12:41 +0200 Subject: [PATCH 04/11] refactor: no namespace scopes in source files --- fpga/gpu/src/kernels.cu | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/fpga/gpu/src/kernels.cu b/fpga/gpu/src/kernels.cu index c03ed7e0c..db0c96cd0 100644 --- a/fpga/gpu/src/kernels.cu +++ b/fpga/gpu/src/kernels.cu @@ -20,8 +20,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . *********************************************************************************/ - - #include + +#include #include @@ -30,8 +30,7 @@ #include "kernels.hpp" -namespace villas { -namespace gpu { +using namespace villas::gpu; __global__ void @@ -61,6 +60,3 @@ kernel_memcpy(volatile uint8_t* dst, volatile uint8_t* src, size_t length) length--; } } - -} // namespace villas -} // namespace gpu From 74f55fa98ce45aa7b0d68b203a99152d6ec648d2 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:08:49 +0200 Subject: [PATCH 05/11] refactor: more code-style improvements --- fpga/gpu/src/gpu.cpp | 15 ++++++++------- fpga/include/villas/fpga/card.hpp | 12 +++++++++--- fpga/include/villas/fpga/node.hpp | 6 +++--- fpga/lib/core.cpp | 7 +++---- fpga/lib/ips/dma.cpp | 4 ++-- fpga/lib/ips/pcie.cpp | 4 +--- 6 files changed, 26 insertions(+), 22 deletions(-) diff --git a/fpga/gpu/src/gpu.cpp b/fpga/gpu/src/gpu.cpp index 602a3a015..910dfd19d 100644 --- a/fpga/gpu/src/gpu.cpp +++ b/fpga/gpu/src/gpu.cpp @@ -115,14 +115,14 @@ bool Gpu::registerIoMemory(const MemoryBlock &mem) // overlapping window, so this will fail badly! auto translation = mm.getTranslation(masterPciEAddrSpaceId, mem.getAddrSpaceId()); - if (translation.getSize() >= mem.getSize()) { + if (translation.getSize() >= mem.getSize()) // there is already a sufficient path logger->debug("Already mapped through another mapping"); return true; - } else { + else logger->warn("There's already a mapping, but too small"); - } - } catch(const std::out_of_range&) { + } + catch(const std::out_of_range&) { // not yet reachable, that's okay, proceed } @@ -333,7 +333,8 @@ Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem) mem.getAddrSpaceId()); return registerIoMemory(mem); - } else { + } + else { logger->debug("Memory block {} is assumed to be non-CUDA host memory", mem.getAddrSpaceId()); @@ -400,8 +401,8 @@ GpuAllocator::allocateBlock(size_t size) logger->debug("Found existing chunk that can host the requested block"); return (*chunk)->allocateBlock(size); - - } else { + } + else { // allocate a new chunk // rounded-up multiple of GPU page size diff --git a/fpga/include/villas/fpga/card.hpp b/fpga/include/villas/fpga/card.hpp index ceacebc44..b555bc6e3 100644 --- a/fpga/include/villas/fpga/card.hpp +++ b/fpga/include/villas/fpga/card.hpp @@ -75,9 +75,15 @@ public: bool reset() { return true; } void dump() { } - ip::Core::Ptr lookupIp(const std::string &name) const; - ip::Core::Ptr lookupIp(const Vlnv &vlnv) const; - ip::Core::Ptr lookupIp(const ip::IpIdentifier &id) const; + ip::Core::Ptr + lookupIp(const std::string &name) const; + + ip::Core::Ptr + lookupIp(const Vlnv &vlnv) const; + + ip::Core::Ptr + lookupIp(const ip::IpIdentifier &id) const; + bool mapMemoryBlock(const MemoryBlock &block); diff --git a/fpga/include/villas/fpga/node.hpp b/fpga/include/villas/fpga/node.hpp index e879bb717..6108e7034 100644 --- a/fpga/include/villas/fpga/node.hpp +++ b/fpga/include/villas/fpga/node.hpp @@ -125,8 +125,8 @@ public: protected: virtual bool - connectInternal(const std::string& slavePort, - const std::string& masterPort); + connectInternal(const std::string &slavePort, + const std::string &masterPort); private: std::pair getLoopbackPorts() const; @@ -142,7 +142,7 @@ class NodeFactory : public CoreFactory { public: using CoreFactory::CoreFactory; - virtual bool configureJson(Core& ip, json_t *json_ip); + virtual bool configureJson(Core &ip, json_t *json_ip); }; /** @} */ diff --git a/fpga/lib/core.cpp b/fpga/lib/core.cpp index 91297ebdc..325525183 100644 --- a/fpga/lib/core.cpp +++ b/fpga/lib/core.cpp @@ -36,7 +36,7 @@ #include #include - +using namespace villas::fpga; using namespace villas::fpga::ip; // Special IPs that have to be initialized first. Will be initialized in the @@ -115,10 +115,9 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips) if (CoreFactory == nullptr) { loggerStatic->warn("No plugin found to handle {}", id.getVlnv()); continue; - } else { - loggerStatic->debug("Using {} for IP {}", - CoreFactory->getName(), id.getVlnv()); } + else + loggerStatic->debug("Using {} for IP {}", CoreFactory->getName(), id.getVlnv()); auto logger = CoreFactory->getLogger(); diff --git a/fpga/lib/ips/dma.cpp b/fpga/lib/ips/dma.cpp index 1121384a8..7dd6dc8cf 100644 --- a/fpga/lib/ips/dma.cpp +++ b/fpga/lib/ips/dma.cpp @@ -73,9 +73,9 @@ Dma::init() if (XAxiDma_Selftest(&xDma) != XST_SUCCESS) { logger->error("DMA selftest failed"); return false; - } else { - logger->debug("DMA selftest passed"); } + else + logger->debug("DMA selftest passed"); /* Map buffer descriptors */ if (hasScatterGather()) { diff --git a/fpga/lib/ips/pcie.cpp b/fpga/lib/ips/pcie.cpp index bb656dc7d..cac9f5471 100644 --- a/fpga/lib/ips/pcie.cpp +++ b/fpga/lib/ips/pcie.cpp @@ -157,12 +157,10 @@ AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip) .size = static_cast(size), .translation = translation }; - - } else { + } else pcie.pcieToAxiTranslations[bar_name] = { .translation = translation }; - } } } From 6c225c8faed532c006bbff33524c88af47815fd4 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:21:05 +0200 Subject: [PATCH 06/11] update VILLAScommon submodule --- fpga/common | 2 +- fpga/include/villas/fpga/card.hpp | 42 +++++++++++-------------- fpga/include/villas/fpga/node.hpp | 2 ++ fpga/lib/card.cpp | 52 +++++++++++++------------------ fpga/lib/ips/intc.cpp | 6 ++-- fpga/lib/ips/pcie.cpp | 26 +++++++--------- fpga/src/fpga.c | 5 +-- fpga/src/villas-fpga-pipe.cpp | 11 +++---- fpga/tests/fpga.cpp | 9 ++---- 9 files changed, 64 insertions(+), 91 deletions(-) diff --git a/fpga/common b/fpga/common index 952945fc4..3b5952a41 160000 --- a/fpga/common +++ b/fpga/common @@ -1 +1 @@ -Subproject commit 952945fc4bcdcdca0dfbe1389f811ceb7b5c5744 +Subproject commit 3b5952a413ba8f8c7731c6a0c8336e1f523884b8 diff --git a/fpga/include/villas/fpga/card.hpp b/fpga/include/villas/fpga/card.hpp index b555bc6e3..7efd21988 100644 --- a/fpga/include/villas/fpga/card.hpp +++ b/fpga/include/villas/fpga/card.hpp @@ -38,35 +38,32 @@ #include #include -#include +#include #include #include #include -#define PCI_FILTER_DEFAULT_FPGA { \ - .id = { \ - .vendor = FPGA_PCI_VID_XILINX, \ - .device = FPGA_PCI_PID_VFPGA, \ - .class_code = 0 \ - }, \ - .slot = { } \ -} - namespace villas { namespace fpga { - /* Forward declarations */ struct vfio_container; class PCIeCardFactory; -class PCIeCard { +class Card { public: + using Ptr = std::shared_ptr; + using List = std::list; + friend PCIeCardFactory; - PCIeCard() : filter(PCI_FILTER_DEFAULT_FPGA) {} +}; + +class PCIeCard : public Card { +public: + ~PCIeCard(); bool init(); @@ -95,20 +92,18 @@ private: public: // TODO: make this private ip::Core::List ips; ///< IPs located on this FPGA card - bool do_reset; /**< Reset VILLASfpga during startup? */ + bool doReset; /**< Reset VILLASfpga during startup? */ int affinity; /**< Affinity for MSI interrupts */ std::string name; /**< The name of the FPGA card */ - struct pci* pci; - struct pci_device filter; /**< Filter for PCI device. */ - struct pci_device* pdev; /**< PCI device handle */ + std::shared_ptr pdev; /**< PCI device handle */ /// The VFIO container that this card is part of - std::shared_ptr vfioContainer; + std::shared_ptr vfioContainer; /// The VFIO device that represents this card - VfioDevice* vfioDevice; + kernel::vfio::Device* vfioDevice; /// Slave address space ID to access the PCIe address space from the FPGA MemoryManager::AddressSpaceId addrSpaceIdDeviceToHost; @@ -125,16 +120,15 @@ protected: Logger logger; }; -using CardList = std::list>; - class PCIeCardFactory : public plugin::Plugin { public: - static CardList - make(json_t *json, struct pci* pci, std::shared_ptr vc); + static Card::List + make(json_t *json, std::shared_ptr pci, std::shared_ptr vc); static PCIeCard* - create(); + create() + { return new PCIeCard(); } static Logger getStaticLogger() diff --git a/fpga/include/villas/fpga/node.hpp b/fpga/include/villas/fpga/node.hpp index 6108e7034..70e83f304 100644 --- a/fpga/include/villas/fpga/node.hpp +++ b/fpga/include/villas/fpga/node.hpp @@ -88,6 +88,8 @@ public: class Node : public virtual Core { public: + using Ptr = std::shared_ptr; + friend class NodeFactory; struct StreamPort { diff --git a/fpga/lib/card.cpp b/fpga/lib/card.cpp index 4e3fbfceb..6bd6187d7 100644 --- a/fpga/lib/card.cpp +++ b/fpga/lib/card.cpp @@ -33,13 +33,16 @@ #include #include +using namespace villas; using namespace villas::fpga; // instantiate factory to register -static PCIeCardFactory PCIeCardFactory; +static PCIeCardFactory villas::fpga::PCIeCardFactory; + +static const kernel::pci::Device defaultFilter((kernel::pci::Id(FPGA_PCI_VID_XILINX, FPGA_PCI_PID_VFPGA))); PCIeCard::List -PCIeCardFactory::make(json_t *json, kernel::pci::DeviceList *pci, std::shared_ptr vc) +PCIeCardFactory::make(json_t *json, std::shared_ptr pci, std::shared_ptr vc) { PCIeCard::List cards; auto logger = getStaticLogger(); @@ -71,19 +74,22 @@ PCIeCardFactory::make(json_t *json, kernel::pci::DeviceList *pci, std::shared_pt // populate generic properties card->name = std::string(card_name); - card->pci = pci; card->vfioContainer = std::move(vc); card->affinity = affinity; card->doReset = do_reset != 0; - const char* error; + kernel::pci::Device filter = defaultFilter; + + if (pci_id) + filter.id = kernel::pci::Id(pci_id); + if (pci_slot) + filter.slot = kernel::pci::Slot(pci_slot); - if (pci_slot != nullptr and pci_device_parse_slot(&card->filter, pci_slot, &error) != 0) { - logger->warn("Failed to parse PCI slot: {}", error); - } - - if (pci_id != nullptr and pci_device_parse_id(&card->filter, pci_id, &error) != 0) { - logger->warn("Failed to parse PCI ID: {}", error); + /* Search for FPGA card */ + card->pdev = pci->lookupDevice(filter); + if (!card->pdev) { + logger->warn("Failed to find PCI device"); + continue; } if (not card->init()) { @@ -107,14 +113,6 @@ PCIeCardFactory::make(json_t *json, kernel::pci::DeviceList *pci, std::shared_pt return cards; } - -PCIeCard* -PCIeCardFactory::create() -{ - return new fpga::PCIeCard; -} - - PCIeCard::~PCIeCard() { auto &mm = MemoryManager::get(); @@ -183,12 +181,11 @@ PCIeCard::mapMemoryBlock(const MemoryBlock &block) auto &mm = MemoryManager::get(); const auto &addrSpaceId = block.getAddrSpaceId(); - if (memoryBlocksMapped.find(addrSpaceId) != memoryBlocksMapped.end()) { + if (memoryBlocksMapped.find(addrSpaceId) != memoryBlocksMapped.end()) // block already mapped return true; - } else { + else logger->debug("Create VFIO mapping for {}", addrSpaceId); - } auto translationFromProcess = mm.getTranslationFromProcess(addrSpaceId); uintptr_t processBaseAddr = translationFromProcess.getLocalAddr(0); @@ -221,16 +218,9 @@ PCIeCard::init() logger->info("Initializing FPGA card {}", name); - /* Search for FPGA card */ - pdev = pci_lookup_device(pci, &filter); - if (!pdev) { - logger->error("Failed to find PCI device"); - return false; - } - /* Attach PCIe card to VFIO container */ - kernel::vfio::Device &device = vfioContainer->attachDevice(pdev); - this->kernel::vfio::Device = &device; + kernel::vfio::Device &device = vfioContainer->attachDevice(*pdev); + this->vfioDevice = &device; /* Enable memory access and PCI bus mastering for DMA */ if (not device.pciEnable()) { @@ -241,7 +231,7 @@ PCIeCard::init() /* Reset system? */ if (doReset) { /* Reset / detect PCI device */ - if (not kernel::vfio::Device->pciHotReset()) { + if (not vfioDevice->pciHotReset()) { logger->error("Failed to reset PCI device"); return false; } diff --git a/fpga/lib/ips/intc.cpp b/fpga/lib/ips/intc.cpp index 098886e3e..ee877119c 100644 --- a/fpga/lib/ips/intc.cpp +++ b/fpga/lib/ips/intc.cpp @@ -38,7 +38,7 @@ static InterruptControllerFactory factory; InterruptController::~InterruptController() { - card->kernel::vfio::Device->pciMsiDeinit(this->efds); + card->vfioDevice->pciMsiDeinit(this->efds); } bool @@ -46,11 +46,11 @@ InterruptController::init() { const uintptr_t base = getBaseAddr(registerMemory); - num_irqs = card->kernel::vfio::Device->pciMsiInit(efds); + num_irqs = card->vfioDevice->pciMsiInit(efds); if (num_irqs < 0) return false; - if (not card->kernel::vfio::Device->pciMsiFind(nos)) { + if (not card->vfioDevice->pciMsiFind(nos)) { return false; } diff --git a/fpga/lib/ips/pcie.cpp b/fpga/lib/ips/pcie.cpp index cac9f5471..4e71d258f 100644 --- a/fpga/lib/ips/pcie.cpp +++ b/fpga/lib/ips/pcie.cpp @@ -43,14 +43,14 @@ AxiPciExpressBridge::init() card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface); /* Map PCIe BAR0 via VFIO */ - const void* bar0_mapped = card->kernel::vfio::Device->regionMap(VFIO_PCI_BAR0_REGION_INDEX); + const void* bar0_mapped = card->vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX); if (bar0_mapped == MAP_FAILED) { logger->error("Failed to mmap() BAR0"); return false; } // determine size of BAR0 region - const size_t bar0_size = card->kernel::vfio::Device->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX); + const size_t bar0_size = card->vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX); // create a mapping from process address space to the FPGA card via vfio mm.createMapping(reinterpret_cast(bar0_mapped), @@ -72,34 +72,28 @@ AxiPciExpressBridge::init() auto pciAddrSpaceId = mm.getPciAddressSpace(); - struct pci_region* pci_regions = nullptr; - size_t num_regions = pci_get_regions(card->pdev, &pci_regions); + auto regions = card->pdev->getRegions(); - for (size_t i = 0; i < num_regions; i++) { - const size_t region_size = pci_regions[i].end - pci_regions[i].start + 1; + int i = 0; + for (auto region : regions) { + const size_t region_size = region.end - region.start + 1; char barName[] = "BARx"; - barName[3] = '0' + pci_regions[i].num; + barName[3] = '0' + region.num; auto pciBar = pcieToAxiTranslations.at(barName); logger->info("PCI-BAR{}: bus addr={:#x} size={:#x}", - pci_regions[i].num, pci_regions[i].start, region_size); + region.num, region.start, region_size); logger->info("PCI-BAR{}: AXI translation offset {:#x}", i, pciBar.translation); - mm.createMapping(pci_regions[i].start, pciBar.translation, region_size, + mm.createMapping(region.start, pciBar.translation, region_size, std::string("PCI-") + barName, pciAddrSpaceId, card->addrSpaceIdHostToDevice); } - if (pci_regions != nullptr) { - logger->debug("freeing pci regions"); - free(pci_regions); - } - - for (auto& [barName, axiBar] : axiToPcieTranslations) { logger->info("AXI-{}: bus addr={:#x} size={:#x}", barName, axiBar.base, axiBar.size); @@ -114,6 +108,8 @@ AxiPciExpressBridge::init() mm.createMapping(0, axiBar.translation, axiBar.size, std::string("AXI-") + barName, barXAddrSpaceId, pciAddrSpaceId); + + i++; } return true; diff --git a/fpga/src/fpga.c b/fpga/src/fpga.c index 80e40ce5c..08e130352 100644 --- a/fpga/src/fpga.c +++ b/fpga/src/fpga.c @@ -54,7 +54,6 @@ int main(int argc, char *argv[]) struct list cards; struct vfio_container vc; - struct pci pci; struct fpga_card *card; /* Parse arguments */ @@ -88,9 +87,7 @@ check: if (optarg == endptr) json_error_t err; json_t *json; - ret = pci_init(&pci); - if (ret) - return -1; + auto pciDevices = std::make_shared(); ret = vfio_init(&vc); if (ret) diff --git a/fpga/src/villas-fpga-pipe.cpp b/fpga/src/villas-fpga-pipe.cpp index 418e47832..7a33135cf 100644 --- a/fpga/src/villas-fpga-pipe.cpp +++ b/fpga/src/villas-fpga-pipe.cpp @@ -43,7 +43,7 @@ using namespace villas; -static struct pci pci; +static std::shared_ptr pciDevices; static auto logger = villas::logging.get("streamer"); void setupColorHandling() @@ -66,12 +66,9 @@ void setupColorHandling() std::shared_ptr setupFpgaCard(const std::string &configFile, const std::string &fpgaName) { - if (pci_init(&pci) != 0) { - logger->error("Cannot initialize PCI"); - exit(1); - } + pciDevices = std::make_shared(); - auto vfioContainer = villas::VfioContainer::create(); + auto vfioContainer = kernel::vfio::Container::create(); /* Parse FPGA configuration */ FILE* f = fopen(configFile.c_str(), "r"); @@ -102,7 +99,7 @@ setupFpgaCard(const std::string &configFile, const std::string &fpgaName) } // create all FPGA card instances using the corresponding plugin - auto cards = fpgaCardPlugin->make(fpgas, &pci, vfioContainer); + auto cards = fpgaCardPlugin->make(fpgas, pciDevices, vfioContainer); for (auto &fpgaCard : cards) { if (fpgaCard->name == fpgaName) { diff --git a/fpga/tests/fpga.cpp b/fpga/tests/fpga.cpp index 97f2b6eb0..b71569056 100644 --- a/fpga/tests/fpga.cpp +++ b/fpga/tests/fpga.cpp @@ -40,14 +40,12 @@ using namespace villas; -static struct pci pci; +static std::shared_ptr pciDevices; FpgaState state; static void init() { - int ret; - FILE *f; json_error_t err; @@ -56,8 +54,7 @@ static void init() plugin::Registry::dumpList(); - ret = pci_init(&pci); - cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system"); + pciDevices = std::make_shared(); auto vfioContainer = kernel::vfio::Container::create(); @@ -80,7 +77,7 @@ static void init() cr_assert_not_null(fpgaCardPlugin, "No plugin for FPGA card found"); // create all FPGA card instances using the corresponding plugin - state.cards = fpgaCardPlugin->make(fpgas, &pci, vfioContainer); + state.cards = fpgaCardPlugin->make(fpgas, pciDevices, vfioContainer); cr_assert(state.cards.size() != 0, "No FPGA cards found!"); From c5e3d3dd4ada039bf65181f10a7e9ff3883ab612 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:21:16 +0200 Subject: [PATCH 07/11] node: add connect() with reverse path --- fpga/include/villas/fpga/node.hpp | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/fpga/include/villas/fpga/node.hpp b/fpga/include/villas/fpga/node.hpp index 70e83f304..34d9ab1b2 100644 --- a/fpga/include/villas/fpga/node.hpp +++ b/fpga/include/villas/fpga/node.hpp @@ -105,10 +105,23 @@ public: getSlavePort(const std::string &name) const { return *portsSlave.at(name); } + bool connect(const StreamVertex &from, const StreamVertex &to); + bool connect(const StreamVertex &from, const StreamVertex &to, bool reverse) + { + bool ret; + + ret = connect(from, to); + + if (reverse) + ret &= connect(to, from); + + return ret; + } + // easy-usage assuming that the slave IP to connect to only has one slave // port and implements the getDefaultSlavePort() function - bool connect(const Node& slaveNode) - { return this->connect(this->getDefaultMasterPort(), slaveNode.getDefaultSlavePort()); } + bool connect(const Node &slaveNode, bool reverse = false) + { return this->connect(this->getDefaultMasterPort(), slaveNode.getDefaultSlavePort(), reverse); } // used by easy-usage connect, will throw if not implemented by derived node virtual const StreamVertex& From 2700493f2f4005e422c650763395313ad4eb4103 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:25:55 +0200 Subject: [PATCH 08/11] docker: fix location of FEIN e.V. repo --- fpga/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/Dockerfile b/fpga/Dockerfile index 57d5969ef..027861b0e 100644 --- a/fpga/Dockerfile +++ b/fpga/Dockerfile @@ -43,7 +43,7 @@ LABEL \ org.label-schema.usage="https://villas.fein-aachen.org/doc/fpga.html" # Some of the dependencies are only available in our own repo -ADD https://villas.fein-aachen.org/packages/villas.repo /etc/yum.repos.d/ +ADD https://packages.fein-aachen.org/redhat/fein.repo /etc/yum.repos.d/ # Enable Extra Packages for Enterprise Linux (EPEL) and Software collection repo RUN yum -y install epel-release centos-release-scl From a935a5856ab431822e174bd0cd4df4a39f524cf2 Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:29:46 +0200 Subject: [PATCH 09/11] docker: add mising ssl headers --- fpga/Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/fpga/Dockerfile b/fpga/Dockerfile index 027861b0e..08a850b16 100644 --- a/fpga/Dockerfile +++ b/fpga/Dockerfile @@ -62,6 +62,7 @@ RUN yum -y install \ # Dependencies RUN yum -y install \ jansson-devel \ + openssl-devel \ libxil-devel \ lapack-devel From 031311ba9582428c740d3827ac7a6126dcb1dcfb Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:45:50 +0200 Subject: [PATCH 10/11] docker: add missing deps --- fpga/Dockerfile | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/fpga/Dockerfile b/fpga/Dockerfile index 08a850b16..00924d1c7 100644 --- a/fpga/Dockerfile +++ b/fpga/Dockerfile @@ -42,9 +42,6 @@ LABEL \ org.label-schema.vcs-url="https://git.rwth-aachen.de/VILLASframework/VILLASfpga" \ org.label-schema.usage="https://villas.fein-aachen.org/doc/fpga.html" -# Some of the dependencies are only available in our own repo -ADD https://packages.fein-aachen.org/redhat/fein.repo /etc/yum.repos.d/ - # Enable Extra Packages for Enterprise Linux (EPEL) and Software collection repo RUN yum -y install epel-release centos-release-scl @@ -63,13 +60,34 @@ RUN yum -y install \ RUN yum -y install \ jansson-devel \ openssl-devel \ - libxil-devel \ + curl-devel \ lapack-devel +# Build & Install Fmtlib +RUN git clone --recursive https://github.com/fmtlib/fmt.git /tmp/fmt && \ + mkdir -p /tmp/fmt/build && cd /tmp/fmt/build && \ + git checkout 5.2.0 && \ + cmake3 -DBUILD_SHARED_LIBS=1 .. && \ + make -j$(nproc) install && \ + rm -rf /tmp/fmt + + +# Build & Install spdlog +RUN git clone --recursive https://github.com/gabime/spdlog.git /tmp/spdlog && \ + mkdir -p /tmp/spdlog/build && cd /tmp/spdlog/build && \ + git checkout v1.3.1 && \ + cmake3 -DSPDLOG_FMT_EXTERNAL=ON -DSPDLOG_BUILD_BENCH=OFF .. && \ + make -j$(nproc) install && \ + rm -rf /tmp/spdlog + # Build & Install Criterion COPY thirdparty/criterion /tmp/criterion RUN mkdir -p /tmp/criterion/build && cd /tmp/criterion/build && cmake3 .. && make install && rm -rf /tmp/* +# Build & Install libxil +COPY thirdparty/libxil /tmp/libxil +RUN mkdir -p /tmp/libxil/build && cd /tmp/libxil/build && cmake3 .. && make install && rm -rf /tmp/* + ENV LD_LIBRARY_PATH /usr/local/lib:/usr/local/lib64 WORKDIR /fpga From 7e2365bfa09acb978ca6cf104f5c15885eb4994e Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 15 Jun 2020 21:55:03 +0200 Subject: [PATCH 11/11] ci: update CI config --- fpga/.gitlab-ci.yml | 47 ++++----------------------------------------- fpga/CMakeLists.txt | 2 ++ fpga/Dockerfile | 16 ++++++++++----- 3 files changed, 17 insertions(+), 48 deletions(-) diff --git a/fpga/.gitlab-ci.yml b/fpga/.gitlab-ci.yml index 66deb89c8..c4f754035 100644 --- a/fpga/.gitlab-ci.yml +++ b/fpga/.gitlab-ci.yml @@ -1,19 +1,13 @@ variables: - GIT_STRATEGY: fetch GIT_SUBMODULE_STRATEGY: recursive PREFIX: /usr/ DOCKER_TAG_DEV: ${CI_BUILD_REF_SLUG} DOCKER_IMAGE_DEV: villas/fpga-dev -# For some reason, GitLab CI prunes the contents of the submodules so we need to restore them. -before_script: - - git submodule foreach git checkout . - stages: - prepare - build - test -# - deploy # Stage: prepare ############################################################################## @@ -43,19 +37,6 @@ build:source: tags: - docker -#build:packages: -# stage: build -# script: -# - mkdir build && cd build && cmake3 .. && make package -# artifacts: -# expire_in: 1 week -# name: ${CI_PROJECT_NAME}-${CI_BUILD_REF} -# paths: -# - build/ -# image: ${DOCKER_IMAGE_DEV}:${DOCKER_TAG_DEV} -# tags: -# - docker - # Stage: test ############################################################################## @@ -66,32 +47,12 @@ test:unit: - cuda allow_failure: true script: | - rm -r build && mkdir build && cd build && cmake3 .. && make unit-tests -j8 + rm -r build && mkdir build && cd build + cmake3 .. + make -j$(nproc) unit-tests if [ "$(who | wc -l)" -eq "0" ]; then - tests/unit-tests --jobs 1 --filter 'fpga/*' + tests/fpga-unit-tests --jobs 1 --filter 'fpga/*' else echo "System is currently used by: $(who)" echo "We are skipping the test. Please restart manually." fi - -# Stage: deploy -############################################################################## - -#deploy:packages: -# stage: deploy -# script: -# - ssh ${DEPLOY_USER}@${DEPLOY_HOST} mkdir -p ${DEPLOY_PATH}/{dist,../packages} -# - rsync ${RSYNC_OPTS} build/*.rpm ${DEPLOY_USER}@${DEPLOY_HOST}:${DEPLOY_PATH}/../packages/ -# - rsync ${RSYNC_OPTS} build//*.tar.gz ${DEPLOY_USER}@${DEPLOY_HOST}:${DEPLOY_PATH}/dist/ -# - ssh ${DEPLOY_USER}@${DEPLOY_HOST} createrepo ${DEPLOY_PATH}/../packages -# dependencies: -# - build:packages -# tags: -# - villas-deploy -# only: -# - tags -# -#deploy:git-mirror: -# stage: deploy -# script: -# - git push --force --mirror --prune https://${GITHUB_USER}:${GITHUB_TOKEN}@github.com:VILLASframework/VILLASnode.git diff --git a/fpga/CMakeLists.txt b/fpga/CMakeLists.txt index 2531ea8f9..ab1a1c66f 100644 --- a/fpga/CMakeLists.txt +++ b/fpga/CMakeLists.txt @@ -51,6 +51,8 @@ endif() include(FindPkgConfig) +set(ENV{PKG_CONFIG_PATH} "$ENV{PKG_CONFIG_PATH}:/usr/local/lib/pkgconfig:/usr/local/lib64/pkgconfig:/usr/local/share/pkgconfig:/usr/lib64/pkgconfig") + pkg_check_modules(JANSSON REQUIRED IMPORTED_TARGET jansson) pkg_check_modules(XIL REQUIRED IMPORTED_TARGET libxil) diff --git a/fpga/Dockerfile b/fpga/Dockerfile index 00924d1c7..ab34ee66b 100644 --- a/fpga/Dockerfile +++ b/fpga/Dockerfile @@ -71,7 +71,6 @@ RUN git clone --recursive https://github.com/fmtlib/fmt.git /tmp/fmt && \ make -j$(nproc) install && \ rm -rf /tmp/fmt - # Build & Install spdlog RUN git clone --recursive https://github.com/gabime/spdlog.git /tmp/spdlog && \ mkdir -p /tmp/spdlog/build && cd /tmp/spdlog/build && \ @@ -81,12 +80,19 @@ RUN git clone --recursive https://github.com/gabime/spdlog.git /tmp/spdlog && \ rm -rf /tmp/spdlog # Build & Install Criterion -COPY thirdparty/criterion /tmp/criterion -RUN mkdir -p /tmp/criterion/build && cd /tmp/criterion/build && cmake3 .. && make install && rm -rf /tmp/* +RUN git clone --recursive https://github.com/Snaipe/Criterion /tmp/criterion && \ + mkdir -p /tmp/criterion/build && cd /tmp/criterion/build && \ + git checkout v2.3.3 && \ + cmake3 .. && \ + make -j$(nproc) install && \ + rm -rf /tmp/* # Build & Install libxil -COPY thirdparty/libxil /tmp/libxil -RUN mkdir -p /tmp/libxil/build && cd /tmp/libxil/build && cmake3 .. && make install && rm -rf /tmp/* +RUN git clone https://git.rwth-aachen.de/acs/public/villas/fpga/libxil.git /tmp/libxil && \ + mkdir -p /tmp/libxil/build && cd /tmp/libxil/build && \ + cmake3 .. && \ + make -j$(nproc) install && \ + rm -rf /tmp/* ENV LD_LIBRARY_PATH /usr/local/lib:/usr/local/lib64