From e626abfb5244628473d17594cad80eda383e02cb Mon Sep 17 00:00:00 2001
From: daniel-k <github@daniel-krebs.net>
Date: Tue, 16 Jan 2018 15:08:12 +0100
Subject: [PATCH] tests/timer: add basic timer test

---
 fpga/tests/CMakeLists.txt |  2 +-
 fpga/tests/timer.cpp      | 55 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 fpga/tests/timer.cpp

diff --git a/fpga/tests/CMakeLists.txt b/fpga/tests/CMakeLists.txt
index 103abb6c4..bb9988ba2 100644
--- a/fpga/tests/CMakeLists.txt
+++ b/fpga/tests/CMakeLists.txt
@@ -5,7 +5,7 @@ set(SOURCES
 #	hls.c
 #	intc.c
 #	rtds_rtt.c
-#	tmrctr.c
+	timer.cpp
 #	xsg.c
 )
 
diff --git a/fpga/tests/timer.cpp b/fpga/tests/timer.cpp
new file mode 100644
index 000000000..b25935c13
--- /dev/null
+++ b/fpga/tests/timer.cpp
@@ -0,0 +1,55 @@
+/** Timer/Counter unit test.
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2017, Steffen Vogel
+ * @license GNU General Public License (version 3)
+ *
+ * VILLASfpga
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *********************************************************************************/
+
+#include <criterion/criterion.h>
+
+#include "config.h"
+
+#include <villas/log.hpp>
+#include <villas/fpga/card.hpp>
+#include <villas/fpga/ips/timer.hpp>
+
+extern villas::fpga::PCIeCard* fpga;
+
+Test(fpga, timer, .description = "Timer Counter")
+{
+	auto logger = loggerGetOrCreate("unittest:timer");
+
+	for(auto& ip : fpga->ips) {
+		// skip non-timer IPs
+		if(*ip != villas::fpga::Vlnv("xilinx.com:ip:axi_timer:")) {
+			continue;
+		}
+
+		logger->info("Testing {}", *ip);
+
+		auto timer = reinterpret_cast<villas::fpga::ip::Timer&>(*ip);
+
+		timer.start(timer.getFrequency() / 10);
+		cr_assert(timer.wait(), "Timer failed");
+
+		logger->info("Timer passed: {}", timer);
+	}
+
+	return;
+}