From f2db38fe443621b1e40c0359c5029ce13f2260f6 Mon Sep 17 00:00:00 2001 From: Niklas Eiling Date: Wed, 7 Feb 2024 15:08:08 +0100 Subject: [PATCH] ip/switch: reformat and add function that prints current switch config Signed-off-by: Niklas Eiling --- fpga/include/villas/fpga/ips/switch.hpp | 67 +++++++++---------------- fpga/lib/ips/switch.cpp | 25 +++++++++ 2 files changed, 50 insertions(+), 42 deletions(-) diff --git a/fpga/include/villas/fpga/ips/switch.hpp b/fpga/include/villas/fpga/ips/switch.hpp index 974691f59..c55a4af56 100644 --- a/fpga/include/villas/fpga/ips/switch.hpp +++ b/fpga/include/villas/fpga/ips/switch.hpp @@ -22,68 +22,51 @@ namespace ip { class AxiStreamSwitch : public Node { public: - friend class AxiStreamSwitchFactory; + friend class AxiStreamSwitchFactory; - virtual - bool init() override; + virtual bool init() override; - bool connectInternal(const std::string &slavePort, - const std::string &masterPort); + bool connectInternal(const std::string &slavePort, + const std::string &masterPort); + + void printConfig() const; private: - int portNameToNum(const std::string &portName); + int portNameToNum(const std::string &portName); -private: - static constexpr - const char* PORT_DISABLED = "DISABLED"; + static constexpr const char *PORT_DISABLED = "DISABLED"; - static constexpr - char registerMemory[] = "Reg"; + static constexpr char registerMemory[] = "Reg"; - std::list getMemoryBlocks() const - { - return { - registerMemory - }; - } + std::list getMemoryBlocks() const { + return {registerMemory}; + } - XAxis_Switch xSwitch; - XAxis_Switch_Config xConfig; + XAxis_Switch xSwitch; + XAxis_Switch_Config xConfig; - std::map portMapping; + std::map portMapping; }; class AxiStreamSwitchFactory : NodeFactory { public: - virtual - std::string getName() const - { - return "switch"; - } + virtual std::string getName() const { return "switch"; } - virtual - std::string getDescription() const - { - return "Xilinx's AXI4-Stream switch"; - } + virtual std::string getDescription() const { + return "Xilinx's AXI4-Stream switch"; + } private: - virtual - Vlnv getCompatibleVlnv() const - { - return Vlnv("xilinx.com:ip:axis_switch:"); - } + virtual Vlnv getCompatibleVlnv() const { + return Vlnv("xilinx.com:ip:axis_switch:"); + } - // Create a concrete IP instance - Core* make() const - { - return new AxiStreamSwitch; - }; + // Create a concrete IP instance + Core *make() const { return new AxiStreamSwitch; }; protected: - virtual - void parse(Core &, json_t *) override; + virtual void parse(Core &, json_t *) override; }; } // namespace ip diff --git a/fpga/lib/ips/switch.cpp b/fpga/lib/ips/switch.cpp index a55949eb6..7a6031fb6 100644 --- a/fpga/lib/ips/switch.cpp +++ b/fpga/lib/ips/switch.cpp @@ -47,6 +47,31 @@ bool AxiStreamSwitch::init() return true; } +void AxiStreamSwitch::printConfig() const { + u32 MiPortAddr; + u32 RegValue; + u8 Enable; + logger->info( + "Switch configuration: {} Master Interfaces, {} Slave Interfaces", + xConfig.MaxNumMI, xConfig.MaxNumSI); + + for (int i = 0; i < xConfig.MaxNumMI; i++) { + /* Calculate MI port address to be enabled */ + MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * i; + + /* Read MI port data */ + RegValue = XAxisScr_ReadReg(xSwitch.Config.BaseAddress, MiPortAddr); + + /* Fetch enable bit */ + Enable = RegValue >> XAXIS_SCR_MI_X_DISABLE_SHIFT; + + /* Fetch SI value */ + RegValue &= XAXIS_SCR_MI_X_MUX_MASK; + + logger->info("Master Interface {}: {} (enabled: {})", i, RegValue, Enable); + } +} + bool AxiStreamSwitch::connectInternal(const std::string &portSlave, const std::string &portMaster) {