From f5a3c8c7129a65ec1fa9074fcf11e3a226130b48 Mon Sep 17 00:00:00 2001 From: daniel-k Date: Wed, 17 Jan 2018 16:31:47 +0100 Subject: [PATCH] scripts/hwdef-parse: only set irqs and ports if there are any --- fpga/scripts/hwdef-parse.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/fpga/scripts/hwdef-parse.py b/fpga/scripts/hwdef-parse.py index f114d3a34..a1ca66923 100755 --- a/fpga/scripts/hwdef-parse.py +++ b/fpga/scripts/hwdef-parse.py @@ -119,9 +119,7 @@ for module in modules: continue ips[instance] = { - 'vlnv' : vlnv, - 'irqs' : { }, - 'ports' : { } + 'vlnv' : vlnv } # find PCI-e module to extract memory map @@ -151,9 +149,9 @@ for busif in busifs: port = int(m.group(2)) ep = bus_trace(root, busname, opponent[type], whitelist) - if ep in ips: - ips[ep]['ports'][type.lower()] = port + ports = ips[ep].setdefault('ports', {}) + ports[type.lower()] = port # find Interrupt assignments intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]') @@ -182,7 +180,8 @@ for port in ports: irqname = port.get('NAME') if instance in ips: - ips[instance]['irqs'][irqname] = irq + irqs = ips[instance].setdefault('irqs', {}) + irqs[irqname] = irq # Find BRAM storage depths (size) brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')