From f644a9faa8437bd80971e5f2af81c8696d01b97a Mon Sep 17 00:00:00 2001 From: Daniel Krebs Date: Tue, 15 May 2018 17:50:48 +0200 Subject: [PATCH] ips/pcie: move BAR0 mapping from card into PCIe IP --- fpga/lib/card.cpp | 30 ------------------------------ fpga/lib/ips/pcie.cpp | 23 ++++++++++++++++------- 2 files changed, 16 insertions(+), 37 deletions(-) diff --git a/fpga/lib/card.cpp b/fpga/lib/card.cpp index 4581d7482..de32310f5 100644 --- a/fpga/lib/card.cpp +++ b/fpga/lib/card.cpp @@ -205,7 +205,6 @@ PCIeCard::mapMemoryBlock(const MemoryBlock& block) bool PCIeCard::init() { - auto& mm = MemoryManager::get(); logger = getLogger(); logger->info("Initializing FPGA card {}", name); @@ -221,41 +220,12 @@ PCIeCard::init() VfioDevice& device = vfioContainer->attachDevice(pdev); this->vfioDevice = &device; - /* Enable memory access and PCI bus mastering for DMA */ if (not device.pciEnable()) { logger->error("Failed to enable PCI device"); return false; } - /* Map PCIe BAR */ - const void* bar0_mapped = vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX); - if (bar0_mapped == MAP_FAILED) { - logger->error("Failed to mmap() BAR0"); - return false; - } - - // determine size of BAR0 region - const size_t bar0_size = vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX); - - - /* Link mapped BAR0 to global memory graph */ - - // get the address space of the current application - const auto villasAddrSpace = mm.getProcessAddressSpace(); - - // get the address space for the PCIe proxy we use with VFIO - const auto cardPCIeAddrSpaceName = mm.getMasterAddrSpaceName(name, "PCIe"); - - // create a new address space for this FPGA card - addrSpaceIdHostToDevice = mm.getOrCreateAddressSpace(cardPCIeAddrSpaceName); - - // create a mapping from our address space to the FPGA card via vfio - mm.createMapping(reinterpret_cast(bar0_mapped), - 0, bar0_size, "VFIO_map", - villasAddrSpace, addrSpaceIdHostToDevice); - - /* Reset system? */ if (do_reset) { /* Reset / detect PCI device */ diff --git a/fpga/lib/ips/pcie.cpp b/fpga/lib/ips/pcie.cpp index 3b273bbd8..c058056ff 100644 --- a/fpga/lib/ips/pcie.cpp +++ b/fpga/lib/ips/pcie.cpp @@ -42,14 +42,23 @@ AxiPciExpressBridge::init() // Throw an exception if the is no bus master interface and thus no // address space we can use for translation -> error - const MemoryManager::AddressSpaceId myAddrSpaceid = - busMasterInterfaces.at(axiInterface); + card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface); - // Create an identity mapping from the FPGA card to this IP as an entry - // point to all other IPs in the FPGA, because Vivado will generate a - // memory view for this bridge that can see all others. - MemoryManager::get().createMapping(0x00, 0x00, SIZE_MAX, "PCIeBridge", - card->addrSpaceIdHostToDevice, myAddrSpaceid); + /* Map PCIe BAR0 via VFIO */ + const void* bar0_mapped = card->vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX); + if (bar0_mapped == MAP_FAILED) { + logger->error("Failed to mmap() BAR0"); + return false; + } + + // determine size of BAR0 region + const size_t bar0_size = card->vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX); + + // create a mapping from process address space to the FPGA card via vfio + mm.createMapping(reinterpret_cast(bar0_mapped), + 0, bar0_size, "VFIO-H2D", + mm.getProcessAddressSpace(), + card->addrSpaceIdHostToDevice); /* Make PCIe (IOVA) address space available to FPGA via BAR0 */