diff --git a/config-fpga.h b/config-fpga.h
deleted file mode 100644
index e92db69da..000000000
--- a/config-fpga.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/** Hardcoded configuration for VILLASfpga
- *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
- * @copyright 2015-2016, Steffen Vogel
- *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
- *   Unauthorized copying of this file, via any medium is strictly prohibited.
- **********************************************************************************/
-
-#ifndef _CONFIG_FPGA_H_
-#define _CONFIG_FPGA_H_
-
-#define AFFINITY		(1 << 3)
-#define PRIORITY		90
-
-#define RTDS_DM_FIFO		1
-#define RTDS_DM_DMA_SIMPLE	2
-#define RTDS_DM_DMA_SG		3
-#define DATAMOVER		RTDS_DM_DMA_SIMPLE
-
-/** PCIe BAR number of VILLASfpga registers */
-#define PCI_BAR			0
-
-/** AXI Bus frequency for all components
- * except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
-#define AXI_HZ			125000000 // 125 MHz
-
-#define PCI_VID_XILINX		0x10ee
-#define PCI_PID_VFPGA		0x7022
-
-#endif /* _CONFIG_FPGA_H_ */
\ No newline at end of file
diff --git a/config.h b/config.h
index 736a30920..087f7b3f9 100644
--- a/config.h
+++ b/config.h
@@ -52,6 +52,15 @@
 #define BENCH_DM_EXP_MIN	0
 #define BENCH_DM_EXP_MAX	20
 
+/** PCIe BAR number of VILLASfpga registers */
+#define FPGA_PCI_BAR		0
+#define FPGA_PCI_VID_XILINX	0x10ee
+#define FPGA_PCI_PID_VFPGA	0x7022
+
+/** AXI Bus frequency for all components
+ * except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
+#define FPGA_AXI_HZ		125000000 // 125 MHz
+
 /** Global configuration */
 struct settings {
 	int priority;		/**< Process priority (lower is better) */
diff --git a/lib/fpga/ip.c b/lib/fpga/ip.c
index 9d4687a12..d97c49cf2 100644
--- a/lib/fpga/ip.c
+++ b/lib/fpga/ip.c
@@ -10,7 +10,7 @@
 #include "fpga/fifo.h"
 #include "nodes/fpga.h"
 
-#include "config-fpga.h"
+#include "config.h"
 
 struct list ip_types;	/**< Table of existing FPGA IP core drivers */
 
diff --git a/lib/fpga/timer.c b/lib/fpga/timer.c
index 55fe48a73..a5a9cd4b2 100644
--- a/lib/fpga/timer.c
+++ b/lib/fpga/timer.c
@@ -9,7 +9,7 @@
  *   Unauthorized copying of this file, via any medium is strictly prohibited.
  **********************************************************************************/
 
-#include "config-fpga.h"
+#include "config.h"
 
 #include "fpga/ip.h"
 #include "fpga/timer.h"
@@ -22,7 +22,7 @@ int timer_init(struct ip *c)
 	XTmrCtr *xtmr = &tmr->inst;
 	XTmrCtr_Config xtmr_cfg = {
 		.BaseAddress = (uintptr_t) f->map + c->baseaddr,
-		.SysClockFreqHz = AXI_HZ
+		.SysClockFreqHz = FPGA_AXI_HZ
 	};
 
 	XTmrCtr_CfgInitialize(xtmr, &xtmr_cfg, (uintptr_t) f->map + c->baseaddr);
diff --git a/lib/nodes/fpga.c b/lib/nodes/fpga.c
index 1d1e21af2..12cddd44f 100644
--- a/lib/nodes/fpga.c
+++ b/lib/nodes/fpga.c
@@ -17,7 +17,7 @@
 
 #include "nodes/fpga.h"
 
-#include "config-fpga.h"
+#include "config.h"
 #include "utils.h"
 #include "timing.h"
 
@@ -94,8 +94,8 @@ int fpga_parse_card(struct fpga *f, int argc, char * argv[], config_setting_t *c
 	config_setting_t *cfg_ips, *cfg_slot, *cfg_id, *cfg_fpgas;
 
 	/* Default values */
-	f->filter.vendor = PCI_VID_XILINX;
-	f->filter.device = PCI_PID_VFPGA;
+	f->filter.vendor = FPGA_PCI_VID_XILINX;
+	f->filter.device = FPGA_PCI_PID_VFPGA;
 
 	cfg_fpgas = config_setting_get_member(cfg, "fpgas");
 	if (!cfg_fpgas)
diff --git a/src/fpga-bench.c b/src/fpga-bench.c
index 9da551742..2ab2523a0 100644
--- a/src/fpga-bench.c
+++ b/src/fpga-bench.c
@@ -22,7 +22,6 @@
 #include <xilinx/xtmrctr_l.h>
 
 #include "config.h"
-#include "config-fpga.h"
 
 int fpga_benchmark_datamover(struct fpga *f);
 int fpga_benchmark_jitter(struct fpga *f);
@@ -106,7 +105,7 @@ int fpga_benchmark_jitter(struct fpga *f)
 	int *hist = alloc(8 << 20);
 
 	XTmrCtr_SetOptions(xtmr, 0, XTC_INT_MODE_OPTION | XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION | XTC_AUTO_RELOAD_OPTION);
-	XTmrCtr_SetResetValue(xtmr, 0, period * AXI_HZ);
+	XTmrCtr_SetResetValue(xtmr, 0, period * FPGA_AXI_HZ);
 	XTmrCtr_Start(xtmr, 0);
 
 	uint64_t end, start = rdtscp();
diff --git a/src/fpga-tests.c b/src/fpga-tests.c
index 76615b670..e6c525530 100644
--- a/src/fpga-tests.c
+++ b/src/fpga-tests.c
@@ -22,7 +22,6 @@
 #include <villas/fpga/intc.h>
 
 #include "config.h"
-#include "config-fpga.h"
 
 #define TEST_LEN 0x1000
 
@@ -335,7 +334,7 @@ int fpga_test_timer(struct fpga *f)
 		error("Failed to enable interrupt");
 
 	XTmrCtr_SetOptions(xtmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
-	XTmrCtr_SetResetValue(xtmr, 0, AXI_HZ / 125);
+	XTmrCtr_SetResetValue(xtmr, 0, FPGA_AXI_HZ / 125);
 	XTmrCtr_Start(xtmr, 0);
 
 	uint64_t counter = intc_wait(f->intc, tmr->irq);
diff --git a/src/fpga.c b/src/fpga.c
index 9c4ac7070..46895c0f6 100644
--- a/src/fpga.c
+++ b/src/fpga.c
@@ -24,7 +24,6 @@
 #include <villas/kernel/kernel.h>
 
 #include "config.h"
-#include "config-fpga.h"
 
 /* Declarations */
 int fpga_benchmarks(int argc, char *argv[], struct fpga *f);