From fb48e36a0b1925012bf9df7f5741bf98ac81f89b Mon Sep 17 00:00:00 2001 From: Niklas Eiling Date: Fri, 11 Nov 2022 04:53:50 -0500 Subject: [PATCH] add villas-fpga-cat app that outputs a stream of data --- fpga/src/CMakeLists.txt | 4 + fpga/src/villas-fpga-cat.cpp | 145 +++++++++++++++++++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 fpga/src/villas-fpga-cat.cpp diff --git a/fpga/src/CMakeLists.txt b/fpga/src/CMakeLists.txt index 51048b155..8721a1d4f 100644 --- a/fpga/src/CMakeLists.txt +++ b/fpga/src/CMakeLists.txt @@ -21,9 +21,13 @@ ############################################################################## add_executable(villas-fpga-pipe villas-fpga-pipe.cpp) +add_executable(villas-fpga-cat villas-fpga-cat.cpp) target_link_libraries(villas-fpga-pipe PUBLIC villas-fpga ) +target_link_libraries(villas-fpga-cat PUBLIC + villas-fpga +) add_executable(pcimem pcimem.c) diff --git a/fpga/src/villas-fpga-cat.cpp b/fpga/src/villas-fpga-cat.cpp new file mode 100644 index 000000000..ce21abc9d --- /dev/null +++ b/fpga/src/villas-fpga-cat.cpp @@ -0,0 +1,145 @@ +/** Streaming data from STDIN/OUT to FPGA. + * + * @author Daniel Krebs + * @copyright 2017-2022, Steffen Vogel + * @license GNU General Public License (version 3) + * + * VILLASfpga + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + *********************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +using namespace villas; + +static std::shared_ptr pciDevices; +static auto logger = villas::logging.get("cat"); + +int main(int argc, char* argv[]) +{ + // Command Line Parser + CLI::App app{"VILLASfpga data output"}; + + try { + std::string configFile; + app.add_option("-c,--config", configFile, "Configuration file") + ->check(CLI::ExistingFile); + + std::string fpgaName = "vc707"; + app.add_option("--fpga", fpgaName, "Which FPGA to use"); + app.parse(argc, argv); + + // Logging setup + spdlog::set_level(spdlog::level::debug); + fpga::setupColorHandling(); + + if (configFile.empty()) { + logger->error("No configuration file provided/ Please use -c/--config argument"); + return 1; + } + + auto card = fpga::setupFpgaCard(configFile, fpgaName); + + std::vector aurora_channels; + for (int i = 0; i < 4; i++) { + auto name = fmt::format("aurora_8b10b_ch{}", i); + auto id = fpga::ip::IpIdentifier("xilinx.com:ip:aurora_8b10b:", name); + auto aurora = std::dynamic_pointer_cast(card->lookupIp(id)); + if (aurora == nullptr) { + logger->error("No Aurora interface found on FPGA"); + return 1; + } + + aurora_channels.push_back(aurora); + } + + auto dma = std::dynamic_pointer_cast + (card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:"))); + if (dma == nullptr) { + logger->error("No DMA found on FPGA "); + return 1; + } + + for (auto aurora : aurora_channels) + aurora->dump(); + + // Configure Crossbar switch +#if 1 + aurora_channels[2]->connect(aurora_channels[2]->getDefaultMasterPort(), dma->getDefaultSlavePort()); + dma->connect(dma->getDefaultMasterPort(), aurora_channels[2]->getDefaultSlavePort()); +#else + dma->connectLoopback(); +#endif + auto &alloc = villas::HostRam::getAllocator(); + auto mem = alloc.allocate(0x100); + auto block = mem.getMemoryBlock(); + + dma->makeAccesibleFromVA(block); + + auto &mm = MemoryManager::get(); + mm.getGraph().dump("graph.dot"); + + while (true) { + // Setup read transfer + dma->read(block, block.getSize()); + + auto bytesRead = dma->readComplete(); + //auto valuesRead = bytesRead / sizeof(int32_t); + //logger->info("Read {} bytes", bytesRead); + + /*for (size_t i = 0; i < valuesRead; i++) + std::cerr << mem[i] << ";"; + std::cerr << std::endl;*/ + + if (bytesRead == 8) { + int64_t ival = (int64_t)(mem[1] & 0xFFFF) << 48 | + (int64_t)(mem[1] & 0xFFFF0000) << 32 | + (int64_t)(mem[0] & 0xFFFF) << 16 | + (int64_t)(mem[0] & 0xFFFF0000); + double dval = *((double*)(&ival)); + printf("%e\n", dval); + //logger->info("Read value: {}", dval); + } + } + } catch (const RuntimeError &e) { + logger->error("Error: {}", e.what()); + return -1; + } catch (const CLI::ParseError &e) { + return app.exit(e); + } + + return 0; +}