Niklas Eiling
ddbe16c841
fpga: fix empty search path being an error
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
c168838773
Fix missing idle_stop setting in integration tests
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
d6c04f4cb1
Revert default sample length to 64
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0049540e9d
test_rtt: Disable integration test in CI
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
4be302b480
test_rtt: Fix possible use of uninitialized variable
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
937242ca84
test_rtt: Add missing cooldown phase in runtime estimation
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
3c7fca7ce6
Increase default sample length
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0765e456fa
test_rtt: Fix logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6c6d37d00d
webrtc: Improve logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
7848dd7019
test_rtt: Fix compiler errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6114f6dcc2
webrtc: Show connection details
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
69b00f8915
test_rtt: Improve handling of defaults
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
b4b86aa220
test_rtt: Print estimated test durations
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0601ede07b
test_rtt: Rework calculation of test duration
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
19982bf49b
test_rtt: Improve statistics
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
f75bf8536c
webrtc: Enable ICE TCP
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6efaa9e55b
test_rtt: Another round of new features
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
bae0a37526
format: Allow printing test meta data to result file
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
247f1ead42
csv, tsv: Fix printing of optional fields
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
f695225a3a
test_rtt: Fix wrong option identifier
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
7f857f392c
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
36220d3308
format-all: Exclude third-party or generated code
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
ffe804e177
iec61850_sv: Fix IEC 61850-9-2 Sampled Values node and unit test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
550eb14758
super_node: Fix configuration of idle_stop setting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0ae86790b6
test_rtt: Fix test case numbering
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
d0b9bd5935
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
59a76927fd
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
Steffen Vogel
d867880e2c
hypersim: Update UCM code for multiple signal values
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-06-18 12:39:42 +02:00
Niklas Eiling
a6751c4c6e
fpga: improve comments in register.cpp
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
28c24ea22a
fpga: fix includes and various comments
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
0ae08e8434
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
98c1f36a02
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
87a1628c4a
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
d03b19613f
fpga: update ips json in fpga.conf
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
3e525d075b
fpga: expose methods for finer control over DMA data path
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
f67ca37b0c
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
937cdda11f
fpga: turn off all interrupts when using polling
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this improves the latency by at least 4 us in my setup.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
69b5425c0c
fpga: optimize sg descriptor rings
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we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
5e1750e885
Update .gitlab-ci.yml
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
a7d24f756f
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
71d493cb42
test_rtt: Fix integration test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
a5487f4210
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
95610be274
Fix signal and format handling
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
55238f58b9
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
176e969c6a
Fix code formatting in commented code section
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
75c580af82
Remove obsolete villas-test-rtt CLI application
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
5ffc0f92f0
test_rtt: Show test process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
6b0d6891a0
stats: Indent histogram output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
d4bc2409c3
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
284901bbc3
Harmonize formatting and style of example configuration files
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
