{
  "timer_0_axi_timer_0": {
    "vlnv": "xilinx.com:ip:axi_timer:2.0",
    "irqs": {
      "generateout0": "pcie_0_axi_pcie_intc_0:0"
    }
  },
  "hier_0_axis_data_fifo_1": {
    "ports": [
      {
        "role": "master",
        "name": "AXIS",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS"
      },
      {
        "role": "slave",
        "name": "AXIS",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS"
      }
    ],
    "vlnv": "xilinx.com:ip:axis_data_fifo:2.0"
  },
  "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
    "ports": [
      {
        "role": "slave",
        "name": "S00_AXIS",
        "target": "hier_0_aurora_axis_0:m_axis"
      },
      {
        "role": "master",
        "name": "M00_AXIS",
        "target": "hier_0_aurora_axis_0:s_axis"
      },
      {
        "role": "slave",
        "name": "S01_AXIS",
        "target": "hier_0_axi_dma_axi_dma_0:MM2S"
      },
      {
        "role": "master",
        "name": "M01_AXIS",
        "target": "hier_0_axi_dma_axi_dma_0:S2MM"
      },
      {
        "role": "slave",
        "name": "S02_AXIS",
        "target": "hier_0_axi_fifo_mm_s_0:STR_TXD"
      },
      {
        "role": "master",
        "name": "M02_AXIS",
        "target": "hier_0_axi_fifo_mm_s_0:STR_RXD"
      },
      {
        "role": "slave",
        "name": "S03_AXIS",
        "target": "hier_0_axis_data_fifo_0:AXIS"
      },
      {
        "role": "master",
        "name": "M03_AXIS",
        "target": "hier_0_axis_data_fifo_0:AXIS"
      },
      {
        "role": "slave",
        "name": "S04_AXIS",
        "target": "hier_0_axis_data_fifo_1:AXIS"
      },
      {
        "role": "master",
        "name": "M04_AXIS",
        "target": "hier_0_axis_data_fifo_1:AXIS"
      }
    ],
    "num_ports": 5,
    "vlnv": "xilinx.com:ip:axis_switch:1.1"
  },
  "hier_0_axis_data_fifo_0": {
    "ports": [
      {
        "role": "master",
        "name": "AXIS",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS"
      },
      {
        "role": "slave",
        "name": "AXIS",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS"
      }
    ],
    "vlnv": "xilinx.com:ip:axis_data_fifo:2.0"
  },
  "hier_0_aurora_axis_0": {
    "ports": [
      {
        "role": "master",
        "name": "m_axis",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS"
      },
      {
        "role": "slave",
        "name": "s_axis",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS"
      }
    ],
    "vlnv": "acs.eonerc.rwth-aachen.de:user:aurora_axis:1.16"
  },
  "pcie_0_axi_reset_0": {
    "vlnv": "xilinx.com:ip:axi_gpio:2.0"
  },
  "hier_0_axi_fifo_mm_s_0": {
    "ports": [
      {
        "role": "master",
        "name": "STR_TXD",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS"
      },
      {
        "role": "slave",
        "name": "STR_RXD",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS"
      }
    ],
    "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2",
    "irqs": {
      "interrupt": "pcie_0_axi_pcie_intc_0:1"
    }
  },
  "hier_0_axi_dma_axi_dma_0": {
    "ports": [
      {
        "role": "master",
        "name": "MM2S",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS"
      },
      {
        "role": "slave",
        "name": "S2MM",
        "target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS"
      }
    ],
    "vlnv": "xilinx.com:ip:axi_dma:7.1",
    "memory-view": {
      "M_AXI_MM2S": {
        "pcie_0_axi_pcie_0": {
          "BAR0": {
            "highaddr": 4294967295,
            "size": 4294967296,
            "baseaddr": 0
          }
        }
      },
      "M_AXI_S2MM": {
        "pcie_0_axi_pcie_0": {
          "BAR0": {
            "highaddr": 4294967295,
            "size": 4294967296,
            "baseaddr": 0
          }
        }
      }
    },
    "irqs": {
      "s2mm_introut": "pcie_0_axi_pcie_intc_0:3",
      "mm2s_introut": "pcie_0_axi_pcie_intc_0:2"
    }
  },
  "pcie_0_axi_pcie_intc_0": {
    "vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.4"
  },
  "pcie_0_axi_pcie_0": {
    "vlnv": "xilinx.com:ip:axi_pcie:2.9",
    "memory-view": {
      "M_AXI": {
        "timer_0_axi_timer_0": {
          "Reg": {
            "highaddr": 20479,
            "size": 4096,
            "baseaddr": 16384
          }
        },
        "hier_0_axi_fifo_mm_s_0": {
          "Mem0": {
            "highaddr": 40959,
            "size": 8192,
            "baseaddr": 32768
          },
          "Mem1": {
            "highaddr": 57343,
            "size": 8192,
            "baseaddr": 49152
          }
        },
        "pcie_0_axi_pcie_0": {
          "CTL0": {
            "highaddr": 536870911,
            "size": 268435456,
            "baseaddr": 268435456
          }
        },
        "hier_0_aurora_axis_0": {
          "reg0": {
            "highaddr": 12287,
            "size": 4096,
            "baseaddr": 8192
          }
        },
        "pcie_0_axi_reset_0": {
          "Reg": {
            "highaddr": 32767,
            "size": 4096,
            "baseaddr": 28672
          }
        },
        "hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
          "Reg": {
            "highaddr": 24575,
            "size": 4096,
            "baseaddr": 20480
          }
        },
        "hier_0_axi_dma_axi_dma_0": {
          "Reg": {
            "highaddr": 16383,
            "size": 4096,
            "baseaddr": 12288
          }
        },
        "pcie_0_axi_pcie_intc_0": {
          "reg0": {
            "highaddr": 8191,
            "size": 4096,
            "baseaddr": 4096
          }
        }
      }
    },
    "pcie_bars": {
      "BAR0": {
        "translation": 0
      }
    },
    "axi_bars": {
      "BAR0": {
        "highaddr": 4294967295,
        "size": 4294967296,
        "translation": 0,
        "baseaddr": 0
      }
    }
  }
}