fpga = {
	/* Card identification */
	id = "10ee:7022";
	slot = "01:00.0";

	do_reset = true;

	ips = {
		axi_pcie_intc_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0";
			baseaddr = 0xb000;
		},
		axi_reset_0 = {
			vlnv = "xilinx.com:ip:axi_gpio:2.0";
			baseaddr = 0x7000;
		},
		bram_0 = {
			vlnv = "xilinx.com:ip:axi_bram_ctrl:4.0";
			baseaddr = 0x0000;
			size = 0x2000;
		},
		xsg_multiply_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:sysgen:xsg_multiply:1.0";
			baseaddr = 0x2000;
			port = 4;
			parameters = {
				factor = 2.0;
			}
		},
		dma_0 = {
			vlnv = "xilinx.com:ip:axi_dma:7.1";
			baseaddr = 0x3000;
			port = 1;
			irq = 3; /* 3 - 4 */
		},
		timer_0 = {
			vlnv = "xilinx.com:ip:axi_timer:2.0";
			baseaddr = 0x4000;
			irq = 0; /* 0 - 1 */
		},
		switch_0 = {
			vlnv = "xilinx.com:ip:axis_interconnect:2.1"
			baseaddr = 0x5000;
			numports = 10;
		},
		fifo_mm_s_0 = {
			vlnv = "xilinx.com:ip:axi_fifo_mm_s:4.1";
			baseaddr = 0x6000;
			baseaddr_axi4 = 0xC000;
			port = 2;
			irq = 2;
		},
		rtds_axis_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0";
			baseaddr = 0x8000;
			port = 5;
			irq = 5; /* 5 -7 */
		},
		hls_multiply_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_multiply:1.1";
			baseaddr = 0x9000;
			port = 5;
		},
		dma_1 = {
			vlnv = "xilinx.com:ip:axi_dma:7.1";
			baseaddr = 0xA000;
			port = 7;
			irq = 3; /* 3 - 4 */
		},
		hls_decimate_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_decimate:1.0";
			baseaddr = 0xE000;
			port = 8;
		},
		hls_dft_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0";
			baseaddr = 0xF000;
			port = 9;
		},
		axis_data_fifo_0 = {
			vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
			port = 3;
		},
		axis_data_fifo_1 = {
			vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
			port = 6;
		},
	}

	/* Configure switch */
	paths = (
		{ in = "dma",     out = "hls_dft" },
		{ in = "hls_dft", out = "dma" }
	)
}

nodes = {
	dma = {
		datamover = "dma_0";
		use_irqs = false;
	}

}