affinity = 0xC;

debug = 0;

stats = 1;

fpga = {
	/* Card identification */
	id = "10ee:7022";
	slot = "01:00.0";

	do_reset = true;

	ips = {
		axi_pcie_intc_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0";
			baseaddr = 0xb000;
		},
		axi_reset_0 = {
			vlnv = "xilinx.com:ip:axi_gpio:2.0";
			baseaddr = 0x7000;
		},
		bram_0 = {
			vlnv = "xilinx.com:ip:axi_bram_ctrl:4.0";
			baseaddr = 0x0000;
			size = 0x2000;
		},
		dma_0 = {
			vlnv = "xilinx.com:ip:axi_dma:7.1";
			baseaddr = 0x3000;
			port = 1;
			irq = 3; /* 3 - 4 */
		},
		timer_0 = {
			vlnv = "xilinx.com:ip:axi_timer:2.0";
			baseaddr = 0x4000;
			irq = 0;
		},
		switch_0 = {
			vlnv = "xilinx.com:ip:axis_interconnect:2.1"
			baseaddr = 0x5000;
			num_ports = 10;
		},
		fifo_mm_s_0 = {
			vlnv = "xilinx.com:ip:axi_fifo_mm_s:4.1";
			baseaddr = 0x6000;
			baseaddr_axi4 = 0xC000;
			port = 2;
			irq = 2;
		},
		rtds_axis_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0";
			baseaddr = 0x8000;
			port = 0;
			irq = 5; /* 5 -7 */

			inputs = {
				in  = "axis_interconnect:0"
			},
			outputs = {
				out  = "axis_interconnect:0",
			};
			irqs = {
				ts   = "axi_pcie_intc_0:5",
				ovfl = "axi_pcie_intc_0:6",
				case = "axi_pcie_intc_0:7",
			}
		},
		dma_1 = {
			vlnv = "xilinx.com:ip:axi_dma:7.1";
			baseaddr = 0x2000;
			port = 6;
			irq = 3; /* 3 - 4 */
		},
		hls_dft_0 = {
			vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0";
			baseaddr = 0x9000;
			port = 5;
			irq = 1;
			
			period = 400; /* in samples: 20ms / 50uS = 400*/
			harmonics = [ 0, 1, 3, 5, 7 ]
			decimation = 1; /* 0 = disabled */
			//harmonics = [ 0, 1, 2, 5, 22 ]
		},
		axis_data_fifo_0 = {
			vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
			port = 3;
		},
		axis_data_fifo_1 = {
			vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
			port = 6;
		},
	}

	/* Configure switch */
	paths = (
// DM Tests
//		{ in = "fifo_mm_s_0",	out = "fifo_mm_s_0" },
//		{ in = "dma_1",		out = "dma_1" },
//		{ in = "dma_0",		out = "dma_0" }

// DFT <-> RTDS
//		{ in = "rtds_axis_0",	out = "hls_dft_0" },
//		{ in = "hls_dft_0",	out = "rtds_axis_0" }

// Linux <-> RTDS
//		{ in = "rtds_axis_0",	out = "dma_1" },
//		{ in = "dma_1",		out = "rtds_axis_0" }

// DFT <-> Linux
		{ in = "dma_0",		out = "hls_dft_0" },
		{ in = "hls_dft_0",	out = "dma_0" }
	)
}

plugins = [
	"./lib/cbmodels/simple_circuit.so"
]

nodes = {
	dma_0 = {
		type = "fpga";
		datamover = "dma_0";
	},
	dma_1 = {
		type = "fpga";
		datamover = "dma_1";
	},
	fifo_0 = {
		type = "fpga";
		datamover = "fifo_mm_s_0";
		use_irqs = true
	},
	simple_circuit = {
		type = "cbuilder";
		model = "simple_circuit",
		timestep = 25e-6;
		parameters = [
			1.0,	/**< R2 = 1 Ohm */
			0.001	/**< C2 = 1000 uF */
		];
	}
}

paths = (
//	{ in = "dma_1", out = "dma_1" },
	{ in = "dma_1", out = "simple_circuit", reverse = true }
)