# 
VILLASfpga
[](https://git.rwth-aachen.de/acs/public/villas/fpga/fpga/-/pipelines/)
VILLASfpga provides a flexbible, real-time capable interconnect between FPGAs and Linux, e.g., to connect simulators and devices for hardware-in-the loop simulations. VILLASfpga can guarantee fixed latencies in the nanosecond range.
VILLASfpga supports Xilinx FPGAs connected to a Linux system via PCI-Express or via a platform bus as found on MPSoC devices.
## Documentation
User documentation is available here:
## License
This project is released under the terms of the [Apache 2.0](LICENSE) license:
- SPDX-FileCopyrightText: 2022-2023 Niklas Eiling
- SPDX-FileCopyrightText: 2018-2023 Steffen Vogel
- SPDX-FileCopyrightText: 2018 Daniel Krebs
- SPDX-License-Identifier: Apache-2.0
We kindly ask all academic publications employing components of VILLASframework to cite one of the following papers:
- A. Monti et al., "[A Global Real-Time Superlab: Enabling High Penetration of Power Electronics in the Electric Grid](https://ieeexplore.ieee.org/document/8458285/)," in IEEE Power Electronics Magazine, vol. 5, no. 3, pp. 35-44, Sept. 2018.
- S. Vogel, M. Mirz, L. Razik and A. Monti, "[An open solution for next-generation real-time power system simulation](http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8245739&isnumber=8244404)," 2017 IEEE Conference on Energy Internet and Energy System Integration (EI2), Beijing, 2017, pp. 1-6.
## Related Projects
- [MIOB](https://github.com/RWTH-ACS/miob)
- [DINO](https://github.com/RWTH-ACS/dino)
## Contact
- Niklas Eiling
- Steffen Vogel
- Daniel Krebs
[Institute for Automation of Complex Power Systems (ACS)](http://www.acs.eonerc.rwth-aachen.de)
[RWTH University Aachen, Germany](http://www.rwth-aachen.de)