{
  "affinity": 1,
  "stats": 3,
  "name": "villas-acs",
  "logging": {
    "level": 5,
    "faciltities": [
      "path",
      "socket"
    ],
    "file": "/var/log/villas-node.log",
    "syslog": true
  },
  "http": {
    "enabled": true,
    "htdocs": "/villas/web/socket/",
    "port": 80
  },
  "plugins": [
    "simple_circuit.so",
    "example_hook.so"
  ],
  "fpgas": {
    "vc707": {
      "id": "10ee:7022",
      "slot": "03:00.0",
      "do_reset": true,
      "ips": {
        "axi_pcie_intc_0": {
          "vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0",
          "baseaddr": 45056
        },
        "switch_0": {
          "vlnv": "xilinx.com:ip:axis_interconnect:2.1",
          "baseaddr": 20480,
          "num_ports": 10,
          "paths": [
            {
              "in": "rtds_axis_0",
              "out": "dma_1",
              "reverse": true
            }
          ]
        },
        "axi_reset_0": {
          "vlnv": "xilinx.com:ip:axi_gpio:2.0",
          "baseaddr": 28672
        },
        "timer_0": {
          "vlnv": "xilinx.com:ip:axi_timer:2.0",
          "baseaddr": 16384,
          "irq": 0
        },
        "dma_0": {
          "vlnv": "xilinx.com:ip:axi_dma:7.1",
          "baseaddr": 12288,
          "port": 1,
          "irq": 3
        },
        "dma_1": {
          "vlnv": "xilinx.com:ip:axi_dma:7.1",
          "baseaddr": 8192,
          "port": 6,
          "irq": 3
        },
        "fifo_mm_s_0": {
          "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1",
          "baseaddr": 24576,
          "baseaddr_axi4": 49152,
          "port": 2,
          "irq": 2
        },
        "rtds_axis_0": {
          "vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0",
          "baseaddr": 32768,
          "port": 0,
          "irq": 5
        },
        "hls_dft_0": {
          "vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0",
          "baseaddr": 36864,
          "port": 5,
          "irq": 1,
          "period": 400,
          "harmonics": [
            0,
            1,
            3,
            5,
            7
          ],
          "decimation": 0
        },
        "axis_data_fifo_0": {
          "vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
          "port": 3
        },
        "axis_data_fifo_1": {
          "vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
          "port": 6
        }
      }
    }
  },
  "nodes": {
    "dma_0": {
      "type": "fpga",
      "datamover": "dma_0",
      "use_irqs": false
    },
    "dma_1": {
      "type": "fpga",
      "datamover": "dma_1",
      "use_irqs": false
    },
    "fifo_0": {
      "type": "fpga",
      "datamover": "fifo_mm_s_0",
      "use_irqs": false
    },
    "simple_circuit": {
      "type": "cbuilder",
      "model": "simple_circuit",
      "timestep": 2.5000000000000001e-5,
      "parameters": [
        1.0,
        0.001
      ]
    }
  },
  "paths": [
    {
      "in": "dma_1",
      "out": "simple_circuit",
      "reverse": true
    }
  ]
}