2018-03-23 04:04:44 -04:00
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/*
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* Copyright (c) 2017, Stefan Lankes, RWTH Aachen University
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* 2014, Steffen Vogel, RWTH Aachen University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @author Stefan Lankes
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* @file arch/arm64/include/asm/page.h
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* @brief Paging related functions
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*
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* This file contains the several functions to manage the page tables
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*/
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#include <hermit/stddef.h>
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#include <hermit/stdlib.h>
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#include <asm/processor.h>
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#ifndef __PAGE_H__
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#define __PAGE_H__
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/// Page offset bits
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#define PAGE_BITS 12
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#define PAGE_2M_BITS 21
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2018-08-01 23:59:42 +02:00
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#define HUGE_PAGE_BITS 12
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2018-03-23 04:04:44 -04:00
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/// The size of a single page in bytes
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#define PAGE_SIZE ( 1L << PAGE_BITS)
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2018-08-01 23:59:42 +02:00
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#define PAGE_2M_SIZE ( 1L << PAGE_2M_BITS)
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#define HUGE_PAGE_SIZE ( 1L << HUGE_PAGE_BITS)
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2018-03-23 04:04:44 -04:00
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#define PAGE_MASK ((~0L) << PAGE_BITS)
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#define PAGE_2M_MASK ((~0L) << PAGE_2M_BITS)
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2018-08-01 23:59:42 +02:00
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#define HUGE_PAGE_MASK ((~0L) << HUGE_PAGE_BITS)
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2018-03-23 04:04:44 -04:00
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/// Total operand width in bits
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#define BITS 64
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/// Physical address width (maximum value)
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#define PHYS_BITS 48
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/// Linear/virtual address width
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#define VIRT_BITS 48
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/// Page map bits
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#define PAGE_MAP_BITS 9
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/// Number of page map indirections
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#define PAGE_LEVELS 4
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/// The number of entries in a page map table
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#define PAGE_MAP_ENTRIES (1L << PAGE_MAP_BITS)
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/// Align to next page
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#define PAGE_CEIL(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
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/// Align to page
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#define PAGE_FLOOR(addr) ( (addr) & PAGE_MASK)
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/// Align to next 2M boundary
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#define PAGE_2M_CEIL(addr) (((addr) + (1L << 21) - 1) & ((~0L) << 21))
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/// Align to 2M boundary
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#define PAGE_2M_FLOOR(addr) ( (addr) & ((~0L) << 21))
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2018-08-01 23:59:42 +02:00
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/// Align to next huge boundary
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#define PAGE_HUGE_CEIL(addr) (((addr) + HUGE_PAGE_MASK - 1) & HUGE_PAGE_MASK)
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/// Align to huge page boundary
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#define PAGE_HUGE_FLOOR(addr) ( (addr) & HUGE_PAGE_MASK)
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2018-03-23 04:04:44 -04:00
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// Align the kernel end
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2018-06-25 08:14:15 +00:00
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#define KERNEL_END_CEIL(addr) (((addr) + (16L << 10) - 1) & ~0x3FFFL)
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/// Page is present
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#define PG_PRESENT (1UL << 0)
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/// Page is read- and writable
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#define PG_RW (1UL << 1)
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/// Page is addressable from userspace
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#define PG_USER (1UL << 2)
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/// Page write through is activated
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#define PG_PWT (1UL << 3)
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/// Page cache is disabled
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#define PG_PCD (1UL << 4)
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/// Page was recently accessed (set by CPU)
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#define PG_ACCESSED (1UL << 5)
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/// Page is dirty due to recent write-access (set by CPU)
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#define PG_DIRTY (1UL << 6)
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/// Huge page: 4MB (or 2MB, 1GB)
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#define PG_PSE (1UL << 7)
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/// Page attribute table
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#define PG_PAT PG_PSE
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#define PG_DEVICE (1UL << 8)
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#define PG_NX 0
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#define PG_GLOBAL 0
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/// This table is a self-reference and should skipped by page_map_copy()
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#define PG_SELF (1UL << 63)
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#define PT_PT 0x713UL
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#define PT_MEM 0x713UL
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#define PT_MEM_CD 0x70FUL
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#define PT_DEVICE 0x707UL
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#define PT_SELF (1UL << 55)
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#define PT_AF (1UL << 10) /* Access Flag */
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#define PT_CONTIG (1UL << 52) /* Contiguous bit */
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#define PT_S (3UL << 8)
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#define PT_PXN (1UL << 53)
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#define PT_UXN (1UL << 54)
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/** @brief Converts a virtual address to a physical
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*
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* A non mapped virtual address causes a pagefault!
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*
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* @param addr Virtual address to convert
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* @return physical address
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*/
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size_t virt_to_phys(size_t vir);
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/** @brief Initialize paging subsystem
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*
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* This function uses the existing bootstrap page tables (boot_{pgd, pgt})
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* to map required regions (video memory, kernel, etc..).
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* Before calling page_init(), the bootstrap tables contain a simple identity
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* paging. Which is replaced by more specific mappings.
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*/
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int page_init(void);
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/** @brief Map a continuous region of pages
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*
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* @param viraddr Desired virtual address
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* @param phyaddr Physical address to map from
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* @param npages The region's size in number of pages
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* @param bits Further page flags
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* @param do_ipi if set, inform via IPI all other cores
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* @return
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*/
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int __page_map(size_t viraddr, size_t phyaddr, size_t npages, size_t bits);
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/** @brief Map a continuous region of pages
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*
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* @param viraddr Desired virtual address
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* @param phyaddr Physical address to map from
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* @param npages The region's size in number of pages
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* @param bits Further page flags
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* @return
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*/
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static inline int page_map(size_t viraddr, size_t phyaddr, size_t npages, size_t bits)
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{
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return __page_map(viraddr, phyaddr, npages, bits);
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}
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/** @brief Unmap a continuous region of pages
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*
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* @param viraddr The virtual start address
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* @param npages The range's size in pages
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* @return
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*/
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int page_unmap(size_t viraddr, size_t npages);
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/** @brief Change the page permission in the page tables of the current task
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*
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* Applies given flags noted in the 'flags' parameter to
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* the range denoted by virtual start and end addresses.
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*
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* @param start Range's virtual start address
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* @param end Range's virtual end address
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* @param flags flags to apply
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*
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* @return
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* - 0 on success
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* - -EINVAL (-22) on failure.
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*/
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int page_set_flags(size_t viraddr, uint32_t npages, int flags);
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/** @brief Handler to map on demand pages for the heap
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2018-07-21 21:42:11 +02:00
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*
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* * @param viraddr Virtual address, which triggers the page fault
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* * @param pc Instruction pointer, where the handler is triggered
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2018-03-23 04:04:44 -04:00
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*
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* @return
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* - 0 on success
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* - -EINVAL (-22) on failure.
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*/
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2018-07-21 21:42:11 +02:00
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int page_fault_handler(size_t viraddr, size_t pc);
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2018-03-23 04:04:44 -04:00
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/** @brief Flush Translation Lookaside Buffer
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*/
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static inline void tlb_flush(void)
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{
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asm volatile(
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"dsb ishst\n\t" // ensure write has completed
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"tlbi vmalle1is\n\t" // invalidate all TLB entries
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"dsb ish\n\t" // ensure completion of TLB invalidation
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"isb" // synchronize context
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:
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:
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: "memory"
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);
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}
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/** @brief Flush a specific page entry in TLB
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* @param addr The (virtual) address of the page to flush
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*/
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static inline void tlb_flush_one_page(size_t addr)
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{
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addr = addr >> PAGE_BITS;
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asm volatile(
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"dsb ishst\n\t" // ensure write has completed
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"tlbi vale1is, %0 \n\t"
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"dsb ish\n\t" // ensure completion of TLB invalidation
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"isb" // synchronize context
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:
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: "r"(addr)
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: "memory"
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);
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}
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/** @brief Flush a range of page entries in TLB
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* @param addr The (virtual) start address
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* @param end The (virtual) end address
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*/
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static inline void tlb_flush_range(size_t start, size_t end)
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{
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if ((end - start) > (1024ULL << PAGE_BITS)) {
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tlb_flush();
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return;
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}
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start = start >> PAGE_BITS;
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end = end >> PAGE_BITS;
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asm volatile ("dsb ishst" ::: "memory");
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for (size_t addr = start; addr < end; addr++)
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asm("tlbi vaae1is, %0" :: "r"(addr));
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asm volatile ("dsb ish" ::: "memory");
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asm volatile ("isb" ::: "memory");
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}
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2018-06-29 06:01:33 +00:00
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/** @brief Print the current page table tree
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*/
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void page_dump(void);
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2018-03-23 04:04:44 -04:00
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#endif
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