mirror of
https://github.com/hermitcore/libhermit.git
synced 2025-03-09 00:00:03 +01:00
revise code, stop x2APIC support if Linux doesn't use it
This commit is contained in:
Stefan Lankes
parent
60fd64381d
commit
03551659d4
4 changed files with 119 additions and 48 deletions
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@ -194,6 +194,8 @@ extern "C" {
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/// SwapGS GS shadow
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#define MSR_KERNEL_GS_BASE 0xc0000102
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#define MSR_XAPIC_ENABLE (1UL << 11)
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#define MSR_X2APIC_ENABLE (1UL << 10)
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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@ -150,6 +150,48 @@ int apic_is_enabled(void)
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return (lapic && initialized);
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}
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static inline void x2apic_disable(void)
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{
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uint64_t msr;
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if (!has_x2apic())
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return;
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msr = rdmsr(MSR_APIC_BASE);
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if (!(msr & MSR_X2APIC_ENABLE)) {
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kprintf("X2APIC already disabled!\n");
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return;
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}
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/* Disable xapic and x2apic first and then reenable xapic mode */
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wrmsr(MSR_APIC_BASE, msr & ~(MSR_X2APIC_ENABLE | MSR_XAPIC_ENABLE));
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wrmsr(MSR_APIC_BASE, msr & ~MSR_X2APIC_ENABLE);
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kprintf("Disable X2APIC support\n");
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lapic_read = lapic_read_default;
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lapic_write = lapic_write_default;
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}
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static inline void x2apic_enable(void)
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{
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uint64_t msr;
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if (!has_x2apic())
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return;
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msr = rdmsr(MSR_APIC_BASE);
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if (msr & MSR_X2APIC_ENABLE) {
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kprintf("X2APIC already enabled!\n");
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return;
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}
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wrmsr(MSR_APIC_BASE, msr | MSR_X2APIC_ENABLE);
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kprintf("Enable X2APIC support!\n");
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lapic_read = lapic_read_msr;
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lapic_write = lapic_write_msr;
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}
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/*
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* Send a 'End of Interrupt' command to the APIC
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*/
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@ -303,6 +345,8 @@ static int lapic_reset(void)
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if (!lapic)
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return -ENXIO;
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x2apic_enable();
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max_lvt = apic_lvt_entries();
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lapic_write(APIC_SVR, 0x17F); // enable the apic and connect to the idt entry 127
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@ -543,15 +587,16 @@ check_lapic:
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kprintf("Found APIC at 0x%x\n", lapic);
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if (has_x2apic()) {
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kprintf("Enable X2APIC support!\n");
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wrmsr(MSR_APIC_BASE, lapic | 0xD00);
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lapic_read = lapic_read_msr;
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lapic_write = lapic_write_msr;
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x2apic_enable();
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} else {
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page_map(LAPIC_ADDR, (size_t)lapic & PAGE_MASK, 1, PG_GLOBAL | PG_RW | PG_PCD);
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vma_add(LAPIC_ADDR, LAPIC_ADDR + PAGE_SIZE, VMA_READ | VMA_WRITE);
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lapic = LAPIC_ADDR;
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kprintf("Map APIC to 0x%x\n", lapic);
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if (page_map(LAPIC_ADDR, (size_t)lapic & PAGE_MASK, 1, PG_GLOBAL | PG_RW | PG_PCD)) {
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kprintf("Failed to map APIC to 0x%x\n", LAPIC_ADDR);
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goto out;
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} else {
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kprintf("Mapped APIC 0x%x to 0x%x\n", lapic, LAPIC_ADDR);
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vma_add(LAPIC_ADDR, LAPIC_ADDR + PAGE_SIZE, VMA_READ | VMA_WRITE);
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lapic = LAPIC_ADDR;
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}
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}
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kprintf("Maximum LVT Entry: 0x%x\n", apic_lvt_entries());
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@ -592,8 +637,7 @@ extern atomic_int32_t current_boot_id;
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#if MAX_CORES > 1
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int smp_start(void)
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{
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if (has_x2apic()) // enable x2APIC support
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wrmsr(MSR_APIC_BASE, lapic | 0xD00);
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x2apic_enable();
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// reset APIC and set id
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lapic_reset();
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@ -645,7 +689,7 @@ int ipi_tlb_flush(void)
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if (atomic_int32_read(&cpu_online) == 1)
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return 0;
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if (BUILTIN_EXPECT(has_x2apic(), 1)) {
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if (has_x2apic()) {
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flags = irq_nested_disable();
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for(i=0; i<MAX_APIC_CORES; i++)
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{
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@ -703,26 +747,27 @@ int apic_send_ipi(uint64_t dest, uint8_t irq)
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uint32_t j;
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uint8_t flags;
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if (BUILTIN_EXPECT(has_x2apic(), 1)) {
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if (has_x2apic()) {
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flags = irq_nested_disable();
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//kprintf("send IPI %d to %lld\n", (int)irq, dest);
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wrmsr(0x830, (dest << 32)|APIC_INT_ASSERT|APIC_DM_FIXED|irq);
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irq_nested_enable(flags);
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} else {
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if (lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kputs("ERROR: previous send not complete");
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return -EIO;
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}
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flags = irq_nested_disable();
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while (lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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PAUSE;
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}
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//kprintf("send IPI %d to %lld\n", (int)irq, dest);
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set_ipi_dest((uint32_t)dest);
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DM_FIXED|irq);
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j = 0;
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (j < 1000))
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (j < 1000)) {
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j++; // wait for it to finish, give up eventualy tho
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PAUSE;
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}
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irq_nested_enable(flags);
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}
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@ -735,19 +780,23 @@ static void apic_err_handler(struct state *s)
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kprintf("Got APIC error 0x%x\n", lapic_read(APIC_ESR));
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}
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static void apic_shutdown(struct state *s)
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extern uint32_t disable_x2apic;
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void shutdown_system(void)
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{
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int if_bootprocessor = (apic_processors[boot_processor]->id == apic_cpu_id());
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irq_disable();
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if (if_bootprocessor) {
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kprintf("Receive an IPI to shutdown HermitCore\n");
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kprintf("Try to shutdown HermitCore\n");
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while(atomic_int32_read(&cpu_online) != 1)
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PAUSE;
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network_shutdown();
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kprintf("Diable APIC timer\n");
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kprintf("Disable APIC timer\n");
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}
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apic_disable_timer();
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@ -757,16 +806,29 @@ static void apic_shutdown(struct state *s)
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lapic_write(APIC_LVT_TSR, 0x10000); // disable thermal sensor interrupt
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lapic_write(APIC_LVT_PMC, 0x10000); // disable performance counter interrupt
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lapic_write(APIC_SVR, 0x00); // disable the apic
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lapic_write(APIC_SVR, 0x00); // disable the apic
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// disable x2APIC
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if (if_bootprocessor && disable_x2apic)
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x2apic_disable();
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if (if_bootprocessor)
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kprintf("System goes down...\n");
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flush_cache();
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atomic_int32_dec(&cpu_online);
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HALT;
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kprintf("Ups, we should never reach this point!\n");
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while(1);
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while(1) {
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HALT;
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}
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}
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volatile uint32_t go_down = 0;
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static void apic_shutdown(struct state * s)
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{
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go_down = 1;
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kputs("Receive shutdown interrupt\n");
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}
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static void apic_lint0(struct state * s)
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@ -65,6 +65,7 @@ align 4
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global header_start_address
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global heap_size
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global header_size
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global disable_x2apic
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base dq 0
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limit dq 0
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cpu_freq dd 0
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@ -83,6 +84,7 @@ align 4
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possible_isles dd 1
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heap_start_address dq 0
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header_start_address dq 0
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disable_x2apic dd 1
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; Bootstrap page tables are used during the initialization.
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align 4096
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@ -140,30 +140,8 @@ int timer_wait(unsigned int ticks)
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while(rdtsc() - start < 1000000) ; \
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} while (0)
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/*
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* Sets up the system clock by installing the timer handler
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* into IRQ0
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*/
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int timer_init(void)
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static int pit_init(void)
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{
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/*
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* Installs 'timer_handler' for the PIC and APIC timer,
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* only one handler will be later used.
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*/
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irq_install_handler(32, timer_handler);
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irq_install_handler(123, timer_handler);
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irq_install_handler(121, wakeup_handler);
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#ifdef DYNAMIC_TICKS
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if (has_rdtscp())
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last_rdtsc = rdtscp(NULL);
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else
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last_rdtsc = rdtsc();
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#endif
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if (cpu_freq) // do we need to configure the timer?
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return 0;
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/*
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* Port 0x43 is for initializing the PIT:
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*
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@ -189,3 +167,30 @@ int timer_init(void)
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return 0;
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}
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/*
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* Sets up the system clock by installing the timer handler
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* into IRQ0
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*/
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int timer_init(void)
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{
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/*
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* Installs 'timer_handler' for the PIC and APIC timer,
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* only one handler will be later used.
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*/
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irq_install_handler(32, timer_handler);
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irq_install_handler(123, timer_handler);
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irq_install_handler(121, wakeup_handler);
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#ifdef DYNAMIC_TICKS
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if (has_rdtscp())
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last_rdtsc = rdtscp(NULL);
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else
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last_rdtsc = rdtsc();
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#endif
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if (cpu_freq) // do we need to configure the timer?
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return 0;
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return pit_init();
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}
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