From 40bbe61145256164fae6824bc7b967923afdf3ec Mon Sep 17 00:00:00 2001
From: Stefan Lankes <slankes@eonerc.rwth-aachen.de>
Date: Fri, 18 Aug 2017 01:01:42 +0200
Subject: [PATCH] increase the readability

---
 .travis.yml               |  2 +-
 arch/x86/kernel/entry.asm | 10 ----------
 2 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index d00ebb6a1..dc5b90598 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -29,7 +29,7 @@ notifications:
   slack: hermitcore:UtcfeEXkbpx3WyIDK2Wm2beS
 
 deploy:
-  on: 
+  on:
     branch: master
     condition: "$CC = gcc"
   provider: bintray
diff --git a/arch/x86/kernel/entry.asm b/arch/x86/kernel/entry.asm
index f494f4ffc..c33d9b97e 100644
--- a/arch/x86/kernel/entry.asm
+++ b/arch/x86/kernel/entry.asm
@@ -256,16 +256,6 @@ Lsmp_main:
     jmp $
 %endif
 
-;ALIGN 64
-;global gdt_flush
-extern gp
-
-; This will set up our new segment registers and is declared in
-; C as 'extern void gdt_flush();'
-;gdt_flush:
-;    lgdt [gp]
-;    ret
-
 ; The first 32 interrupt service routines (ISR) entries correspond to exceptions.
 ; Some exceptions will push an error code onto the stack which is specific to
 ; the exception caused. To decrease the complexity, we handle this by pushing a