mirror of
https://github.com/hermitcore/libhermit.git
synced 2025-03-09 00:00:03 +01:00
move trampoline code to Linux, where the code is used
This commit is contained in:
Stefan Lankes
parent
1418450e88
commit
4f8be4efc1
2 changed files with 2 additions and 268 deletions
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@ -1,9 +1,6 @@
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MAKE = make
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NASM = nasm
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NASMFLAGS = -fbin
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CC = gcc
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CFLAGS = -O2 -Wall
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HEXDUMP = hexdump
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PROXYFILES = proxy init.sh $(shell find ../usr/tests ../usr/benchmarks ../usr/openmpbench -type f -executable)
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# Prettify output
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@ -18,28 +15,17 @@ endif
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@echo [CC] $@
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$Q$(CC) -c $(CFLAGS) -o $@ $<
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all: init.h proxy
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all: proxy
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proxy: proxy.o
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@echo [LD] $@
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$Q$(CC) $(CFLAGS) -o $@ $< -lelf
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init.bin: init.asm
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@echo [NASM] $@
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$Q$(NASM) $(NASMFLAGS) -o $@ $<
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init.h: init.bin
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@echo [HEXDUMP] $@
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$Q@echo "static const uint8_t boot_code[] = {" > $@
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$Q$(HEXDUMP) -v -e '"0x" 1/1 "%02X" ", "' $< >> $@
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$Q@echo "};" >> $@
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clean:
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@echo Cleaning tools
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$Q$(RM) -rf *.o *~ *.bin *.obj *.h
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$Q$(RM) -rf *.o *~ *.bin *.obj
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veryclean: clean
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$Q$(RM) -rf iso
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depend:
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$(CC) -MM $(CFLAGS) *.c > Makefile.dep
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@ -1,252 +0,0 @@
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; Copyright 2010-2015 Stefan Lankes, RWTH Aachen University
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; All rights reserved.
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;
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; This software is licensed under the terms of the GNU General Public
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; License version 2, as published by the Free Software Foundation, and
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; may be copied, distributed, and modified under those terms.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; This is the kernel's entry point for the application processors.
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; We switch to the protected mode and jump to HermitCore's kernel.
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KERNEL_STACK_SIZE equ 0x100
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kernel_start equ 0x800000
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[BITS 16]
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SECTION .text
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GLOBAL _start
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ORG 0x00
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_start:
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cli
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lgdt [gdtr]
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; switch to protected mode by setting PE bit
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mov eax, cr0
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or al, 0x1
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mov cr0, eax
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; far jump to the 32bit code
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jmp dword codesel : _pmstart
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[BITS 32]
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ALIGN 4
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_pmstart:
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xor eax, eax
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mov ax, datasel
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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mov esp, boot_stack+KERNEL_STACK_SIZE-16
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mov ebp, 0x00 ; dummy value
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jmp short stublet
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jmp $
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; GDT for the protected mode
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ALIGN 4
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gdtr: ; descritor table
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dw gdt_end-gdt-1 ; limit
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dd gdt ; base adresse
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gdt:
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dd 0,0 ; null descriptor
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codesel equ $-gdt
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dw 0xFFFF ; segment size 0..15
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dw 0x0000 ; segment address 0..15
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db 0x00 ; segment address 16..23
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db 0x9A ; access permissions und type
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db 0xCF ; additional information and segment size 16...19
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db 0x00 ; segment address 24..31
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datasel equ $-gdt
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dw 0xFFFF ; segment size 0..15
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dw 0x0000 ; segment address 0..15
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db 0x00 ; segment address 16..23
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db 0x92 ; access permissions and type
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db 0xCF ; additional informationen and degment size 16...19
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db 0x00 ; segment address 24..31
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gdt_end:
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ALIGN 4
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GDTR64:
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dw GDT64_end - GDT64 - 1 ; Limit.
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dq GDT64 ; Base.
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; we need a new GDT to switch in the 64bit modus
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GDT64: ; Global Descriptor Table (64-bit).
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.Null: equ $ - GDT64 ; The null descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 0 ; Access.
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db 0 ; Granularity.
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db 0 ; Base (high).
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.Code: equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10011000b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.Data: equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10010010b ; Access.
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db 00000000b ; Granularity.
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db 0 ; Base (high).
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GDT64_end:
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ALIGN 4
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stublet:
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; This will set up the x86 control registers:
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; Caching and the floating point unit are enabled
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; Bootstrap page tables are loaded and page size
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; extensions (huge pages) enabled.
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cpu_init:
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; relocate page tables
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mov edi, boot_pml4
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add edi, ebp
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mov eax, DWORD [edi]
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add eax, ebp
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mov DWORD [edi], eax
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mov eax, DWORD [edi+511*8]
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add eax, ebp
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mov DWORD [edi+511*8], eax
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mov edi, boot_pdpt
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add edi, ebp
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mov eax, DWORD [edi]
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add eax, ebp
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mov DWORD [edi], eax
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mov eax, DWORD [edi+511*8]
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add eax, ebp
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mov DWORD [edi+511*8], eax
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mov edi, boot_pgd
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add edi, ebp
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mov eax, DWORD [edi]
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add eax, ebp
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mov DWORD [edi], eax
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mov eax, DWORD [edi+511*8]
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add eax, ebp
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mov DWORD [edi+511*8], eax
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; initialize page tables
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; map kernel at link address, use a page size of 2M
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mov eax, 0x00 ; lower part of the page addres, Linux will relocate this value
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and eax, 0xFFE00000
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or eax, 0x183
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mov ebx, 0x00 ; higher part of the page address, Linux will relocate this value
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mov edi, kernel_start
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and edi, 0xFFE00000
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shr edi, 18 ; (edi >> 21) * 8 (index for boot_pgd)
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add edi, boot_pgd
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add edi, ebp
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mov DWORD [edi], eax
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mov DWORD [edi+4], ebx
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; check for long mode
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; do we have the instruction cpuid?
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz $ ; there is no long mode
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; cpuid > 0x80000000?
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb $ ; It is less, there is no long mode.
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; do we have a long mode?
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz $ ; They aren't, there is no long mode.
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; we need to enable PAE modus
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; Set CR3
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mov eax, boot_pml4
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add eax, ebp
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or eax, (1 << 0) ; set present bit
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mov cr3, eax
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; Set CR4 (PAE is already set)
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mov eax, cr4
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and eax, 0xfffbf9ff ; disable SSE
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or eax, (1 << 7) ; enable PGE
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or eax, (1 << 20) ; enable SMEP
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mov cr4, eax
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; Set CR0 (PM-bit is already set)
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mov eax, cr0
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and eax, ~(1 << 2) ; disable FPU emulation
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or eax, (1 << 1) ; enable FPU montitoring
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and eax, ~(1 << 30) ; enable caching
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and eax, ~(1 << 29) ; disable write through caching
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and eax, ~(1 << 16) ; allow kernel write access to read-only pages
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or eax, (1 << 31) ; enable paging
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mov cr0, eax
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lgdt [GDTR64] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:start64 ; Set the code segment and enter 64-bit long mode.
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[BITS 64]
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ALIGN 8
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start64:
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push kernel_start
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ret
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ALIGN 16
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global boot_stack
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boot_stack:
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TIMES (KERNEL_STACK_SIZE) DB 0xcd
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; Bootstrap page tables are used during the initialization.
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ALIGN 4096
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boot_pml4:
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DQ boot_pdpt + 0x7 ; PG_PRESENT | PG_RW | PG_USER
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times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
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DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
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boot_pdpt:
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DQ boot_pgd + 0x7 ; PG_PRESENT | PG_RW | PG_USER
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times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
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DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
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boot_pgd:
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DQ boot_pgt + 0x7 ; PG_PRESENT | PG_RW | PG_USER
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times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
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DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
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boot_pgt:
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%assign i 0
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%rep 512
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DQ i*0x1000 + 0x103
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%assign i i+1
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%endrep
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