mirror of
https://github.com/hermitcore/libhermit.git
synced 2025-03-09 00:00:03 +01:00
enable to boot a kernel per NUMA node
- redesign of the startup code => moving of 32bit stuff to the trampoline code - create entry for each numa node in /sys/hermit
This commit is contained in:
Stefan Lankes
parent
00a5719142
commit
787b2a0634
4 changed files with 247 additions and 291 deletions
1
hermit/.gitignore
vendored
1
hermit/.gitignore
vendored
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@ -5,7 +5,6 @@
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*.elf32
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*.sym
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*.bin
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*.hex
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documentation/html/
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include/hermit/config.inc
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newlib/examples/hello
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@ -1,5 +1,5 @@
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; Copyright (c) 2010, Stefan Lankes, RWTH Aachen University
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; Copyright (c) 2010-2015, Stefan Lankes, RWTH Aachen University
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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@ -31,7 +31,7 @@
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%include "config.inc"
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[BITS 32]
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[BITS 64]
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extern kernel_start ; defined in linker script
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extern kernel_end
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@ -41,288 +41,22 @@ extern kernel_end
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SECTION .mboot
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global start
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start:
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; do we have a multiboot info? => no relocation required
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cmp ebx, 0
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je short Lnoreset
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mov ebp, kernel_start
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Lnoreset:
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; relocate jmp
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mov eax, stublet
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sub eax, kernel_start
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add eax, ebp ; ebp contains the physical address of the kernel
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jmp eax
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jmp start64
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; This part MUST be 4 byte aligned, so we solve that issue using 'ALIGN 4'.
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align 4
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mboot:
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; Multiboot macros to make a few lines more readable later
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MULTIBOOT_PAGE_ALIGN equ (1 << 0)
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MULTIBOOT_MEMORY_INFO equ (1 << 1)
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MULTIBOOT_HEADER_MAGIC equ 0x1BADB002
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MULTIBOOT_HEADER_FLAGS equ MULTIBOOT_PAGE_ALIGN | MULTIBOOT_MEMORY_INFO
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MULTIBOOT_CHECKSUM equ -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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; This is the GRUB Multiboot header. A boot signature
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dd MULTIBOOT_HEADER_MAGIC
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dd MULTIBOOT_HEADER_FLAGS
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dd MULTIBOOT_CHECKSUM
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dd 0, 0, 0, 0, 0 ; address fields
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dd 0, 0, 0, 0,
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global base
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global limit
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global cpu_freq
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global boot_processor
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global cpu_online
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base dd kernel_start
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limit dd 0
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base dq 0
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limit dq 0
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cpu_freq dd 0
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boot_processor dd -1
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cpu_online dd 0
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align 4
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; we need already a valid GDT to switch in the 64bit modus
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GDT64: ; Global Descriptor Table (64-bit).
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.Null: equ $ - GDT64 ; The null descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 0 ; Access.
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db 0 ; Granularity.
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db 0 ; Base (high).
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.Code: equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10011000b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.Data: equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10010010b ; Access.
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db 00000000b ; Granularity.
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db 0 ; Base (high).
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.Pointer: ; The GDT-pointer.
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dw $ - GDT64 - 1 ; Limit.
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dq GDT64 ; Base.
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SECTION .text
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align 4
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stublet:
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; Relocate stack pointer
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mov eax, boot_stack
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sub eax, kernel_start
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add eax, ebp
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mov esp, eax
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add esp, KERNEL_STACK_SIZE - 16
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mov eax, boot_processor
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sub eax, kernel_start
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add eax, ebp
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mov eax, DWORD [eax]
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cmp eax, -1
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je L0
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imul eax, KERNEL_STACK_SIZE
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add esp, eax
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L0:
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; Interpret multiboot information
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mov eax, mb_info
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [eax], ebx
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; This will set up the x86 control registers:
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; Caching and the floating point unit are enabled
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; Bootstrap page tables are loaded and page size
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; extensions (huge pages) enabled.
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cpu_init:
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push edi
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; do we have to relocate / to intialize the page tables?
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; only the boot_processor have to do it
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mov eax, cpu_online
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sub eax, kernel_start
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add eax, ebp
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mov eax, DWORD [eax]
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cmp eax, 0
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je short Lrelocate
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mov eax, Lmap_kernel
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sub eax, kernel_start
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add eax, ebp ; ebp contains the physical address of the kernel
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jmp eax
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Lrelocate:
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; relocate page tables
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mov edi, boot_pml4
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sub edi, kernel_start
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add edi, ebp
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mov eax, DWORD [edi]
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [edi], eax
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mov eax, DWORD [edi+511*8]
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [edi+511*8], eax
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mov edi, boot_pdpt
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sub edi, kernel_start
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add edi, ebp
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mov eax, DWORD [edi]
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [edi], eax
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mov eax, DWORD [edi+511*8]
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [edi+511*8], eax
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mov edi, boot_pgd
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sub edi, kernel_start
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add edi, ebp
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mov eax, DWORD [edi]
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [edi], eax
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mov eax, DWORD [edi+511*8]
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sub eax, kernel_start
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add eax, ebp
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mov DWORD [edi+511*8], eax
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; initialize page tables
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; map vga 1:1
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%ifdef CONFIG_VGA
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mov eax, VIDEO_MEM_ADDR ; map vga
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and eax, 0xFFFFF000 ; page align lower half
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mov edi, eax
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shr edi, 9 ; (edi >> 12) * 8 (index for boot_pgt)
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add edi, boot_pgt
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sub edi, kernel_start
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add edi, ebp
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or eax, 0x113 ; set present, global, writable and cache disable bits
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mov DWORD [edi], eax
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%endif
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; map multiboot info 1:1
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mov eax, mb_info ; map multiboot info
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sub eax, kernel_start
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add eax, ebp
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mov eax, DWORD [eax]
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cmp eax, 0
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je short Lno_mbinfo
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and eax, 0xFFFFF000 ; page align lower half
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mov edi, eax
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shr edi, 9 ; (edi >> 12) * 8 (index for boot_pgt)
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add edi, boot_pgt
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sub edi, kernel_start
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add edi, ebp
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or eax, 0x101 ; set present and global bits
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mov DWORD [edi], eax
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Lno_mbinfo:
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; map kernel at link address, use a page size of 2MB
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mov eax, ebp
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and eax, 0xFFE00000
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mov edi, kernel_start
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and edi, 0xFFE00000
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shr edi, 18 ; (edi >> 21) * 8 (index for boot_pgd)
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add edi, boot_pgd
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sub edi, kernel_start
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add edi, ebp
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or eax, 0x183
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mov DWORD [edi], eax
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Lmap_kernel:
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cmp ebp, kernel_start
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je Lno_remap
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; map kernel 1:1, use a page size of 2MB
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mov eax, ebp
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and eax, 0xFFE00000
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mov edi, eax
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shr edi, 18 ; (edi >> 21) * 8 (index for boot_pgd)
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add edi, boot_pgd
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sub edi, kernel_start
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add edi, ebp
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or eax, 0x183
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mov DWORD [edi], eax
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Lno_remap:
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pop edi
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; check for long mode
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; do we have the instruction cpuid?
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz $ ; there is no long mode
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; cpuid > 0x80000000?
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb $ ; It is less, there is no long mode.
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; do we have a long mode?
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz $ ; They aren't, there is no long mode.
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; we need to enable PAE modus
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; switch to the compatibility mode (which is part of long mode)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; Set CR3
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mov eax, boot_pml4
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sub eax, kernel_start
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add eax, ebp
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or eax, (1 << 0) ; set present bit
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mov cr3, eax
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; Set CR4 (PAE is already set)
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mov eax, cr4
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and eax, 0xfffbf9ff ; disable SSE
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or eax, (1 << 7) ; enable PGE
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or eax, (1 << 20) ; enable SMEP
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mov cr4, eax
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; Set CR0 (PM-bit is already set)
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mov eax, cr0
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and eax, ~(1 << 2) ; disable FPU emulation
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or eax, (1 << 1) ; enable FPU montitoring
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and eax, ~(1 << 30) ; enable caching
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and eax, ~(1 << 29) ; disable write through caching
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and eax, ~(1 << 16) ; allow kernel write access to read-only pages
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or eax, (1 << 31) ; enable paging
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mov cr0, eax
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lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:start64 ; Set the code segment and enter 64-bit long mode.
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[BITS 64]
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start64:
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; initialize segment registers
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mov ax, 0x00
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@ -333,16 +67,60 @@ start64:
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mov fs, ax
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mov gs, ax
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cmp ebp, kernel_start
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je Lno_unmap
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; unmap temporary 1:1 mapping of the kernel
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mov edi, ebp
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shr edi, 18 ; (edi >> 21) * 8 (index for boot_pgd)
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add edi, boot_pgd
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mov DWORD [edi], 0
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xor rdi, rdi
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mov eax, DWORD [cpu_online]
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cmp eax, 0
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jne Lno_pml4_init
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; relocate page tables
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mov rdi, boot_pml4
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mov rax, QWORD [rdi]
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sub rax, kernel_start
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add rax, [base]
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mov QWORD [rdi], rax
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mov rax, QWORD [rdi+511*8]
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sub rax, kernel_start
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add rax, [base]
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mov QWORD [rdi+511*8], rax
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mov rdi, boot_pdpt
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mov rax, QWORD [rdi]
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sub rax, kernel_start
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add rax, [base]
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mov QWORD [rdi], rax
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mov rax, QWORD [rdi+511*8]
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sub rax, kernel_start
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add rax, [base]
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mov QWORD [rdi+511*8], rax
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mov rdi, boot_pgd
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mov rax, QWORD [rdi]
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sub rax, kernel_start
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add rax, [base]
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mov QWORD [rdi], rax
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mov rax, QWORD [rdi+511*8]
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sub rax, kernel_start
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add rax, [base]
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mov QWORD [rdi+511*8], rax
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; remap kernel
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mov rdi, kernel_start
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shr rdi, 18 ; (edi >> 21) * 8 (index for boot_pgd)
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add rdi, boot_pgd
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mov rax, [base]
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or rax, 0x183
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mov QWORD [rdi], rax
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Lno_pml4_init:
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; Set CR3
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mov rax, boot_pml4
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sub rax, kernel_start
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add rax, [base]
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or rax, (1 << 0) ; set present bit
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mov cr3, rax
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Lno_unmap:
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%if MAX_CORES > 1
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mov eax, DWORD [cpu_online]
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cmp eax, 0
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@ -21,15 +21,17 @@ endif
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default: all
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all: init.hex make_initrd initrd.o
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all: init.h make_initrd initrd.o
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init.bin: init.asm
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@echo [NASM] $@
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$Q$(NASM) $(NASMFLAGS) -o $@ $<
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init.hex: init.bin
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init.h: init.bin
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@echo [HEXDUMP] $@
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$Q$(HEXDUMP) -v -e '"0x" 1/1 "%02X" ", "' $< > $@
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$Q@echo "static const uint8_t boot_code[] = {" > $@
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$Q$(HEXDUMP) -v -e '"0x" 1/1 "%02X" ", "' $< >> $@
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$Q@echo "};" >> $@
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initrd.o: initrd.S initrd.img
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@echo [CC] Build initrd as object file
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@ -44,7 +46,7 @@ make_initrd: make_initrd.o
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clean:
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@echo Cleaning tools
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$Q$(RM) -rf *.o *~ *.bin *.obj *.hex
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$Q$(RM) -rf *.o *~ *.bin *.obj *.h
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veryclean: clean
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@ -26,6 +26,9 @@
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; This is the kernel's entry point for the application processors.
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; We switch to the protected mode and jump to HermitCore's kernel.
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KERNEL_STACK_SIZE equ 0x100
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kernel_start equ 0x200000
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[BITS 16]
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SECTION .text
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GLOBAL _start
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@ -53,14 +56,12 @@ _pmstart:
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mov gs, ax
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mov ss, ax
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xor ebx, ebx ; invalid multiboot address
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mov esp, -16
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mov ebp, 0x00 ; dummy value
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push DWORD 0x00 ; dummy value
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push DWORD 0x00 ; dummy value
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jmp codesel : 0x00 ; dummy value
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mov esp, boot_stack+KERNEL_STACK_SIZE-16
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mov ebp, 0x00 ; dummy value
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jmp short stublet
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jmp $
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; GDT for the protected mode
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ALIGN 4
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gdtr: ; descritor table
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dw gdt_end-gdt-1 ; limit
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@ -82,3 +83,179 @@ datasel equ $-gdt
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db 0xCF ; additional informationen and degment size 16...19
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db 0x00 ; segment address 24..31
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gdt_end:
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ALIGN 4
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; we need a new GDT to switch in the 64bit modus
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GDT64: ; Global Descriptor Table (64-bit).
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.Null: equ $ - GDT64 ; The null descriptor.
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dw 0 ; Limit (low).
|
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dw 0 ; Base (low).
|
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db 0 ; Base (middle)
|
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db 0 ; Access.
|
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db 0 ; Granularity.
|
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db 0 ; Base (high).
|
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.Code: equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
|
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dw 0 ; Base (low).
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db 0 ; Base (middle)
|
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db 10011000b ; Access.
|
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.Data: equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
|
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dw 0 ; Base (low).
|
||||
db 0 ; Base (middle)
|
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db 10010010b ; Access.
|
||||
db 00000000b ; Granularity.
|
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db 0 ; Base (high).
|
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.Pointer: ; The GDT-pointer.
|
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dw $ - GDT64 - 1 ; Limit.
|
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dq GDT64 ; Base.
|
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|
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ALIGN 4
|
||||
stublet:
|
||||
|
||||
; This will set up the x86 control registers:
|
||||
; Caching and the floating point unit are enabled
|
||||
; Bootstrap page tables are loaded and page size
|
||||
; extensions (huge pages) enabled.
|
||||
cpu_init:
|
||||
; relocate page tables
|
||||
mov edi, boot_pml4
|
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add edi, ebp
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mov eax, DWORD [edi]
|
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add eax, ebp
|
||||
mov DWORD [edi], eax
|
||||
|
||||
mov eax, DWORD [edi+511*8]
|
||||
add eax, ebp
|
||||
mov DWORD [edi+511*8], eax
|
||||
|
||||
mov edi, boot_pdpt
|
||||
add edi, ebp
|
||||
mov eax, DWORD [edi]
|
||||
add eax, ebp
|
||||
mov DWORD [edi], eax
|
||||
|
||||
mov eax, DWORD [edi+511*8]
|
||||
add eax, ebp
|
||||
mov DWORD [edi+511*8], eax
|
||||
|
||||
mov edi, boot_pgd
|
||||
add edi, ebp
|
||||
mov eax, DWORD [edi]
|
||||
add eax, ebp
|
||||
mov DWORD [edi], eax
|
||||
|
||||
mov eax, DWORD [edi+511*8]
|
||||
add eax, ebp
|
||||
mov DWORD [edi+511*8], eax
|
||||
|
||||
; initialize page tables
|
||||
|
||||
; map kernel at link address, use a page size of 2M
|
||||
mov eax, 0x00 ; dummy value
|
||||
and eax, 0xFFE00000
|
||||
mov edi, kernel_start
|
||||
and edi, 0xFFE00000
|
||||
shr edi, 18 ; (edi >> 21) * 8 (index for boot_pgd)
|
||||
add edi, boot_pgd
|
||||
add edi, ebp
|
||||
or eax, 0x183
|
||||
mov DWORD [edi], eax
|
||||
|
||||
; check for long mode
|
||||
|
||||
; do we have the instruction cpuid?
|
||||
pushfd
|
||||
pop eax
|
||||
mov ecx, eax
|
||||
xor eax, 1 << 21
|
||||
push eax
|
||||
popfd
|
||||
pushfd
|
||||
pop eax
|
||||
push ecx
|
||||
popfd
|
||||
xor eax, ecx
|
||||
jz $ ; there is no long mode
|
||||
|
||||
; cpuid > 0x80000000?
|
||||
mov eax, 0x80000000
|
||||
cpuid
|
||||
cmp eax, 0x80000001
|
||||
jb $ ; It is less, there is no long mode.
|
||||
|
||||
; do we have a long mode?
|
||||
mov eax, 0x80000001
|
||||
cpuid
|
||||
test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
|
||||
jz $ ; They aren't, there is no long mode.
|
||||
|
||||
; we need to enable PAE modus
|
||||
mov eax, cr4
|
||||
or eax, 1 << 5
|
||||
mov cr4, eax
|
||||
|
||||
mov ecx, 0xC0000080
|
||||
rdmsr
|
||||
or eax, 1 << 8
|
||||
wrmsr
|
||||
|
||||
; Set CR3
|
||||
mov eax, boot_pml4
|
||||
add eax, ebp
|
||||
or eax, (1 << 0) ; set present bit
|
||||
mov cr3, eax
|
||||
|
||||
; Set CR4 (PAE is already set)
|
||||
mov eax, cr4
|
||||
and eax, 0xfffbf9ff ; disable SSE
|
||||
or eax, (1 << 7) ; enable PGE
|
||||
or eax, (1 << 20) ; enable SMEP
|
||||
mov cr4, eax
|
||||
|
||||
; Set CR0 (PM-bit is already set)
|
||||
mov eax, cr0
|
||||
and eax, ~(1 << 2) ; disable FPU emulation
|
||||
or eax, (1 << 1) ; enable FPU montitoring
|
||||
and eax, ~(1 << 30) ; enable caching
|
||||
and eax, ~(1 << 29) ; disable write through caching
|
||||
and eax, ~(1 << 16) ; allow kernel write access to read-only pages
|
||||
or eax, (1 << 31) ; enable paging
|
||||
mov cr0, eax
|
||||
|
||||
lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
|
||||
jmp GDT64.Code:start64 ; Set the code segment and enter 64-bit long mode.
|
||||
|
||||
[BITS 64]
|
||||
ALIGN 8
|
||||
start64:
|
||||
mov rax, kernel_start
|
||||
jmp rax
|
||||
|
||||
ALIGN 16
|
||||
global boot_stack
|
||||
boot_stack:
|
||||
TIMES (KERNEL_STACK_SIZE) DB 0xcd
|
||||
|
||||
; Bootstrap page tables are used during the initialization.
|
||||
ALIGN 4096
|
||||
boot_pml4:
|
||||
DQ boot_pdpt + 0x7 ; PG_PRESENT | PG_RW | PG_USER
|
||||
times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
|
||||
DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
|
||||
boot_pdpt:
|
||||
DQ boot_pgd + 0x7 ; PG_PRESENT | PG_RW | PG_USER
|
||||
times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
|
||||
DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
|
||||
boot_pgd:
|
||||
DQ boot_pgt + 0x7 ; PG_PRESENT | PG_RW | PG_USER
|
||||
times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
|
||||
DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
|
||||
boot_pgt:
|
||||
%assign i 0
|
||||
%rep 512
|
||||
DQ i*0x1000 + 0x103
|
||||
%assign i i+1
|
||||
%endrep
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue