mirror of
https://github.com/hermitcore/libhermit.git
synced 2025-03-09 00:00:03 +01:00
simplify uart device
- HermitCore uses on uart to send log messages to qemu - unidirectional communication => remove interrupt handler - remove mmio support for uart
This commit is contained in:
Stefan Lankes
parent
815937216f
commit
890134dc82
4 changed files with 8 additions and 151 deletions
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@ -40,12 +40,6 @@ extern "C" {
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*/
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int uart_init(void);
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/** @brief Initialize UART output without a device check
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*
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* @return Returns 0 on success
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*/
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int uart_early_init(char*);
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/** @brief Simple string output on a serial device.
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*
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* If you want a new line you will have to "\\n".
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@ -97,40 +97,28 @@
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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static uint8_t mmio = 0;
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static size_t iobase = 0;
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static inline unsigned char read_from_uart(uint32_t off)
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{
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uint8_t c = 0;
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if (mmio)
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c = *((const volatile unsigned char*) (iobase + off));
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else if (iobase)
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if (iobase)
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c = inportb(iobase + off);
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return c;
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}
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static void write_to_uart(uint32_t off, unsigned char c)
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static inline void write_to_uart(uint32_t off, unsigned char c)
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{
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if (mmio)
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*((volatile unsigned char*) (iobase + off)) = c;
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else if (iobase)
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if (iobase)
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outportb(iobase + off, c);
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}
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/* Get a single character on a serial device */
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static unsigned char uart_getchar(void)
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{
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return read_from_uart(UART_RX);
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}
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/* Puts a single character on a serial device */
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int uart_putchar(unsigned char c)
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{
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if (!iobase && !mmio)
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if (!iobase)
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return 0;
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write_to_uart(UART_TX, c);
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@ -143,7 +131,7 @@ int uart_puts(const char *text)
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{
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size_t i, len = strlen(text);
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if (!iobase && !mmio)
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if (!iobase)
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return 0;
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for (i = 0; i < len; i++)
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@ -152,39 +140,6 @@ int uart_puts(const char *text)
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return len;
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}
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/* Handles all UART's interrupt */
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static void uart_handler(struct state *s)
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{
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unsigned char c = read_from_uart(UART_IIR);
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while (!(c & UART_IIR_NO_INT)) {
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if (c & UART_IIR_RDI) {
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c = uart_getchar();
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//TODO: handle input messages
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goto out;
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}
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if(c & UART_IIR_THRI) {
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// acknowledge interrupt
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c = read_from_uart(UART_IIR);
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goto out;
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}
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if(c & UART_IIR_RLSI) {
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// acknowledge interrupt
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c = read_from_uart(UART_LSR);
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goto out;
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}
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out:
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c = read_from_uart(UART_IIR);
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}
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}
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static int uart_config(void)
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{
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/*
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@ -226,105 +181,14 @@ static int uart_config(void)
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extern const void kernel_start;
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int uart_early_init(char* cmdline)
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{
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if (is_uhyve())
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return 0;
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#if 1
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// default value of our QEMU configuration
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iobase = 0xc110;
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#else
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if (BUILTIN_EXPECT(!cmdline, 0))
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return -EINVAL;
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char* str = strstr(cmdline, "uart=");
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if (!str)
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return -EINVAL;
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if (strncmp(str, "uart=io:", 8) == 0) {
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iobase = strtol(str+8, (char **)NULL, 16);
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if (!iobase)
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return -EINVAL;
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mmio = 0;
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} else if (strncmp(str, "uart=mmio:", 10) == 0) {
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iobase = strtol(str+10, (char **)NULL, 16);
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if (!iobase)
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return -EINVAL;
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if (iobase >= PAGE_MAP_ENTRIES*PAGE_SIZE) {
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/* at this point we use the boot page table
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* => IO address is not mapped
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* => dirty hack, map device before the kernel
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*/
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int err;
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size_t newaddr = ((size_t) &kernel_start - PAGE_SIZE);
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err = page_map_bootmap(newaddr & PAGE_MASK, iobase & PAGE_MASK, PG_GLOBAL | PG_ACCESSED | PG_DIRTY | PG_RW | PG_PCD);
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if (BUILTIN_EXPECT(err, 0)) {
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iobase = 0;
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return err;
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}
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iobase = newaddr;
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}
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mmio = 1;
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}
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#endif
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// configure uart
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return uart_config();
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}
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int uart_init(void)
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{
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if (is_uhyve())
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return 0;
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#ifdef CONFIG_PCI
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pci_info_t pci_info;
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uint32_t bar = 0;
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// Searching for Intel's UART device
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if (pci_get_device_info(0x8086, 0x0936, iobase, &pci_info) == 0)
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goto Lsuccess;
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// Searching for Qemu's UART device
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if (pci_get_device_info(0x1b36, 0x0002, iobase, &pci_info) == 0)
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goto Lsuccess;
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// Searching for Qemu's 2x UART device (pci-serial-2x)
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if (pci_get_device_info(0x1b36, 0x0003, iobase, &pci_info) == 0)
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goto Lsuccess;
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// Searching for Qemu's 4x UART device (pci-serial-4x)
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if (pci_get_device_info(0x1b36, 0x0004, iobase, &pci_info) == 0)
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goto Lsuccess;
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return -1;
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Lsuccess:
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iobase = pci_info.base[bar];
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irq_install_handler(32+pci_info.irq, uart_handler);
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if (pci_info.type[0]) {
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mmio = 0;
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LOG_INFO("UART uses io address 0x%x\n", iobase);
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} else {
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mmio = 1;
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page_map(iobase & PAGE_MASK, iobase & PAGE_MASK, 1, PG_GLOBAL | PG_ACCESSED | PG_DIRTY | PG_RW | PG_PCD);
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LOG_INFO("UART uses mmio address 0x%x\n", iobase);
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vma_add(iobase, iobase + PAGE_SIZE, VMA_READ|VMA_WRITE);
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}
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// default value of our QEMU configuration
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iobase = 0xc110;
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// configure uart
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return uart_config();
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#else
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// per default we use COM1...
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if (!iobase)
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iobase = 0x3F8;
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mmio = 0;
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if ((iobase == 0x3F8) || (iobase == 0x3E8))
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irq_install_handler(32+4, uart_handler);
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else if ((iobase == 0x2F8) || (iobase == 0x2E8))
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irq_install_handler(32+3, uart_handler);
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else
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return -EINVAL;
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// configure uart
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return uart_config();
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#endif
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}
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@ -132,7 +132,6 @@ static int hermit_init(void)
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multitasking_init();
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memory_init();
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signal_init();
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uart_init();
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return 0;
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}
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@ -45,7 +45,7 @@ spinlock_irqsave_t stdio_lock = SPINLOCK_IRQSAVE_INIT;
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int koutput_init(void)
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{
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if (is_single_kernel())
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uart_early_init(NULL);
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uart_init();
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return 0;
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}
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