From aeab719a2ff25085b9f920b3f2262da7c4f4ed79 Mon Sep 17 00:00:00 2001
From: Stefan Lankes <slankes@eonerc.rwth-aachen.de>
Date: Sun, 7 Aug 2016 20:28:10 +0200
Subject: [PATCH] reactivate IPI for a TLB shootdown

- required if an existing mapping  (virtual addr -> physical addr)
  changed
---
 hermit/arch/x86/include/asm/processor.h | 10 +---------
 hermit/arch/x86/kernel/apic.c           | 23 +++++++++--------------
 2 files changed, 10 insertions(+), 23 deletions(-)

diff --git a/hermit/arch/x86/include/asm/processor.h b/hermit/arch/x86/include/asm/processor.h
index 7f5db2eb9..fbe6650c5 100644
--- a/hermit/arch/x86/include/asm/processor.h
+++ b/hermit/arch/x86/include/asm/processor.h
@@ -577,19 +577,15 @@ inline static void invalidate_cache(void) {
 	asm volatile ("invd" ::: "memory");
 }
 
-#if 0
 /// Send IPIs to the other core, which flush the TLB on the other cores.
 int ipi_tlb_flush(void);
-#endif
 
 /** @brief Flush Translation Lookaside Buffer
  *
  * Just reads cr3 and writes the same value back into it.
  */
-static inline void flush_tlb(void)
+static inline void tlb_flush(void)
 {
-/* single-address space OS => no TLB flush required */
-#if 0
 	size_t val = read_cr3();
 
 	if (val)
@@ -598,7 +594,6 @@ static inline void flush_tlb(void)
 #if MAX_CORES > 1
 	ipi_tlb_flush();
 #endif
-#endif
 }
 
 /** @brief Flush a specific page entry in TLB
@@ -606,14 +601,11 @@ static inline void flush_tlb(void)
  */
 static inline void tlb_flush_one_page(size_t addr)
 {
-/* single-address space OS => no TLB flush required */
-#if 0
 	asm volatile("invlpg (%0)" : : "r"(addr) : "memory");
 
 #if MAX_CORES > 1
 	ipi_tlb_flush();
 #endif
-#endif
 }
 
 /** @brief Invalidate cache
diff --git a/hermit/arch/x86/kernel/apic.c b/hermit/arch/x86/kernel/apic.c
index ff9df9268..ae20d0440 100644
--- a/hermit/arch/x86/kernel/apic.c
+++ b/hermit/arch/x86/kernel/apic.c
@@ -851,27 +851,23 @@ int smp_start(void)
 	return smp_main();
 }
 
-#if 0
 int ipi_tlb_flush(void)
 {
 	uint32_t id = CORE_ID;
-	uint32_t j;
-	uint64_t i;
-	uint8_t flags;
 
 	if (atomic_int32_read(&cpu_online) == 1)
 		return 0;
 
 	if (has_x2apic()) {
-		flags = irq_nested_disable();
-		for(i=0; i<MAX_APIC_CORES; i++)
+		uint8_t flags = irq_nested_disable();
+		for(uint64_t i=0; i<MAX_APIC_CORES; i++)
 		{
-			 if (i == id)
+			if (i == id)
 				continue;
 			if (!online[i])
 				continue;
 
-			//kprintf("send IPI to %zd\n", i);
+			kprintf("Send IPI to %zd\n", i);
 			wrmsr(0x830, (i << 32)|APIC_INT_ASSERT|APIC_DM_FIXED|112);
 		}
 		irq_nested_enable(flags);
@@ -881,19 +877,19 @@ int ipi_tlb_flush(void)
 			return -EIO;
 		}
 
-		flags = irq_nested_disable();
-		for(i=0; i<MAX_APIC_CORES; i++)
+		uint8_t flags = irq_nested_disable();
+		for(uint64_t i=0; i<MAX_APIC_CORES; i++)
 		{
 			if (i == id)
 				continue;
 			if (!online[i])
 				continue;
 
-			//kprintf("send IPI to %zd\n", i);
+			kprintf("Send IPI to %zd\n", i);
 			set_ipi_dest(i);
 			lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DM_FIXED|112);
 
-			j = 0;
+			uint32_t j = 0;
 			while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (j < 1000))
 				j++; // wait for it to finish, give up eventualy tho
 		}
@@ -913,7 +909,6 @@ static void apic_tlb_handler(struct state *s)
 		write_cr3(val);
 }
 #endif
-#endif
 
 int apic_send_ipi(uint64_t dest, uint8_t irq)
 {
@@ -1025,7 +1020,7 @@ int apic_init(void)
 	// set APIC error handler
 	irq_install_handler(126, apic_err_handler);
 #if MAX_CORES > 1
-	//irq_install_handler(80+32, apic_tlb_handler);
+	irq_install_handler(80+32, apic_tlb_handler);
 #endif
 	irq_install_handler(81+32, apic_shutdown);
 	irq_install_handler(124, apic_lint0);