mirror of
https://github.com/hermitcore/libhermit.git
synced 2025-03-09 00:00:03 +01:00
add SMP support for the single-kernel version of HermitCore
This commit is contained in:
Stefan Lankes
parent
d8c891a32c
commit
b85b714813
5 changed files with 405 additions and 18 deletions
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@ -73,7 +73,7 @@ endif
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default: all
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all: bootstrap $(NAME) toolchain tools
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all: arch/x86/kernel/boot.h bootstrap $(NAME) toolchain tools
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toolchain:
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$Q$(MAKE) ARCH=$(ARCH) \
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@ -134,6 +134,16 @@ doc:
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@echo [DEP] $*.dep
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$Q$(CC_FOR_TARGET) -MF $*.dep -MT $*.o -MM $(CFLAGS) $<
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arch/x86/kernel/boot.bin: arch/x86/kernel/boot.asm
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@echo " NASM $@"
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$Q$(NASM) -fbin -o $@ $<
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arch/x86/kernel/boot.h: arch/x86/kernel/boot.bin
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@echo " HEXDUMP $@"
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$Qecho "static const uint8_t boot_code[] = { \
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$(shell hexdump -v -e '"0x" 1/1 "%02X" ", "' $<) \
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};" > $@
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include/hermit/config.inc: include/hermit/config.h
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@echo "; This file is generated automatically from the config.h file." > include/hermit/config.inc
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@echo "; Before editing this, you should consider editing config.h." >> include/hermit/config.inc
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@ -40,6 +40,13 @@
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extern "C" {
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#endif
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#ifndef CMOS_PORT_ADDRESS
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#define CMOS_PORT_ADDRESS 0x70
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#endif
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#ifndef CMOS_PORT_DATA
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#define CMOS_PORT_DATA 0x71
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#endif
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/** @brief Read a byte from an IO port
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*
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* @param _port The port you want to read from
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@ -101,6 +108,18 @@ inline static void outportl(unsigned short _port, unsigned int _data)
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asm volatile("outl %1, %0"::"dN"(_port), "a"(_data));
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}
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/**
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* write a byte in CMOS
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* @param offset CMOS offset
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* @param val the value you want wto write
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*/
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inline static void cmos_write(uint8_t offset, uint8_t val)
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{
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outportb(CMOS_PORT_ADDRESS, offset);
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outportb(CMOS_PORT_DATA, val);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -41,6 +41,7 @@
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/apic.h>
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#include "boot.h"
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/*
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* Note that linker symbols are not variables, they have no memory allocated for
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@ -51,6 +52,7 @@ extern const void kernel_start;
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#define IOAPIC_ADDR ((size_t) &kernel_start - 2*PAGE_SIZE)
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#define LAPIC_ADDR ((size_t) &kernel_start - 1*PAGE_SIZE)
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#define MAX_APIC_CORES MAX_CORES
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#define SMP_SETUP_ADDR 0x8000ULL
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// IO APIC MMIO structure: write reg, then read or write data.
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typedef struct {
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@ -65,6 +67,8 @@ extern uint32_t cpu_freq;
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extern atomic_int32_t cpu_online;
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extern int32_t isle;
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extern int32_t possible_isles;
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extern int32_t possible_cpus;
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extern atomic_int32_t current_boot_id;
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apic_mp_t* apic_mp __attribute__ ((section (".data"))) = NULL;
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static apic_config_table_t* apic_config = NULL;
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static size_t lapic = 0;
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@ -80,8 +84,6 @@ spinlock_t bootlock = SPINLOCK_INIT;
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// forward declaration
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static int lapic_reset(void);
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extern atomic_int32_t cpu_online;
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static uint32_t lapic_read_default(uint32_t addr)
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{
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return *((const volatile uint32_t*) (lapic+addr));
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@ -270,6 +272,15 @@ static inline uint32_t apic_lvt_entries(void)
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return 0;
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}
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static inline void set_ipi_dest(uint32_t cpu_id) {
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uint32_t tmp;
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tmp = lapic_read(APIC_ICR2);
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tmp &= 0x00FFFFFF;
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tmp |= (cpu_id << 24);
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lapic_write(APIC_ICR2, tmp);
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}
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int apic_timer_deadline(uint32_t t)
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{
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if (BUILTIN_EXPECT(apic_is_enabled() && icr, 1)) {
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@ -382,6 +393,135 @@ static int lapic_reset(void)
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return 0;
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}
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#if MAX_CORES > 1
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/*
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* use the universal startup algorithm of Intel's MultiProcessor Specification
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*/
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static int wakeup_ap(uint32_t start_eip, uint32_t id)
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{
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static char* reset_vector = 0;
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uint32_t i;
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kprintf("Wakeup application processor %d via IPI\n", id);
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// set shutdown code to 0x0A
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cmos_write(0x0F, 0x0A);
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if (!reset_vector) {
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reset_vector = (char*) vma_alloc(PAGE_SIZE, VMA_READ|VMA_WRITE);
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page_map((size_t)reset_vector, 0x00, 1, PG_RW|PG_GLOBAL|PG_PCD);
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reset_vector += 0x467; // add base address of the reset vector
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kprintf("Map reset vector to %p\n", reset_vector);
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}
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*((volatile unsigned short *) (reset_vector+2)) = start_eip >> 4;
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*((volatile unsigned short *) reset_vector) = 0x00;
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if (lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kputs("ERROR: previous send not complete");
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return -EIO;
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}
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//kputs("Send IPI\n");
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// send out INIT to AP
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if (has_x2apic()) {
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uint64_t dest = ((uint64_t)id << 32);
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wrmsr(0x800 + (APIC_ICR1 >> 4), dest|APIC_INT_LEVELTRIG|APIC_INT_ASSERT|APIC_DM_INIT);
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udelay(200);
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// reset INIT
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wrmsr(0x800 + (APIC_ICR1 >> 4), APIC_INT_LEVELTRIG|APIC_DM_INIT);
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udelay(10000);
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// send out the startup
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wrmsr(0x800 + (APIC_ICR1 >> 4), dest|APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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// do it again
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wrmsr(0x800 + (APIC_ICR1 >> 4), dest|APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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//kputs("IPI done...\n");
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return 0;
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} else {
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_INT_LEVELTRIG|APIC_INT_ASSERT|APIC_DM_INIT);
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udelay(200);
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// reset INIT
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lapic_write(APIC_ICR1, APIC_INT_LEVELTRIG|APIC_DM_INIT);
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udelay(10000);
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// send out the startup
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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// do it again
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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//kputs("IPI done...\n");
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i = 0;
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (i < 1000))
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i++; // wait for it to finish, give up eventualy tho
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return ((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) ? -EIO : 0); // did it fail (still delivering) or succeed ?
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}
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}
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int smp_init(void)
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{
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uint32_t i, j;
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int err;
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if (ncores <= 1)
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return -EINVAL;
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kprintf("CR0 of core %u: 0x%x\n", apic_cpu_id(), read_cr0());
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/*
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* dirty hack: Reserve memory for the bootup code.
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* In a single core enviroment is everythink below 8 MB free.
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*
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* Copy 16bit startup code to a 16bit address.
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* Wakeup the other cores via IPI. They start at this address
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* in real mode, switch to protected and finally they jump to smp_main.
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*/
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page_map(SMP_SETUP_ADDR, SMP_SETUP_ADDR, PAGE_FLOOR(sizeof(boot_code)) >> PAGE_BITS, PG_RW|PG_GLOBAL);
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vma_add(SMP_SETUP_ADDR, SMP_SETUP_ADDR + PAGE_FLOOR(sizeof(boot_code)), VMA_READ|VMA_WRITE|VMA_CACHEABLE);
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memcpy((void*)SMP_SETUP_ADDR, boot_code, sizeof(boot_code));
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for(i=0; i<sizeof(boot_code); i++)
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{
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if (*((uint32_t*) (SMP_SETUP_ADDR + i)) == 0xDEADBEAF) {
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*((uint32_t*) (SMP_SETUP_ADDR + i)) = (uint32_t) read_cr3();
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break;
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}
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}
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//kprintf("size of the boot_code %d\n", sizeof(boot_code));
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for(i=1; (i<ncores) && (i<MAX_CORES); i++)
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{
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atomic_int32_set(¤t_boot_id, i);
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err = wakeup_ap(SMP_SETUP_ADDR, i);
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if (err)
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kprintf("Unable to wakeup application processor %d: %d\n", i, err);
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for(j=0; (i >= atomic_int32_read(&cpu_online)) && (j < 1000); j++)
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udelay(1000);
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if (i >= atomic_int32_read(&cpu_online)) {
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kprintf("Unable to wakeup processor %d, cpu_online %d\n", i, atomic_int32_read(&cpu_online));
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return -EIO;
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}
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}
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kprintf("%d cores online\n", atomic_int32_read(&cpu_online));
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return 0;
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}
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#endif
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/*
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* detects the timer frequency of the APIC and restart
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* the APIC timer with the correct period
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@ -467,6 +607,9 @@ int apic_calibration(void)
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}
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initialized = 1;
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#if MAX_CORES > 1
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smp_init();
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#endif
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irq_nested_enable(flags);
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return 0;
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@ -601,6 +744,8 @@ found_mp:
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goto no_mp;
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}
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ncores = count;
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if (is_single_kernel())
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possible_cpus = count;
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check_lapic:
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if (apic_config)
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@ -658,7 +803,6 @@ no_mp:
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extern int smp_main(void);
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extern void gdt_flush(void);
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extern int set_idle_task(void);
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extern atomic_int32_t current_boot_id;
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#if MAX_CORES > 1
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int smp_start(void)
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@ -701,15 +845,6 @@ int smp_start(void)
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return smp_main();
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}
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static inline void set_ipi_dest(uint32_t cpu_id) {
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uint32_t tmp;
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tmp = lapic_read(APIC_ICR2);
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tmp &= 0x00FFFFFF;
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tmp |= (cpu_id << 24);
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lapic_write(APIC_ICR2, tmp);
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}
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#if 0
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int ipi_tlb_flush(void)
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{
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223
hermit/arch/x86/kernel/boot.asm
Normal file
223
hermit/arch/x86/kernel/boot.asm
Normal file
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@ -0,0 +1,223 @@
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; Copyright 2010-2016 Stefan Lankes, RWTH Aachen University
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; * Neither the name of the University nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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KERNEL_STACK_SIZE equ 0x100
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kernel_start equ 0x800000
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[BITS 16]
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SECTION .text
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GLOBAL _start
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ORG 0x8000
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_start:
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cli
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lgdt [gdtr]
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; switch to protected mode by setting PE bit
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mov eax, cr0
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or al, 0x1
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mov cr0, eax
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; far jump to the 32bit code
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jmp dword codesel : _pmstart
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[BITS 32]
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ALIGN 4
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_pmstart:
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xor eax, eax
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mov ax, datasel
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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mov esp, boot_stack+KERNEL_STACK_SIZE-16
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jmp short stublet
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jmp $
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; GDT for the protected mode
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ALIGN 4
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gdtr: ; descritor table
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dw gdt_end-gdt-1 ; limit
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dd gdt ; base adresse
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gdt:
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dd 0,0 ; null descriptor
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codesel equ $-gdt
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dw 0xFFFF ; segment size 0..15
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dw 0x0000 ; segment address 0..15
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db 0x00 ; segment address 16..23
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db 0x9A ; access permissions und type
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db 0xCF ; additional information and segment size 16...19
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db 0x00 ; segment address 24..31
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datasel equ $-gdt
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dw 0xFFFF ; segment size 0..15
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dw 0x0000 ; segment address 0..15
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db 0x00 ; segment address 16..23
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db 0x92 ; access permissions and type
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db 0xCF ; additional informationen and degment size 16...19
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db 0x00 ; segment address 24..31
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gdt_end:
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ALIGN 4
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GDTR64:
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dw GDT64_end - GDT64 - 1 ; Limit.
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dq GDT64 ; Base.
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; we need a new GDT to switch in the 64bit modus
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GDT64: ; Global Descriptor Table (64-bit).
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.Null: equ $ - GDT64 ; The null descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 0 ; Access.
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db 0 ; Granularity.
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db 0 ; Base (high).
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.Code: equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10011010b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.Data: equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10010010b ; Access.
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db 00000000b ; Granularity.
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db 0 ; Base (high).
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GDT64_end:
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ALIGN 4
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stublet:
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; This will set up the x86 control registers:
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; Caching and the floating point unit are enabled
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; Bootstrap page tables are loaded and page size
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; extensions (huge pages) enabled.
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;
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; HermitCore's boot processor map its kernel into
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; the address space of this trampoline code.
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; => more information in apic.c
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cpu_init:
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; check for long mode
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; do we have the instruction cpuid?
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz $ ; there is no long mode
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; cpuid > 0x80000000?
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb $ ; It is less, there is no long mode.
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; do we have a long mode?
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz $ ; They aren't, there is no long mode.
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; we need to enable PAE modus
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; Set CR3
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mov eax, 0xDEADBEAF ;boot_pml4
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add eax, ebp
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or eax, (1 << 0) ; set present bit
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mov cr3, eax
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||||
|
||||
; Set CR4 (PAE is already set)
|
||||
mov eax, cr4
|
||||
and eax, 0xfffbf9ff ; disable SSE
|
||||
or eax, (1 << 7) ; enable PGE
|
||||
mov cr4, eax
|
||||
|
||||
; Set CR0 (PM-bit is already set)
|
||||
mov eax, cr0
|
||||
and eax, ~(1 << 2) ; disable FPU emulation
|
||||
or eax, (1 << 1) ; enable FPU montitoring
|
||||
and eax, ~(1 << 30) ; enable caching
|
||||
and eax, ~(1 << 29) ; disable write through caching
|
||||
and eax, ~(1 << 16) ; allow kernel write access to read-only pages
|
||||
or eax, (1 << 31) ; enable paging
|
||||
mov cr0, eax
|
||||
|
||||
lgdt [GDTR64] ; Load the 64-bit global descriptor table.
|
||||
mov ax, GDT64.Data
|
||||
mov ss, ax
|
||||
mov ds, ax
|
||||
mov es, ax
|
||||
|
||||
jmp GDT64.Code:start64 ; Set the code segment and enter 64-bit long mode.
|
||||
|
||||
[BITS 64]
|
||||
ALIGN 8
|
||||
start64:
|
||||
push kernel_start
|
||||
ret
|
||||
|
||||
ALIGN 16
|
||||
global boot_stack
|
||||
boot_stack:
|
||||
TIMES (KERNEL_STACK_SIZE) DB 0xcd
|
||||
|
||||
; Bootstrap page tables are used during the initialization.
|
||||
;ALIGN 4096
|
||||
;boot_pml4:
|
||||
; DQ boot_pdpt + 0x7 ; PG_PRESENT | PG_RW | PG_USER
|
||||
; times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
|
||||
; DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
|
||||
;boot_pdpt:
|
||||
; DQ boot_pgd + 0x7 ; PG_PRESENT | PG_RW | PG_USER
|
||||
; times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
|
||||
; DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
|
||||
;boot_pgd:
|
||||
; DQ boot_pgt + 0x7 ; PG_PRESENT | PG_RW | PG_USER
|
||||
; times 510 DQ 0 ; PAGE_MAP_ENTRIES - 2
|
||||
; DQ boot_pml4 + 0x203 ; PG_PRESENT | PG_RW | PG_SELF (self-reference)
|
||||
;boot_pgt:
|
||||
;%assign i 0
|
||||
;%rep 512
|
||||
; DQ i*0x1000 + 0x103
|
||||
;%assign i i+1
|
||||
;%endrep
|
||||
|
|
@ -130,6 +130,7 @@ static int hermit_init(void)
|
|||
#ifndef CONFIG_VGA
|
||||
uart_init();
|
||||
#endif
|
||||
atomic_int32_inc(&cpu_online);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -260,18 +261,18 @@ int network_shutdown(void)
|
|||
#if MAX_CORES > 1
|
||||
int smp_main(void)
|
||||
{
|
||||
atomic_int32_inc(&cpu_online);
|
||||
|
||||
#ifdef DYNAMIC_TICKS
|
||||
enable_dynticks();
|
||||
#endif
|
||||
|
||||
print_status();
|
||||
|
||||
atomic_int32_inc(&cpu_online);
|
||||
|
||||
/* wait for the other cpus */
|
||||
while(atomic_int32_read(&cpu_online) < atomic_int32_read(&possible_cpus))
|
||||
PAUSE;
|
||||
|
||||
print_status();
|
||||
|
||||
//create_kernel_task(NULL, foo, "foo2", NORMAL_PRIO);
|
||||
|
||||
while(1) {
|
||||
|
|
@ -545,7 +546,6 @@ int hermit_main(void)
|
|||
hermit_init();
|
||||
system_calibration(); // enables also interrupts
|
||||
|
||||
atomic_int32_inc(&cpu_online);
|
||||
|
||||
kprintf("This is Hermit %s, build date %u\n", VERSION, &__DATE__);
|
||||
kprintf("Isle %d of %d possible isles\n", isle, possible_isles);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue